Digital-to-Analog (D/A) Conversion

• The input is a binary number

• Let’s introduce

b = {b1b2 ...bn }, f .i. {1001011}

and then define
VFS = Full-Scale Voltage

• The least significant bit (LSB) - the smallest possible binary number
(smallest voltage change) is known as resolution of the converter.
VLSB = 2−n VFS , f .i. {0000001}
• The most significant bit (MSB) – V = 2−1V , f .i. {1000000}
MSB FS
• Then for an n-bit D/A converter, the output voltage is expressedas:
VO = (b1 2−1 + b 22−2 + ... + b n2−n )V FS

= (b1 2n−1 + b2 2n−2 + ... + bn 20 )2−n V FS

= (b1 2n−1 + b2 2n−2 + ... +bn 20 )VLSB
Chap 1 - 1
Bu sorulara benzer soracak
Bu belli değil ama formülü verecek.
Açıklamasını soracak.
Şekil soracak en alttakiler
NPN verecek PNP formülü
isteyecek.
Değişen sadece
aşağıdakiler.
NPN de VBE
PNP de VEB
 Logic Gates: AND
The simples gates are AND and OR. They can be built from switches or using
the simplest form of electronic logic - diode logic.

Doğruluk tablosu ve
açıklama isteyecek.

A = 0 , B = 0 →both diodes are forward biased →both diodes conduct →out is LOW →0.

A = 0 , B = 1 →DB is reverse biased →does not conduct,

DA is forward biased →conducts →out is LOW →0.

A = 1 , B = 0 →DA is reverse biased →does not conduct,

DB is forward biased →conducts →out is LOW →0.

A = 1 , B = 1 →both diodes are reverse biased →

both the diodes do not conduct →out is HIGH →1.

NJIT ECE271 Dr.Serhiy Levkov Topic 7 - 8

 Logic Gates: OR

Doğruluk tablosu ve
açıklama isteyecek.

A = 0 , B = 0 →both diodes are reverse biased →does not conduct →out is LOW →0.

A = 0 , B = 1 →DA is reverse biased →does not conduct,

DB is forward biased →conducts →out is HIGH →1.

A = 1 , B = 0 →DB is reverse biased →does not conduct,

DA is forward biased →conducts →out is HIGH →1.

A = 1 , B = 1 →both diodes are reverse biased →

both the diodes conduct →out is HIGH →1.

NJIT ECE271 Dr.Serhiy Levkov Topic 7 - 9

 VTC of Non-Ideal Inverter
Voltage Level Definitions

VIL VIH – VOL VOH açıklama isteyecek

For the (VTC) of the non-ideal inverter no Vref is defined. There is now an
undefined logic state. The points (VIH ,VOL ) and (VIL ,VOH ) are defined as the points
on the VTC curve where slope is -1.

NJIT ECE271 Dr.Serhiy Levkov Topic 7 - 16

VIL VIH – VOL VOH
Verip Vcc Vce Vbe isteyecek
 Kısa açıklama
isteyebilir muallak tam
belli değil
 R1 direncini
çizmeni isteyecek
Fen in fen out nedir
Fen in girdi sayısı
Fen out çıktı sayısı
 The RTL NOR Gate
• An RTL NOR gate can be made by replicating
the Base resistor and the transistor in parallel for
each input

VCC
Doğruluk tablosu isteyecek kısa
açıklama ile
RC

Vout

RB1 Q1 RB2 Q2 RBN QN

V IN1 V IN2 VINN

Digital Electronics ELE 450A First 2015/2016 Dr. Idrees Al-Kofahi 10

 VCC

The RTL NAND Gate RC

• If all inputs are high, then each of

the transistors becomes saturated Vout

and R B1
Q1

•
V IN1
V out = N * V CE (Sat) (VOL)

• Therefore, the circuit implements a R B2

Q2
Doğruluk tablosu isteyecek kısa
açıklama ile
NAND gate. V IN2

• NOTE:
– Each higher transistor will require a higher input
voltage to reach saturation. This is due to the
emitter of the higher transistor being connected to R BN
the collector of the transistor below it. This makes QN
the maximum number of inputs for the RTL VINN

NAND Gate very limited.

Digital Electronics ELE 450A First 2015/2016 Dr. Idrees Al-Kofahi 14

 The inverter's operation
VIN QS QP QO Vout
HIGH Sat. Off Sat. VCE (Sat)
LOW Off F. A. Off VCC – VBE(FA) V CC

RC RCP
Tabloyu boş verip doldurmamızı isteyecek.
RBP
QP
V in RBS
QS

V out

RBO
QO

Digital Electronics ELE 450A First 2015/2016 Dr. Idrees Al-Kofahi 34