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A B C D E

MS-N011 VER : 1.0 Diamondville


Page 2,3 DC JACK
+3V +5V
TPS51120
Page 27
&
4
Selector 4

HOST Page 25 +1_8VDIMM


133MHZ 4X SC412
Page 28
CRT
Page 21 RGB SYS POWER
Signal Channel DDRII VTT(1.05V)
NORTH 400/533 MHZ
onboard DDR +1_5VRUN
LVDS LVDS
Page 21
BRIDGE Page 9,10 +2_5VRUN
SC412
INTEL Page 29
DDR-SODIMM1
945GMS Page 8
CPU POWER
3 Page 4~7 ISL6261 3

Page 30

DMIx2
Interface CHARGER
Wireless LAN MAX 8724
MINI PCIE Page 26
Conn. SATA 80GB HDD
Page 33 OR
SATA
JMF 602
NAND FLASH
optional
PCIE-LAN Page 22
RTL8102E
Page 18 PCI-EXPRESS SOUTH
2 BRIDGE USB1.1/2.0 2

INTEL
ICH7-M Mini_PCIE x1
Internal SPK ALC888S Azalia Connectors Wireless LAN Camera Cardreader Blue tooth
Internal MIC Page 19 USB 0,1,2 USB 3 USB 4 USB 5 USB 6
MIC Page 23 Page 23 Page 23 Page 22 Page 22
Earphone Page 12~15
optional
Page 20

LPC BUS LPC DUBUG


CLK ICS113 Page 24
1 1
Page 16

KBC SPI MICRO-STAR INT'L CO.,LTD


TP & KB BIOS
Page 24 ENE 3310 Page 24
Page 17 MSI
MS-N011
Size Document Description Rev
Custom 1.0
BLOCK DIAGRAM
Date: Friday, March 28, 2008 Sheet 1 of 39

A B C D E
A B C D E

H_A#[31:3]
4 H_A#[31:3]
H_RS#[2:0]
4 H_RS#[2:0]
H_REQ#[4:0]
4 H_REQ#[4:0]

U28A
H_A#3 P21 V19
A[3]# ADS# H_ADS# 4 U28B
4 H_A#4 H20 Y19 4 H_D#[63:0] H_D#[63:0] 4 4
A[4]# BNR# H_BNR# 4

0
ADDR GROUP
H_A#5 N20 U21 H_D#0 Y11 R3 H_D#32
A[5]# BPRI# H_BPRI# 4 D[0]# D[32]#
H_A#6 R20 H_D#1 W10 R2 H_D#33
H_A#7 A[6]# VTT H_D#2 D[1]# D[33]# H_D#34
J19 A[7]# DEFER# T21 H_DEFER# 4 Y12 D[2]# D[34]# P1
H_A#8 N19 T19 H_D#3 AA14 N1 H_D#35
A[8]# DRDY# H_DRDY# 4 D[3]# D[35]#

DATA GRP0
H_A#9 G20 Y18 H_D#4 AA11 M2 H_D#36
A[9]# DBSY# H_DBSY# 4 D[4]# D[36]#

CONTROL

DATA GRP2
H_A#10 M19 H_D#5 W12 P2 H_D#37
H_A#11 A[10]# R363 H_D#6 D[5]# D[37]# H_D#38
H21 A[11]# BR0# T20 H_BREQ# 4 AA16 D[6]# D[38]# J3
H_A#12 L20 330R/4 H_D#7 Y10 N3 H_D#39
H_A#13 A[12]# IERR# H_D#8 D[7]# D[39]# H_D#40
M20 A[13]# IERR# F16 Y9 D[8]# D[40]# G3
H_A#14 K19 V16 H_INIT#_R R362 1K1%4 H_D#9 Y13 H2 H_D#41
A[14]# INIT# H_INIT# 12 D[9]# D[41]#
H_A#15 J20 H_D#10 W15 N2 H_D#42
H_A#16 A[15]# H_D#11 D[10]# D[42]# H_D#43
L21 A[16]# LOCK# W20 H_LOCK# 4 AA13 D[11]# D[43]# L2
4 H_ADSTB#0 K20 H_D#12 Y16 M3 H_D#44
T19 AP0 ADSTB[0]# H_D#13 D[12]# D[44]# H_D#45
D17 AP0 RESET# D15 H_CPURST# 4 W13 D[13]# D[45]# J2
H_REQ#0 N21 W18 H_RS#0 H_D#14 AA9 H1 H_D#46
H_REQ#1 REQ[0]# RS[0]# H_RS#1 H_D#15 D[14]# D[46]# H_D#47
J21 REQ[1]# RS[1]# Y17 W9 D[15]# D[47]# J1
H_REQ#2 G19 U20 H_RS#2 4 H_DSTBN#0 Y14 K2 H_DSTBN#2 4
H_REQ#3 REQ[2]# RS[2]# DSTBN[0]# DSTBN[2]#
P20 REQ[3]# TRDY# W19 H_TRDY# 4 4 H_DSTBP#0 Y15 DSTBP[0]# DSTBP[2]# K3 H_DSTBP#2 4
H_REQ#4 R19 4 H_DINV#0 W16 L1 H_DINV#2 4
REQ[4]# T16 DP#0 V9 DINV[0]# DINV[2]# DP#2 T8
HIT# AA17 H_HIT# 4 4 H_D#[63:0] DP#0 DP#2 M4
HITM# V20 H_HITM# 4 H_D#[63:0] 4
H_A#17 C19 H_D#16 AA5 C2 H_D#48
H_A#18 A[17]# H_D#17 D[16]# D[48]# H_D#49
F19 A[18]# BPM[0]# K17 Y8 D[17]# D[49]# G2
H_A#19 E21 J18 H_D#18 W3 F1 H_D#50
H_A#20 A[19]# BPM[1]# H_D#19 D[18]# D[50]# H_D#51
H_A#21
A16 A[20]# XDP/ITP SIGNALS BPM[2]# H15
H_D#20
U1 D[19]# D[51]# D3
H_D#52
D19 A[21]# BPM[3]# J15 W7 D[20]# D[52]# B4
ADDR GROUP 1

DATA GRP1

DATA GRP3
H_A#22 C14 K18 H_D#21 W6 E1 H_D#53
H_A#23 A[22]# PRDY# PREQ# VTT H_D#22 D[21]# D[53]# H_D#54
C18 A[23]# PREQ# J16 Y7 D[22]# D[54]# A5
H_A#24 C20 M17 HTCK H_D#23 AA6 C3 H_D#55
H_A#25 A[24]# TCK HTDI H_D#24 D[23]# D[55]# H_D#56
E20 A[25]# TDI N16 Y3 D[24]# D[56]# A6
3 VTT H_A#26 D20 M16 H_D#25 W2 F2 H_D#57 3
H_A#27 A[26]# TDO HTMS H_D#26 D[25]# D[57]# H_D#58
B18 A[27]# TMS L17 V3 D[26]# D[58]# C6
RN54 H_A#28 C15 K16 HTRST# R202 H_D#27 U2 B6 H_D#59
H_A#32 H_A#29 A[28]# TRST# H_D#28 D[27]# D[59]# H_D#60
1 2 B16 A[29]# BR1# V15 68R/4 T3 D[28]# D[60]# B3
3 4 H_A#34 H_A#30 B17 R201 H_D#29 AA8 C4 H_D#61
H_A#33 H_A#31 A[30]# PROCHOT# H_D#30 D[29]# D[61]# H_D#62
5 6 C16 A[31]# PROCHOT# G17 H_PROCHOT# 30 V2 D[30]# D[62]# C7
7 8 H_A#35 H_A#32 A17 E4 THERMDA H_D#31 W4 D2 H_D#63
H_A#33 A[32]# THERMDA THERMDC 22R/4 D[31]# D[63]#
B14 E5 4 H_DSTBN#1 Y4 E2 H_DSTBN#3 4 0.5" max length
THERM

8P4R-1K/4 H_A#34 A[33]# THERMDC DSTBN[1]# DSTBN[3]#


B15 A[34]# 4 H_DSTBP#1 Y5 DSTBP[1]# DSTBP[3]# F3 H_DSTBP#3 4
H_A#35 A14 4 H_DINV#1 Y6 C5 H_DINV#3 4 25 MIL AWAY FROM HIGH
A[35]# T7 DP#1 R4 DINV[1]# DINV[3]# DP#3 T11
4 H_ADSTB#1 B19 ADSTB[1]# DP#1 DP#3 D4 SPEED SIGNAL
T21 AP1 M18 H17 PM_THRMTRIP# 12 GTLREF A7 T1 HCOMP0 R318 27.4R1%6 HCOMP0,2==>18MIL
AP1 THERMTRIP# GTLREF COMP[0]
R343
R352
X_1K/4
X_1K/4
U5
V5
ACLKPH MISC COMP[1] T2
F20
HCOMP1
HCOMP2
R323
R372
54.9R1%4
27.4R1%6 HCOMP1,3==>5MIL
BINIT# DCLKPH COMP[2] HCOMP3 R371 54.9R1%4
12 H_A20M# U18 A20M# T18 T17 BINIT# COMP[3] F21
T16 EDM R6
12 H_FERR# FERR# T15 EDM
12 H_IGNNE# J4 VTT EXTBGREF M6 R18 H_DPRSTP# H_DPRSTP# 12,30
IGNNE# T12 EXTBGR DPRSTP#
R16 V11 FORCEPR# N15 R17 H_DPSLP#
H CLK

12 H_STPCLK# STPCLK# BCLK[0] CLK_CPU_BCLK 16 T17 FORCEPR# DPSLP# H_DPSLP# 12


12 H_INTR T15 V12 IERR# R185 56R/4 HFPLL N6 U4 H_DPWR# H_DPWR# 4
LINT0 BCLK[1] CLK_CPU_BCLK# 16 T14 HFPLL DPWR#
12 H_NMI R15 MCERR# P17 V17 CPU_PWRGD CPU_PWRGD 12
LINT1 T20 MCERR# PWRGOOD
12 H_SMI# U17 RN57 RSP# T6 N18 CPUSLP# CPUSLP# 4
SMI# T13 RSP# SLP#
PREQ# 1 2 A13 CORE_D T33
HTMS CORE_D
3 4
HTDI 5 6 B7 CPU_CMREF VTT
HTCK CMREF
D6 NC1 7 8 16,17 CPU_BSEL0 J6 BSEL[0]
VTT G6 C21 H5
NC2 RSVD3 8P4R-56R/4 16,17 CPU_BSEL1 CPU_BSEL2 BSEL[1]
H6 NC3 RSVD2 C1 T9 G5 BSEL[2]
R365 X_1K/4 H_A20M# K4 A3 R154
R322 X_1K/4 H_IGNNE# NC4 RSVD1
K5 NC5 X_1K/4
M15 HTRST# R370 56R/4
2 NC6 2
L16 NC7
R356 X_51R/4 H_INTR Diamondville H_DPWR#
R361 X_51R/4 H_NMI
R366 X_1K/4 H_SMI#
R150
Diamondville X_1K/4

VTT VTT 0.5" max VTT


0.5" max 0.5" max length
+3VRUN length length
R319 R326 R327
SMB_CPU_CLK R124 2.2K/4
Cap close to 1K1%4 1K1%4 1K1%4

thermal SMB_CPU_DATA R134 2.2K/4 EXTBGREF GTLREF CPU_CMREF VTT

sensor THERMAL_INT# R137 2.2K/4


Trace : 10/4/10 Close to CPU socket R321 R333 C416 R334
+3VRUN 2K1%4 C401 2K1%4 C415 0.1u10X4 2K1%4 R188
THERMDA U11 1u6.3Y4 X_0.1u10X4 X_1K/4

1 VDD SMBCLK 8 SMB_CPU_CLK 17


C119 2 7 CPU_PWRGD
D+ SMBData SMB_CPU_DATA 17
100p16N4 3 6 THERMAL_INT# 17
D- ALERT
4 T_CRIT_A GND 5
THERMDC
SNSR-LM95245CIMM-RH
PM_THRMTRIP# R144 X_0R/4

1 1
C116
0.1u10X4

MICRO-STAR INT'L CO.,LTD

MSI
MS-N011
Size Document Description Rev
Custom 1.0
Diamondville signal
Date: Friday, April 11, 2008 Sheet 2 of 39

A B C D E
A B C D E

U28D
1.05V
A2 VTT
VSS VTT
A4 VSS VSS N9 U28C
A8 VSS VSS N7
A15 VSS VSS N5
A18 VSS VSS N4 V10 VCCF VTT1 C9
A19 VSS VSS M21 VTT2 D9
A20 VSS VSS N13 A9 VCCQ1 VTT3 E9
4 B1 VSS VSS N17 B9 VCCQ2 VTT4 F8 4
B2 P3 V_CORE F9 C141 C175 C142 C171 C139
VSS VSS VTT5 0.1u10X4 1u6.3X4 1u6.3X4 X_10u6.3X8 10u6.3X8
B5 VSS VSS P4 VTT6 G8
B8 VSS VSS P5 1.1V VTT7 G14
B13 VSS VSS P6 A10 VCCP1 VTT8 H8
B20 VSS VSS P7 A11 VCCP2 VTT9 H14
B21 VSS VSS P9 A12 VCCP3 VTT10 J8 Place in cavity
C8 VSS VSS P13 B10 VCCP4 VTT11 J14
C17 VSS VSS P15 B11 VCCP5 VTT12 K8
D1 VSS VSS P16 B12 VCCP6 VTT13 K14
D5 VSS VSS P18 C10 VCCP7 VTT14 L8
D8 VSS VSS P19 C11 VCCP8 VTT15 L14
D14 R1 C12 M8 V_CORE
VSS VSS VCCP9 VTT16
D18 VSS VSS R5 D10 VCCP10 VTT17 M14 Place in cavity
D21 VSS VSS R7 D11 VCCP11 VTT18 N8
E3 VSS VSS R9 D12 VCCP12 VTT19 N14
E6 VSS VSS R13 E10 VCCP13 VTT20 P8
E7 VSS VSS R21 E11 VCCP14 VTT21 P14
E8 VSS VSS T4 E12 VCCP15 VTT22 R8
E15 T5 F10 R14 C163 C159 C152 C169 C162
VSS VSS VCCP16 VTT23 1u6.3X4 1u6.3X4 1u6.3X4 1u6.3X4 X_1u6.3X4
E16 VSS VSS T7 F11 VCCP17 VTT24 T8
E19 VSS VSS T9 F12 VCCP18 VTT25 T14
F4 T10 G10 U8

POWER
VSS VSS VCCP19 VTT26
F5 VSS VSS T11 G11 VCCP20 VTT27 U9
F6 T12 G12 U10
GND

VSS VSS VCCP21 VTT28


F7 VSS VSS T13 H10 VCCP22 VTT29 U11
F17 T18 H11 U12 +1_5VRUN
VSS VSS VCCP23 VTT30
F18 VSS VSS U3 H12 VCCP24 VTT31 U13
G1 VSS VSS U6 J10 VCCP25 VTT32 U14
G4 U7 J11 V_CORE
VSS VSS VCCP26
G7 VSS VSS U15 J12 VCCP27 VCCPC64 F14
3 G9 U16 K10 F13 C140 3
VSS VSS VCCP28 VCCPC63
G13 VSS VSS U19 K11 VCCP29 VCCPC62 E14 0.1u16X6
G21 VSS VSS V1 K12 VCCP30 VCCPC61 E13
H3 VSS VSS V4 L10 VCCP31
H4 VSS VSS V6 L11 VCCP32 130mA
H7 V7 L12 D7 C148 C151 C161
VSS VSS VCCP33 VCCA 1u6.3X4 1u6.3X4 1u6.3X4
H9 VSS VSS V8 M10 VCCP34
H13 V13 M11 F15 CPU_VID0 V_CORE
VSS VSS VCCP35 VID[0] CPU_VID0 30
H16 V14 M12 D16 CPU_VID1
VSS VSS VCCP36 VID[1] CPU_VID1 30
H18 V18 N10 E18 CPU_VID2
VSS VSS VCCP37 VID[2] CPU_VID2 30
H19 V21 N11 G15 CPU_VID3
VSS VSS VCCP38 VID[3] CPU_VID3 30
J5 W1 N12 G16 CPU_VID4 R359
VSS VSS VCCP39 VID[4] CPU_VID4 30
J7 W5 P10 E17 CPU_VID5 100R1%4
VSS VSS VCCP40 VID[5] CPU_VID5 30
J9 W8 P11 G18 CPU_VID6
VSS VSS VCCP41 VID[6] CPU_VID6 30
J13 VSS VSS W11 P12 VCCP42
J17 VSS VSS W14 R10 VCCP43 VCCSENSE C13 VCCSENSE 30
K1 VSS VSS W17 R11 VCCP44 VSSSENSE D13 VSSSENSE 30
K6 VSS VSS W21 R12 VCCP45
K7 VSS VSS Y1
K9 Y2 R358
VSS VSS Diamondville
K13 VSS VSS Y20 2.5A: before VCC stable 100R1%4
K15 VSS VSS Y21 1.5A: after VCC stable
K21 VSS VSS AA2
L3 VSS VSS AA3
L4 VSS VSS AA4
L5 VSS VSS AA7
L6 VSS VSS AA10
L7 VSS VSS AA12
L9 VSS VSS AA15
L13 AA18 V_CORE
VSS VSS
2
L15 VSS VSS AA19 Place in cavity 2
L18 VSS VSS AA20
L19 VSS
M1 VSS
M5 VSS
M7 VSS
M9 C160 C153 C154 C164 C170
VSS
M13 VSS 10u6.3X8 10u6.3X8 10u6.3X8 10u6.3X8 10u6.3X8

Diamondville

LAYOUT NOTE:
close to cpu socket
Route VCCSENSE and VSSSENSE
traces at 27.4Ohms with 50
mil spacing.
Place PU and PD within 1
inch of CPU.

1 1

MICRO-STAR INT'L CO.,LTD

MSI
MS-N011
Size Document Description Rev
Custom 1.0
Diamondville Pown/GND
Date: Friday, April 11, 2008 Sheet 3 of 39

A B C D E
5 4 3 2 1

2 H_D#[63:0] U26A H_A#[31:3] 2


H_D#0 C4 F8 H_A#3
H_D#1 H_D#_0 H_A#_3 H_A#4
F6 H_D#_1 H_A#_4 D12
H_D#2 H9 C13 H_A#5
H_D#3 H_D#_2 H_A#_5 H_A#6
H6 H_D#_3 H_A#_6 A8
H_D#4 F7 E13 H_A#7
H_D#5 H_D#_4 H_A#_7 H_A#8 U26G
E3 H_D#_5 H_A#_8 E12
H_D#6 C2 J12 H_A#9
H_D#7 H_D#_6 H_A#_9 H_A#10
C3 H_D#_7 H_A#_10 B13 W33 NC1 NC61 W30
H_D#8 K9 A13 H_A#11 AM33 Y6
H_D#9 H_D#_8 H_A#_11 H_A#12 NC2 NC62
F5 H_D#_9 H_A#_12 G13 AL33 NC3 NC63 AL1
D H_D#10 J7 A12 H_A#13 C33 Y5 D
H_D#11 H_D#_10 H_A#_13 H_A#14 NC4 NC64
K7 H_D#_11 H_A#_14 D14 B33 NC5 NC65 Y10
H_D#12 H8 F14 H_A#15 AN32 W10
H_D#13 H_D#_12 H_A#_15 H_A#16 NC6 NC66
E5 H_D#_13 H_A#_16 J13 A32 NC7 NC67 W25
H_D#14 K8 E17 H_A#17 AN31 V24
H_D#15 H_D#_14 H_A#_17 H_A#18 NC8 NC68
J8 H_D#_15 H_A#_18 H15 W28 NC9 NC69 U24
H_D#16 J2 G15 H_A#19 V27 V10
H_D#17 H_D#_16 H_A#_19 H_A#20 NC10 NC70
J3 H_D#_17 H_A#_20 G14 W29 NC11 NC71 U10
H_D#18 N1 A15 H_A#21 J24 K18
H_D#19 H_D#_18 H_A#_21 H_A#22 NC12 NC72
M5 H_D#_19 H_A#_22 B18 H24 NC13
H_D#20 K5 B15 H_A#23 W32
H_D#21 H_D#_20 H_A#_23 H_A#24 NC14
J5 H_D#_21 H_A#_24 E14 G24 NC15
H_D#22 H3 H13 H_A#25 F24
H_D#23 H_D#_22 H_A#_25 H_A#26 NC16
J4 H_D#_23 H_A#_26 C14 E24 NC17
0.3125 * VTT H_D#24 N3 A17 H_A#27 D24
H_D#25 H_D#_24 H_A#_27 H_A#28 NC18
Trace wide/spacing=10/20 M4 H_D#_25 H_A#_28 E15 K33 NC19
H_D#26 M3 H17 H_A#29 VTT A31
H_D#27 H_D#_26 H_A#_29 H_A#30 NC20
N8 H_D#_27 H_A#_30 D17 E21 NC21
VTT VTT H_D#28 N6 G17 H_A#31 C23
H_D#29 H_D#_28 H_A#_31 NC22
K3 H_D#_29 AN19 NC23
H_D#30 N9 R325 AM19
H_D#31 H_D#_30 NC24
M1 H_D#_31 H_ADS# F10 H_ADS# 2 100R1%4 AL19 NC25
R336 R315 H_D#32 V8 C12 H_ADSTB#0 2 place <100mils from pin. AK19
221R1%4 221R1%4 H_D#33 H_D#_32 H_ADSTB#_0 NC26
V9 H_D#_33 H_ADSTB#_1 H16 H_ADSTB#1 2 AJ19 NC27
H_D#34 R6 E2 HVREF AH19

HOST
H_D#_34 H_VREF0 NC28

NC
H_D#35 T8 B9 H_BNR# 2 AN3
HXSWING HYSWING H_D#36 H_D#_35 H_BNR# NC29
R2 H_D#_36 H_BPRI# C7 H_BPRI# 2 Y9 NC30
H_D#37 N5 G8 H_BREQ# 2 J19
H_D#38 H_D#_37 H_BREQ0# C405 R324 NC31
N2 H_D#_38 H_CPURST# B10 H_CPURST# 2 H19 NC32
R335 R316 H_D#39 R5 E1 0.1u10X4 200R1%4 G19
100R1%4 C408 100R1%4 C395 H_D#40 H_D#_39 H_VREF1 NC33
U7 H_D#_40 F19 NC34
C 0.1u10X4 0.1u10X4 H_D#41 R8 AA6 E19 C
H_D#_41 HCLKN CLK_MCH_BCLK# 16 NC35
H_D#42 T4 AA5 D19
H_D#_42 HCLKP CLK_MCH_BCLK 16 NC36
H_D#43 T7 C10 H_DBSY# H_DBSY# 2 C19
H_D#44 H_D#_43 H_DBSY# H_DEFER# NC37
R3 H_D#_44 H_DEFER# C6 H_DEFER# 2 B19 NC38
H_D#45 T5 H5 H_DINV#0 H_DINV#0 2 A19 Y25
H_D#46 H_D#_45 H_DINV#_0 H_DINV#1 NC39 RESERVED26
V6 H_D#_46 H_DINV#_1 J6 H_DINV#1 2 Y8 NC40 RESERVED27 Y24
H_D#47 V3 T9 H_DINV#2 H_DINV#2 2 G16 AB22
H_D#48 H_D#_47 H_DINV#_2 H_DINV#3 NC41 RESERVED28
W2 H_D#_48 H_DINV#_3 U6 H_DINV#3 2 F16 NC42 RESERVED29 AB21
H_D#49 W1 G7 H_DPWR# H_DPWR# 2 E16 AB19
H_D#50 H_D#_49 H_DPWR# H_DRDY# NC43 RESERVED30
V2 H_D#_50 H_DRDY# E6 H_DRDY# 2 D16 NC44 RESERVED31 AB16
H_D#51 W4 F3 H_DSTBN#0 H_DSTBN#0 2 C16 AB14
H_D#52 H_D#_51 H_DSTBN#_0 H_DSTBN#1 NC45 RESERVED32
W7 H_D#_52 H_DSTBN#_1 M8 H_DSTBN#1 2 B16 NC46 RESERVED33 AA12
H_D#53 W5 T1 H_DSTBN#2 H_DSTBN#2 2 AN2 W24
H_D#54 H_D#_53 H_DSTBN#_2 H_DSTBN#3 NC47 RESERVED34
V5 H_D#_54 H_DSTBN#_3 AA3 H_DSTBN#3 2 A16 NC48 RESERVED35 AA24
H_D#55 AB4 F4 H_DSTBP#0 H_DSTBP#0 2 Y7 AB24
H_D#56 H_D#_55 H_DSTBP#_0 H_DSTBP#1 NC49 RESERVED36
AB8 H_D#_56 H_DSTBP#_1 M7 H_DSTBP#1 2 AM4 NC50 RESERVED37 AB20
H_D#57 W8 T2 H_DSTBP#2 H_DSTBP#2 2 AF4 AB18
H_D#58 H_D#_57 H_DSTBP#_2 H_DSTBP#3 NC51 RESERVED38
AA9 H_D#_58 H_DSTBP#_3 AB3 H_DSTBP#3 2 AD4 NC52 RESERVED39 AB15
H_D#59 AA8 AL4 AB13
VTT VTT H_D#60 H_D#_59 NC53 RESERVED40
AB1 H_D#_60 AK4 NC54 RESERVED41 AB12
Trace wide/spacing=10/20 H_D#61 AB7 W31 AB17
H_D#62 H_D#_61 NC55 RESERVED42
AA2 H_D#_62 H_HIT# C8 H_HIT# 2 AJ4 NC56
H_D#63 AB5 B4 H_HITM# 2 AH4
R312 R328 H_D#_63 H_HITM# NC57
H_LOCK# C5 H_LOCK# 2 H_REQ#[4:0] 2 AG4 NC58
54.9R1%4 54.9R1%4 G9 H_REQ#0 AE4
HXRCOMP HYRCOMP H_REQ#_0 H_REQ#1 NC59
H_REQ#_1 E9 AM1 NC60
HXRCOMP A10 G12 H_REQ#2
HXSCOMP H_XRCOMP H_REQ#_2 H_REQ#3
A6 H_XSCOMP H_REQ#_3 B8
R329 R313 HXSWING C15 F12 H_REQ#4 H_RS#[2:0] 2
HYRCOMP H_XSWING H_REQ#_4 H_RS#0
24.9R1%4 24.9R1%4 J1 H_YRCOMP H_RS#_0 A5
HYSCOMP K1 B6 H_RS#1
B HYSWING H_YSCOMP H_RS#_1 H_RS#2 945GSE B
H1 H_YSWING H_RS#_2 G10
E8 CPUSLP# CPUSLP# 2
H_SLPCPU#
H_TRDY# E10 H_TRDY# 2
T6

945GSE

A A

MICRO-STAR INT'L CO.,LTD

MSI
MS-N011
Size Document Description Rev
Custom 1.0
945GMS_HOST
Date: Friday, April 11, 2008 Sheet 4 of 39

5 4 3 2 1
5 4 3 2 1

U26B
VGA_B +1_5VRUN_PCIE
DMI_TXN0 Y29 C18 MCH_BSEL0 16 VGA_G U26F
13 DMI_TXN0 DMI_RXN_0 CFG_0
DMI_TXN1 Y32 E18 MCH_BSEL1 16 VGA_R
13 DMI_TXN1 DMI_RXN_1 CFG_1
DMI_TXP0 Y28 G20 MCH_BSEL2 H27 R28 R122 24.9R1%4
13 DMI_TXP0 DMI_RXP_0 CFG_2 SDVO_CTRLDATA EXP_A_COMPI
DMI_TXP1 Y31 G18 R332 R331 R330 J27 M28
13 DMI_TXP1 DMI_RXP_1 CFG_3 SDVO_CTRLCLK EXP_A_ICOMPO
J20 CFG_5 16 CLK_PCIE_3GPLL# Y26

DMI
CFG_5 G_CLKN

150R1%4

150R1%4

150R1%4
DMI_RXN0 V28 J18 16 CLK_PCIE_3GPLL AA26 N30

MISC
13 DMI_RXN0 DMI_TXN_0 CFG_6 G_CLKP SDVO_TVCLKIN#
13 DMI_RXN1 DMI_RXN1 V31 R142 R30 Layout within 500mil
D
DMI_RXP0 DMI_TXN_1 SDVO_INT# D
13 DMI_RXP0 V29 DMI_TXP_0 1K/4 SDVO_FLDSTALL# T29 of GMCH pin out.
13 DMI_RXP1 DMI_RXP1 V32 R138 R141
DMI_TXP_1 R136 2.2K/4 X_2.2K/4
X_2.2K/4 21 VGA_CLK H20 CRT_DDC_CLK SDVO_TVCLKIN M30
21 VGA_DATA H22 CRT_DDC_DATA SDVO_INT P30
AF33 K32 VGA_B A24 T30
9,10 CLK_SDRAM0 SM_CK_0 RESERVED1 21 VGA_B CRT_BLUE SDVO_FLDSTALL
9,10 CLK_SDRAM1 AG1 SM_CK_1 RESERVED2 K31 SXGA+ 1400x1050 A23 CRT_BLUE#
C17 LOW=DMIX2 VGA_G E25
AJ1
RESERVED7
F18
60Hz 21 VGA_G
F25
CRT_GREEN

SDVO
8 CLK_SDRAM2 SM_CK_2 RESERVED8 CRT_GREEN#
AM30 A3 VGA_R C25
8 CLK_SDRAM3 SM_CK_3 RESERVED9 21 VGA_R CRT_RED

VGA
D25 CRT_RED#
AG33 R153 39R/4 F27
9,10 CLK_SDRAM-0 SM_CK#_0 21 VGA_VSYNC CRT_VSYNC
AF1 R152 39R/4 D27

CFG/RSVD
DDR2 MUXING
9,10 CLK_SDRAM-1 SM_CK#_1 21 VGA_HSYNC CRT_HSYNC
H25 CRT_IREF SDVO_RED# P28
8 CLK_SDRAM-2 AK1 SM_CK#_2 SDVO_GREEN# N32
AN30 +3VRUN T31 H30 P32
8 CLK_SDRAM-3 SM_CK#_3 L_BKLTCTL SDVO_BLUE#
R145 G29 T32
21 LVDS_BLON L_BKLTEN SDVO_CLKN
9,11 CKE0 AN21 SM_CKE_0 255R1%4 F28 L_CLKCTLA
10,11 CKE1 AN22 SM_CKE_1 E28 L_CTLBDATA
8,11 CKE2 AF26 SM_CKE_2 21 LVDS_CLK G28 L_DDC_CLK SDVO_RED N28
AF25 PM_EXTTS#0 R146 10K/4 H28 M32
8,11 CKE3 SM_CKE_3 21 LVDS_DATA L_DDC_DATA SDVO_GREEN
21 LVDS_VDDEN K30 L_VDDEN SDVO_BLUE P33
9,11 SM_CS-0 AG14 SM_CS#_0 K27 L_IBG SDVO_CLKP R32
10,11 SM_CS-1 AF12 SM_CS#_1
PM_EXTTS#0: memory thermal throttling J29 L_VBG
8,11 SM_CS-2 AK14 SM_CS#_2 J30 L_VREFH
AH12 R311 K29
8,11 SM_CS-3 SM_CS#_3 L_VREFL
1.5K1%4 +1_5VRUN
T4 AJ21 SM_OCDCOMP_0 21 LVDS_TXCKN D30 LA_CLKN TV_DACA A21
T5 AF11 SM_OCDCOMP_1 PM_ICHSYNC# E31 MCH_ICH_SYNC# 13 21 LVDS_TXCKP C30 LA_CLKP TV_DACB C20
C G21 A30 E20 C

LVDS
PM_BMBUSY# PM_BMBUSY# 14 LB_CLKN TV_DACC
AE12 F26 A29 G23

TV
9,11 SM_ODT0 SM_ODT_0 PM_EXTTS#_0 PM_EXTTS#0 8 LB_CLKP TV_IREF
10,11 SM_ODT1 AF14 SM_ODT_1 PM_EXTTS#_1 H26 PM_DPRSLPVR 14,30 TV_IRTNA B21 Disable TV
8,11 SM_ODT2 AJ14 SM_ODT_2 THRMTRIP# J15 THERMTRIP_GMCH# 12 21 LVDS_TX0N G31 LA_DATAN_0 TV_IRTNB C21
+1_8VDIMM AJ12 AB29 F32 D21
8,11 SM_ODT3 SM_ODT_3 PWROK CHIP_PWRGD 14,17,19 21 LVDS_TX1N LA_DATAN_1 TV_IRTNC
W27 D31
R306 80.6R1%4 M_RCOMPN AN12
SM_RCOMPN
PM RSTIN# NB_RST# 13
800x480 21 LVDS_TX2N LA_DATAN_2
R305 80.6R1%4 M_RCOMPP AN14
AA33
SM_RCOMPP CLK 21 LVDS_TX0P H31
G32
LA_DATAP_0
G26
SM_VREF_0 21 LVDS_TX1P LA_DATAP_1 TV_DCONSEL0
SM_VREF AE1 SM_VREF_1 D_REFCLKN A27 CLK_DOT96# 16 21 LVDS_TX2P C31 LA_DATAP_2 TV_DCONSEL1 J26
D_REFCLKP A26 CLK_DOT96 16
D_REFSSCLKN J33 CLK_GFX_REFCLKN 16 F33 LB_DATAN_0
+1_8VDIMM H33 CLK_GFX_REFCLKP 16 D33
D_REFSSCLKP LB_DATAN_1
CLKREQ# J22 MCH_CLKREQ# 16 F30 LB_DATAN_2
E33 LB_DATAP_0
R308 SM_VREF D32
10K1%4 LB_DATAP_1
F29 LB_DATAP_2

945GSE CLKREQ#: Driven by GMCH to control the PCIe clock


R309
to External Graphics and the DMI clock. 945GSE
10K1%4 C384
0.1u10X4
+3VRUN

as close as
945GM
B B
MCH_CLKREQ# R149 10K/4

DPRSLPVR: Enable power savings by speeding up the C4 exit latency.

+3VRUN

PM_DPRSLPVR R148 X_10K/4

un-stuffed, if support C4E feature.

A A

MICRO-STAR INT'L CO.,LTD

MSI
MS-N011
Size Document Description Rev
Custom 1.0
945GMS_DMI/ VGA
Date: Friday, April 11, 2008 Sheet 5 of 39

5 4 3 2 1
5 4 3 2 1

+1_5VRUN
VTT U26H
8,9 SA_MD[0..63] T25 VCC_NCTF1 VCCAUX_NCTF1 AD25
U26C R25 AC25
SA_BS-[0..2] 9,10,11 VCC_NCTF2 VCCAUX_NCTF2
SA_MD0 AC31 AK12 SA_BS-0 P25 AB25
SA_MD1 SA_DQ_0 SA_BS_0 SA_BS-1 VCC_NCTF3 VCCAUX_NCTF3
AB28 SA_DQ_1 SA_BS_1 AH11 N25 VCC_NCTF4 VCCAUX_NCTF4 AD24
SA_MD2 AE33 AG17 SA_BS-2 M25 AC24
SA_MD3 SA_DQ_2 SA_BS_2 VCC_NCTF5 VCCAUX_NCTF5
AF32 SA_DQ_3 SA_DM[0..7] 8,9 P24 VCC_NCTF6 VCCAUX_NCTF6 AD22
SA_MD4 AC33 AB30 SA_DM0 N24 AD21
SA_MD5 SA_DQ_4 SA_DM_0 SA_DM1 VCC_NCTF7 VCCAUX_NCTF7
AB32 SA_DQ_5 SA_DM_1 AL31 M24 VCC_NCTF8 VCCAUX_NCTF8 AD20
SA_MD6 AB31 AF30 SA_DM2 Y22 AD19
SA_MD7 SA_DQ_6 SA_DM_2 SA_DM3 VCC_NCTF9 VCCAUX_NCTF9
AE31 SA_DQ_7 SA_DM_3 AK26 W22 VCC_NCTF10 VCCAUX_NCTF10 AD18
D SA_MD8 AH31 AL9 SA_DM4 V22 AD17 D
SA_MD9 SA_DQ_8 SA_DM_4 SA_DM5 VCC_NCTF11 VCCAUX_NCTF11
AK31 SA_DQ_9 SA_DM_5 AG7 U22 VCC_NCTF12 VCCAUX_NCTF12 AD16
SA_MD10 AL28 AK5 SA_DM6 T22 AD15
SA_MD11 SA_DQ_10 SA_DM_6 SA_DM7 VCC_NCTF13 VCCAUX_NCTF13
AK27 SA_DQ_11 SA_DM_7 AH3 R22 VCC_NCTF14 VCCAUX_NCTF14 AD14
SA_MD12 AH30 P22 K14
SA_DQ_12 SA_DQS[0..7] 8,9 VCC_NCTF15 VCCAUX_NCTF15
SA_MD13 AL32 AC28 SA_DQS0 N22 AD13
SA_MD14 SA_DQ_13 SA_DQS_0 SA_DQS1 VCC_NCTF16 VCCAUX_NCTF16
AJ28 SA_DQ_14 SA_DQS_1 AJ30 M22 VCC_NCTF17 VCCAUX_NCTF17 Y13
SA_MD15 AJ27 AK33 SA_DQS2 Y21 W13
SA_MD16 SA_DQ_15 SA_DQS_2 SA_DQS3 VCC_NCTF18 VCCAUX_NCTF18
AH32 SA_DQ_16 SA_DQS_3 AL25 W21 VCC_NCTF19 VCCAUX_NCTF19 V13
SA_MD17 AF31 AN9 SA_DQS4 V21 U13
SA_MD18 SA_DQ_17 SA_DQS_4 SA_DQS5 VCC_NCTF20 VCCAUX_NCTF20
AH27 SA_DQ_18 SA_DQS_5 AH8 U21 VCC_NCTF21 VCCAUX_NCTF21 T13
SA_MD19 AF28 AM2 SA_DQS6 T21 R13
SA_MD20 SA_DQ_19 SA_DQS_6 SA_DQS7 VCC_NCTF22 VCCAUX_NCTF22
AJ32 SA_DQ_20 SA_DQS_7 AE3 R21 VCC_NCTF23 VCCAUX_NCTF23 P13
SA_MD21 AG31 P21 N13
SA_DQ_21 SA_DQS-[0..7] 8,9 VCC_NCTF24 VCCAUX_NCTF24
SA_MD22 AG28 AC29 SA_DQS-0 N21 M13
SA_MD23 SA_DQ_22 SA_DQS#_0 SA_DQS-1 VCC_NCTF25 VCCAUX_NCTF25
AG27 SA_DQ_23 SA_DQS#_1 AK30 M21 VCC_NCTF26 VCCAUX_NCTF26 AD12
SA_MD24 AN27 AJ33 SA_DQS-2 Y20 Y12
SA_DQ_24 SA_DQS#_2 VCC_NCTF27 VCCAUX_NCTF27

DDR2 SYSTEM MEMORY


SA_MD25 AM26 AM25 SA_DQS-3 W20 W12
SA_MD26 SA_DQ_25 SA_DQS#_3 SA_DQS-4 VCC_NCTF28 VCCAUX_NCTF28
AJ26 SA_DQ_26 SA_DQS#_4 AN8 V20 VCC_NCTF29 VCCAUX_NCTF29 V12
SA_MD27 AJ25 AJ8 SA_DQS-5 U20 U12
SA_MD28 SA_DQ_27 SA_DQS#_5 SA_DQS-6 VCC_NCTF30 VCCAUX_NCTF30
AL27 SA_DQ_28 SA_DQS#_6 AM3 T20 VCC_NCTF31 VCCAUX_NCTF31 T12
SA_MD29 AN26 AE2 SA_DQS-7 R20 R12
SA_MD30 SA_DQ_29 SA_DQS#_7 VCC_NCTF32 VCCAUX_NCTF32
AH25 SA_DQ_30 SA_MA[0..13] 9,10,11 P20 VCC_NCTF33 VCCAUX_NCTF33 P12
SA_MD31 AG26 AJ15 SA_MA0 N20 N12
SA_MD32 SA_DQ_31 SA_MA_0 SA_MA1 VCC_NCTF34 VCCAUX_NCTF34
AM12 SA_DQ_32 SA_MA_1 AM17 M20 VCC_NCTF35 VCCAUX_NCTF35 M12
SA_MD33 AL11 AM15 SA_MA2 Y19 AD11
SA_MD34 SA_DQ_33 SA_MA_2 SA_MA3 VCC_NCTF36 VCCAUX_NCTF36
AH9 SA_DQ_34 SA_MA_3 AH15 P19 VCC_NCTF37 VCCAUX_NCTF37 AD10
SA_MD35 AK9 AK15 SA_MA4 N19 K10
SA_MD36 SA_DQ_35 SA_MA_4 SA_MA5 VCC_NCTF38 VCCAUX_NCTF38
AM11 SA_DQ_36 SA_MA_5 AN15 M19 VCC_NCTF39 VSS_NCTF1 AN33
SA_MD37 AK11 AJ18 SA_MA6 Y18 AA25
SA_MD38 SA_DQ_37 SA_MA_6 SA_MA7 VCC_NCTF40 VSS_NCTF2
AM8 AF19 P18 V25
C SA_MD39
SA_MD40
SA_MD41
AK8
AG9
AF9
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_MA_7
SA_MA_8
SA_MA_9
AN17
AL17
AG16
SA_MA8
SA_MA9
SA_MA10
N18
M18
Y17
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
NCTF VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
U25
AA22
AA21
C

SA_MD42 SA_DQ_41 SA_MA_10 SA_MA11 VCC_NCTF44 VSS_NCTF6


AF8 SA_DQ_42 SA_MA_11 AL18 P17 VCC_NCTF45 VSS_NCTF7 AA20
SA_MD43 AK6 AG18 SA_MA12 N17 AA19
SA_MD44 SA_DQ_43 SA_MA_12 SA_MA13 VCC_NCTF46 VSS_NCTF8
AF7 SA_DQ_44 SA_MA_13 AL14 M17 VCC_NCTF47 VSS_NCTF9 AA18
SA_MD45 AG11 Y16 AA17
SA_MD46 SA_DQ_45 SA_CAS- VCC_NCTF48 VSS_NCTF10
AJ6 SA_DQ_46 SA_CAS# AJ17 SA_CAS- 9,10,11 P16 VCC_NCTF49 VSS_NCTF11 AA16
SA_MD47 AH6 AK18 SA_RAS- N16 AA15
SA_DQ_47 SA_RAS# SA_RAS- 9,10,11 VCC_NCTF50 VSS_NCTF12
SA_MD48 AN6 AN28 SA_RCVENIN- T2 M16 AA14
SA_MD49 SA_DQ_48 SA_RCVENIN# SA_RCVENOUT- VCC_NCTF51 VSS_NCTF13
AM6 SA_DQ_49 SA_RCVENOUT# AM28 T3 Y15 VCC_NCTF52 VSS_NCTF14 AA13
SA_MD50 AK3 AH17 SA_WE- P15 A4
SA_DQ_50 SA_WE# SA_WE- 9,10,11 SB_BS-[0..2] 8,11 VCC_NCTF53 VSS_NCTF15
SA_MD51 AL2 N15 A33
SA_MD52 SA_DQ_51 SB_BS-0 VCC_NCTF54 VSS_NCTF16
AM5 SA_DQ_52 SB_BS_0 AH21 M15 VCC_NCTF55 VSS_NCTF17 B2
SA_MD53 AL5 AJ20 SB_BS-1 Y14 AN1
SA_MD54 SA_DQ_53 SB_BS_1 SB_BS-2 VCC_NCTF56 VSS_NCTF18
AJ3 SA_DQ_54 SB_BS_2 AE27 W14 VCC_NCTF57 VSS_NCTF19 C1
SA_MD55 AJ2 V14
SA_DQ_55 SB_MA[0..13] 8,11 VCC_NCTF58
SA_MD56 AG2 AN20 SB_MA0 U14 K28
SA_MD57 SA_DQ_56 SB_MA_0 SB_MA1 VCC_NCTF59 CFG_19
AF3 SA_DQ_57 SB_MA_1 AL21 T14 VCC_NCTF60
SA_MD58 AE7 AK21 SB_MA2 R14 K25 CFG_19: DMI Lane Reversal
SA_MD59 SA_DQ_58 SB_MA_2 SB_MA3 VCC_NCTF61 RESERVED10
AF6 SA_DQ_59 SB_MA_3 AK22 P14 VCC_NCTF62 RESERVED11 K26 0= default (internal pull-down)
SA_MD60 AH5 AL22 SB_MA4 N14 R24
SA_MD61 SA_DQ_60 SB_MA_4 SB_MA5 VCC_NCTF63 RESERVED12 1= Reversal Lanes
AG3 SA_DQ_61 SB_MA_5 AH22 M14 VCC_NCTF64 RESERVED13 T24
SA_MD62 AG5 SA_DQ_62 SB_MA_6 AG22 SB_MA6
VTT RESERVED14 K21 (945GMS does not support)
SA_MD63 AF5 AF21 SB_MA7 T10 K19
SA_DQ_63 SB_MA_7 SB_MA8 VTT_NCTF1 RESERVED15
SB_MA_8 AM21 R10 VTT_NCTF2 RESERVED16 K20
AE21 SB_MA9 P10 K24
SB_CAS- SB_MA_9 SB_MA10 VTT_NCTF3 RESERVED17
8,11 SB_CAS- AG19 SB_CAS# SB_MA_10 AL20 N10 VTT_NCTF4 RESERVED18 K22
SB_RAS- AG21 AE22 SB_MA11 L10 J17
8,11 SB_RAS- SB_RAS# SB_MA_11 VTT_NCTF5 RESERVED19
SB_WE- AG20 AE26 SB_MA12 D1 K23
8,11 SB_WE- SB_WE# SB_MA_12 VTT_NCTF6 RESERVED20
AE20 SB_MA13 K17
B SB_MA_13 RESERVED21 B
M10 RSVD_3 RESERVED22 K12
A18 RSVD_4 RESERVED23 K13
AB10 RSVD_5 RESERVED24 K16
945GSE AA10 K15
RSVD_6 RESERVED25
945GSE
AM18

AM20

AM22

AM27

AM31
AG25

AG30

AG32
AH16

AH18

AH20

AN25

AH26

AH28

AC30

AC32

AH33
AK17

AK20

AE25

AK25

AA27
AB27

AA28
AE28

AK28

AA29

AA30

AE30

AA31

AA32

AE32

AK32
AF18

AF20

AF22

AF27
AL26

AL30
AJ22

AJ31
W19

W26

M27

M29

M31
G22

G25

G27

G30

G33
U16

D18
H18
U18

R19

D20

H21

H23

U26

C27

N27

R27

U27

D28

U28

H29

N29

R29
U29

U30

N31

R31

U31

C32

H32
U32

R33
B17

V17

E22

B23

A25

B27

E27

P27

Y27

B29
E29

P29

B30
E30

V30
Y30

P31

E32

V33
Y33
F17
T17

F21

F23

T27

T28

F31

T31
J21

J25

J28

J31
U26E
VSS_110
VSS_109
VSS_108
VSS_107
VSS_106
VSS_105
VSS_104
VSS_103
VSS_102
VSS_101
VSS_100
VSS_99
VSS_98
VSS_97
VSS_96
VSS_95
VSS_94
VSS_93
VSS_92
VSS_91
VSS_90
VSS_89
VSS_88
VSS_87
VSS_86
VSS_85
VSS_84
VSS_83
VSS_82
VSS_81
VSS_80
VSS_79
VSS_78
VSS_77
VSS_76
VSS_75
VSS_74
VSS_73
VSS_72
VSS_71
VSS_70
VSS_69
VSS_68
VSS_67
VSS_66
VSS_65
VSS_64
VSS_63
VSS_62
VSS_61
VSS_60
VSS_59
VSS_58
VSS_57
VSS_56
VSS_55
VSS_54
VSS_53
VSS_52
VSS_51
VSS_50
VSS_49
VSS_48
VSS_47
VSS_46
VSS_45
VSS_44
VSS_43
VSS_42
VSS_41
VSS_40
VSS_39
VSS_38
VSS_37
VSS_36
VSS_35
VSS_34
VSS_33
VSS_32
VSS_31
VSS_30
VSS_29
VSS_28
VSS_27
VSS_26
VSS_25
VSS_24
VSS_23
VSS_22
VSS_21
VSS_20
VSS_19
VSS_18
VSS_17
VSS_16
VSS_15
VSS_14
VSS_13
VSS_12
VSS_11
VSS_10
VSS_9
VSS_8
VSS_7
VSS_6
VSS_5
VSS_4
VSS_3
VSS_2
VSS_1
945GSE

VSS
VSS_185
VSS_184
VSS_183
VSS_182
VSS_181
VSS_180
VSS_179
VSS_178
VSS_177
VSS_176
VSS_175
VSS_174
VSS_173
VSS_172
VSS_171
VSS_170
VSS_169
VSS_168
VSS_167
VSS_166
VSS_165
VSS_164
VSS_163
VSS_162
VSS_161
VSS_160
VSS_159
VSS_158
VSS_157
VSS_156
VSS_155
VSS_154
VSS_153
VSS_152
VSS_151
VSS_150
VSS_149
VSS_148
VSS_147
VSS_146
VSS_145
VSS_144
VSS_143
VSS_142
VSS_141
VSS_140
VSS_139
VSS_138
VSS_137
VSS_136
VSS_135
VSS_134
VSS_133
VSS_132
VSS_131
VSS_130
VSS_129
VSS_128
VSS_127
VSS_126
VSS_125
VSS_124
VSS_123
VSS_122
VSS_121
VSS_120
VSS_119
VSS_118
VSS_117
VSS_116
VSS_115
VSS_114
VSS_113
VSS_112
VSS_111
A A
R1
V1
F2
H2
K2
M2
AB2
AF2
AH2
AK2
B3
T3
W3
AD3
AL3
E4
H4
K4
N4
R4
V4
AA4
B5
AJ5
AN5
K6
M6
T6
W6
AB6
AE6
AG6
AL6
B7
E7
H7
N7
R7
V7
AA7
U8
AE8
AG8
AL8
A9
C9
F9
J9
M9
R9
W9
AB9
AJ9
AM9
AE11
AJ11
AN11
B12
H12
AG12
AL12
D13
F13
B14
H14
AE14
AH14

D15
F15
R15
W15
AM14

AG15
AL15
J16
MICRO-STAR INT'L CO.,LTD

MSI
MS-N011
Size Document Description Rev
Custom 1.0
945GMS_DDR
Date: Friday, April 11, 2008 Sheet 6 of 39

5 4 3 2 1
5 4 3 2 1

2940mA
U26D
C385 C407 C406 C388 C100 T26 B20 +1_5VRUN
VTT VCC0 VCCATVDACA0
R26 VCC1 VCCATVDACA1 A20

4.7u6.3X8

4.7u6.3X8

X_0.1u10X4

X_0.1u10X4

0.1u10X4
+
P26 B22
945 GMS Power EC16
C220u6.3-RH
N26
M26
VCC2
VCC3
VCCATVDACB0
VCCATVDACB1 A22
D22
Disable TV

2
VCC4 VCCATVDACC0
VTT=> 3.72A V19
U19
VCC5
VCC6
VCCATVDACC1
VCCATVBG
C22
D23 120mA +1_5VRUN
T19 VCC7 VSSATVBG E23
D
+1_5VRUN=> 1.98A W18
V18
VCC8
VCC9
VCCDTVDAC
VCCDQTVDAC
F20
F22 C134 C136 20mA
D

T18 C28 0.1u10X4 X_10u10Y8


+1_8VDIMM=> 1.72A R18
W17
VCC10
VCC11
VCCDLVDS0
VCCDLVDS1 B28
A28
VCC12 VCCDLVDS2
+2_5VRUN=>142mA U17
R17
W16
VCC13
VCC14
VCCHV0
VCCHV1
E26
D26
C26
+3VRUN

VCC15 VCCHV2 C418


+3VRUN=> 40mA V16
T16
VCC16
VCC17
VCCSM0
VCCSM1
AB33
AM32
C124
0.1u10X4 10u10Y8 40mA
R16 VCC18 VCCSM2 AN29
V15 AM29 C383
VCC19 VCCSM3 C377
U15 VCC20 VCCSM4 AL29 1u6.3Y4
T15 VCC21 VCCSM5 AK29 1u6.3Y4
VCCSM6 AJ29
+1_5VRUN AD33 VCCAUX1 VCCSM7 AH29
AD32 VCCAUX2 VCCSM8 AG29
+1_5VRUN AD31 AF29
C381 VCCAUX3 VCCSM9
1250mA AD30 VCCAUX4 VCCSM10 AE29
DDR2 DLL X_0.1u10X4 AD29 VCCAUX5 VCCSM11 AN24
L26 AD28 AM24
+1_5VRUN_DPLLA DDR2 VCCAUX6 VCCSM12
AD27 VCCAUX7 VCCSM13 AL24 1720mA
X_120L600mA-250 50mA FSB HSIO AC27 AK24
AD26
VCCAUX8 VCCSM14
AJ24
DDR2 One Channel
VCCAUX9 VCCSM15
AC26 VCCAUX10 VCCSM16 AH24
X_10u25X12
C256

AB26 VCCAUX11 VCCSM17 AG24 +1_8VDIMM


C412 AE19 AF24
VCCAUX12 VCCSM18

+1
CP21 0.1u10X4 AE18 AE24
X_COPPER VCCAUX13 VCCSM19 C379 C376 C375 EC8
AF17 VCCAUX14 VCCSM20 AN18
AE17 AN16 1u6.3Y4 2.2u6.3Y6 2.2u6.3Y6 C220u6.3-RH

2
L25 +1_5VRUN_DPLLB VCCAUX15 VCCSM21
AF16 AM16

POWER
X_120L600mA-250 VCCAUX16 VCCSM22 C378
C 50mA AE16 VCCAUX17 VCCSM23 AL16 C
AF15 VCCAUX18 VCCSM24 AK16 1u6.3Y4
AE15 VCCAUX19 VCCSM25 AJ16
+1

J14 VCCAUX20 VCCSM26 AN13 Place in cavity


EC10 C393 J10 AM13
CP20 X_C100U6.3PT VCCAUX21 VCCSM27
0.1u10X4 H10 AL13
2

X_COPPER VCCAUX22 VCCSM28


AE9 VCCAUX23 VCCSM29 AK13
AD9 VCCAUX24 VCCSM30 AJ13
L3 +1_5VRUN_HPLL U9 AH13
X_120L600mA-250 VCCAUX25 VCCSM31
45mA AD8 VCCAUX26 VCCSM32 AG13
AD7 VCCAUX27 VCCSM33 AF13
AD6 VCCAUX28 VCCSM34 AE13
780mA VCCSM35 AN4
C97 C95 C413 0.47u10X6 A14 AM10
CP6 VTT0 VCCSM36
X_22u6.3X8 0.1u10X4 VTT D10 VTT1 VCCSM37 AL10
X_COPPER P9 AK10 C380
VTT2 VCCSM38
L9 VTT3 VCCSM39 AH1 1u6.3Y4
L2 +1_5VRUN_MPLL C109 C104 D9 AH10
X_120L600mA-250 VTT4 VCCSM40
45mA X_4.7u6.3X8 4.7u6.3X8 P8 VTT5 VCCSM41 AG10
L8 AF10 C86
VTT6 VCCSM42
D8 VTT7 VCCSM43 AE10 1u6.3Y4
P7 VTT8 VCCSM44 AN7
C88 C89 L7 AM7
CP5 VTT9 VCCSM45
X_22u6.3X8 0.1u10X4 Place in cavity D7 VTT10 VCCSM46 AL7 60mA
X_COPPER A7 AK7 +2_5VRUN
VTT11 VCCSM47
P6 VTT12 VCCSM48 AJ7
L6 VTT13 VCCSM49 AH7
C409 G6 AN10 C123 C129
VTT14 VCCSM50
Place close to 945GMS 0.47u10X6 D6 VTT15 VCCSM51 AJ10 X_0.1u10X4 4.7u6.3X8
U5 VTT16 VCCAMPLL AD1 +1_5VRUN_MPLL
P5 VTT17 VCCAHPLL AD2 +1_5VRUN_HPLL
B B
L5 VTT18 VCCADPLLA B26 +1_5VRUN_DPLLA
X_COPPER G5 J32
CP19 VTT19 VCCADPLLB +1_5VRUN_DPLLB
+1_5VRUN D5 AE5 +1_5VRUN +1_5VRUN_3GPLL
+1_5VRUN_PCIE VTT20 VCCDHMPLL1
Y4 VTT21 VCCDHMPLL2 AD5
U4 VTT22 VCCTXLVDS0 D29
L22 P4 C29 C110 C112
X_91n1.5A_1210 VTT23 VCCTXLVDS1
400mA L4 VTT24 VCC3G0 U33 +1_5VRUN_PCIE 0.1u10X4 X_4.7u6.3X8
G4 VTT25 VCC3G1 T33
C387 C386 D4 V26
CP18 VTT26 VCCA3GPLL
10u6.3X8 X_4.7u6.3X8 Y3 VTT27 VCCA3GBG N33 +2_5VRUN
X_COPPER U3 M33
VTT28 VSSA3GBG
P3 VTT29 VCCSYNC J23 +2_5VRUN 2mA
L4 L3 C24
VTT30 VCCACRTDAC0 C390
+1_5VRUN_3GPLL G3 VTT31 VCCACRTDAC1 B24
1u500mA_0805 D3 B25 C389 C122 0.1u10X4
VTT32 VSSACRTDAC X_10u10Y8
Y2 VTT33 VCCALVDS B31 X_0.1u10X4
U2 VTT34 VSSALVDS B32
P2 VTT36
L2 VTT35 VTT41 P1 VTT +2_5VRUN_CRT
G2 VTT37 VTT42 L1
D2 VTT38 VTT43 G1
AA1 U1 C132 C137
VTT39 VTT44 0.022u16X4
F1 VTT40 VTT45 Y1 0.1u10X4

+2_5VRUN C99 C400 945GSE


L7 70mA 0.47u10X6 0.47u10X6 10mA
D26 R157 X_100L3A-30-RH +2_5VRUN
VTT +2_5VRUN_CRT

A
S-RB551V-30_SOD323 10R/4 C399 C404 A
C135 X_0.01u16X4 X_0.1u10X4
CP14 10u6.3X8
X_COPPER

MICRO-STAR INT'L CO.,LTD

MSI
MS-N011
Size Document Description Rev
Custom 1.0
945GMS_POWER
Date: Friday, April 11, 2008 Sheet 7 of 39

5 4 3 2 1
5 4 3 2 1

DIMM1A

SA_MD0 5 102 SB_MA0 SA_MD[0..63]


DQ0 A0 SA_MD[0..63] 6,9
SA_MD1 7 101 SB_MA1
SA_MD2 DQ1 A1 SB_MA2 SA_DM[0..7]
17 DQ2 A2 100 SA_DM[0..7] 6,9
SA_MD3 19 99 SB_MA3
SA_MD4 DQ3 A3 SB_MA4 SA_DQS[0..7] +1_8VDIMM
4 DQ4 A4 98 SA_DQS[0..7] 6,9
SA_MD5 6 97 SB_MA5
SA_MD6 DQ5 A5 SB_MA6 SA_DQS-[0..7] DIMM1B
14 DQ6 A6 94 SA_DQS-[0..7] 6,9
D SA_MD7 SB_MA7 D
16 DQ7 A7 92 112 VDD1 VSS16 18
SA_MD8 23 93 SB_MA8 SB_MA[0..13] 111 24
DQ8 A8 SB_MA[0..13] 6,11 VDD2 VSS17
SA_MD9 25 91 SB_MA9 117 41
SA_MD10 DQ9 A9 SB_MA10 SB_BS-[0..2] VDD3 VSS18
35 DQ10 A10/AP 105 SB_BS-[0..2] 6,11 96 VDD4 VSS19 53
SA_MD11 37 90 SB_MA11 95 42
SA_MD12 DQ11 A11 SB_MA12 VDD5 VSS20
20 DQ12 A12 89 118 VDD6 VSS21 54
SA_MD13 22 116 SB_MA13 81 59
SA_MD14 DQ13 A13 VDD7 VSS22
36 DQ14 A14 86 82 VDD8 VSS23 65
SA_MD15 38 84 +3VRUN 87 60
SA_MD16 DQ15 A15 SB_BS-2 VDD9 VSS24
43 DQ16 A16_BA2 85 103 VDD10 VSS25 66
SA_MD17 45 88 127
SA_MD18 DQ17 SB_BS-0 VDD11 VSS26
55 DQ18 BA0 107 104 VDD12 VSS27 139
SA_MD19 57 106 SB_BS-1 128
SA_MD20 DQ19 BA1 SM_CS-2 +1_8VDIMM CT35 CT34 VSS28
44 DQ20 S0# 110 SM_CS-2 5,11 199 VDDSPD VSS29 145
SA_MD21 46 115 SM_CS-3 SM_CS-3 5,11 2.2u6.3Y6 0.1u10X4 165
SA_MD22 DQ21 S1# CLK_SDRAM3 VSS30
56 DQ22 CK0 30 CLK_SDRAM3 5 83 NC1 VSS31 171
SA_MD23 58 32 CLK_SDRAM-3 CLK_SDRAM-3 5 120 172
SA_MD24 DQ23 CK0# CLK_SDRAM2 NC2 VSS32
61 DQ24 CK1 164 CLK_SDRAM2 5 5 PM_EXTTS#0 50 NC3 VSS33 177
SA_MD25 63 166 CLK_SDRAM-2 CLK_SDRAM-2 5 CT27 R74 69 187
SA_MD26 DQ25 CK1# CKE2 10K1%4 SODIMM thermal sensor pin NC4 VSS34
73 DQ26 CKE0 79 CKE2 5,11 163 NCTEST VSS35 178
SA_MD27 75 80 CKE3 CKE3 5,11 X_0.01u16X4 SMDDR_VREF 203 190
SA_MD28 DQ27 CKE1 SB_CAS- NC5 VSS36
62 DQ28 CAS# 113 SB_CAS- 6,11 204 NC6 VSS37 9
SA_MD29 64 108 SB_RAS- SB_RAS- 6,11 SMDDR_VREF 1 21
SA_MD30 DQ29 RAS# SB_WE- VREF VSS38
C 74 DQ30 WE# 109 SB_WE- 6,11 VSS39 33 C
SA_MD31 76 198 SA_SA0 R75 201 155
SA_MD32 DQ31 SA0 SA_SA1 CT24 CT25 CT23 GND0 VSS40
123 DQ32 SA1 200 202 GND1 VSS41 34
SA_MD33 125 197 RUN_SMBCLK 10K1%4 2.2u6.3Y6 0.1u10X4 132
DQ33 SCL RUN_SMBCLK 14,16 VSS42
SA_MD34 135 195 RUN_SMBDATA 0.01u16X4 47 144
DQ34 SDA RUN_SMBDATA 14,16 VSS1 VSS43
SA_MD35 137 133 156
SA_MD36 DQ35 SM_ODT2 VSS2 VSS44
124 DQ36 ODT0 114 SM_ODT2 5,11 183 VSS3 VSS45 168
SA_MD37 126 119 SM_ODT3 77 2
DQ37 ODT1 SM_ODT3 5,11 VSS4 VSS46
SA_MD38 134 12 3
SA_MD39 DQ38 SA_DM0 VSS5 VSS47
136 DQ39 DM0 10 48 VSS6 VSS48 15
SA_MD40 141 26 SA_DM1 184 27
SA_MD41 DQ40 DM1 SA_DM2 VSS7 VSS49
143 DQ41 DM2 52 78 VSS8 VSS50 39
SA_MD42 151 67 SA_DM3 71 149
SA_MD43 DQ42 DM3 SA_DM4 VSS9 VSS51
153 DQ43 DM4 130 72 VSS10 VSS52 161
SA_MD44 140 147 SA_DM5 121 28
SA_MD45 DQ44 DM5 SA_DM6 SA_SA1 R284 10K/4 VSS11 VSS53
142 DQ45 DM6 170 122 VSS12 VSS54 40
SA_MD46 152 185 SA_DM7 196 138
SA_MD47 DQ46 DM7 VSS13 VSS55
154 193 150
SA_MD48 157
DQ47
DQ48 DQS0 13 SA_DQS0 ADDRESS: 001 8
VSS14
VSS15
VSS56
VSS57 162
SA_MD49 159 31 SA_DQS1
SA_MD50 173
DQ49
DQ50
DQS1
DQS2 51 SA_DQS2 +3VRUN 0xA2 DIMM-200S_black-1
SA_MD51 175 70 SA_DQS3 SA_SA0 R283 10K/4
SA_MD52 DQ51 DQS3 SA_DQS4
158 DQ52 DQS4 131
SA_MD53 160 148 SA_DQS5
SA_MD54 DQ53 DQS5 SA_DQS6
B 174 DQ54 DQS6 169 B
SA_MD55 176 188 SA_DQS7
SA_MD56 DQ55 DQS7 SA_DQS-0
179 DQ56 DQS#0 11
SA_MD57 181 29 SA_DQS-1
SA_MD58 DQ57 DQS#1 SA_DQS-2
189 DQ58 DQS#2 49
SA_MD59 191 68 SA_DQS-3
SA_MD60 DQ59 DQS#3 SA_DQS-4
180 DQ60 DQS#4 129
SA_MD61 182 146 SA_DQS-5
SA_MD62 DQ61 DQS#5 SA_DQS-6
192 DQ62 DQS#6 167
SA_MD63 194 186 SA_DQS-7 Layout note: Place capacitors between and
DQ63 DQS#7
near DDR connector if possible.
DIMM-200S_black-1 +1_8VDIMM

N13-2000220-A10 CT28 CT29 CT31 CT30


Bottom 0.1u10X4 0.1u10X4 0.1u10X4 0.1u10X4

A +1_8VDIMM A

MICRO-STAR INT'L CO.,LTD


CT41 CT32 CT33 CT42 CT43 MS-N011
2.2u6.3Y6 2.2u6.3Y6 X_2.2u6.3Y6 2.2u6.3Y6 2.2u6.3Y6 MSI
Size Document Description Rev
B 1.0
ONBOARD DDR2 memory
Date: Friday, April 11, 2008 Sheet 8 of 39

5 4 3 2 1
A B C D E

SA_MD[0..63] SA_DQS-[0..7]
6,8 SA_MD[0..63] 6,8 SA_DQS-[0..7]
SA_MA[0..12] M_SA_DQS-[0..7]
6,10,11 SA_MA[0..12] 10 M_SA_DQS-[0..7]
SA_BS-[0..2] M_SA_DQS[0..7]
6,10,11 SA_BS-[0..2] 10 M_SA_DQS[0..7]
SA_DM[0..7] M_SA_MD[0..63] M12-K4T1G05-S02
6,8 SA_DM[0..7] 10 M_SA_MD[0..63]
SA_DQS[0..7] M_SA_DM[0..7]
M12-5PS1G25-H23
6,8 SA_DQS[0..7] 10 M_SA_DM[0..7]

U19 U20 U21 U22


4 SA_BS-0 L2 B9 M_SA_MD10 SA_BS-0 L2 B9 M_SA_MD26 SA_BS-0 L2 B9 M_SA_MD44 SA_BS-0 L2 B9 M_SA_MD61 4
SA_BS-1 BA0 DQ15 M_SA_MD15 SA_BS-1 BA0 DQ15 M_SA_MD31 SA_BS-1 BA0 DQ15 M_SA_MD40 SA_BS-1 BA0 DQ15 M_SA_MD57
L3 BA1 DQ14 B1 L3 BA1 DQ14 B1 L3 BA1 DQ14 B1 L3 BA1 DQ14 B1
SA_BS-2 L1 D9 M_SA_MD8 SA_BS-2 L1 D9 M_SA_MD29 SA_BS-2 L1 D9 M_SA_MD43 SA_BS-2 L1 D9 M_SA_MD58
BA2 DQ13 M_SA_MD9 BA2 DQ13 M_SA_MD28 BA2 DQ13 M_SA_MD42 BA2 DQ13 M_SA_MD59
DQ12 D1 DQ12 D1 DQ12 D1 DQ12 D1
SA_MA12 R2 D3 M_SA_MD12 SA_MA12 R2 D3 M_SA_MD24 SA_MA12 R2 D3 M_SA_MD47 SA_MA12 R2 D3 M_SA_MD62
SA_MA11 A12 DQ11 M_SA_MD13 SA_MA11 A12 DQ11 M_SA_MD25 SA_MA11 A12 DQ11 M_SA_MD46 SA_MA11 A12 DQ11 M_SA_MD63
P7 A11 DQ10 D7 P7 A11 DQ10 D7 P7 A11 DQ10 D7 P7 A11 DQ10 D7
SA_MA10 M2 C2 M_SA_MD14 SA_MA10 M2 C2 M_SA_MD30 SA_MA10 M2 C2 M_SA_MD41 SA_MA10 M2 C2 M_SA_MD56
SA_MA9 A10/AP DQ9 M_SA_MD11 SA_MA9 A10/AP DQ9 M_SA_MD27 SA_MA9 A10/AP DQ9 M_SA_MD45 SA_MA9 A10/AP DQ9 M_SA_MD60
P3 A9 DQ8 C8 P3 A9 DQ8 C8 P3 A9 DQ8 C8 P3 A9 DQ8 C8
SA_MA8 P8 F9 M_SA_MD2 SA_MA8 P8 F9 M_SA_MD19 SA_MA8 P8 F9 M_SA_MD38 SA_MA8 P8 F9 M_SA_MD55
SA_MA7 A8 DQ7 M_SA_MD3 SA_MA7 A8 DQ7 M_SA_MD18 SA_MA7 A8 DQ7 M_SA_MD39 SA_MA7 A8 DQ7 M_SA_MD54
P2 A7 DQ6 F1 P2 A7 DQ6 F1 P2 A7 DQ6 F1 P2 A7 DQ6 F1
SA_MA6 N7 H9 M_SA_MD4 SA_MA6 N7 H9 M_SA_MD16 SA_MA6 N7 H9 M_SA_MD33 SA_MA6 N7 H9 M_SA_MD53
SA_MA5 A6 DQ5 M_SA_MD5 SA_MA5 A6 DQ5 M_SA_MD17 SA_MA5 A6 DQ5 M_SA_MD32 SA_MA5 A6 DQ5 M_SA_MD48
N3 A5 DQ4 H1 N3 A5 DQ4 H1 N3 A5 DQ4 H1 N3 A5 DQ4 H1
SA_MA4 N8 H3 M_SA_MD1 SA_MA4 N8 H3 M_SA_MD20 SA_MA4 N8 H3 M_SA_MD37 SA_MA4 N8 H3 M_SA_MD49
SA_MA3 A4 DQ3 M_SA_MD0 SA_MA3 A4 DQ3 M_SA_MD21 SA_MA3 A4 DQ3 M_SA_MD36 SA_MA3 A4 DQ3 M_SA_MD52
N2 A3 DQ2 H7 N2 A3 DQ2 H7 N2 A3 DQ2 H7 N2 A3 DQ2 H7
SA_MA2 M7 G2 M_SA_MD6 SA_MA2 M7 G2 M_SA_MD22 SA_MA2 M7 G2 M_SA_MD35 SA_MA2 M7 G2 M_SA_MD50
SA_MA1 A2 DQ1 M_SA_MD7 SA_MA1 A2 DQ1 M_SA_MD23 SA_MA1 A2 DQ1 M_SA_MD34 SA_MA1 A2 DQ1 M_SA_MD51
M3 A1 DQ0 G8 M3 A1 DQ0 G8 M3 A1 DQ0 G8 M3 A1 DQ0 G8
SA_MA0 M8 SA_MA0 M8 SA_MA0 M8 SA_MA0 M8
A0 A0 A0 A0

VDDQ A9 +1_8VDIMM VDDQ A9 +1_8VDIMM VDDQ A9 +1_8VDIMM VDDQ A9 +1_8VDIMM


CLK_SDRAM-0 K8 C1 CLK_SDRAM-0 K8 C1 CLK_SDRAM-1 K8 C1 CLK_SDRAM-1 K8 C1
5,10 CLK_SDRAM-0 CK VDDQ CK VDDQ 5,10 CLK_SDRAM-1 CK VDDQ CK VDDQ
CLK_SDRAM0 J8 C3 CLK_SDRAM0 J8 C3 CLK_SDRAM1 J8 C3 CLK_SDRAM1 J8 C3
5,10 CLK_SDRAM0 CK VDDQ CK VDDQ 5,10 CLK_SDRAM1 CK VDDQ CK VDDQ
VDDQ C7 VDDQ C7 VDDQ C7 VDDQ C7
CKE0 K2 C9 CKE0 K2 C9 CKE0 K2 C9 CKE0 K2 C9
5,11 CKE0 CKE VDDQ CKE VDDQ CKE VDDQ CKE VDDQ
VDDQ E9 VDDQ E9 VDDQ E9 VDDQ E9
VDDQ G1 VDDQ G1 VDDQ G1 VDDQ G1
VDDQ G3 VDDQ G3 VDDQ G3 VDDQ G3
SM_CS-0 L8 G7 SM_CS-0 L8 G7 SM_CS-0 L8 G7 SM_CS-0 L8 G7
5,11 SM_CS-0 CS VDDQ CS VDDQ CS VDDQ CS VDDQ
VDDQ G9 VDDQ G9 VDDQ G9 VDDQ G9
SA_WE- K3 SA_WE- K3 SA_WE- K3 SA_WE- K3
6,10,11 SA_WE- WE WE WE WE
VDD A1 VDD A1 VDD A1 VDD A1
SA_RAS- K7 E1 SA_RAS- K7 E1 SA_RAS- K7 E1 SA_RAS- K7 E1
3
6,10,11 SA_RAS- RAS VDD RAS VDD RAS VDD RAS VDD 3
VDD J9 VDD J9 VDD J9 VDD J9
SA_CAS- L7 M9 SA_CAS- L7 M9 SA_CAS- L7 M9 SA_CAS- L7 M9
6,10,11 SA_CAS- CAS VDD CAS VDD CAS VDD CAS VDD
VDD R1 VDD R1 VDD R1 VDD R1
M_SA_DM0 F3 M_SA_DM2 F3 M_SA_DM4 F3 M_SA_DM6 F3
M_SA_DM1 LDM M_SA_DM3 LDM M_SA_DM5 LDM M_SA_DM7 LDM
B3 UDM VDDL J1 B3 UDM VDDL J1 B3 UDM VDDL J1 B3 UDM VDDL J1
VSSDL J7 VSSDL J7 VSSDL J7 VSSDL J7

SM_ODT0 K9 C27 SM_ODT0 K9 C28 SM_ODT0 K9 C24 SM_ODT0 K9 C322


5,11 SM_ODT0 ODT ODT ODT ODT
1u6.3Y4 68p50N4 1u6.3Y4 47p50N4

M_SA_DQS0 F7 A7 M_SA_DQS2 F7 A7 EMI M_SA_DQS4 F7 A7 M_SA_DQS6 F7 A7 EMI


M_SA_DQS-0 LDQS VSSQ M_SA_DQS-2 LDQS VSSQ M_SA_DQS-4 LDQS VSSQ M_SA_DQS-6 LDQS VSSQ
E8 LDQS VSSQ B2 E8 LDQS VSSQ B2 E8 LDQS VSSQ B2 E8 LDQS VSSQ B2
VSSQ B8 VSSQ B8 VSSQ B8 VSSQ B8
VSSQ D2 VSSQ D2 VSSQ D2 VSSQ D2
VSSQ D8 VSSQ D8 VSSQ D8 VSSQ D8
M_SA_DQS1 B7 E7 M_SA_DQS3 B7 E7 M_SA_DQS5 B7 E7 M_SA_DQS7 B7 E7
M_SA_DQS-1 UDQS VSSQ M_SA_DQS-3 UDQS VSSQ M_SA_DQS-5 UDQS VSSQ M_SA_DQS-7 UDQS VSSQ
A8 UDQS VSSQ F2 A8 UDQS VSSQ F2 A8 UDQS VSSQ F2 A8 UDQS VSSQ F2
SMDDR_VREF F8 F8 F8 F8
VSSQ VSSQ VSSQ VSSQ
VSSQ H2 VSSQ H2 VSSQ H2 VSSQ H2
SMDDR_VREF J2 H8 SMDDR_VREF J2 H8 SMDDR_VREF J2 H8 SMDDR_VREF J2 H8
VREF VSSQ VREF VSSQ VREF VSSQ VREF VSSQ
A2 NC#A2 VSS A3 A2 NC#A2 VSS A3 A2 NC#A2 VSS A3 A2 NC#A2 VSS A3
C45 C41 E2 E3 E2 E3 E2 E3 E2 E3
2.2u6.3Y6 0.1u10X4 NC#E2 VSS NC#E2 VSS NC#E2 VSS NC#E2 VSS
R3 NC#R3 VSS J3 R3 NC#R3 VSS J3 R3 NC#R3 VSS J3 R3 NC#R3 VSS J3
R7 NC#R7 VSS N1 R7 NC#R7 VSS N1 R7 NC#R7 VSS N1 R7 NC#R7 VSS N1
R8 NC VSS P9 R8 NC VSS P9 R8 NC VSS P9 R8 NC VSS P9

Trace : 10 mils
K4T1G164QQ-HCE6 K4T1G164QQ-HCE6 K4T1G164QQ-HCE6 K4T1G164QQ-HCE6

2 2

4P2R-10R 4P2R-10R
CLK_SDRAM-0 CLK_SDRAM-0
SA_MD0 RN44 1 2 M_SA_MD0 SA_MD32 RN36 1 2 M_SA_MD32 4P2R-10R
SA_MD1 3 4 M_SA_MD1 SA_MD33 3 4 M_SA_MD33 RN43 RN26
SA_MD2 RN42 1 2 M_SA_MD2 SA_MD34 RN25 1 2 M_SA_MD34 SA_DQS0 1 2 M_SA_DQS0 SA_DQS4 1 2 M_SA_DQS4 SA_DM1 RN15 1 2 M_SA_DM1 R61 C38
SA_MD3 3 4 M_SA_MD3 SA_MD35 3 4 M_SA_MD35 SA_DQS-0 3 4 M_SA_DQS-0 SA_DQS-4 3 4 M_SA_DQS-4 SA_MD7 3 4 M_SA_MD7 200R/4 3p50N4
SA_MD4 RN17 1 2 M_SA_MD4 SA_MD37 RN24 1 2 M_SA_MD37 SA_DM3 RN10 1 2 M_SA_DM3 CLK_SDRAM0
SA_MD5 3 4 M_SA_MD5 SA_MD36 3 4 M_SA_MD36 4P2R-10R 4P2R-10R SA_MD23 3 4 M_SA_MD23 CLK_SDRAM0
SA_DM0 RN16 1 2 M_SA_DM0 SA_MD39 RN23 1 2 M_SA_MD39 SA_MD45 RN22 1 2 M_SA_MD45
SA_MD6 3 4 M_SA_MD6 SA_MD38 3 4 M_SA_MD38 SA_DM4 3 4 M_SA_DM4
SA_MD8 RN41 1 2 M_SA_MD8 SA_MD40 RN35 1 2 M_SA_MD40 RN40 SA_DM7 RN5 1 2 M_SA_DM7 CLK_SDRAM-0
SA_MD9 3 4 M_SA_MD9 SA_MD41 3 4 M_SA_MD41 SA_DQS-1 1 2 M_SA_DQS-1 RN20 SA_DM6 3 4 M_SA_DM6
SA_MD11 RN39 1 2 M_SA_MD11 SA_MD42 RN34 1 2 M_SA_MD42 SA_DQS1 3 4 M_SA_DQS1 SA_DQS5 1 2 M_SA_DQS5
SA_MD10 3 4 M_SA_MD10 SA_MD43 3 4 M_SA_MD43 SA_DQS-5 3 4 M_SA_DQS-5 R60
SA_MD13 RN14 1 2 M_SA_MD13 SA_DM5 RN21 1 2 M_SA_DM5 4P2R-10R 200R/4
SA_MD12 3 4 M_SA_MD12 SA_MD44 3 4 M_SA_MD44 4P2R-10R
SA_MD15 RN13 1 2 M_SA_MD15 SA_MD47 RN19 1 2 M_SA_MD47 CLK_SDRAM0
SA_MD14 3 4 M_SA_MD14 SA_MD46 3 4 M_SA_MD46
SA_MD16 RN38 1 2 M_SA_MD16 SA_MD49 RN33 1 2 M_SA_MD49
SA_MD17 3 4 M_SA_MD17 SA_MD48 3 4 M_SA_MD48 RN37 RN32 +1_8VDIMM EMI EMI EMI
SA_MD18 RN29 1 2 M_SA_MD18 SA_MD51 RN6 1 2 M_SA_MD51 SA_DQS2 1 2 M_SA_DQS2 SA_DQS6 1 2 M_SA_DQS6
SA_MD19 3 4 M_SA_MD19 SA_MD50 3 4 M_SA_MD50 SA_DQS-2 3 4 M_SA_DQS-2 SA_DQS-6 3 4 M_SA_DQS-6
SA_MD20 RN12 1 2 M_SA_MD20 SA_MD53 RN18 1 2 M_SA_MD53
1
SA_MD21 3 4 M_SA_MD21 SA_MD52 3 4 M_SA_MD52 4P2R-10R 4P2R-10R 1
SA_MD22 RN11 1 2 M_SA_MD22 SA_MD54 RN4 1 2 M_SA_MD54 C40 C331 C25 C333 C340 C338 C327 C47
SA_DM2 3 4 M_SA_DM2 SA_MD55 3 4 M_SA_MD55 0.1u10X4 47p50N4 1u6.3Y4 68p50N4 0.1u10X4 100p16N4 1u6.3X8 1u6.3X8
SA_MD25 RN28 1 2 M_SA_MD25 SA_MD56 RN31 1 2 M_SA_MD56 RN2
SA_MD24 3 4 M_SA_MD24 SA_MD57 3 4 M_SA_MD57 RN8 SA_DQS7 1 2 M_SA_DQS7
SA_MD27 RN27 1 2 M_SA_MD27 SA_MD58 RN30 1 2 M_SA_MD58 SA_DQS3 1 2 M_SA_DQS3 SA_DQS-7 3 4 M_SA_DQS-7
SA_MD26 3 4 M_SA_MD26 SA_MD59 3 4 M_SA_MD59 SA_DQS-3 3 4 M_SA_DQS-3
SA_MD29 RN9 1 2 M_SA_MD29 SA_MD61 RN3 1 2 M_SA_MD61 4P2R-10R
SA_MD28 3 4 M_SA_MD28 SA_MD60 3 4 M_SA_MD60 4P2R-10R MICRO-STAR INT'L CO.,LTD
SA_MD30 RN7 1 2 M_SA_MD30 SA_MD63 RN1 1 2 M_SA_MD63
SA_MD31 3 4 M_SA_MD31 SA_MD62 3 4 M_SA_MD62 MS-N011
MSI
Size Document Description Rev
Custom 1.0
DDR2 64*16 BGA A
Date: Friday, April 11, 2008 Sheet 9 of 39
A B C D E
A B C D E

SA_MD[0..63] SA_DQS-[0..7]
6,8,9 SA_MD[0..63] 6,8,9 SA_DQS-[0..7]
SA_MA[0..12] M_SA_DQS-[0..7]
6,9,11 SA_MA[0..12] 9 M_SA_DQS-[0..7]
SA_BS-[0..2] M_SA_DQS[0..7]
6,9,11 SA_BS-[0..2] 9 M_SA_DQS[0..7] M12-K4T1G05-S02 D-die turn to Q-die next version
SA_DM[0..7] M_SA_MD[0..63]
6,8,9 SA_DM[0..7] 9 M_SA_MD[0..63]
SA_DQS[0..7] M_SA_DM[0..7]
6,8,9 SA_DQS[0..7] 9 M_SA_DM[0..7]

U6 U5 U4 U3
4 SA_BS-0 L2 B9 M_SA_MD10 SA_BS-0 L2 B9 M_SA_MD26 SA_BS-0 L2 B9 M_SA_MD44 SA_BS-0 L2 B9 M_SA_MD61 4
SA_BS-1 BA0 DQ15 M_SA_MD15 SA_BS-1 BA0 DQ15 M_SA_MD31 SA_BS-1 BA0 DQ15 M_SA_MD40 SA_BS-1 BA0 DQ15 M_SA_MD57
L3 BA1 DQ14 B1 L3 BA1 DQ14 B1 L3 BA1 DQ14 B1 L3 BA1 DQ14 B1
SA_BS-2 L1 D9 M_SA_MD8 SA_BS-2 L1 D9 M_SA_MD29 SA_BS-2 L1 D9 M_SA_MD43 SA_BS-2 L1 D9 M_SA_MD58
BA2 DQ13 M_SA_MD9 BA2 DQ13 M_SA_MD28 BA2 DQ13 M_SA_MD42 BA2 DQ13 M_SA_MD59
DQ12 D1 DQ12 D1 DQ12 D1 DQ12 D1
SA_MA12 R2 D3 M_SA_MD12 SA_MA12 R2 D3 M_SA_MD24 SA_MA12 R2 D3 M_SA_MD47 SA_MA12 R2 D3 M_SA_MD62
SA_MA11 A12 DQ11 M_SA_MD13 SA_MA11 A12 DQ11 M_SA_MD25 SA_MA11 A12 DQ11 M_SA_MD46 SA_MA11 A12 DQ11 M_SA_MD63
P7 A11 DQ10 D7 P7 A11 DQ10 D7 P7 A11 DQ10 D7 P7 A11 DQ10 D7
SA_MA10 M2 C2 M_SA_MD14 SA_MA10 M2 C2 M_SA_MD30 SA_MA10 M2 C2 M_SA_MD41 SA_MA10 M2 C2 M_SA_MD56
SA_MA9 A10/AP DQ9 M_SA_MD11 SA_MA9 A10/AP DQ9 M_SA_MD27 SA_MA9 A10/AP DQ9 M_SA_MD45 SA_MA9 A10/AP DQ9 M_SA_MD60
P3 A9 DQ8 C8 P3 A9 DQ8 C8 P3 A9 DQ8 C8 P3 A9 DQ8 C8
SA_MA8 P8 F9 M_SA_MD2 SA_MA8 P8 F9 M_SA_MD19 SA_MA8 P8 F9 M_SA_MD38 SA_MA8 P8 F9 M_SA_MD55
SA_MA7 A8 DQ7 M_SA_MD3 SA_MA7 A8 DQ7 M_SA_MD18 SA_MA7 A8 DQ7 M_SA_MD39 SA_MA7 A8 DQ7 M_SA_MD54
P2 A7 DQ6 F1 P2 A7 DQ6 F1 P2 A7 DQ6 F1 P2 A7 DQ6 F1
SA_MA6 N7 H9 M_SA_MD4 SA_MA6 N7 H9 M_SA_MD16 SA_MA6 N7 H9 M_SA_MD33 SA_MA6 N7 H9 M_SA_MD53
SA_MA5 A6 DQ5 M_SA_MD5 SA_MA5 A6 DQ5 M_SA_MD17 SA_MA5 A6 DQ5 M_SA_MD32 SA_MA5 A6 DQ5 M_SA_MD48
N3 A5 DQ4 H1 N3 A5 DQ4 H1 N3 A5 DQ4 H1 N3 A5 DQ4 H1
SA_MA4 N8 H3 M_SA_MD1 SA_MA4 N8 H3 M_SA_MD20 SA_MA4 N8 H3 M_SA_MD37 SA_MA4 N8 H3 M_SA_MD49
SA_MA3 A4 DQ3 M_SA_MD0 SA_MA3 A4 DQ3 M_SA_MD21 SA_MA3 A4 DQ3 M_SA_MD36 SA_MA3 A4 DQ3 M_SA_MD52
N2 A3 DQ2 H7 N2 A3 DQ2 H7 N2 A3 DQ2 H7 N2 A3 DQ2 H7
SA_MA2 M7 G2 M_SA_MD6 SA_MA2 M7 G2 M_SA_MD22 SA_MA2 M7 G2 M_SA_MD35 SA_MA2 M7 G2 M_SA_MD50
SA_MA1 A2 DQ1 M_SA_MD7 SA_MA1 A2 DQ1 M_SA_MD23 SA_MA1 A2 DQ1 M_SA_MD34 SA_MA1 A2 DQ1 M_SA_MD51
M3 A1 DQ0 G8 M3 A1 DQ0 G8 M3 A1 DQ0 G8 M3 A1 DQ0 G8
SA_MA0 M8 SA_MA0 M8 SA_MA0 M8 SA_MA0 M8
A0 A0 A0 A0

VDDQ A9 +1_8VDIMM VDDQ A9 +1_8VDIMM VDDQ A9 +1_8VDIMM VDDQ A9 +1_8VDIMM


CLK_SDRAM-0 K8 C1 CLK_SDRAM-0 K8 C1 CLK_SDRAM-1 K8 C1 CLK_SDRAM-1 K8 C1
5,9 CLK_SDRAM-0 CK VDDQ CK VDDQ 5,9 CLK_SDRAM-1 CK VDDQ CK VDDQ
CLK_SDRAM0 J8 C3 CLK_SDRAM0 J8 C3 CLK_SDRAM1 J8 C3 CLK_SDRAM1 J8 C3
5,9 CLK_SDRAM0 CK VDDQ CK VDDQ 5,9 CLK_SDRAM1 CK VDDQ CK VDDQ
VDDQ C7 VDDQ C7 VDDQ C7 VDDQ C7
CKE1 K2 C9 CKE1 K2 C9 CKE1 K2 C9 CKE1 K2 C9
5,11 CKE1 CKE VDDQ CKE VDDQ CKE VDDQ CKE VDDQ
VDDQ E9 VDDQ E9 VDDQ E9 VDDQ E9
VDDQ G1 VDDQ G1 VDDQ G1 VDDQ G1
VDDQ G3 VDDQ G3 VDDQ G3 VDDQ G3
SM_CS-1 L8 G7 SM_CS-1 L8 G7 SM_CS-1 L8 G7 SM_CS-1 L8 G7
5,11 SM_CS-1 CS VDDQ CS VDDQ CS VDDQ CS VDDQ
VDDQ G9 VDDQ G9 VDDQ G9 VDDQ G9
SA_WE- K3 SA_WE- K3 SA_WE- K3 SA_WE- K3
6,9,11 SA_WE- WE WE WE WE
VDD A1 VDD A1 VDD A1 VDD A1
SA_RAS- K7 E1 SA_RAS- K7 E1 SA_RAS- K7 E1 SA_RAS- K7 E1
3
6,9,11 SA_RAS- RAS VDD RAS VDD RAS VDD RAS VDD 3
VDD J9 VDD J9 VDD J9 VDD J9
SA_CAS- L7 M9 SA_CAS- L7 M9 SA_CAS- L7 M9 SA_CAS- L7 M9
6,9,11 SA_CAS- CAS VDD CAS VDD CAS VDD CAS VDD
VDD R1 VDD R1 VDD R1 VDD R1
M_SA_DM0 F3 M_SA_DM2 F3 M_SA_DM4 F3 M_SA_DM6 F3
M_SA_DM1 LDM M_SA_DM3 LDM M_SA_DM5 LDM M_SA_DM7 LDM
B3 UDM VDDL J1 B3 UDM VDDL J1 B3 UDM VDDL J1 B3 UDM VDDL J1
VSSDL J7 VSSDL J7 VSSDL J7 VSSDL J7

SM_ODT1 K9 C305 SM_ODT1 K9 C46 SM_ODT1 K9 C304 SM_ODT1 K9 C309


5,11 SM_ODT1 ODT ODT ODT ODT
100p16N4 68p50N4 0.1u10X4 1u6.3Y4

M_SA_DQS0 F7 A7 EMI M_SA_DQS2 F7 A7 EMI M_SA_DQS4 F7 A7 M_SA_DQS6 F7 A7


M_SA_DQS-0 LDQS VSSQ M_SA_DQS-2 LDQS VSSQ M_SA_DQS-4 LDQS VSSQ M_SA_DQS-6 LDQS VSSQ
E8 LDQS VSSQ B2 E8 LDQS VSSQ B2 E8 LDQS VSSQ B2 E8 LDQS VSSQ B2
VSSQ B8 VSSQ B8 VSSQ B8 VSSQ B8
VSSQ D2 VSSQ D2 VSSQ D2 VSSQ D2
VSSQ D8 VSSQ D8 VSSQ D8 VSSQ D8
M_SA_DQS1 B7 E7 M_SA_DQS3 B7 E7 M_SA_DQS5 B7 E7 M_SA_DQS7 B7 E7
M_SA_DQS-1 UDQS VSSQ M_SA_DQS-3 UDQS VSSQ M_SA_DQS-5 UDQS VSSQ M_SA_DQS-7 UDQS VSSQ
A8 UDQS VSSQ F2 A8 UDQS VSSQ F2 A8 UDQS VSSQ F2 A8 UDQS VSSQ F2
SMDDR_VREF F8 F8 F8 F8
VSSQ VSSQ VSSQ VSSQ
VSSQ H2 VSSQ H2 VSSQ H2 VSSQ H2
SMDDR_VREF J2 H8 SMDDR_VREF J2 H8 SMDDR_VREF J2 H8 SMDDR_VREF J2 H8
VREF VSSQ VREF VSSQ VREF VSSQ VREF VSSQ
A2 NC#A2 VSS A3 A2 NC#A2 VSS A3 A2 NC#A2 VSS A3 A2 NC#A2 VSS A3
C44 C43 E2 E3 E2 E3 E2 E3 E2 E3
2.2u6.3Y6 0.1u10X4 NC#E2 VSS NC#E2 VSS NC#E2 VSS NC#E2 VSS
R3 NC#R3 VSS J3 R3 NC#R3 VSS J3 R3 NC#R3 VSS J3 R3 NC#R3 VSS J3
R7 NC#R7 VSS N1 R7 NC#R7 VSS N1 R7 NC#R7 VSS N1 R7 NC#R7 VSS N1
R8 NC VSS P9 R8 NC VSS P9 R8 NC VSS P9 R8 NC VSS P9

Trace : 10 mils
K4T1G164QQ-HCE6 K4T1G164QQ-HCE6 K4T1G164QQ-HCE6 K4T1G164QQ-HCE6

2 2

CLK_SDRAM-1

R57 +3VSUS M12-5PS1G25-H23 M12-1GE4C05-M20


200R/4 SPD EEPROM
U901 U903
CLK_SDRAM1

C478 C481 C479 5020 5020


U32 X_2.2u6.3Y6 X_0.1u10X4 X_0.1u10X4 Hynix Mira
DDR R402
R401
X_1K/4
X_1K/4
1 A0 VCC 8
2 A1 WP 7
3 A2 SCL 6 SUS_SMBCLK 14,23
CLK_SDRAM-1 CLK_SDRAM-1 4 5 SUS_SMBDATA 14,23 HY5PS1G1631CLFP P3R1GE4CFF-G8E-E
GND SDA
X_AT24C02B-TH-T
C37 R59 U902
3p50N4 200R/4

CLK_SDRAM1 CLK_SDRAM1 ADDRESS: 000


Hynix 5010
0xA0
1
DDR +1_8VDIMM HY5PS1G1631CLFP
1

EMI EMI EMI EMI

C31 C316 C49 C337 C48 C26 C334 C330 MICRO-STAR INT'L CO.,LTD
100p16N4 100p16N4 68p50N4 0.1u10X4 68p50N4 1u6.3Y4 68p50N4 1u6.3X8

MSI
MS-N011
Size Document Description Rev
Custom 1.0
DDR2 64*16 BGA B
Date: Monday, April 14, 2008 Sheet 10 of 39

A B C D E
5 4 3 2 1

SA_MA[0..13]
SA_MA[0..13] 6,9,10
SA_BS-[0..2]
SA_BS-[0..2] 6,9,10
SB_MA[0..13]
SB_MA[0..13] 6,8
D SB_BS-[0..2] D
SB_BS-[0..2] 6,8
SMDDR_VTERM
RNT8 RNT4
SM_CS-0 1 2 1 2 SB_MA13
5,9 SM_CS-0
SA_MA13 3 4 3 4 SM_ODT2
SM_ODT2 5,8
SA_MA2 5 6 5 6 SM_CS-2
SM_CS-2 5,8
SA_MA12 7 8 7 8 SM_CS-3
SM_CS-3 5,8
SMDDR_VTERM
RNT7 RNT5 8P4R-56R/4 8P4R-56R/4
SA_BS-1 1 2 1 2 SB_BS-0
SA_BS-0 3 4 3 4 SB_MA10 RNT12 RNT11
SM_CS-1 5 6 5 6 SB_MA0 SA_MA8 7 8 8 7 SA_MA6
5,10 SM_CS-1
SM_ODT0 7 8 7 8 SB_MA2 CKE0 5 6 6 5 SA_MA1
5,9 SM_ODT0 5,9 CKE0
SA_MA7 3 4 4 3 SA_RAS-
SA_RAS- 6,9,10
8P4R-56R/4 8P4R-56R/4 SA_MA10 1 2 2 1 SA_MA9

RNT9 RNT3 8P4R-56R/4 8P4R-56R/4


SA_MA4 1 2 1 2 SB_MA6
SA_MA0 3 4 3 4 SB_MA3 RNT1 RNT2
SA_MA3 5 6 5 6 SB_MA4 SB_MA8 2 1 1 2 SB_BS-1
SA_MA5 7 8 7 8 SB_MA1 SB_MA5 4 3 3 4 SB_WE-
SB_WE- 6,8
SB_MA7 6 5 5 6 SB_RAS-
SB_RAS- 6,8
8P4R-56R/4 8P4R-56R/4 SB_MA11 8 7 7 8 SB_CAS-
SB_CAS- 6,8
C C
RNT10 RNT6 8P4R-56R/4 8P4R-56R/4
SA_MA11 7 8 1 2 SB_BS-2
SA_WE- 5 6 3 4 SB_MA12
6,9,10 SA_WE-
SA_CAS- 3 4 5 6 SB_MA9 SM_ODT1 RT2 56R/4 RT1 56R/4 CKE2
6,9,10 SA_CAS- 5,10 SM_ODT1 CKE2 5,8
SA_BS-2 1 2 7 8 CKE3
CKE3 5,8
CKE1 RT3 56R/4 RT5 56R/4 SM_ODT3
5,10 CKE1 SM_ODT3 5,8
8P4R-56R/4 8P4R-56R/4

SMDDR_VTERM

CT17 CT21 CT8 CT10 CT13 CT16 CT4 CT12 CT19 CT9 CT11 CT14 CT5
0.1u10X4 1u6.3Y4 X_0.1u10X4 1u6.3Y4 0.1u10X4 1u6.3Y4 1u6.3Y4 1u6.3Y4 X_0.1u10X4 X_0.1u10X4 X_0.1u10X4 1u6.3Y4 1u6.3Y4

B B
SMDDR_VTERM

CT18 CT1 CT3 CT22 CT2 CT7 CT20 CT15 CT26 CT40 CT37 CT38 CT36
1u6.3Y4 1u6.3Y4 1u6.3Y4 X_0.1u10X4 1u6.3Y4 0.1u10X4 0.1u10X4 0.1u10X4 X_0.1u10X4 0.1u10X4 100p16N4 100p16N4 2.2u6.3Y6

EMI
Layout note: Place one cap close to every 2 pullup resistors terminated to +0.9V.

SMDDR_VTERM

CT6
10u10Y8 CT39
A 2.2u6.3Y6 A

MICRO-STAR INT'L CO.,LTD

MSI
MS-N011
Size Document Description Rev
B 1.0
DDR2 Termination
Date: Friday, April 11, 2008 Sheet 11 of 39

5 4 3 2 1
5 4 3 2 1

C433 18p50N6 SB_RTCX1

2
1

2
+3VALW Y5 R367

3
32.768KHZ12.5P 10M/6 U30A

3
RTCVCC AB1 AA6 LAD0
LAD0 17

X
D C437 18p50N6 SB_RTCX2 RTXC1 LAD0 LAD1 D
AB2 RTCX2 LAD1 AB5 LAD1 17
D13 R210 AC4 LAD2
LAD2 LAD2 17
S-BAT54C_SOT23 RTCRST# LAD3 VTT

RTC
Z AA3 RTCRST# LAD3 Y6 LAD3 17
20K/4 SM_INTRUDER-

LPC
Y5 INTRUDER# LDRQ0# AC3 L_LDRQ0# 17
C221 R191 C220 RTCVCC INTVRMEN W4 AA5 L_LDRQ1- T22 H_DPRSTP# R341 X_1K/4
Y
R192 330K/4 INTVRMEN LDRQ1#/GPIO23 H_DPSLP# R340 X_1K/4
1u10X6 1M/4 1u10X6
W1 EE_CS LFRAME# AB3 LPC_FRAME# 17
Y1 H_FERR# R346 56R/4
EE_SHCLK H_A20GATE H_STPCLK# R349 X_1K/4
Y2 EE_DOUT A20GATE AE22 H_A20GATE 17
R203 W3 AH28 H_A20M# 2
SM_INTRUDER- EE_DIN A20M#
1K/4
V3 LAN_CLK CPUSLP# AG27
6

U3 AF24 H_DPRSTP#_R R348 0R/4 H_DPRSTP# H_DPRSTP# 2,30


JRTC1 LAN_RSTSYNC TP1/DPRSTP# H_DPSLP#_R R347 0R/4 H_DPSLP#
TP2/DPSLP# AH25 H_DPSLP# 2
2 BH1X2S-1.25PITCH_WHITE U5 LAN_RXD0

LAN
1 V4 LAN_RXD1 FERR# AG26 H_FERR# 2
T5 LAN_RXD2 CPU_PWRGD
N32-1020730-A81 U7
GPIO49/CPUPWRGD AG24 CPU_PWRGD 2
5

LAN_TXD0
TOP

CPU
V6 LAN_TXD1 IGNNE# AG22 H_IGNNE# 2
V7 AG21 FWH_INIT# T32
LAN_TXD2 INT3_3V# H_INIT#
C INIT# AF22 H_INIT# 2 C
ACZ_BIT_CLK_ICH7 U1 AF25 H_INTR

AC-97/AZALIA
ACZ_BCLK INTR H_INTR 2
ACZ_SYNC R6 ACZ_SYNC KBRST# VTT
RCIN# AG23 KBRST# 17
ACZ_RST# R5
RN56 ACZ_RST# H_NMI
NMI AH24 H_NMI 2 Layout within 2"
1 2 ACZ_SYNC T2 AF23 H_SMI# H_SMI# 2 of 24R
19 CODEC_HDA_SYNC ACZ_RST# 19 CODEC_HDA_SDIN0 ACZ_SDIN0 SMI# R344
19 CODEC_HDA_RST# 3 4 T3 ACZ_SDIN1
5 6 ACZ_SDOUT T1 AH22 H_STPCLK# 2 56R/4
19 CODEC_HDA_SDOUT ACZ_BIT_CLK_ICH7 ACZ_SDIN2 STPCLK#
19 CODEC_HDA_BITCLK 7 8
ACZ_SDOUT T4 AF26 R345 24R/4
ACZ_SDOUT THERMTRIP# PM_THRMTRIP# 2
8P4R-39R/4
SATAHD_LED# AF18 Layout within 2" R338 0R/4
24 SATAHD_LED# SATALED# THERMTRIP_GMCH# 5
EMC88 AB15 of ICH7M
C226 0.01u16X4 SATA0RXN_C DD0
X_33p50N4 22 SATA0RXN AF3 SATA0RXN DD1 AE14
C227 0.01u16X4 SATA0RXP_C AE3 AG13
22 SATA0RXP SATA0RXP DD2
C229 0.01u16X4 SATA0TXN_C AG2 AF13
22 SATA0TXN SATA0TXN DD3
C228 0.01u16X4 SATA0TXP_C AH2 AD14
22 SATA0TXP SATA0TXP DD4
For EMI DD5 AC13
AF7 AD12

SATA
SATA2RXN DD6
AE7 AC12

IDE
SATA2RXP DD7
AG6 SATA2TXN DD8 AE12
AH6 SATA2TXP DD9 AF12
DD10 AB13
B 16 CLK_SATA# AF1 SATA_CLKN DD11 AC14 B
16 CLK_SATA AE1 SATA_CLKP DD12 AF14
DD13 AH13
Layout within 500mil R353 SATARBIAS AH10 AH14
SATARBIASN DD14
of ICH7M pin out. AG10 SATARBIASP DD15 AC15
20R1%4
DA0 AH17
24.9R-->20R for modify SATA eye pattern. AF15 DIOR# DA1 AE17
+3VRUN AH15
AF16
DIOW# ICH7-M DA2 AF17

R350 10K/4 IDE_IRQ14 DDACK#


R351 4.7K/4 IDE_IORDY
AH16
AG16
IDEIRQ PARTA DCS1# AE16
AD16
R179 X_100K/4 IDE_DREQ IORDY DCS3#
AE15 DDREQ

INTEL-82801GBM-B0-RH

A A

MICRO-STAR INT'L CO.,LTD

MSI
MS-N011
Size Document Description Rev
Custom 1.0
ICH7M_CPU, LPC, SATA, HDA
Date: Friday, April 11, 2008 Sheet 12 of 39

5 4 3 2 1
5 4 3 2 1

U30B
P_GNT5# R395 X_1K/4 E18 D7 P_REQ0#
P_GNT4# R394 X_1K/4 AD0 REQ0#
C18 AD1 GNT0# E7 the top-blick swap mode
A16 C16 P_REQ1# NO STUFF by default.
AD2 REQ1# +3VRUN
F18 D16
E16
AD3
AD4
PCI GNT1#
REQ2# C17 P_REQ2#
STUFF for A16 swap override
A18 D17 8P4R-8.2KR/4 RN60
AD5 GNT2# P_REQ3# P_TRDY#
BOOT BIOS SELECT STRAPS E17 AD6 REQ3# E13 2 1
D A17 F13 P_GNT3# R212 X_1K/4 4 3 D
AD7 GNT3# P_REQ4#
BOOT DEVICE STRAPS GNT5# GNT4# A15 AD8 REQ4#/GPIO22 A13 6 5
C14 A14 P_GNT4# P_REQ3# 8 7
AD9 GNT4#/GPIO48 P_REQ5#
FWH(LPC default) 11 UNSTUFF UNSTUFF E14 AD10 GPIO1/REQ5# C8
D14 D8 P_GNT5#
AD11 GPIO17/GNT5# 8P4R-8.2KR/4 RN61
PCI 10 UNSTUFF STUFF B12 AD12
C13 B15 P_REQ4# 2 1
AD13 C/BE0# P_PLOCK#
SPI 01 STUFF UNSTUFF G15 AD14 C/BE1# C12 4 3
G13 D12 P_DEVSEL# 6 5
AD15 C/BE2# P_SERR#
E12
C11
AD16 ICH7-M C/BE3# C15 8 7
AD17 P_IRDY#
D11
A11
AD18 PARTB IRDY# A7
E10 8P4R-8.2KR/4 RN64
AD19 PAR INT_PIRQD#
A10 AD20 PCIRST# B18 2 1
F11 A12 P_DEVSEL# INT_PIRQC# 4 3
AD21 DEVSEL# P_PERR# INT_PIRQA#
F10 AD22 PERR# C9 6 5
E9 E11 P_PLOCK# INT_PIRQB# 8 7
AD23 PLOCK# P_SERR#
D9 AD24 SERR# B10
B9 F15 P_STOP#
U30D AD25 STOP# P_TRDY# 8P4R-8.2KR/4 RN62
A8 AD26 TRDY# F14
18 PCIE_LAN_RXN F26 V26 A6 F16 P_FRAME# P_PERR# 2 1
PERn1 DMI0RXN DMI_RXN0 5 AD27 FRAME#
18 PCIE_LAN_RXP F25 V25 C7 INT_PIRQE# 4 3
PERp1 DMI0RXP DMI_RXP0 5 AD28
C454 0.1u10X4 PCIE_LAN_TXN_C E28 U28 DMI_TXN0 5 B6 C26 PLTRST# INT_PIRQG# 6 5
18 PCIE_LAN_TXN C452 0.1u10X4 PCIE_LAN_TXP_C PETn1 DMI0TXN AD29 PLTRST# CLK_PCI_ICH P_REQ5#
18 PCIE_LAN_TXP E27 PETp1 DMI0TXP U27 DMI_TXP0 5 E6 AD30 PCICLK A9 CLK_PCI_ICH 16 8 7
D6 AD31 PME# B19
23 PCIE_MINI_RXN1 H26 PERn2 DMI1RXN Y26 DMI_RXN1 5 PME# has internal pull +3VSUS
23 PCIE_MINI_RXP1 H25 Y25 8P4R-8.2KR/4 RN59
PERp2 DMI1RXP DMI_RXP1 5
C 23 PCIE_MINI_TXN1
C451
C447
0.1u10X4
0.1u10X4
PCIE_MINI_TXN1_C
PCIE_MINI_TXP1_C
G28
G27
PETn2 DMI1TXN W28
W27
DMI_TXN1 5
INT_PIRQA# A3
Interrupt I/F G8 INT_PIRQE#
P_REQ2#
P_FRAME#
2 1 C
23 PCIE_MINI_TXP1 PETp2 DMI1TXP DMI_TXP1 5 PIRQA# GPIO2/PIRQE# 4 3
INT_PIRQB# B4 F7 INT_PIRQF# P_STOP# 6 5
PCI-Express INT_PIRQC# PIRQB# GPIO3/PIRQF# INT_PIRQG# P_REQ1#

DMI
K26 PERn3 DMI2RXN AB26 C5 PIRQC# GPIO4/PIRQG# F8 8 7
place Cap close to K25 AB25 INT_PIRQD# B5 G7 INT_PIRQH#
PERp3 DMI2RXP PIRQD# GPIO5/PIRQH#
J28 AA28
ICH7 within 250mils J27
PETn3 DMI2TXN
AA27 8P4R-8.2KR/4 RN63
PETp3 DMI2TXP P_IRDY# 2 1
M26 PERn4 DMI3RXN AD25 AE5 RSVD[1]
MISC RSVD[6] AE9 P_REQ0# 4 3
M25 AD24 Please within AD5 AG8 INT_PIRQH# 6 5
PERp4 DMI3RXP RSVD[2] RSVD[7] INT_PIRQF#
L28 AC28 AG4 AH8 8 7
L27
PETn4 DMI3TXN
AC27 500mils of AH4
RSVD[3] RSVD[8]
F21 T28
PETp4 DMI3TXP RSVD[4] TP3
ICH7 AD9 RSVD[5] MCH_SYNC# AH20 MCH_ICH_SYNC# 5
P26 PERn5 DMI_CLKN AE28 CLK_PCIE_ICH# 16
P25 AE27 L_ICH7_1.5V INTEL-82801GBM-B0-RH
PERp5 DMI_CLKP CLK_PCIE_ICH 16
N28 PETn5
N27 PETp5 DMI_ZCOMP C25
D25 DMI_IRCOMP_R R218 24.9R1%4 +3VSUS
DMI_IRCOMP
T25 PERn6
T24 F1 C480
PERp6 USBP0N USB0N 23
R28 PETn6 USBP0P F2 USB0P 23
R27 G4 X_0.1u16Y4
PETp6 USBP1N USB1N 23

14
USBP1P G3 USB1P 23
R2 H1 USB 0 : USB CONN. U33A
SPI_CLK USBP2N USB2N 23 VCC
P6 SPI_CS# USBP2P H2 USB2P 23 USB 1 : USB CONN. 1 A
CP26 1 X_COPPER
USB

P1 SPI_ARB USBP3N J4 USB3N 23 USB 2 : USB CONN. O 3 2 LPC_RST# 17


J3 PLTRST# 2
USB3P 23
SPI

USBP3P B
CP27 1 X_COPPER
B P5 SPI_MOSI USBP4N K1 USB4N 23 USB 3 : CAMERA GND 2 LAN_RST# 18 B
+3VSUS P2 K2 USB 4 : MINI PCIE LCX08MTC_NL_TSSOP14
USB4P 23

7
SPI_MISO USBP4P CP28 1 X_COPPER
USBP5N L4 USB5N 22 USB 5 : CardReader 2 SB_LAN_RST# 14
R217 L5
USBP5P USB5P 22 USB 6 : Blue tooth
OC0# D3 M1
OC0# USBP6N USB6N 22
10K/4
C4
D5
OC1# ICH7-M USBP6P M2
N4
USB6P 22
OC2# USBP7N +3VSUS
D4
E5
OC3# PARTD USBP7P N3
OC4# C482
C3 OC5# / GPIO29
A2 OC6# / GPIO30 USBRBIAS# D2
B3 D1 USBRBIAS X_0.1u16Y4
OC7# / GPIO31 USBRBIAS

14
INTEL-82801GBM-B0-RH Please within U33B
R379 4
VCC

22.6R1%4 500mils of A

O 6 CP31 1 2 X_COPPER NB_RST# 5


ICH 5 B
GND

LCX08MTC_NL_TSSOP14 CP32 1 2 X_COPPER MINIPCIE1_RST# 23

7
A A

MICRO-STAR INT'L CO.,LTD

MSI MS-N011
Size Document Description Rev
Custom 1.0
ICH7M_PCI, USB, DMI, PCIE
Date: Friday, April 11, 2008 Sheet 13 of 39

5 4 3 2 1
5 4 3 2 1

U30C
+3VRUN SUS_SMBCLK C22 AF19 SATA0GP
SUS_SMBDATA SMBCLK GPIO21/SATA0GP SATA1GP
B22 SMBDATA GPIO19/SATA1GP AH18

Clocks SATA
GPIO
SMB_LINK_ALERT# A26 AH19 SATA2GP

SMB
P_CLKRUN# SMLINK0 LINKALERT# GPIO36/SATA2GP SATA3GP
1 2 B25 SMLINK0 GPIO37/STAT3GP AE19
3 4 SATA1GP SMLINK1 A25
SATA0GP SMLINK1 CLK_14M_ICH
5 6 CLK14 AC1 CLK_14M_ICH 16
7 8 SATA2GP PM_RI# A28 B2 CLK_USB48
RI# CLK48 CLK_USB48 16
D RN53 8P4R-10K/4 SPKR SUSCLK D
19 SPKR A19 SPKR SUSCLK C20
PM_THRM# PM_SUS_STAT- T37
1 2 T38 A27 SUS_STAT#
3 4 SATA3GP PM_SYS_RESET A22 B24 PM_SLP_S3#
SIRQ SYS_RST# SLP_S3# PM_SLP_S4# PM_SLP_S3# 17
5 6 SLP_S4# D23 PM_SLP_S4# 17
7 8 5 PM_BMBUSY# PM_BMBUSY# AB18 F22 PM_SLP_S5# T27
GPIO0/BM_BUSY# SLP_S5#

Power MGT
RN52 8P4R-10K/4 SMBALERT# B23 AA4 CHIP_PWRGD
GPIO11/SMBALERT# PWROK CHIP_PWRGD 5,17,19
+3VSUS
PM_STPPCI# AC20 AC22 DPRSLPVR R184 0R/4
16 PM_STPPCI# PM_STPCPU# GPIO18/STPPCI# GPIO16/DPRSLPVR PM_DPRSLPVR 5,30
16 PM_STPCPU# AF21 GPIO20/STPCPU#
RN58 8P4R-10K/4 C21 PM_BATLOW# PWRBTN# internal pull high
pin AC20, AF21 internal pull high TP0/BATLOW#
1 2 SMB_LINK_ALERT# A21 EL_RSVD/GPIO26 Internal debounced inside 82801GBM

GPIO
3 4 SMLINK0 C23 PM_PWRBTN#
PWRBTN# PM_PWRBTN# 17

SYS
5 6 SMLINK1 B21
SMBALERT# EL_STATE0/GPIO27 SB_LAN_RST#
7 8 E23 EL_STATE1/GPIO28 LAN_RST# C19 SB_LAN_RST# 13
R391 10K/4 PM_SYS_RESET P_CLKRUN# AG18 Y4 RSMRST#
17 P_CLKRUN# GPIO32/CLKRUN# RSMRST# RSMRST# 17
R385 10K/4 PM_RI#
R392 10K/4 PM_BATLOW# AC19 E20 RSMRST- is pulled low near KBC
R213 1K/4 PCIE_WAKE# GPIO33/AZ_DOCK_EN# GPIO9
U2 GPIO34/AZ_DOCK_RST# GPIO10 A20
GPIO12 F19 SB_BLON 21
18,23 PCIE_WAKE# PCIE_WAKE# F20 E19
R393 X_10K/4 SB_LAN_RST# SIRQ WAKE# GPIO13

GPIO
17 SIRQ AH21 SERIRQ GPIO14 R4
PM_THRM# AF20 E22
C THRM# GPIO15 C
R187 X_10K/4 CHIP_PWRGD R3 MB_ID0 T35
ICH_VRMPG GPIO24 MB_ID1
AD22 VRMPWRGD GPIO25 D20 Power
T29 GPIO Default
GPIO35/STATCLKREQ# AD21 SATA_CLKREQ# 16 Plane
GPIO38 AD20
AC21 GPIO6 GPIO39 AE20
KBSCI# 6,7 Core GPI
+3VRUN
17 KBSCI#
KBSMI#
AC18
E21
GPIO7 ICH7-M
17 KBSMI# GPIO8
PARTC 8~10 Resume GPI

INTEL-82801GBM-B0-RH 12~15 Resume GPI


R380
10K/4 24,25 Resume GPO
38,39 Core GPI
Q56
B

16 VR_PG_CLKEN CP35 1 2 X_COPPER ICH_VRMPG


PM_SYS_RESET C E WTDG# 16,17
17,30 IMVP_PWRGD R405 X_0R/4
N-MMBT3904_NL_SOT23

B B

+3VRUN

Q34
G

10,23 SUS_SMBCLK SUS_SMBCLK D S RUN_SMBCLK 8,16


N-BSS138_SOT23 +3VSUS
RN50
SUS_SMBCLK 8 7
RUN_SMBCLK 6 5 +3VRUN
+3VRUN RUN_SMBDATA 4 3
SUS_SMBDATA 2 1
G

Q35
SUS_SMBDATA 8P4R-2.2KR
10,23 SUS_SMBDATA D S RUN_SMBDATA 8,16
A A
N-BSS138_SOT23
MICRO-STAR INT'L CO.,LTD

MSI
MS-N011
Size Document Description Rev
Custom 1.0
ICH7M_GPIO, CLK, SM
Date: Friday, April 11, 2008 Sheet 14 of 39

5 4 3 2 1
5 4 3 2 1

U30F
ICH7 M Power +3VRUN
D10 S-RB551V-30_SOD323
A4
A23
VSS[0] VSS[98] P28
R1
VSS[1] VSS[99]
VTT=> 0.954A +5VRUN
R165
0.94 A
B1
B8
VSS[2]
VSS[3]
VSS[100]
VSS[101]
R11
R12
6 mA B11 VSS[4] VSS[102] R13
+1_5VRUN=> 1.52A V5REF
U30E
VTT
B14
B17
VSS[5]
VSS[6]
VSS[103]
VSS[104]
R14
R15
100R/6 B20 R16
+3VRUN=> 336mA VSS[7] VSS[105]

VCC AUX
C155 C223 G10 L11 B26 R17
V5REF[1] Vcc1_05[1] VSS[8] VSS[106]
1u6.3Y4 X_0.1u16Y4 Vcc1_05[2] L12 B28 VSS[9] VSS[107] R18
V5REF
D +3VSUS=> 132mA V5REF_SUS
AD17

F6
V5REF[2] Vcc1_05[3]
Vcc1_05[4]
L14
L16
L17 C205 C198 C185 C197
C2
C6
C27
VSS[10]
VSS[11]
VSS[108]
VSS[109]
T6
T12
T13
D
V5REF_Sus Vcc1_05[5] VSS[12] VSS[110]
+5VRUN=> 6mA +3VSUS AA22 Vcc1_5_B[1]
Vcc1_05[6]
Vcc1_05[7]
L18
M11
0.1u16Y4 X_0.1u16Y4 0.1u16Y4 1u6.3Y4 D10
D13
VSS[13]
VSS[14]
VSS[111]
VSS[112]
T14
T15
D28 S-RB551V-30_SOD323 AA23 M18 D18 T16

CORE
+5VSUS=> 10mA +5VSUS
AB22
AB23
Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_05[8]
Vcc1_05[9]
Vcc1_05[10]
P11
P18
D21
D24
VSS[15]
VSS[16]
VSS[17]
VSS[113]
VSS[114]
VSS[115]
T17
U4
R376 10 mA AC23 T11 40 mA 56 mA 10 mA E1 U12
RTCVCC=> NA V5REF_SUS AC24
AC25
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_05[11]
Vcc1_05[12] T18
U11 +3VRUN +3VRUN +3VSUS
E2
E4
VSS[18]
VSS[19]
VSS[116]
VSS[117] U13
U14
10R/6 Vcc1_5_B[7] Vcc1_05[13] VSS[21] VSS[118]
AC26 Vcc1_5_B[8] Vcc1_05[14] U18 E8 VSS[22] VSS[119] U15
C456 C455 AD26 V11 E15 U16
Vcc1_5_B[9] Vcc1_05[15] VSS[23] VSS[120]
X_1u6.3Y4 0.1u16Y4 AD27 Vcc1_5_B[10] Vcc1_05[16] V12 F3 VSS[24] VSS[121] U17
AD28 Vcc1_5_B[11] Vcc1_05[17] V14 F4 VSS[25] VSS[122] U24
D26 V16 C186 C192 C193 F5 U25
Vcc1_5_B[12] Vcc1_05[18] VSS[26] VSS[123]
D27 Vcc1_5_B[13] Vcc1_05[19] V17 X_0.1u16Y4 0.1u16Y4 0.1u16Y4 F12 VSS[27] VSS[124] U26
D28 Vcc1_5_B[14] Vcc1_05[20] V18 F27 VSS[28] VSS[125] V2
E24 Vcc1_5_B[15] F28 VSS[29] VSS[126] V13
L8 L_ICH7_1.5V E25 V5 G1 V15
+1_5VRUN Vcc1_5_B[16] VccSus3_3/VccLAN3_3[1] VSS[30] VSS[127]
E26 Vcc1_5_B[17] VccSus3_3/VccLAN3_3[2] V1 G2 VSS[31] VSS[128] V24
X_80L3A/8 F23 W2 G5 V27
L_ICH7_1.5V Vcc1_5_B[18] VccSus3_3/VccLAN3_3[3] VSS[32] VSS[129]
0.77 A F24 Vcc1_5_B[19] VccSus3_3/VccLAN3_3[4] W7 G6 VSS[33] VSS[130] V28
G22 VTT G9 W6
Vcc1_5_B[20] VSS[34] VSS[131]
G23 U6 14 mA G14 W24

ICH7-M PART F
CP17 C216 Vcc1_5_B[21] Vcc3_3/VccHDA VSS[35] VSS[132]
H22 Vcc1_5_B[22] G18 VSS[36] VSS[133] W25

VCCA3GP
10u10Y8 C215 C184 C179 H23 R7 G21 W26
Vcc1_5_B[23] VccSus3_3/VccSusHDA C143 VSS[37] VSS[134]
X_0.1u16Y4 X_0.1u16Y4 0.1u16Y4 J22 Vcc1_5_B[24] G24 VSS[38] VSS[135] Y3
X_COPPER J23 AE23 C176 C168 X_10u10Y8 G25 Y24
Vcc1_5_B[25] V_CPU_IO[1] VSS[39] VSS[136]
K22 Vcc1_5_B[26] V_CPU_IO[2] AE26 X_0.1u16Y4 0.1u16Y4 G26 VSS[40] VSS[137] Y27
CP16 K23 AH26 H3 Y28
Vcc1_5_B[27] V_CPU_IO[3] VSS[41] VSS[138]
L22 Vcc1_5_B[28] H4 VSS[42] VSS[139] AA1
C L23 AA7 +3VRUN H5 AA24 C
X_COPPER Vcc1_5_B[29] Vcc3_3[3] VSS[43] VSS[140]
M22 Vcc1_5_B[30] Vcc3_3[4] AB12 H24 VSS[44] VSS[141] AA25
M23 Vcc1_5_B[31] Vcc3_3[5] AB20 H27 VSS[45] VSS[142] AA26
N22 Vcc1_5_B[32] Vcc3_3[6] AC16 H28 VSS[46] VSS[143] AB4
C201 C233 C191 N23 AD13 C474 C473 J1 AB6

IDE
Vcc1_5_B[33] Vcc3_3[7] VSS[47] VSS[144]
X_0.1u16Y4 X_0.1u16Y4 0.1u16Y4 P22 Vcc1_5_B[34] Vcc3_3[8] AD18 X_0.1u16Y4 X_0.1u16Y4 J2 VSS[48] VSS[145] AB11
P23 Vcc1_5_B[35] Vcc3_3[9] AG12 J5 VSS[49] VSS[146] AB14
R22 Vcc1_5_B[36] Vcc3_3[10] AG15 J24 VSS[50] VSS[147] AB16
R23 AG19 +3VRUN J25 AB19
Vcc1_5_B[37] Vcc3_3[11] VSS[51] VSS[148]
R24 Vcc1_5_B[38] 0.27 A J26 VSS[52] VSS[149] AB21
R25 Vcc1_5_B[39] Vcc3_3[12] A5 K24 VSS[53] VSS[150] AB24
R26 Vcc1_5_B[40] Vcc3_3[13] B13 K27 VSS[54] VSS[151] AB27
T22 Vcc1_5_B[41] Vcc3_3[14] B16 K28 VSS[55] VSS[152] AB28
T23 B7 C177 C173 C225 L13 AC2
+3VRUN Vcc1_5_B[42] Vcc3_3[15] VSS[56] VSS[153]
T26 C10 X_0.1u16Y4 0.1u16Y4 0.1u16Y4 L15 AC5

PCI
Vcc1_5_B[43] Vcc3_3[16] VSS[57] VSS[154]
T27 Vcc1_5_B[44] Vcc3_3[17] D15 L24 VSS[58] VSS[155] AC9
+1_5VRUN T28 F9 L25 AC11
R337 L28 Vcc1_5_B[45] Vcc3_3[18] VSS[59] VSS[156]
50 mA U22 Vcc1_5_B[46] Vcc3_3[19] G11 L26 VSS[60] VSS[157] AD1
+1_5V_DMIPLL U23 G12 M3 AD3
X_1u500mA_0805 C464 Vcc1_5_B[47] Vcc3_3[20] RTCVCC VSS[61] VSS[158]
V22 Vcc1_5_B[48] Vcc3_3[21] G16 M4 VSS[62] VSS[159] AD4
1R1%6 X_0.1u16Y4 V23 M5 AD7
CP22 C425 C421 Vcc1_5_B[49] VSS[63] VSS[160]
W22 Vcc1_5_B[50] VccRTC W5 M12 VSS[64] VSS[161] AD8
0.1u16Y4 10u10Y8 W23 M13 AD11
Vcc1_5_B[51] C183 C187 VSS[65] VSS[162]
Y22 Vcc1_5_B[52] VccSus3_3[1] P7 M14 VSS[66] VSS[163] AD15
X_COPPER Y23 0.1u16Y4 0.1u16Y4 M15 AD19
Vcc1_5_B[53] +3VSUS VSS[67] VSS[164]
VccSus3_3[2] A24 45 mA M16 VSS[68] VSS[165] AD23
B27 Vcc3_3[1] VccSus3_3[3] C24 M17 VSS[69] VSS[166] AE2
VccSus3_3[4] D19 M24 VSS[70] VSS[167] AE4
+1_5VRUN VCCDMIPLL AG28 D22 M27 AE8
VccDMIPLL[1] VccSus3_3[5] VSS[71] VSS[168]
VccSus3_3[6] G19 M28 VSS[72] VSS[169] AE11
B
0.64 A AB7 Vcc1_5_A[1] N1 VSS[73] VSS[170] AE13
B
AC6 K3 C231 C235 C212 C211 N2 AE18
Vcc1_5_A[2] VccSus3_3[7] VSS[74] VSS[171]
AC7 Vcc1_5_A[3] VccSus3_3[8] K4 X_0.1u16Y4 0.1u16Y4 0.1u16Y4 X_0.1u16Y4 N5 VSS[75] VSS[172] AE21
ARX
C174 C157 AD6 K5 N6 AE24
Vcc1_5_A[4] VccSus3_3[9] VSS[76] VSS[173]
0.1u16Y4 0.1u16Y4 AE6 Vcc1_5_A[5] VccSus3_3[10] K6 N11 VSS[77] VSS[174] AE25
AF5 Vcc1_5_A[6] VccSus3_3[11] L1 N12 VSS[78] VSS[175] AF2
AF6 Vcc1_5_A[7] VccSus3_3[12] L2 N13 VSS[79] VSS[176] AF4
+1_5VRUN AG5 L3 N14 AF8
Vcc1_5_A[8] VccSus3_3[13] VSS[80] VSS[177]
USB

AH5 Vcc1_5_A[9] VccSus3_3[14] L6 N15 VSS[81] VSS[178] AF11


L29 L7 N16 AF27
+1_5V_SATAPLL VccSus3_3[15] VSS[82] VSS[179]
50 mA AD2 VccSATAPLL VccSus3_3[16] M6 N17 VSS[83] VSS[180] AF28
X_4.7u100mA_8 M7 N18 AG1
VccSus3_3[17] +1_5VRUN VSS[84] VSS[181]
+3VRUN AH11 Vcc3_3[2] VccSus3_3[18] N7 N24 VSS[85] VSS[182] AG3
CP25 C430 C431 N25 AG7
VSS[86] VSS[183]
10u10Y8 X_0.1u16Y4 AB10 Vcc1_5_A[10] Vcc1_5_A[19] AB17 N26 VSS[87] VSS[184] AG11
C414 AB9 AC17 P3 AG14
X_COPPER Vcc1_5_A[11] Vcc1_5_A[20] VSS[88] VSS[185]
0.1u16Y4 AC10 Vcc1_5_A[12] P4 VSS[89] VSS[186] AG17
ATX

+1_5VRUN AD10 T7 C224 C218 P12 AG20


Vcc1_5_A[13] Vcc1_5_A[21] VSS[90] VSS[187]
AE10 Vcc1_5_A[14] Vcc1_5_A[22] F17 0.1u16Y4 X_0.1u16Y4 P13 VSS[91] VSS[188] AG25
AF10 Vcc1_5_A[15] Vcc1_5_A[23] G17 P14 VSS[92] VSS[189] AH1
AF9 Vcc1_5_A[16] P15 VSS[93] VSS[190] AH3
AG9 Vcc1_5_A[17] Vcc1_5_A[24] AB8 P16 VSS[94] VSS[191] AH7
C422 C423 AH9 AC8 P17 AH12
Vcc1_5_A[18] Vcc1_5_A[25] VSS[95] VSS[192]
1u6.3Y4 X_0.1u16Y4 P24 VSS[96] VSS[193] AH23
E3 K7 TP_VCCSUS1 T25 P27 AH27
VccSus3_3[19] VccSus1_05[1] VSS[97] VSS[194]
ICH7-M 17mA from +3VSUS
C1 C28 TP_VCCSUS2 T36 INTEL-82801GBM-B0-RH
+3VSUS VccUSBPLL PARTE VccSus1_05[2]
VccSus1_05[3] G20 TP_VCCSUS3 T26 +1_5VRUN
T34 TP_VCCSUS4 AA2 VccSus1_05/VccLAN1_05[1]
Vcc1_5_A[26] A1
T23 TP_VCCSUS5 Y7 H6
+1_5VRUN VccSus1_05/VccLAN1_05[2] Vcc1_5_A[27]
A Vcc1_5_A[28] H7 A
C465 10mA 30mA from +3VSUS J6 C219
Vcc1_5_A[29]
X_0.1u16Y4 USB CORE Vcc1_5_A[30] J7 X_0.1u16Y4

C475 INTEL-82801GBM-B0-RH
X_0.1u16Y4
MICRO-STAR INT'L CO.,LTD
PIN AA2,Y7,K7,C28,G20 : VccSus 1.05V for RTCVCC MSI
MS-N011
Size Document Description Rev
Custom 1.0
ICH7M_POWER
Date: Friday, April 11, 2008 Sheet 15 of 39

5 4 3 2 1
A B C D E

CLK Gen ICS9LPRS113


CLOCK GEN STRAPING
U9 RN45
+3VRUN R107 10K/4 CK_RLATCH 16 59 CLK_CPU_BCLK_R 1 2 CLK_CPU_BCLK 2
RLATCH** CPUT_L0*** CLK_CPU_BCLK#_R
CPUC_L0*** 58 3 4 CLK_CPU_BCLK# 2
VR_PG_CLKEN 23 5 6 CLK_MCH_BCLK 4 1 => Pin21/22 96MHz
14 VR_PG_CLKEN VTT_PG/WOL_STOP# CLK_MCH_BCLK_R 0 => Pin21/22 100MHz
1
CPUT_L1F*** 56 7 8 CLK_MCH_BCLK# 4 1
8,14 RUN_SMBCLK 61 55 CLK_MCH_BCLK#_R
SCLK CPUC_L1F*** 8P4R-33R/4
8,14 RUN_SMBDATA 62 SDATA
17 EC_FSBOC1 EC_FSBOC1 4 21 CLK_DOT96 5
EC_FSBOC0 DOC_1** DOT96T_LR/PCIeT_LR0 GSEL R102 4.7K/4
17 EC_FSBOC0 5 DOC_0** DOT96C_LR/PCIeC_LR0 22 CLK_DOT96# 5 +3VRUN
FREERUN 2 24 CLK_GFX_REFCLKP 5 R116 X_4.7K/4
R109 X_1K/4 SEL_STOP 25MHz_0F_2x/PECLKREQ0#/Freerun* PCIeT_LR1
14 SATA_CLKREQ# 3 25MHz_1F/PECLKREQA#/SEL_STOP** PCIeC_LR1 25 CLK_GFX_REFCLKN 5
R119 22R/4 FSA 18
14 CLK_USB48 R79 33R/4 FSC FSLA/USB_48MHz
14 CLK_14M_ICH 71 FSLC/REF0_2x PCIeT_LR2/PECLKREQ4# 26
27 LAN_CLK_EN# R111 1K/4 LAN_CLKREQ# 18
R121 33R/4 TIP_EN PCIeC_LR2/PECLKREQ6#
22 CLK_CARD48M 19 ITP_EN/24_48MHz*
29 PCI_STOP#113 R115 0R/4 PM_STPPCI# 14 L:PCICLK4
*PCI_STOP#/PCIeT_LR3 CPU_STOP#113 R112 0R/4 H:RESET*
remove R96 when MP. 7 PCICLK0 *CPU_STOP#/PCIeC_LR3 30 PM_STPCPU# 14
8 to be WDT rest=> HI
R92 33R/4 LPC_EC_CLK_R PCICLK1
17 LPC_EC_CLK 9 FSD/PCICLK2_3x** PCIeT_LR4 31
17 LPC_DEBUG R96 33R/4 FSB 13 32
R100 33R/4 RESET# FSLB/PCICLK3_2x PCIeC_LR4 RESET# R103 4.7K/4
14,17 WTDG# 14 SELRSET/RESET#/PCICLK4** +3VRUN
13 CLK_PCI_ICH R117 33R/4 GSEL 15 34 PCIE_3GPLL_CLK_EN# R113 1K/4 MCH_CLKREQ# 5
GSEL/PCICLK5** PCIeT_LR5/PECLKREQ7# MINI_PCIE1_CLK_EN# R114 1K/4
PCIeC_LR5/PECLKREQ8# 35 MINI_PCIE_CLKREQ# 23
+3VRUN FB3 X_80L3A/8 VCC3_CLK1 10 VDDPCI
11 VDDPCI PCIeT_LR6 37 CLK_PCIE_LAN 18
C101 C87 C90 C96 C85 C81 41 36 CLK_PCIE_LAN# 18
X_0.1u16Y4 CP7 X_10u10Y8 0.1u16Y4 0.1u16Y4 0.1u16Y4 0.1u16Y4 VDDPCIEX PCIeC_LR6
51 VDDI/O
X_COPPER 52 39 CLK_PCIE_3GPLL 5 113 110
VDDI/O PCIeT_LR7 TIP_EN=0 => PCIEX9, TIP_EN=0 => 48MHz,
57 VDDCPU PCIeC_LR7 38 CLK_PCIE_3GPLL# 5
TIP_EN=1 => CPU_ITP TIP_EN=1 => 24MHz
+3VRUN FB4 X_80L3A/8 VCC3_CLK2 17 43 CLK_MINI_PCIE1 23
VDD48 PCIeT_LR8
PCIeC_LR8 42 CLK_MINI_PCIE1# 23
C108 C106 C107 67
X_0.1u16Y4 CP9 0.1u16Y4 0.1u16Y4 VDDREF TIP_EN R108 4.7K/4
66 VDDSATA CPUCLKT_ITP/PCIeT_LR9 45
2 X_COPPER 1 44 2
VDD25MHz CPUCLKC_ITP/PCIeC_LR9
54 VDDA PCIeT_LR10 48
PCIeC_LR10 47
53 GNDA
6 GNDPCI PCIeT_LR11 50 CLK_PCIE_ICH 13
12 GNDPCI PCIeC_LR11 49 CLK_PCIE_ICH# 13
20 GND
28 GND SATACLKT_LR 65 CLK_SATA 12
+3VRUN FB1 X_80L3A/8 VCC3_CLK3 33 64 CLK_SATA# 12 FREERUN R85 4.7K/4 +3VRUN
GND SATACLKC_LR
40 GND
C60 C66 C72 C75 C76 46 69 XTAL_IN C73 R84 X_4.7K/4
X_0.1u16Y4 10u10Y8 0.1u16Y4 0.1u16Y4 0.1u16Y4 GND X1
60 GND
CP2 63 22p50N4
GND

2
3
X_COPPER 70 GND Y1
72 GND
73 68 XTAL_OUT
PAD X2 14.31818MHZ20P
+3VRUN FB2 X_80L3A/8 VCC3_CLK4 ICS9LPRS113

1
4
C67 C77 C80
X_0.1u16Y4 X_10u10Y8 0.1u16Y4
CP3 C74 Selects pin 29/830
X_COPPER 22p50N4 1 = PCI_STOP#/CPU_STOP#
0 =PCIEX CLK output
LPC_EC_CLK_R

FSC SEL_STOP R88 4.7K/4 +3VRUN


VTT
VTT R86 X_4.7K/4
3 R307 R78 3

10K/4 10K/4 +3VRUN

R131 R125
R128 R133 R110
1K/4 1K/4
1K/4 1K/4
1K/4
EMI
VR_PG_CLKEN
EC_BSEL0 17
2,17 CPU_BSEL0 CPU_BSEL0 R105 10K/4 FSA CLK_PCI_ICH EMC18 X_10p25N4
EC_BSEL1 17
2,17 CPU_BSEL1 CPU_BSEL1 R127 10K/4 FSB LPC_DEBUG EMC15 10p25N4

D
LPC_EC_CLK EMC13 10p25N4
30 VR_PWRGD_CLKEN# G Q47
N-2N7002 CLK_USB48 EMC19 X_22p50N4
CLK_14M_ICH EMC11 X_10p25N4

S
R118 X_10K/4 EC_BSEL0 R130 X_1K/4
R101 X_10K/4 EC_BSEL1 R99 X_1K/4 CLK_CARD48M EMC96 X_10p25N4

R129 1K/4 MCH_BSEL0 5


R126 1K/4 De-Glitch of VR_PG_CLKEN +3VSUS
MCH_BSEL1 5

For EC code NOT ready


R194
10K/4
CPU Table CLK Gen 113

BSEL[2] BSEL[1] BSEL[0] BCLK BSEL[2] BSEL[1] BSEL[0] BCLK Q60


4 2 6 VR_PG_CLKEN 4
1
L L L 100MHZ H L H 100MHZ 17 ALLSYSPG ALLSYSPG R193 10K/4 5 3
4

L L H 133MHZ L L H 133MHZ
NN-CMKT3904_SOT363-6-RH
MICRO-STAR INT'L CO.,LTD
L H L RESERVED L H L 200MHz
MSI
MS-N011
L H H 166MHZ L H H 166MHZ Size Document Description Rev
Custom 1.0
CLK GEN_113
Date: Friday, April 11, 2008 Sheet 16 of 39

A B C D E
5 4 3 2 1

+3VALW
U14 +3VALW

14 SIRQ SIRQ 3 9 L6
LPC_FRAME# SERIRQ VCC
12 LPC_FRAME# 4 LFRAME# VCC 22 For SW Debug
16 LPC_EC_CLK 12 33
+5VSUS 38
PCICLK VCC VCC
96 80L700mA-150-RH port 80
14 P_CLKRUN# GPIO1D/CLKRUN# VCC
RN48 12 LAD0 LAD0 10 111
VDIMM_OV1 LAD1 LAD0 LPC VCC C131 C130 C120

15
1 2 12 LAD1 8 LAD1 VCC 125
3 4 VTT_OV2 LAD2 7 I/F 0.1u16Y4 1u6.3Y4 10u10Y8
12 LAD2 LAD2
5 6 VTT_OV1 12 LAD3 LAD3 5 67 CP10 LPC_FRAME# 1
VDIMM_OV2 LPC_RST# LAD3 AVCC/AGND AVCC LAD3
7 8 13 LPC_RST# 13 GPIO05/PCIRST# AGND 69 1 2 2
LAD2 3
D X_8P4R-100K/4 KBRST# 2 11 X_COPPER LAD1 4 D
+3VALW 12 KBRST# H_A20GATE GPIO01/KBRST# GND LAD0
12 H_A20GATE 1 GPIO00/GA20 GND 24 5
KBSCI# 20 GND 35 L_LDRQ0# 6
R140 10K/4 14 KBSCI# ECRST# GPIO0E/SCI# GND 12 L_LDRQ0#
37 ECRST# GND 94 16 LPC_DEBUG 7
+3VRUN D9 113 SIRQ 8
RN55 KBIN0 GND LPC_RST#
55 GPIO30/KSI0/E51_TX(ISP) 9
1 2 KBSMI# KBIN1 56 10
GPIO31/KSI1 +5VRUN
3 4 KBRST# S-BAS40WS_SOD323-RH KBIN2 57 11
GPIO32/KSI2 +3VRUN
5 6 H_A20GATE C127 KBIN3 58 63 E_BSEL0 12
KBSCI# KBIN4 GPIO33/KSI3 GPI38/AD0 E_BSEL1
7 8 1u6.3Y4 59 GPIO34/KSI4 GPI39/AD1 64 13
KBIN5 60 ADC 65 T24 14
8P4R-10K/4 KBIN6 GPIO35/KSI5 Key Matrix GPI3A/AD2
61 GPIO36/KSI6 Scan GPI3B/AD3 66 T39
KBIN7 62

16
GPIO37/KSI7 JDP1
KBOUT0 39 21 EC_ADJ_FRQ0 21
KBOUT1 GPIO20/KSO0/TP_TEST GPIO0F/PWM0
40 GPIO21/KSO1/TP_PLL 23 EC_ADJ_FRQ1 21
RN49 KBOUT2 41 PWM GPIO10/PWM1 25 X_BH1X14HS-1.25PITCH_WHITE-RH
GPIO22/KSO2 BR-AD-ADJ 21
1 2 IMVP_PWRGD KBOUT3 42 / GPIO11/PWM2 34 CHIP_PWRGD
RSMRST# KBOUT4 GPIO23/KSO3/TP_ISP FAN GPIO19/PWM3 CHIP_PWRGD 5,14,19
3 4 43 GPIO24/KSO4
5 6 ENCHG KBOUT5 44 26 CPUFAN1 24 KBOUT0 1 2
KBOUT6 GPIO25/KSO5 GPIO12/FANPWM1 KBOUT1 CN1
7 8 45 GPIO26/KSO6 GPIO13/FANPWM2 27 3 4
KBOUT7 46 28 CPUFAN_TACH1 24 KBOUT2 5 6
8P4R-100K/4 KBOUT8 GPIO27/KSO7 GPIO14/FANFB1 KBOUT3 100p50N/8P4C
47 GPIO28/KSO8 GPIO15/FANFB2 29 7 8
KBOUT9 48
KBOUT10 GPIO29/KSO9 KB CONN

27
49 GPIO2A/KSO10 GPO3C 68 EC_FSBOC0 16
KBOUT11 50 70 EC_FSBOC1 16 KBOUT4 1 2
KBOUT12 GPIO2B/KSO11 GPO GPO3D KBOUT5 CN2 FPC1
51 GPIO2C/KSO12 GPO3E 71 3 4
R186 4.7K/4 SPI_SEL# KBOUT13 VTT_OV1 29 KBOUT6 FPC26P-B-1PITCH_BLACK-RH
52 GPIO2D/KSO13 GPO3F 72 5 6
KBOUT14 VTT_OV2 29 KBOUT7 100p50N/8P4C
53 GPIO2E/KSO14 7 8
H/W Strap for ENE 3310 KBOUT15 54 97 SPI_SEL#
GPIO2F/KSO15/E51_RX(ISP) GPXIOA00
81 GPIO48/KSO16 GPXIOA01 98 PM_PWRBTN# 14 26
C 82 99 CAMERA_ON# 23 KBOUT8 1 2 25 C
GPIO49/KSO17 GPXIOA02 KBOUT9 CN3 KBOUT15
100 BT_PWR_ON 22 3 4 24
XIOAGPXIOA03 101 KBOUT10 5 6 KBOUT14 23
GPXIOA04 WLAN_PWRON 23
102 VR_ON VR_ON 30 KBOUT11 7 8 100p50N/8P4C KBOUT13 22
LED_NUM# GPXIOA05 KBOUT12
24 LED_NUM# 36 GPIO1A/NUMLED GPXIOA06 103 ENCHG_2P 26 21
+3VALW LED_CAP# 91 LED 104 KBOUT11 20
24 LED_CAP# GPIO53/E51_TMR1/CAPLED GPXIOA07 ENCHG 25,26
24 LED_SCR# LED_SCR# 93 105 LED_BLUETOOTH# 24 KBOUT12 1 2 KBOUT10 19
GPIO55/E51_INT0/SCRLED GPXIOA08 KBOUT13 CN4 KBOUT9
GPXIOA09 106 LED_POWER# 24 3 4 18
R159 4.7K/4 BATCLK_M 107 LED_CHARGE# 24 KBOUT14 5 6 KBOUT8 17
GPXIOA10 KBOUT15 100p50N/8P4C KBOUT7
28 VDIMM_OV1 83 GPIO4A/PSCLK1/P80_CLK GPXIOA11 108 LED_BATLOW# 24 7 8 16
R163 4.7K/4 BATDATA_M 84 KBOUT6 15
28 VDIMM_OV2 GPIO4B/PSDAT1/P80_DAT
85 KBOUT5 14
24 LED_ECO# GPIO4C/PSCLK2 PS2
86 109 SUS_ON 27 For EMI KBOUT4 13
24 LED_TURBO# GPIO4D/PSDAT2 I/F GPXIOD0
TP_CLK 87 110 RUN_ON 27 KBIN7 12
24 TP_CLK GPIO4E/PSCLK3 GPXIOD1
TP_DATA 88 112 RSMRST# 14 KBOUT3 11
24 TP_DATA GPIO4F/PSDAT3 GPXIOD2
114 PRE_CHG 26 KBIN6 10
XIOD GPXIOD3 115 KBIN5 9
GPXIOD4 THERMAL_INT# 2
116 GPXIOD5 KBOUT2 8
GPXIOD5 GPXIOD6 KBOUT1
25 BATCLK_M 77 GPIO44/SCL1 GPXIOD6 117 7
78 118 DIMM_ON 28 KBIN4 6
25 BATDATA_M GPIO45/SDA1 SM BUS GPXIOD7
2 SMB_CPU_CLK 79 KBIN3 5
GPIO46/SCL2 32KXI C188 18p50N4 KBIN2
2 SMB_CPU_DATA 80 GPIO47/SDA2 4
KBOUT0 3
119 EC_RD# KBIN1 2
SPIDI/RD#

2
+3VRUN PWR_SW_KEY# 6 SPI 120 EC_WR# R195 KBIN0 1
24 PWR_SW_KEY# GPIO04 SPIDO/WR#
14 I/F 126 SPICLK R80 33R/4 EC_SPICLK X_10M/6 Y3
14,16 WTDG# GPIO07/GPWU SPICLK/GPIO58
15 128 EC_CS# 32.768KHZ12.5P_S-RH-2
14 PM_SLP_S4#

1
GPIO08 SPICS#/SELMEM#
14 PM_SLP_S3# 16 GPIO0A/GPWU For EMI
R155 17 32KXO C189 18p50N4
16 EC_BSEL0 GPIO0B/ESB_CLK
10K/4 16 EC_BSEL1 18 GPIO0C/ESB_DAT
21 LID# 19 30 T10

28
B GPIO0D GPIO UART GPIO16/E51_TX B
CP13 2 1 X_COPPER
27 SUSPWROK
ALLSYSPG
32
73
GPIO18 GPIO17/E51_RX 31 FFC KB
28 +1_8VDIMM_PG GPIO40
14,30 IMVP_PWRGD 74 GPIO41 GPIO59/TEST_CLK 127 VRM_PGD_IN
VRM_PGD_IN 30 N5A-26F0340-A81
CP12 2 1 X_COPPER 25,26 AC_IN# 75
29 VTT_PWRGD GPI42 TOP
25 BAT_IN# 76 GPI43
CP11 2 1 X_COPPER 89 122 32KXI VRM_PGD_IN rise after VR_ON 650us
29 +1_5VRUN_PG 14 KBSMI# GPIO50/SELIO# XCLK XCLKI 123 32KXO
XCLKO
24 LED_ACPI# 90 GPIO52/E51_CS#
16 ALLSYSPG 24 LED_WLAN# 92 GPIO54/E51_TMR0
25 AC_CTL 95 GPIO56/E51_INT1 V18R 124 C438 10u6.3X8
GPIO57 121 GPIO57/XCLK32K +3VSUS

KB3310_LQFP128 GPXIOD5 R411 X_10K/4


R397 10K/4 for on-board DDR SPD ROM select
check if can remove
+3VRUN VTT GPIO5 GPIO6 GPIO57 DDR cfg-
+3VSUS
Samsung 1G
GPXIOD6 R407 X_10K/4 0 0 0 Hynix 1G FS/FH
8
6
4
2

JSPI1 R408 10K/4


RN46 BIOS +3VALW
0 1 0 Mira 512M FM
11
8P4R-4.7K/4
+3VALW
7
5
3
1

1
Q27 C471 2 +3VSUS X X X RESERVED n/a
B

N-MMBT3904_NL_SOT23 EC_RD# 3
0.1u10X4 EC_WR# 4 GPIO57 R409 X_10K/4
E_BSEL0 U31 R389 EC_CS# R410 10K/4
C E CPU_BSEL0 2,16 5 X X X RESERVED n/a
E_BSEL1 C E EC_CS# 1 8 4.7K/4 EC_SPICLK 6
A CPU_BSEL1 2,16 CS VCC A
EC_RD# 2 7 SPI_HOLD# 7
DO HOLD EC_SPICLK
3 WP CLK 6 8
N-MMBT3904_NL_SOT23 4 5 EC_WR# SPI_HOLD# 9
B

Q26 GND DIO C450 10


W25X80VSSIG-RH
X_22p50N4

MICRO-STAR INT'L CO.,LTD


12

X_BH1X10HS-1.25PITCH-RH

MSI
MS-N011
Size Document Description Rev
Custom 1.0
ENE KB3310
Date: Tuesday, April 15, 2008 Sheet 17 of 39

5 4 3 2 1
A B C D E

RTL8102E 10/100M LAN


+3VRUN

U18

R256 PCIE_LAN_TXP 23 29 PCIE_LAN_RXP_C C286 0.1u10X4 PCIE_LAN_RXP 13


13 PCIE_LAN_TXP PCIE_LAN_TXN HSIP HSOP PCIE_LAN_RXN_C C283 0.1u10X4
4 1K/4 13 PCIE_LAN_TXN 24 HSIN HSON 30 PCIE_LAN_RXN 13 4

13 LAN_RST# LAN_RST# 20 19 PCIE_WAKE# PCIE_WAKE# 14,23


LAN_ISO PERSTB LANWACKB
36 ISOLATEB
16 CLK_PCIE_LAN CLK_PCIE_LAN 26
R255 CLK_PCIE_LAN# REFCLK_P
16 CLK_PCIE_LAN# 27 REFCLK_N
15K1%4
C295 27p50N4 3 TR_D0+
CLK_LANI MDIP0 TR_D0-
60 CKXTAL1 MDIN0 4

2
Y4 CLK_LANO 61 6 TR_D1+
CKXTAL2 MDIP1 TR_D1-
25MHZ20p_S 7

1
MDIN1
C306 27p50N4 R270 2.49K1%4 RSET 64 9
RSET NC
NC 10

VDD1P2 63 12 +3VSUS
VCTRL12D/VCTRL15 NC
VDD1P2 1 VCTRL12A/ VCTRL18 NC 13
C297 16
C301 C323 VDD33 R36
37 VDD33
10u6.3Y12 X_0.1u10X4 C308 46 48 3.6K/4
VDD33 EESK

10u6.3Y12
X_0.1u10X4 53 VDD33 EECS 44
47 LAN_EEDI
EEDI/AUX
+3VSUS 2 AVDD33 EEDO 45
+3VSUS
LED0 57

+1
VDD1P2 15 DVDD12/VDD15 LED1 56
3 21 55 EC21 C287 C277 C274 C311 3
DVDD12/VDD15 LED2 C100u6.3pSO 10u10Y8 0.1u10X4 0.1u10X4 0.1u10X4
43 54

2
DVDD12/VDD15 LED3
49 DVDD12/VDD15
58 AVDD12/VDD15
MAPIN0/NC 17
VDD1P2 28 EVDD12/EVDD18 MAPIN1/NC 18
TEST0/NC 34
22 NC/EVDD18 TEST1/NC 35
C291 5 39
NC/AVDD18 TEST2/NC
0.1u10X4 8 NC/AVDD18 TEST3/NC 40
TEST4/NC 41
11 42 VDD1P2
NC TEST5/NC
14 NC Place near pin15,21,43,49,58
32 NC
38 NC
52 NC
59 50 C276 C282 C292 C300 C313
NC GPI/NC 0.1u10X4 X_0.1u10X4 X_0.1u10X4 0.1u10X4
62 NC GPO/NC 51 0.1u10X4

EGND
EGND
33

GND
16 LAN_CLKREQ# CLKREQB/NC

RTL8102E
65
25
31

2 2

LAN MAGNETICS

MEC2
10
TRD0+ 8
T1
4
5

TRD0- 7
TR_D0+ 1 TX 16 TRD0+ TRD1+ 6
VDD1P2 2 15 MCT0 R32 75R/4 R250 75R/4 5
POWER TR_D0- 3 14 TRD0- 4
TR_D1+ 6 RX 11 TRD1+ TRD1- 3
BOOT DEVICE VDD1P2 VDD1P8 VDD33 7 10 MCT1 R31 75R/4 LANGND R251 75R/4 2
C32 C34 TR_D1- 8 9 TRD1- 1
8101E (378.3mW) 1.5V 1.8V 3.3V 0.1u10X4 0.1u10X4 LAN1
NS0013B LF-RH
ESD
12
13

LAN-RJ45S-RH
8102E 1.2V NC 3.3V
C275
365mA L05-0100440-B09 1000p2000X1808

MEC1

MEC3
OL5-0100010 N55-08F0250-A10
1 1
Bottom

MICRO-STAR INT'L CO.,LTD

MSI
MS-N011
Size Document Description Rev
A3 1.0
LAN_RTL8102E/8101E
Date: Friday, April 11, 2008 Sheet 18 of 39

A B C D E
5 4 3 2 1

VDD3V ADD5V 12mA


ADD5V
U25
6 18 SPK_OUT_R+
PVDD ROUT+ SPK_OUT_R+ 20
R66 X_10K/4 CODEC_HDA_SDIN0 15 14 SPK_OUT_R-
PVDD ROUT- SPK_OUT_R- 20

25
38
16 VDD

1
9
U24 4 SPK_OUT_L+ ADD5V
LOUT+ SPK_OUT_L+ 20
INT_LINE2_L 5 8 SPK_OUT_L-

DVDD2

AVDD1
AVDD2
DVDDCORE
LIN- LOUT- SPK_OUT_L- 20
47 36 FRONT_OUT_R INT_LINE2_R 17
SPI/EAPD FRONT-R FRONT_OUT_L RIN- R301
D
FRONT-L 35 NC 12 D
48 SPO X_100K/4
19 MUTE_INTSPKR
C366 0.47u10X6 RIN+ SHUTDOWN
12 CODEC_HDA_SDOUT 5 SDATAO SURR-R 41 7 RIN+
R65 0R/4 AZ_SDIN0 8 39 C371 0.47u10X6 LIN+ 9
12 CODEC_HDA_SDIN0 SDATAIN SURR-L LIN+ C369 C370
12 CODEC_HDA_SYNC 10 SYNC
12 CODEC_HDA_RST# 11 1u16Y6 X_10u10Y8
RESET# C372 X_0.47u10X6 BYPASS
CCEN 43 10 BYPASS GND 11
12 CODEC_HDA_BITCLK 6 44 13 R71
BCLK LFE C368 10u10Y8 GAIN0 GND 1K/4
2 GAIN0 GND 1
GAIN1 3 20
GAIN1 GND
SIDESURR-R 46
45 AGND APA2031RI-TRL_TSSOP20-LF
SIDESURR-L
2 GPIO0 Internal Speaker Amp AGND
3 GPIO1 CHIP_PWRGD 5,14,17
LINE1-R 24
R302 20K1%4 13 23
20 MIC_JD SENSE A LINE1-L
34 SENSE B
R289 5.1K1%4
20 FRONT_JD
15 C341 1u6.3X8 INT_LINE2_R
LINE2-R C339 1u6.3X8 INT_LINE2_L
20 MIC_VREFOUT_R 32 MIC1-VREFO-R LINE2-L 14
ADD5V
20 MIC2_VREFOUT_L 30
28
MIC2-VREFO FOR APA2031
20 MIC_VREFOUT_L MIC1-VREFO-L
37 22 C347 2.2u6.3X5
LINE1-VREFO-R MIC1-R MIC_IN_R 20 ADD5V
29 21 C345 2.2u6.3X5 R295 X_1K/4 GAIN0
LINE1-VREFO-L MIC1-L MIC_IN_L 20
31 LINE2-VREFO
27 R297 1K/4 GAIN1
R294 10K/4 VREF C344 1u6.3X8
ADD5V 33 DCVOL MIC2-R 17
R288 20K1%4 40 16 C342 1u6.3X8
JDREF/NC MIC2-L INT_MIC 20
C354 C359
10u6.3X8 0.1u10X4 20 R296 1K/4 GAIN0 C353 C346 C365 C362
C CD_R C
19
DVSS1
DVSS2

AVSS1
AVSS2
AGND CD_GND R300 X_1K/4 GAIN1 10u10Y8 0.1u16Y4 0.1u16Y4 X_0.1u16Y4
12 PCBEEP CD_L 18

AGND ALC888DD-GR-A1
4
7

26
42

0.3A AGND
AGND
14 SPKR R278 X_10K/4 PC_BEEP
GAIN0 GAIN1 SE/BTL#
C335
C336 X_0.1u10X4 6dB 0 0 0
X_0.1u16Y4 AGND
10dB 0 1 0
AGND
15.6dB 1 0 0
21.6dB 1 1 0
4.3dB X X 1

B B

ANTIPOP CIRCUIT +5VSUS


EC2
FRONT_OUT_R R292 75R1% 1 2 C100u6.3pSO FORNT_OUT_R_ISO

D
+ FORNT_OUT_R_ISO 20
EC1
FRONT_OUT_L R290 75R1% 1 2 C100u6.3pSO FORNT_OUT_L_ISO 27 RUND_R G Q46
+ FORNT_OUT_L_ISO 20
N-AO3404_SOT23 ADD5V
1A

S
R72 R73
33R/4 33R/4
For EMI solution
C349 C355 C357 C360 C364
+5VSUS 4700p50X6 X_4700p50X6 0.1u16Y4 X_0.1u16Y4 10u10Y8
S

N-2N7002 N-2N7002 EMC79 0.1u16Y4


G G
R90 POWER ISOLATION (ANALOG 5V)
100K/4 R77 Q18 Q17 AGND EMC54 0.1u16Y4
D

0R/4

VDD3V +3VRUN AGND


D

Q23 Q19 Q21


5,14,17 CHIP_PWRGD G G G
1 2
N-2N7002 N-2N7002 N-2N7002
S

CP1 CP23 1 2 X_COPPER


C70 POP_PWRGD from EC3310 X_COPPER
X_1u16Y6 C52 C50 C51
A Use any NB_PWRGD "AND" with SLP_S3# CP24 1
A
2 X_COPPER
TO ensure POP_PWRGD 0.1u16Y4 X_0.1u16Y4 10u10Y8
0 => 1 after RUNPOWER ready
1 => 0 before RUNPOWER drop AGND
POWER ON/OFF/S3/S4 NOISE CONTROL D-S interchange POWER ISOLATION (CODEC 3V)
MICRO-STAR INT'L CO.,LTD

MSI MS-N011
Size Document Description Rev
Custom 1.0
ALC888S
Date: Friday, April 11, 2008 Sheet 19 of 39
5 4 3 2 1
5 4 3 2 1

R287
19 MIC2_VREFOUT_L
JSPK1 2.2K/4
BH1X4#S-1.25PITCH-RH

5
D SPK_OUT_L- 1 D
19 SPK_OUT_L-
SPK_OUT_L+ 2 Internal Speaker
19 SPK_OUT_L+
SPK_OUT_R+ 3 Internal MIC 1
19 SPK_OUT_R+ Connector INT_MIC 19
SPK_OUT_R- 4 2
19 SPK_OUT_R-

2
Connector

6
C343 D21

6
X_0.1u16Y4 X_ESD
C348 C350 C356 C361

1
220P50N4 220P50N4 220P50N4 220P50N4 AGND
AGND JMIC1
N32-1040430-H06 BH1X2S-1.25PITCH_WHITE-RH FOR EMI
Bottom AGND
AGND N32-1020290-H06
Bottom

MEC2
C C
R299 MIC1
2.2K/4
19 MIC_VREFOUT_R 19 MIC_JD 5
L21 300L300mA-350 4
19 MIC_IN_R 3
6
N54-06F0581-H06
19 MIC_IN_L 2 Bottom
1
L20 300L300mA-350
19 MIC_VREFOUT_L

MEC1