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UNIT – II
1. Define gate level modelling.
2. What are tristate gates?
3. Give the syntax of repeat construct.
4. Write the Verilog module for repeat construct.
5. Write the syntax of even construct.
6. Give the syntax of always construct.
7. Give the syntax of case statement.
8. Write the function for fork join construct
9. Draw a flowchart for execution of IF ELSE loop.
10. Define Strength and list out types of Strengths.
11. Write short note on Blocking and Non-Blocking statement.
12. What are Bi-directional Gates and List them.
13. Design an D flip flop with gate primitives?
14. Classify delays?
15. What is inter and intra assignment delay?
16. Design a JK flip flop using NAND gate?
17. What is net delay?
18. What are the advantages of Multiple always block?
19. What is AND gate primitive?
20. What is array of instances of primitives?
UNIT – III