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2017 2nd IEEE International Conference On Recent Trends in Electronics Information & Communication Technology (RTEICT), May 19-20,

2017, India

Design of Low Power Hamming Code Encoding,


Decoding and Correcting Circuits using Reversible
Logic
V. Shiva Prasad Nayak Chinthaparthi Madhulika Uppugunduri Pravali
Dept. of ECE, GITAM University, Dept. of ECE, GITAM University, Dept. of ECE, GITAM University,
shiva6221@gmail.com chinthaparthimadhulika@gmail.com pravaliuppugunduri@gmail.com

Abstract— An ideal communication relies on error detection corresponds to KT*log2 where K represents Boltzmann’s
and correction techniques for faultless data transmission. constant and T represents absolute temperature.
Hamming code is widely known among those techniques for Later, Charles Bennett [2,3] concluded that heat
single bit error detection and correction capacity. Low power dissipation in a digital circuit can be minimized or eliminated
circuit design yields many favorable conditions like increased by performing all the computations using reversible logic.
performance, system capacity, minimized cost etc. Reversible
Using reversible logic circuits, outputs can be recovered from
logic is an excellent approach to optimize heat dissipation and
information loss. As hamming code is designed using irreversible inputs and there is a one-to-one mapping between them. The
logic gates, there is undesired power dissipation. So, to improvise system can run both forward and backward. It facilitates to go
this downside, this paper elucidates the design of low power back at any point in the computation history. It also improves
hamming code using reversible logic gates which detects and the overall performance of the circuitry by allowing higher
corrects the error if any. The mathematical analysis of quantum densities and higher speeds by reducing power dissipation.
cost calculation, garbage outputs, delay and power is presented in In this paper, the design flow of Hamming code encoding
this paper. Finally, simulation results are attained by using and decoding circuits explained is divided into three sections.
cadence virtuoso. The power dissipation for the proposed design Existing work is illustrated in Section II. The proposed design
PW when the power of individual components is added
is 7.2P
is given in Section III. The simulation and power consumption
theoretically. The overall power of the circuit is 5.8PW.
of each circuit is given in Section IV. The mathematical
Keywords— Quantum Cost (QC), Garbage Outputs (GO), analysis of Hamming code encoding and decoding circuits is
Fredkin gate (F), Feynman gate (FG), Double Feynman gate explicated in Section V. Section VI concludes the paper.
(F2G), Encoder Circuit (EC), Check bit generator (CG), Error
detection and Correction circuit (EDC). Introduction (Heading 1) II. EXISTING WORK
I. INTRODUCTION
In the existing paper [4], hamming code encoding and
Digital data transmission is the base of all modern-day decoding circuits are implemented using conventional
applications. During its way from the transmitter to receiver, irreversible logic gates. To perform error detection, the circuit
errors are induced to data due to noise and environmental adds one or more extra bits called parity bits to the existing
interferences. An error occurs when a bit is altered between information bits while transmission of data. This is called
transmitter and receiver. To eliminate these errors, error encoding. Decoding involves calculation of check bits which
detection and error correction circuits are built into all digital is illustrated in the existing work. These check bits help to
circuits. Error correction adds redundancy bits to the existing detect and correct the error. (7, 4) Hamming Code gives out 7-
data to make the data transmission resistant to external bit code by encoding 4 data bits by adding 3 parity bits. With
disturbances. these parity bits, it can not only detect single bit error but it
Various error detection and correction codes are in can also correct them.
existence such as parity checking, cyclic redundancy check,
etc. Hamming code is the most commonly used error checking This paper determines the total number of gates,
and error correction code as it is easy to implement. It adds garbage outputs, quantum cost, and delay and power
limited redundancy bits to the data, keeping the code simple. specifications of proposed circuit design of reversible
However, Hamming code is a single error correcting code. It hamming code by using definitions from [1].
can be used only when the error rate is low.
Hamming code circuit, when constructed using III. PROPOSED DESIGN FOR REVERSIBLE HAMMING
conventional irreversible gates, dissipates a huge amount of CODE ENCODING, DECODING AND CORRECTING
power. Power consumption is the primary consideration in any CIRCUITS
circuit designing. Hence in this paper, the irreversible gates
are replaced with reversible gates, thereby reducing the overall This paper presents power optimized hamming code
power consumption of the circuit. encoding and decoding circuits using reversible logic for
Landauer states that while transmitting data certain detection and correction of single bit errors. This paper
amount of energy is dissipated for each bit lost. This energy designed three reversible blocks, one to encode the existing
978-1-5090-3704-9/17/$31.00 © 2017 IEEE
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2017 2nd IEEE International Conference On Recent Trends in Electronics Information & Communication Technology (RTEICT), May 19-20, 2017, India

data by adding parity bits. The second block generates check


bits. These check bits aid in error detection. If any error is
introduced to the code word during the transmission process,
the third block detects and decodes the check bits, finds out
the faulty bit and corrects it, thereby giving final error free
output. Each of the above circuitry is explained in the coming
sections. In Section 3.1 explains the design of Hamming Code
Encoder Reversible logic cell, section 3.2 explains the design
of Hamming Code Check Bit Generator Reversible Logic Cell
and section 3.3 elucidates the Error Detection and Correction
circuit.
Figure. 2 CG Logic Cell Architecture
A. EC Reversible Logic Cell
EC is constructed using three F2G gates and two FG C. Proposed EDC Reversible Logic Cell
gates. EC has low quantum cost and zero garbage outputs By now, the error position has been determined. To
thereby enhancing the power consumption of the circuit. It has correct the bit, we must invert the bit located in the position
four inputs and seven outputs. The four inputs are data bits. C4C2C1. This is done using EDC cell. It consists of a decoder
EC cell calculates parity bits for the given data. The parity bits which takes C4C2C1 as input and identifies the position of the
are placed in the places that are numbered in powers of 2. The error. The decoder has been implemented using Fredkin gates.
parity bits are calculated using the algorithm suggested in [4]. The FG gates at the end act as EXOR gates. EXOR
The output of FG and F2G gates is simply XOR operation of gate acts as an inverter when the second input is given as 1.
the given inputs. Therefore, after locating the error position, the corresponding
The output is 7-bit code word with four data bits and FG gate inverts the bit in the error position giving us corrected
three parity bits. The output of this cell is given to CG. The output.
architecture of EC is given below. CG is cascaded with EDC cell to obtain proposed
circuit. EDC cell consists of a decoder and seven EXOR gates
implemented using reversible logic. Fig. 3 explains detail
schematic of EDC. Simulation results are analyzed in section 4
to test the proposed circuit.

Figure. 1 EC Logic Cell Architecture

B. CG Reversible Logic Cell

To check if the bit stream has reached safely to the


destination, check bits are calculated at the receiver end. CG
calculates check bits using the algorithm suggested in [4]. If
an error is present, the error position is located by observing
check bits. C4C2C1 gives the position of the error in binary.
To construct CG, two F2G gates and five FG gates
are used. The output of EC is considered as input to CG. CG
has encoded word as input and three outputs i.e., check bits.
Fig.2 shows the construction of CG Reversible Logic cell.

Figure. 3 EDC Logic Cell Architecture

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2017 2nd IEEE International Conference On Recent Trends in Electronics Information & Communication Technology (RTEICT), May 19-20, 2017, India

IV. SIMULATION RESULTS

The simulation results and power curves of each


reversible logic cell used in this circuitry are depicted in this
section. Simulation designs are obtained by cadence virtuoso.

Figure. 7 Overall Reversible HMC Simulation

Figure. 4 Reversible EC Simulation

Figure. 8 Overall power

Figure. 5 Reversible CB Simulation

Figure. 9 HMC Power Curve

V. MATHEMATICAL ANALYSIS
A. Calculating Number of Gates (NOG)

Number of gates is calculated by counting all the


gates used in individual cells. To build hamming code encoder
circuit, two FG gates and three F2G gates are used. To design
Check bit generator, two F2G gates and five FG gates are
used. In designing error detection and correction, six F gates
and nine FG gates are used. So, to calculate total number of
gates, the expression is given as follows

NOGHMC = NOGEC + NOGCG + NOGEDC


= [3(F2G) + 2(FG)] + [2(F2G) + 5(FG)] + [6(F) +
9(FG)]
Figure. 6 Reversible EDC Simulation
= 27 (1)

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2017 2nd IEEE International Conference On Recent Trends in Electronics Information & Communication Technology (RTEICT), May 19-20, 2017, India

B. Calculating Garbage output (GO) CONCLUSION

Total Garbage Output of the proposed hamming code This paper provides an innovative approach to reduce
circuitry using reversible logic is given by the following power consumption in irreversible hamming code circuitry
using reversible logic gates. Proposed reversible Hamming
expression Code encoding and decoding circuit have 27 number of gates
and power consumption is 7.2PW. Number of gates, Quantum
GOHMC = GOEC + GOCG +GOEDC cost, Garbage output and delay are 27, 39, 18 and 1ns
respectively. Simulations of the proposed designs are
= 0 + 4 + 14 implemented with cadence virtuoso 90nm technology.
= 18 (2)
REFERENCES
V.III. Calculating Quantum cost
[1] V. Shiva Prasad Nayak, Govind Prasad, K. Dedeepya Chowdary and K.
The quantum cost for reversible hamming code Manjunatha Chari, “Design of Compact and Low Power Reversible
circuit is Comparator”, 2015 International Conference on Control,
Instrumentation, Communication and Computational Technologies
(ICCICCT-2015).
QCHMC = QCEC + QCCG + QC EDC [2] R. Landauer, “Irreversibility and heat generation in the computational
= [3(QCF2G) + 2(QCFG)] + [2(QCF2G) +5(QCFG)] process”, IBM Journal of Research and Development, volume: 5, Issue:
+ [6(QCF) + 9(QCFG)] 3, July 1961, Pages: 183–191.
= [3(2) +2(1)] + [2(2) +5(1)] + [6(5) +9(1)] [3] C.H. Bennett, “Logical reversibility of computation”, IBM Journal of
Research and Development, volume: 17, Issue: 6, Nov. 1973, Pages:
= 39 (3) 525–532.
[4] Debalina Roy Choudhury, Krishanu Podder, “Design of Hamming Code
V.IV. Calculating Power Encoding and Decoding Circuit Using Transmission Gate Logic”,
IRJET, volume: 02, Issue: 07, Oct. 2015.
The overall power consumption for reversible
hamming code circuit is given by the following expression

PHMC = PEC + PCG +PEDC

When the power of EC, CG and EDC cells are


calculated individually with cadence 90nm CMOS
Technology, the results are as follows
PEC= 1.403PW PCG = 1.864PW PEDC= 3.932PW

PHMC= 1.403PW + 1.864PW + 3.932PW


= 7.199 PW (4)

V.V. Calculating Delay


The delay for reversible hamming code circuit is given by the
following expression
DHMC = DEC + DCG +DEDC

The delay of all individual cells is calculated by using the


cadence 90nm CMOS Technology
DEC= 0.09ns DCG = 0.3ns DEDC= 0.6ns

DHMC = 0.09ns + 0.3ns + 0.6ns


= 0.99ns (5)

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