Vikram PHD Thesis PDF

Low Power and Low Area Techniques
For Neural Recording Application
by
Vikram Chaturvedi
Submitted to the
Department of Electrical Communication Engineering
in partial fulfillment of the requirements for the degree of
Do tor of Philosophy
at the
INDIAN INSTITUTE OF SCIENCE
January 2013
I certify that I have read this thesis and that, in my opinion, it is fully
adequate in scope and quality as a thesis for the degree of Doctor of
Philosophy.
(Dr. Bharadwaj Amrutur) Principal Advisor
ii
© Copyright by Vikram Chaturvedi 2013
All Rights Reserved
iii
To My Mother and Teachers
iv
Abstract
Chronic recording of neural signals is indispensable in designing efficient brain

machine interfaces and to elucidate human neurophysiology. The advent of multi-
channel micro-electrode arrays has driven the need for electronics to record neural
signals from many neurons. The continuous increase in demand of data from more
number of neurons is challenging for the design of an efficient neural recording
front end (NRFE). Power consumption per channel and data rate minimization are
two key problems which need to be addressed by next generation of neural record-
ing systems. Area consumption per channel must be low for small implant size.
Dynamic range in NRFE can vary with time due to change in electrode-neuron dis-
tance or background noise which demands adaptability. In this thesis, techniques
to reduce power-per-channel and area-per-channel in a NRFE, via new circuits and
architectures, are proposed.
An area efficient low power neural LNA is presented in UMC 0.13 µm 1P8M
CMOS technology. The amplifier can be biased adaptively from 200 nA to 2 µA,
modulating input referred noise from 9.92 µV to 3.9 µV . We also describe a low
noise design technique which minimizes the noise contribution of the load circuitry.
Optimum sizing of the input transistors minimizes the accentuation of the input re-
ferred noise of the amplifier. It obviates the need of large input coupling capacitance
in the amplifier which saves considerable amount of chip area. In vitro experiments
were performed to validate the applicability of the neural LNA in neural recording
systems.
ADC is another important block in a NRFE. An 8-bit SAR ADC along with the
input and reference buffer is implemented in 0.13 µm CMOS technology. The use
of ping-pong input sampling is emphasized for multichannel input to alleviate the
bandwidth requirement of the input buffer. To reduce the output data rate, the A/D
process is only enabled through a proposed activity dependent A/D scheme which
ensures that the background noise is not processed. Based on the dynamic range
requirement, the ADC resolution is adjusted from 8 to 1 bit at 1 bit step to reduce
power consumption linearly. The ADC consumes 8.8 µW from 1 V supply at 1 MS/s
and achieves ENOB of 7.7 bit. The ADC achieves FoM of 42.3 fJ/conversion in 0.13
µm CMOS technology.
Power consumption in SAR ADCs is greatly benefited by CMOS scaling due to
its highly digital nature. However the power consumption in the capacitive DAC
does not scale as well as the digital logic. In this thesis, two energy-efficient DAC
switching techniques, FlipDAC and Quaternary capacitor switching, are proposed to
reduce their energy consumption. Using these techniques, the energy consumption
in the DAC can be reduced by 37 % and 42.5 % compared to the present state-
of-the-art. A novel concept of code-independent energy consumption is introduced
and emphasized. It mitigates energy consumption degradation with small input
signal dynamic range.
ii
Acknowledgements
Even though this dissertation has only my name on the first page, it would not have
been possible without the guidance and the help of several individuals who in one
way or another contributed and extended their valuable assistance in this study. It
gives me immense pleasure to thank all those who made this dissertation possible.
First and foremost, I would like to express my sincere gratitude to my advisor
Dr. Bharadwaj Amrutur for the continuous support throughout my Ph.D study, for
his patience, motivation, enthusiasm, and immense knowledge. He inculcated the
skills required for research in me by giving the freedom to explore on my own, and
at the same time the guidance to recover when my steps faltered. I am sure that this
dissertation would not have been possible without his support and encouragement.
I take this opportunity to thank all teachers who have made me learn in my life
till now. I am especially grateful to Prof. Navakanta Bhat, Prof. Gaurab Banerjee,
Prof. K.N Bhat, Prof. K. J. Vinoy, Prof. Kuruvilla Varghese, Prof. Santanu Mahapatra
and others for the knowledge they imparted to me through their courses. I am
indebted to Dr. Sundararajan Krishnan for introducing me to the basics of analog
and mixed signal design through two courses at IISc.
I owe my gratitude to Prof. Shanthi Pavan, Prof. Nagendra Krishnapura, Prof.
Jacob Baker, Prof. Elad Alon and others for generously sharing the video lectures of
courses taught by them at their universities. It has greatly helped me in my research
i
and I will always be indebted to them for this. I would like to acknowledge IEEE
Solid State Circuit Society for providing the student travel grant which enabled me
to attend ISSCC 2011, the Olympics of circuits community. It was definitely a life
changing event.
This dissertation would not have been possible without the support of the staff
of ECE department especially Srinivas Murthy. I would like to single out Subhashini
for her unconditional support, be it grant application, reimbursement etc. I would
also like to acknowledge Ministry of Human Resource Development, Govt. of India
for providing the scholarship.
I have been fortunate to work with many wonderful colleagues. Over the years,
BT, Tejasvi, Nandish, Somya, Pratap, Rajath, Manodipan, Kaushik, Mohan, Manikan-
dan, Karthik, Syam, Siva, Viveka, Pushkar, Harish, Rachit, Arun and many others
have kept surroundings enjoyable and informative.
IISc cricket club and IISc football club must get special mention here which
has helped me cope with the stress of doing a Ph.D. I would like to acknowledge
DJ, Dibyendu, Biman, Sounik, Avijit, Teju, Kiran, Ashith, Harshan, Prof. Arindam
Ghosh, Sridher Sir, Rajkumar, Bhasker, Rogers, Habeeb and other IIScians for mak-
ing my stay in IISc beautiful and memorable.
I take this opportunity to thank friends outside IISc, Tanaya, Mimi, John, Joe,
Tani, Ankush, Anvin, Shanky, Vinamrita, Shivani, Vaibhav, JP, Neha, Deepti, Abhi-
nav, Ajay, Rahul, Rex, Sumit, Suresh and many others for constantly reminding me
to finish my ’student life’ and to get out of university campus !
Finally, I wish to thank my mother for her unconditional love, support, patience
and understanding during these years.
This work was supported by Department of Electronics and Information Tech-
nology, Govt. of India.
ii
Publications from the thesis work
and contributing works
Patent
• Vikram Chaturvedi and Bharadwaj Amrutur, ”An energy-efficient FlipDac switch-

ing technique for capacitive DAC in SAR ADCs”. (applied)
Peer-Reviewed Journal Articles
• Vikram Chaturvedi, Bharadwaj Amrutur, An Area Efficient Noise-Adaptive Neu-

ral Amplifier in 0.13 µm CMOS Technology, Emerging and Selected Topics in
Circuits and Systems, IEEE Journal on, vol. PP, no. 99, pp. 110, 2011.
• Tejasvi Anand, Vikram Chaturvedi, Bharadwaj Amrutur, An energy efficient

asymmetric binary search switching technique for SAR ADC, Electronics Let-
ters, Volume 46, Issue 22, October 2010.
• Vikram Chaturvedi, Tejasvi Anand, Bharadwaj Amrutur, An 8-to-1 bit 1 MS/s

SAR ADC with VGA and integrated data compression for neural recording ap-
plication, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
(accepted)
iii
• Vikram Chaturvedi, Bharadwaj Amrutur, An energy-efficient code-independent
DAC switching scheme with quaternary switching capacitors, IEEE Transac-
tions on Very Large Scale Integration (VLSI) Systems. (under review)
Conference Proceeding
• Vikram Chaturvedi and Bharadwaj Amrutur, A Low-Noise Low-Power Noise-

Adaptive Neural Amplifier in 0.13 µm CMOS technology, 24th International
Conference on VLSI Design, January 2011, Chennai, India.
Presentation
• Student Research Preview in International Solid State Circuit Conference 2011,

San Francisco, CA, USA (Feb 2011).
• 24th International Conference on VLSI Design, January 2011, Chennai, India.
iv
Contents
Acknowledgements i
Publications from the thesis work and contributing works iii
1 Introduction 1
1.1 Brain Machine Interface . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Neural Recording System . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Neural Recording Front End . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Thesis Contribution and Organization . . . . . . . . . . . . . . . . . 7
2 Neural Recording System 10

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Neural Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Challenges in NRS Design . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Neural Recording Front End . . . . . . . . . . . . . . . . . . . . . . . 21
2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3 Neural Low Noise Amplifier Design 28

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2 Neural Amplifier Design . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2.1 Closed Loop vs Open Loop Neural Amplifier . . . . . . . . . . 31
v
3.2.2 MOS in Deep Depletion as Pseudo-resistor . . . . . . . . . . . 33
3.2.3 Low Noise OTA Design . . . . . . . . . . . . . . . . . . . . . . 35
3.2.4 Noise-Power Trade-off . . . . . . . . . . . . . . . . . . . . . . 41
3.3 Cin Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.3.1 Noise Analysis in ac-coupled LNAs . . . . . . . . . . . . . . . 43
3.3.2 Input Capacitance Optimization . . . . . . . . . . . . . . . . . 47
3.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.4.1 Electrical Characterization . . . . . . . . . . . . . . . . . . . . 52
3.4.2 In vitro experiment . . . . . . . . . . . . . . . . . . . . . . . . 57
3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4 Energy-Efficient DAC Switching Techniques 61

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.1.1 SAR ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.1.2 Energy-efficient DAC Switching . . . . . . . . . . . . . . . . . 63
4.2 FlipDAC Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.3 Quaternary Capacitor Switching Scheme . . . . . . . . . . . . . . . . 73
4.3.1 Code-independent Energy Consumption . . . . . . . . . . . . 74
4.3.2 QCS Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.4 Practical Considerations of QCS Scheme . . . . . . . . . . . . . . . . 82
4.4.1 Top-plate switch Mismatch . . . . . . . . . . . . . . . . . . . . 82
4.4.2 Linearity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5 SAR ADC design for NRFE 94

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.2 SAR ADC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.3 Ping-Pong input sampling . . . . . . . . . . . . . . . . . . . . . . . . 97
5.4 Variable resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
vi
5.5 Activity dependent A/D . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6 Neural Recording Front End Design 107

6.1 Low Noise Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.1.1 Gain Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.2 SAR ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.2.1 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.2.2 CDAC Manipulation and Sign Correction . . . . . . . . . . . . 118
6.2.3 Asynchronous Logic and CDAC . . . . . . . . . . . . . . . . . 120
6.2.4 Reference Buffer . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.3 Variable Gain Amplifier (VGA) . . . . . . . . . . . . . . . . . . . . . . 125
6.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.4.1 ADC Characterization . . . . . . . . . . . . . . . . . . . . . . 130
6.4.2 Activity dependent A/D . . . . . . . . . . . . . . . . . . . . . 135
6.4.3 VGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.4.4 Simulation results for NRFE . . . . . . . . . . . . . . . . . . . 139
6.4.5 System Power Consumption Comparison . . . . . . . . . . . . 139
6.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
7 Conclusion 144
7.1 Thesis Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
7.2 Future Directions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
A Noise Analysis and Optimization 149

A.1 Common Source Amplifier . . . . . . . . . . . . . . . . . . . . . . . . 149
A.2 Neural Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
B Capacitive DAC Energy Modeling and Sizing 158

B.1 DAC Digital Energy Consumption Modeling . . . . . . . . . . . . . . 158
vii
B.2 Sizing of the LSB Capacitor . . . . . . . . . . . . . . . . . . . . . . . 162
B.3 Linearity Analysis of binary weighted CDAC . . . . . . . . . . . . . . 165
viii
Contents
ix
List of Tables
3.1 Sizing, gm, gm/Id for all devices . . . . . . . . . . . . . . . . . . . . 40

3.2 Dominant Noise Contributors in the OTA . . . . . . . . . . . . . . . . 40
3.3 Comparison of input coupling capacitance . . . . . . . . . . . . . . . 52
3.4 Summary and comparison of the measured results . . . . . . . . . . 57
4.1 DAC Switching Energy Comparison for 10 bit SAR ADC . . . . . . . . 70
6.1 SAR ADC Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . 135

6.2 VGA Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
7.1 Neural LNA Comparison . . . . . . . . . . . . . . . . . . . . . . . . . 145

7.2 VGA Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
7.3 SAR ADC Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . 147
A.1 Input Referred Noise optimization in a linear circuit. Proper sizing

of the devices can help in achieving correct transconductance ratios
and hence a low noise design. . . . . . . . . . . . . . . . . . . . . . . 153
x
List of Figures
1.1 Brain machine interface for a Neural prosthetic application. The bro-
ken communication link due to SCI can be imitated using an artificial
link to restore the functionality. . . . . . . . . . . . . . . . . . . . . . 3
1.2 A typical N-channel neural recording system. . . . . . . . . . . . . . 4
1.3 A typical N-channel neural recording front end. . . . . . . . . . . . . 5
2.1 Origin of an action potential due to sodium and potassium channels

in the cell membrane of a neuron. . . . . . . . . . . . . . . . . . . . . 11
2.2 Amplitude and frequency characteristics of neural signals. . . . . . . 13
2.3 Block diagram of a typical neural recording system. . . . . . . . . . . 14
2.4 Power and Area Breakdown in a SoC. . . . . . . . . . . . . . . . . . . 15
2.5 DC offset rejection scheme in LNA. . . . . . . . . . . . . . . . . . . . 16
2.6 Background noise and electronic noise in NRFE. . . . . . . . . . . . . 18
2.7 Various schemes of data transmission in a neural recording system. . 19
2.8 A typical N-channel neural recording front end. . . . . . . . . . . . . 22
2.9 Differential signal sensing using a signal electrode and a reference
electrode from the electrolyte for chronic recording. . . . . . . . . . . 23
2.10 Electrical model of ac-impedance of an electrode. . . . . . . . . . . . 23
xi
3.1 Neural LNA is the first stage of a NRFE which senses and amplifies
weak neural signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2 Architectures of Neural LNA. (a) Closed Loop Neural LNA. (b) Open
Loop Neural LNA. Cp,in represents the input parasitic capacitance in
both cases. Large resistance R is emulated using pseudo-resistors. . . 30
3.3 Pseudo-Resistors used to emulate large incremental resistance to achieve
large time constant. (a) Pseudo-Resistors. (b) Comparison between
MOS-bipolar pseudo-resistor and deep depletion NMOS pseudo-resistor
time constants for Cin = 10 pF. . . . . . . . . . . . . . . . . . . . . . 34
3.4 Equivalent circuit of the proposed pseudo-resistor. The charge den-
sity in the depletion region is controlled by the gate which causes
modulation of the resistance with the bias. . . . . . . . . . . . . . . . 34
3.5 Tunability in high pass pole by varying VBIAS. An increase in VBIAS
increases the high pass pole position. . . . . . . . . . . . . . . . . . . 36
3.6 Noise Contribution by input and load transistors at the input. The
2
input referred noise PSD (Vn,in ) is given as total output noise current
PSD (In2), flowing into the output impedance (Rin ||Rload ), divided by
the square of the transconductance (gm, in) of the input transistor. . 37
3.7 Schematic of the proposed neural amplifier. Gm − Gm architecture
is used. Isteal is used to reduce the transconductance of the load
transistors and achieve voltage gain. . . . . . . . . . . . . . . . . . . 38
3.8 Noise-power trade-off. Input referred noise of the amplifier reduces
with increase in power consumption. . . . . . . . . . . . . . . . . . . 42
3.9 Effect of parasitic capacitance on effective input referred noise in
open-loop amplifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.10 Effect of parasitic capacitance on effective input referred noise in
closed-loop amplifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . 46
xii
3.11 Input parasitic capacitance accentuates effective input referred of the
amplifier. Av0 is the voltage gain from gate to drain of the transistor. 48
3.12 Optimum sizing of input transistor pair minimizes input referred
noise for a given Cin . (a) Input referred flicker noise variation with
the gate area of the input pair for different input capacitance Cin .
(b) Input referred noise variation with the gate area in presence of
thermal noise (Vn,th = 2µV ) for input capacitance Cin = 5pF . . . . . 51
3.13 Chip fabricated in UMC 130 nm, 1P8M CMOS technology. (a) Die
micrograph of the chip. (b) Block Diagram of the system fabricated. . 53
3.14 Measured ac response of the amplifier for Vbias = 0 V and Vbias =
Vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.15 PSD for LNA output employing MIMCAPs as Cin. Vin = 100 uVp−p ,
Fin = 500 Hz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.16 Noise characterization. (a) Input referred noise PSD. The power line,
its odd harmonics and flicker noise can be seen in it. (b) Input re-
ferred noise (output noise divided by the voltage gain). The rms
value is Vin,rms = 5.5 µVrms . . . . . . . . . . . . . . . . . . . . . . . . 56
3.17 Test set-up for in vitro testing of the chip. The PCB is shielded using
thin aluminum foils to protect from interference from 50 Hz power
line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.18 In vitro acquisition of artificial EAP signal. Input (Fig. 3.17) is ∼ 8mVpp . 58
4.1 Binary search algorithm for quantization of an input. . . . . . . . . . 62

4.2 Block diagram of a conventional SAR ADC. . . . . . . . . . . . . . . . 63
4.3 Reference Buffer in a SAR ADC. . . . . . . . . . . . . . . . . . . . . . 64
4.4 Energy inefficiency in CDAC. . . . . . . . . . . . . . . . . . . . . . . . 65
4.5 CDAC switching in a 3 bit ADC. . . . . . . . . . . . . . . . . . . . . . 66
xiii
4.6 Input digitization through the proposed FlipDAC switching technique.
In the second case, output 1001 is resolved indirectly by tracking
1110 by Vdacp -Vdacm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.7 Proposed FlipDAC switching scheme for a 4 bit SAR ADC and energy
cost comparison for each step in the binary search tree. . . . . . . . . 68
4.8 Conceptual diagram of FlipDAC switching scheme. . . . . . . . . . . 69
4.9 Comparison of CDAC switching energy for a 10 bit SAR ADC. . . . . . 70
4.10 Offset sensitive and offset insensitive FlipDAC switching. . . . . . . . 71
4.11 Effect of flipping the offset on the linearity of a SAR ADC. . . . . . . 72
4.12 Code dependent energy consumption increases average energy con-
sumption in CDAC for smaller input swings. . . . . . . . . . . . . . . 75
4.13 Energy consumption in CDAC for neural data recorded in vitro from
the Hippocampal culture of a Wistar rat. Eavg = 209 CV 2 . . . . . . 76
4.14 Code dependent energy consumption in CDAC induces harmonic noise
into the supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.15 Proposed Switching technique with quaternary switching capacitors
for a 5 bit ADC. Figure shows the extraction of first 4 bits. . . . . . . 79
4.16 Comparison of the switching capacitance sizes for a 10 bit ADC. . . . 80
4.17 Comparison of the proposed technique for a 10 bit ADC. . . . . . . . 81
4.18 DAC settling equivalent model in a SAR ADC. . . . . . . . . . . . . . 82
4.19 Charge injection mismatch in top-plate switches. . . . . . . . . . . . 83
4.20 Comparison of the charge injection error due to Vgs mismatch nor-
malized to the quantization error. . . . . . . . . . . . . . . . . . . . . 86
4.21 Comparison of the charge injection error due to threshold voltage
mismatch normalized to the quantization error. . . . . . . . . . . . . 88
4.22 Comparison of standard deviation of INL and DNL error in binary
weighted (BW) and QCS DAC. . . . . . . . . . . . . . . . . . . . . . . 92
5.1 VGA and ADC in a N-channel neural recording front end. . . . . . . . 94
xiv
5.2 Block diagram of the proposed SAR ADC. . . . . . . . . . . . . . . . 96
5.3 Input sampling in a SAR ADC. (a) Conventional sampling (b) Ping-
pong input sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.4 Architecture of ping-pong input sampling scheme to relax the band-
width requirement of VGA and reference buffer. Vin,cm is the output
common mode voltage of the VGA. . . . . . . . . . . . . . . . . . . . 98
5.5 Data rate reduction in a NRFE. (a) Simple Thresholding. (b) Spike
Feature Extraction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.6 Data rate reduction through proposed activity dependent A/D scheme.103
5.7 Effective Activity Factor.(a) Spike approximated as a triangular wave-
form. (b) Important spike features that should be preserved. . . . . . 104
6.1 Block Diagram of the 16-channel neural recording system. . . . . . . 108

6.2 Sliding Window Power-on control. Only two channels consume power
at a time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.3 ON/OFF control employed for power scheduling in the amplifiers. . . 109
6.4 Schematic of Neural LNA. . . . . . . . . . . . . . . . . . . . . . . . . 110
6.5 Schematic of an open loop gain stage (A2). . . . . . . . . . . . . . . 112
6.6 Block diagram of the proposed SAR ADC. . . . . . . . . . . . . . . . 113
6.7 Schematic of the 4-input preamplifier. Preamplifier is employed to
mitigate the effect of kickback noise on small sampling capacitors. A
partial positive feedback reduces the output conductance. . . . . . . 115
6.8 Functionality of latch employing cross-coupled inverters. . . . . . . . 116
6.9 Schematic of the sense amplifier based latch. . . . . . . . . . . . . . 117
6.10 Energy-efficient implementation of the FlipDac step by manipulating
DAC reference rails. The sign of the DAC voltage is corrected by
interchanging DAC inputs to the preamplifier. . . . . . . . . . . . . . 119
6.11 Asynchronous logic. Variable resolution is implemented using the
MUX setting controlled by N. . . . . . . . . . . . . . . . . . . . . . . 120
xv
6.12 Timing diagram depicting asynchronous operation. T c consists of
the comparator and NAND gate delay. . . . . . . . . . . . . . . . . . 121
6.13 Architecture of 8 bit CDAC with separate sub-DACs. . . . . . . . . . . 122
6.14 Reference buffer in a SAR ADC employing CDAC as the feedback DAC. 122
6.15 Schematic of reference buffer. . . . . . . . . . . . . . . . . . . . . . . 124
6.16 Architecture of VGA for even or odd numbered channel. . . . . . . . 126
6.17 OTA sharing between even and odd numbered channel. . . . . . . . 126
6.18 Schematic of OTA in the VGA. . . . . . . . . . . . . . . . . . . . . . . 127
6.19 Architecture of each VGA. . . . . . . . . . . . . . . . . . . . . . . . . 128
6.20 Block diagram of the fabricated 16-channel neural recording system. 129
6.21 Die photograph of the chip. . . . . . . . . . . . . . . . . . . . . . . . 130
6.22 Test Setup for the characterization. . . . . . . . . . . . . . . . . . . . 131
6.23 Measured DNL and INL plots. . . . . . . . . . . . . . . . . . . . . . . 132
6.24 16384 point FFT of the ADC output for -1 dBFS input at Fin = 62.439
kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.25 Measured SNDR vs Fin for -1 dBFS input at 1 MS/s speed. . . . . . . 133
6.26 Relative power dissipation vs resolution with Pmax = 8.8 µW . . . . 133
6.27 Comparison with SAR ADCs published. . . . . . . . . . . . . . . . . . 134
6.28 Measured Digital output of the activity dependent ADC. The X-axis
and Y-axis represents the time in µsec and the output code respec-
tively. The asymmetric rejection of the background noise is due to
the fact that only 5 bits were used to encode ST H . . . . . . . . . . . . 136
6.29 Relative reduction in power consumption with different σn and ST H .
(Pmax = 10.7 µW ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.30 Relative reduction in ODR with different σn and ST H . . . . . . . . . 137
6.31 Measured Digital output of the activity dependent ADC. The X-axis
and Y-axis represents the sample number and the output code respec-
tively. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
xvi
6.32 Simulated AC response of the system with two modes of gain of LNA. 139
6.33 Simulated AC response to illustrate tunable high pass cut-off of the
system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.34 Simulated output referred noise for two modes of LNA: low-noise
and not-so-low noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
7.1 Comparison with SAR ADCs published. . . . . . . . . . . . . . . . . . 146
A.1 Noise Contribution by input and load transistors at the input. . . . . 150
A.2 Small signal equivalent schematic of the proposed neural amplifier. . 153
B.1 Digital energy consumption in a SAR ADC. . . . . . . . . . . . . . . . 159

B.2 FO4 buffer chain driving a load capacitance. . . . . . . . . . . . . . . 160
B.3 Variation of LSB capacitor size with resolution. . . . . . . . . . . . . 164
B.4 Behavioral simulation results for standard deviation of INL and DNL
in a binary weighted DAC. . . . . . . . . . . . . . . . . . . . . . . . . 167
xvii
Chapter 1
Introduction
HERE has been a great rise in interest in technologies for neuroscience and
T neuro-prosthetic applications over last few decades. The main aim of neu-
roscience is better understanding of the brain, human neurophysiology and origin
of disorders as schizophrenia, epilepsy, Parkinson’s disease etc. Whereas neuro-
prosthetic basically deals with the restoration of a lost biological function by mim-
icking the functionality. The constraints on the neuro-prosthetic application are
much more rigid than for neuroscience application. A neuro-prosthetic system must
ensure safety and reliability for its complete acceptance and has to keep in view the
economic challenges too.
The area of retinal [1] and cochlear [2] prosthetics have made great progress
in last few decades and implants have been successfully tested on human beings.
A great deal of work is going on the rehabilitation of lower limb malfunction due
to spinal cord injury (SCI) [3]. Deep brain stimulation (DBS) has been found to be
very effective in the treatment of Parkinson’s disease [4]. Vagus nerve stimulation
is proved to be a safe and reliable way to treat epilepsy [5]. In the very core of
these prosthetic systems, there is a brain-machine-interface (BMI) whose accuracy
directly decides the reliability and efficiency of the system.
1.1 Brain Machine Interface
Typically brain acts as the main controller of the various limbs/organs in a human
body and commands them using the central nervous system. Different regions of
the brain are dedicated to control various limbs or organs. If the brain loses its
1
Chapter 1. Introduction 2
ability to communicate with a limb or organ, due to any mishap or disease, they
become malfunctional.
Fig. 1.1 shows the block diagram of a system that is meant to rehabilitate func-
tions lost due to SCI. As shown in the figure, the communication link between the
brain and the lower body is broken which prevents the lower limbs from working,
even though both the brain and limbs are healthy. To restore the functionality, the
communication link between the brain and the limb has to be re-established. For
this, a parallel artificial link, from the brain to the limb, can be made which mimics
the process exactly as in a normal human being.
The prosthetic device should have the following capabilities for an efficient so-
lution:
• BMI should be able to read the thoughts from the specific region of the brain
to understand the intended action.
• Process the information to reduce the amount of data to be transmitted.
• Transmit the information to an actuator outside the body which can control
the limb or the organ.
• Decode the information by processing the information and convert it to a form

understandable to the actuator.
• Precisely control the movement or function of the limb or the organ based on
the information decoded.
Two very important blocks for a neural prosthetic system are: recording and
stimulation which act as the interface between the machine and the human body.
Stimulation block deals with the last requisite of a BMI and controls the movement
or function of the body part. It can be electrical or magnetic in nature with elec-
trical stimulation being more popular. Device reliability is an important issue in
Figure 1.1: Brain machine interface for a Neural prosthetic application. The broken
communication link due to SCI can be imitated using an artificial link to restore the
functionality.
Figure 1.2: A typical N-channel neural recording system.
stimulation circuitry as large voltages are required to send strong current pulses to
stimulate the organ.
On the other hand, recording block deals with the first requisite of a BMI and
is more commonly known as neural recording system (NRS). It must be able to ex-
tract the information from the brain without disrupting the normal behavior of the
brain. There are many signals, as electroencephalogram (EEG), electrocorticogram
(ECoG) and extracellular action potential (EAP), that can be used for this purpose.
All signals have their own merits and demerits for their use in the recording. This
work focuses on the recording of EAPs and will discuss only of it henceforth. NRS
should not corrupt the information by adding large amount of noise or interference.
NRS is usually implanted in the brain to keep it in the proximity of the neurons
which are basic building unit of a human brain. This protects the signals from noise
and other potential interference source.
1.2 Neural Recording System
Fig. 1.2 represents a typical multichannel neural recording system. The system
consists of m N-channel neural recording front ends (NRFE) which can cater to
Figure 1.3: A typical N-channel neural recording front end.
different regions of a human brain. The main role of a NRFE is to sense, amplify
and digitize neural signals extracted from a number of neurons without corrupting
it with electronic noise. NRFE typically consists of low-noise-amplifiers (LNA),
gain stages and ADC. NRFE must be designed to be adaptive to the dynamic range
requirement to potentially reduce power consumption when conditions are better
than the worst. The digital data is fed to a digital signal processor (DSP) which
applies spike sorting algorithm [6] to attribute a spike to its source neuron. This
DSP also helps in reducing the amount of data to be transmitted by either doing
spike thresholding [7] or extracting important spike features [8] and transmitting
only them. The output of the DSP is fed to RF telemetry block which serializes,
encodes and transmits the data over a wireless link. Each block of a NRS should
necessarily have low power consumption, should add low noise and must take small
area. Typically NRFE consumes maximum power (excluding RF telemetry) and area
in a NRS, and needs careful optimization [9, 10] to reduce them.
1.3 Neural Recording Front End
Fig. 1.3 presents a typical N-channel neural recording front end (NRFE). Each chan-
nel consists of a low-noise-amplifier (LNA) which senses a differential small voltage
created in the electrolyte through a multi-electrode array (MEA) and amplifies it

to protect from the noise of the succeeding stages. Each channel has additional
gain stage(s) (Av ) to add more amplification to the weak neural signals and to
enable the signal cover the full dynamic range of the ADC. Each channel is usu-
ally AC-coupled through an input capacitance Cin to block large dc offsets at the
electrode-electrolyte interface. The N-channels are time division multiplexed into
a variable gain amplifier (VGA) followed by a k-bit ADC which digitizes the signal
and feeds it to the DSP of the NRS for further processing.
NRFE usually dictates the number of channels that can be employed for record-
ing for a given chip area [11]. However there is a continuous demand of data from
more and more number of neurons which needs more number of channels in the
same chip area. Safety issues due to power dissipation per unit area also sets an
upper limit on the number of channels allowed in a given area. Two very important
metrics used for evaluation of a NRFE are power-per-channel and area-per-channel.
A NRFE with low power-per-channel and area-per-channel number is well suited for
a NRS that can perform chronic recording of neural signals from a large number of
neurons and will result in a BMI with high accuracy and reliability.
1.4 Thesis Contribution and Organization
This work focuses on the design of a NRFE with low power-per-channel and area-
per-channel, with an emphasis on their design in deep sub-micron CMOS technol-
ogy. The application targeted is an implantable neural sensor for a neuro-prosthetic
application. The main highlights of the thesis are:
• The design of a low-power noise-adaptive neural LNA is presented. An em-

phasis on the use of open-loop LNA is put by carefully weighing it against
the close loop configuration. A novel architecture of the neural LNA is pro-
posed which uses Gm − Gm architecture with current stealing for low noise
and moderate voltage gain. The ability to exploit noise-power trade-off in the
LNA helps in optimizing the power consumption in it under various noise con-
ditions. The LNA is also made area-efficient by investigating the cause of their
area-inefficiency and then optimizing the sizing of the input transistors to re-
lax the size of the input coupling capacitance. A novel solution for achieving
a high pass pole in a few Hz range using a deep depletion MOS as the pseudo-
resistor is proposed. The neural LNA is designed and fabricated in UMC 0.13
µm CMOS technology. Its electrical characteristics are validated using bench
top testing and the usefulness in neural recording application is proved via in
vitro experiment.
• The design considerations of a low power VGA and SAR ADC for a NRFE
are described. Architectural changes in the VGA and SAR ADC is proposed
to reduce the power consumption in both. For multichannel input, the use of
ping-pong input sampling structure is emphasized which enables full sampling
period for bit cycling and input tracking. It saves power in both VGA and
reference buffer by providing more time for settling and relaxing their output
resistance. This sampling scheme also helps in employing master clock of half
the sampling speed. This reduces the power consumption in the clock buffers
and makes the NRFE system more energy-efficient.
• A novel activity dependent A/D scheme is proposed to mitigate the processing

of the background noise. This reduces both power consumption and output
data rate (ODR) of the NRFE. The logic is in-built in the ADC and reuses
important blocks of it to save area and design time. The savings in power
consumption and ODR are analyzed and presented for a spike input to the
ADC.
• An energy efficient FlipDAC switching scheme is proposed for capacitive DAC

in SAR ADCs. The scheme obviates the energy-inefficient DOWN transitions
at higher MSBs by flipping the role of positive and negative DAC inputs to the
comparator during the decision of the 2nd MSB. This scheme reduces energy
consumption in the CDAC without using extra capacitors or sacrificing speed
of the ADC. The DAC switching scheme is compared with the state-of-the-art
techniques and was found more energy efficient from all of them. The DAC
switching technique consumes 37 % less energy than the present state-of-the-
art.
• Another energy-efficient switching technique for a capacitive DAC, QCS, is

described in Section 4.3. It employs switching capacitors that vary in a qua-
ternary manner, instead of binary as in conventional SAR ADCs, to reduce
the amount of charge taken by the reference. The reduction in size of the
switching capacitance is also helpful in achieving a faster settling in the DAC
and hence improves the speed of the successive approximation register (SAR)
ADC. In this technique, the MSB capacitors do not influence the energy con-
sumption during the extraction of remaining bits which makes the energy
consumption independent of the output code. The proposed technique, com-
pared to the Vcm -based switching technique, consumes 42.5 % less switching
energy for a 10-bit SAR ADC. Analysis of errors due to top plate switch charge
injection mismatch is presented. An analysis on the linearity for this scheme

is also presented and is compared to the schemes employing binary switching
capacitors.
Chapter 2 introduces the neural recording system and reviews important chal-
lenges faced by them. Chapter 3 discusses the design and implementation of the
proposed neural LNA in UMC 130 nm CMOS technology. Chapter 4 presents the
design considerations and architectural suggestions for a SAR ADC to be used in a
multichannel system. Energy efficient DAC switching techniques, FlipDAC and QCS,
are also explained and analyzed in Chapter 4. Ping-pong input sampling scheme to
relax VGA and reference buffer is addressed in Chapter 5. The concept of activity
dependent A/D scheme to reduce ODR is also described in Chapter 5. Chapter 6
delves into the implementation of each block in a 16-channel NRFE. The electrical
characterization for the evaluation of the FlipDAC switching scheme and activity
dependent A/D scheme are discussed. Chapter 7 concludes the thesis and presents
some of open problems for future work.
Chapter 2
Neural Recording System
2.1 Introduction
HRONIC recording of neural signals from a large number of neurons [12] is

C indispensable in designing efficient BMIs and to elucidate human neuro-
physiology. Advances in MEMS technology has catalyzed the fabrication of minia-
turized micro-electrode arrays (MEA), capable of accessing a number of neurons
(100-1000) at once [13, 14]. In additions to MEAs, integrated electronics should
also be able to withstand the challenges presented by such systems. These sys-
tems [7, 11, 15–17] must necessarily have low power consumption, low electronic
noise and should occupy smallest area for small implant size. The demand of data
from ever increasing number of neurons exacerbates the situation.
Section 2.2 will look upon the origin and characteristics of important neural
signals. Following this, Section 2.3 will introduce and discuss some of the very
important challenges faced by a NRS and some solutions proposed by various re-
searches are also discussed. Section 2.4 will discuss important blocks of a NRFE
briefly. Section 2.5 concludes the chapter.
2.2 Neural Signal Characteristics
Neural signals primarily consists of two types: extra-cellular action potential (EAP)
and low field potential (LFP). Fig. 2.1 shows the origin of an action potential due to
sodium and potassium channels in the membrane of a neuron cell. These channels
are responsible for exchange of ions with the outside of the cell. Sodium channels
10
Chapter 2. Neural Recording System 11
External
Medium
g g
Cell Membrane
Na g L
Cm K
E E E
Na K L
tion
repo
lariza
lariza
0 mV
resting
depo
potential
tion
-70 mV
Figure 2.1: Origin of an action potential due to sodium and potassium channels in
the cell membrane of a neuron.
are responsible for depolarization portion and potassium channels are responsible
for the re-polarization portion of an action potential (Fig. 2.1). The current that
moves inside the cell body at the initiation of the action potential pulls the region
around the signal electrode to a negative voltage compared to the reference elec-
trode. The end of the action potential lifts the voltage on the signal electrode.
Neurons communicate with each other through the exchange of these electrical
signals and also chemical signals known as neuro-transmitters. The acquisition of
neural signals primarily means the sensing of the electrical activity of the neuron
but researchers have also tried to acquire neural data using the chemical record-
ing method [18]. LFPs are known to be generated due to synchronous firing of a
number of neurons and is of low frequency (∼ 100 Hz). The energy of the LFPs
signals in motor cortex is correlated with specific arm movement reach parameters
as speed, direction etc and is important for neuro-prosthetic applications.
Chronic recording of neural signals necessitates that the signals be sensed ex-
tracellularly. This causes the magnitude of the detectable signal to attenuate from
what is shown in Fig. 2.1. The strength of the EAP that can be sensed is highly
dependent on the distance of the electrode from the neuron, area of the electrode
and impedance characteristics of the electrode. It is usually few hundreds of µV olts
for a magnitude ∼ 100 mV of the action potential generated inside the cell. In-
tracellular recording is also performed by biologists in some experiments to sense
strong signals but it kills the cell from which the data is recorded and hence can not
be used for chronic recording.
Fig. 2.2 depicts the comparison of the amplitude and frequency characteristics
of neural signals. Electroencephalogram (EEG) and Electrocorticogram (ECoG) sig-
nals are also included in the figure to get a better idea of these characteristics. EAPs
have higher frequency content than LFPs whereas LFPs are more robust than EAPs.
The amplitude of the EAPs typically varies from ∼ 10µV to 500 µV and bandwidth
is ∼ 200 Hz to 5 kHz. The duration is an EAP is ∼ 1 msec and the firing rate is
10 mV
Amplitude (V) 1 mV LFP
100 uV EAP
ECoG
10 uV
1 uV EEG
100 nV
1 10 100 1k 10k
Frequency (Hz)
Figure 2.2: Amplitude and frequency characteristics of neural signals.
dependent on the type of the neuron but is usually smaller than 100 spikes/sec.
2.3 Challenges in NRS Design
Fig. 2.3 represents the block diagram of a typical NRS. The system consists of m
N-channel neural recording front ends (NRFE), data compression and spike sorting
DSP, on-chip bias and supply generators, clock generation circuitry and RF teleme-
try block. The main role of NRFE is to sense, amplify and digitize neural signals
from a number of neurons without corrupting it with electronic noise. NRFE typi-
cally consists of low-noise-amplifiers (LNA), gain stages and ADC. NRFE must be
designed to be adaptive to the dynamic range requirement to potentially reduce
power consumption. This is explained more in Section 2.4.
The digital data is fed to a DSP which applies spike sorting algorithm [6] to it to
find the original source neuron of the spike. This DSP can also reduce the amount
of data to be transmitted by either doing spike thresholding [7] or extracting spike
features [8]. The output of the DSP is fed to RF telemetry block which serializes,
Figure 2.3: Block diagram of a typical neural recording system.
encodes and transmits the data over a wireless link. Power supply generation and
clock genration blocks are other important blocks of a NRS. Researchers have earlier
employed a battery as the power source but are now focused on transmitting power
with control signals using inductive coupling link [19].
Each block of a NRS should necessarily have low power consumption, should
add low noise and must take small area. Typically NRFE consumes maximum power
and area in a NRS and needs careful optimization [9, 10] to save area and power.
Following sections will focus on various challenges faced by a NRS.
Power Consumption
The power dissipation should be minimal in an implantable NRS. Low power con-
sumption in a NRS primarily arises due to low power dissipation constraint. This re-
quirement comes from the fact that even a moderate amount of heat flux can cause
irreparable damage to the surrounding tissues which is know as necrosis [20]. A
heat flux of only 80 mW att/cm2 can lead to necrosis of the muscle tissue [21]. A 1
mm2 chip with 16 channels must not consume more than a few hundreds of µW att
per channel in the NRFE block. Low power operation also becomes very impor-
tant for systems which use battery as the source of the power for the circuitry. A
Figure 2.4: Power and Area Breakdown in a SoC presented in [11].
lower power consumption ensures a longer operating time of the device without
recharging or replacement of the battery.
Fig. 2.4 shows the power breakdown in a NRS presented in [11]. It shows that
NRFE (amplifier, HPF, ADC) contribute to at least 50 % of the power consumed in
the chip. Hence any reduction in the power consumption of the NRFE will have
considerable positive impact on the power consumption of the whole system.
Fully Integrated
The neural recording systems [16, 22, 23] should be fully implantable and wireless
to record signals from freely moving primates. The use of any off-chip component
in the system goes against this requirement. One major bottleneck in the low area
design of NRS arises due to the requirement that the recording system should reject
large dc-offsets at the electrode-electrolyte interface [21, 24, 25]. This is essential
for the correct biasing of the input transistors in the LNA and safety of the patient.
A small dc current through the electrode can trigger reactions at the electrode-
electrolyte interface whose by-products can affect the tissues adversely.
The dc-suppression is typically performed by using ac-coupling through an input
dc bias
Unknown Unknown
dc-offset LPF dc-offset LPF
+ - +
HPF +
Av Av
− + −
HPF
-
LPF LPF
dc bias
(a) (b)
Figure 2.5: DC offset rejection scheme in LNA.
coupling capacitor. Fig. 2.5(a) shows such a scheme for the input dc-offset rejec-
tion. The challenge is to achieve a high pass pole around a few Hertz. The cut-off
should pass low field potentials (LFP) without using very large passive devices (re-
sistance and capacitance). The design of such large time constants in integrated
circuit technology is quite challenging. The situation exacerbates when simulta-
neous recording is required from a large number of neurons. The rejection of the
dc offset can also be performed through an active feedback technique [25]. This
scheme of dc offset suppression is shown in Fig. 2.5(b). This technique has not
received much popularity, partially due to need of designing another active block
which cause additional power consumption. It also lower the input impedance of
the NRFE.
Fig. 2.4 also shows the area breakdown of the SoC [11] where amplifier and HPF
take a lot a area. This area is dominated by the input coupling capacitance used in
the LNA for the rejection of input dc-offsets. The use of smaller Cin can potentially
reduce the area consumption per channel in a NRS which can be utilized to design
other blocks to do some important functions as offset cancellation [26], power-line
interference rejection [27] etc.
Noise
The amplitude of EAPs varies from few tens of µV olts to few hundreds of µV olts,
based on the distance of the electrode from the neuron, in a bandwidth of few
hundreds of Hz to ∼ 5 kHz. These signals are very weak and hence susceptible to
noise and interference. The NRS must not add large amount of noise that it corrupts
the smallest detectable signal. The noise added by the first amplification stage, LNA,
dominates the total noise contribution and hence design of a LNA is usually power-
hungry which reflects in Fig. 2.4. The resistive portion of the electrode also act as
a source of electronic noise. However the total noise from a 1000 µm2 electrode is
only ≈ 5µVrms [28].
Typically the noise added by the NRFE must not be greater than a few µV olts
√
[24, 29] which make the required thermal noise floor equal to ∼ 50 nV / Hz for
a 10 kHz bandwidth. The design of a low noise NRFE becomes more challenging
due to the presence of flicker noise in addition to the thermal noise in this low
frequency region. Chopper modulation seems to be an option to get rid of flicker
noise but they prove to be more power hungry. Correct biasing of the devices is
very important for a low noise design. Also, to increase the number of channels,
power-per-channel and area-per-channel have to be reduced. This motivates the
need to design these systems in lower technology nodes to benefit from technology
scaling where, unfortunately, low noise design is more challenging [30, 31].
Adaptivity
The minimum detectable signal in a NRS is usually limited by the background noise
[32, 33]. The background noise (σbk ) in a NRS is a result a firing of the distant
neurons. A part of this noise is also contributed by the resistive portion of the
impedance of the electrodes. The variance of the total system noise is given by the
sum of the variance of this background noise and that of the noise (σnrf e ) added by
the circuitry.
Background
Noise Electronic
Noise
+
Total
Av Noise
−
Figure 2.6: Background noise and electronic noise in NRFE.
2 2
σtotal = σbk · A2V + σnrf
2
e (2.1)
It is found that the background noise is dynamic in nature and varies in NRS
based on the firing rate, type of the neurons and the density of the neurons [28].
Hence designing a system with very low noise contribution, which consumes large
power, when background noise is large does not look practical. Hence the NRFE
must possess the adaptivity to reduce the power consumption by exploiting noise-
power trade-off when the background noise is large.
The signal amplitude detected using MEA also varies based on the distance from
of the electrode from the neuron and impedance characteristics of the electrode.
This distance can also change with time due to shift in the position of the MEA. Also
frequently an electrode senses signal from a number of neuron (∼ 6) which can also
results in large variation in the signal strength based on the kind of the interference
(constructive or destructive). It basically points towards the large dynamic range of
the input to the NRS. If various blocks of the NRS are made adaptive to the dynamic
range requirement, rather than being designed for the largest dynamic range, a lot
of energy can be saved.
10b
ADC 400 Kb/s
40 KS/s
Raw Data Transmission
(a)
Signal
Electrode
+
−
LNA BPF −
−
(10 KHz) + ~100 b/s
Reference DAC +
Electrode
Noise
Threshold
Simple Thresholding
(b)
Spike Feature Classifi
Detection Extraction -cation
Feature
(d) ADC DSP Data
Spike Feature Extraction
(c)
Figure 2.7: Various schemes of data transmission in a neural recording system.
Output Data Rate
There is a continuous demand of data from more and more number of the neurons.
This data has to transmitted from the implant using a wireless link [19, 34, 35]
to outside. A 100 channel NRS with sampling frequency 40 KS/s and digitizing
using a 10 bit ADC needs a wireless link that supports 40 Mbps of data rate. Fig.
2.7(a) shows such a scheme in which the ADC is free running and digitizes the
data which is transmitted without any on-chip compression. The transmission of
this tremendous amount of data in a power-efficient way pose serious threat to the
scalability of NRS. The next generation of these systems must incorporate enough
on-chip processing capability to record from thousands of neurons and reduce the
amount of data to be transmitted, that too in a power-efficient way. The output
data rate (ODR) of a NRS has been reduced by researchers using either simple
thresholding or spike feature extraction.
Simple thresholding (Fig. 2.7(b)) is another popular scheme of spike data trans-
mission. It basically discriminates a spike against background noise by using a spike
threshold which is decided on the variance of the background noise [36]. As shown
in Fig. 2.7(b), spike threshold is compared with the input data with the help of
a comparator and a digital-to-analog converter (DAC). The spike threshold is cal-
culated for each channel separately and is stored in a register. The spike threshold
should be adapted according to the variance of the back ground noise [37,38] if the
noise is quite dynamic. As shown in Fig. 2.7(a), if a free running ADC is employed,
ODR is 400 Kb/s-per-channel for a 40 KS/s sampling. However by employing sim-
ple thresholding (Fig. 2.7(b)), the ODR can be reduced to ∼ 100 b/s for a spike
rate of 100 spike/sec. In this technique, the spike event is encoded in a single bit,
1 for spike and 0 for no spike, which leads to drastic reduction in ODR. However,
it suffers from the drawback of losing potential information required for the spike
sorting algorithm. It also suffers from detecting noise as false spikes and missing
real spikes if background noise is very strong. The off-chip DSP algorithm must be
designed to detect and correct these errors.
Presently spike feature extraction [39, 40] is most popular way of reducing ODR
(Fig. 2.7(c)). The vital information is essentially encoded in the spike time-stamps
and inter-spike duration in EAPs. But the amplitude information is also important
for assigning the correct origin to a spike using spike sorting algorithm [41]. It is
shown that out of many features of a spike that can characterize a spike shape if we
keep only some of the spike features intact in the data, it does not causes any loss
of information required for the spike sorting. For example the peaks of the original
spike waveforms and, maximum and minimum values for its first derivatives were
chosen as important features in [8]. In this technique, an on-chip DSP processes
the raw signal from NRFE and extracts the required spike features. Then only these
spike features are transmitted via the RF telemetry. Fig. 2.7(d) shows important
blocks of a DSP used to extract spike features from the digitized data. Spike de-
tection block is used to detect spike event in presence of back background noise.
Simple thresholding is one popular way to perform this [6]. Energy operators as
NEO, TEO [8] are also frequently employed for this purpose which are efficient in
separating spikes from background activities. However their implementations are
quite complex. Frequency-shaping filters are often used for help in discriminating
between similar spike from different neurons. Feature extraction can be performed
by using principle component analysis(PCA) which usually needs training. Spike
classification is performed in the end by clustering. A sample is considered to be
informative if if the superimposed spikes can be classified into multiple clusters by
evaluating the sample alone [8].
Spike feature extraction (Fig. 2.7(c)) does reduce ODR and energy in the RF
telemetry block but there is no reduction in power consumption of the NRFE, espe-
cially the ADC. Moreover, its needs complicated circuitry for spike detection using
energy operators, noise-shaping filters and feature extractors etc. An energy and
area efficient way of reducing the ODR without losing the information for spike
sorting is indispensable in the design of next generation NRS.
2.4 Neural Recording Front End
Fig. 2.8 presents a typical N-channel neural recording front end (NRFE). Each chan-
nel consists of a LNA and gain stage(s) (Av ) which sense a differential small voltage
created in the electrolyte through a multi-electrode array (MEA). Each channel is
ac-coupled through an input capacitance Cin though some researchers have care-
fully used dc-coupled LNAs [42] too. The N-channels are time division multiplexed
into a variable gain amplifier (VGA) followed by a ADC. SAR ADCs are predomi-
nantly employed in NRFE due to their high energy efficiency in moderate resolution
and moderate speed region. Moreover due to highly digital nature of them, they are
Figure 2.8: A typical N-channel neural recording front end.
benefited by CMOS scaling which saves power and increases speed for same area.
MEA
Each amplifier in a NRFE connect to two electrodes: a signal electrode and a refer-
ence electrode (Fig. 2.9). It helps in reducing the environmental noise by rejecting
them as a common mode noise if reference electrode is close to the the signal elec-
trode. Usually many LNAs share a single reference electrode but the number of
reference electrodes can be more than one based on the number of the channels for
the signal acquisition.
As the interface of the electrode and the electrolyte contains different types of
carrier on the two sides, ions in electrolyte and electrons in metal, it does not follow
Ohm’s law. A small dc current of 100 pA can lead to chemical reactions with by-
products as oxygen or hydrogen which can damage tissues [28]. Any dc current
must be sensed and eliminated from flowing in the the electrode. It also requires
that the first amplifier (LNA) must have very high input impedance at dc. A high
input impedance is also required as electrode impedance and LNA input impedance
forms a voltage divider circuit which is responsible for the input signal attenuation.
Fig. 2.10 shows electrical model of ac-impedance of a metal electrode. The
resistor RHF (high frequency resistance) presents the dominant impedance at high
e
lyt
Signal
tro
c
Electrode
+
Ele
Neur
LNA
−
on
Reference
e
lyt
Electrode
tro
c
Ele
−
Neur
LNA
on
Signal
+
Electrode
Figure 2.9: Differential signal sensing using a signal electrode and a reference elec-
trode from the electrolyte for chronic recording.
RDC
RCT
RHF W
CDL
Figure 2.10: Electrical model of ac-impedance of an electrode.

frequencies and consists of interconnect resistance, spreading resistance etc. RCT

represents charge transfer resistance and signifies low frequency resistance. CDL
represents the double layer capacitance at the electrode-electrolyte interface. The
element W is Warburg element and it models the mass transport of the reactants
in the extracellular fluid [28] and is not same as the CPE element used in [43] for
modeling. Element RDC (dc resistance) models the non-zero mass transport at dc.
These models are quite complex but for the frequency range for EAPs, modeling
of an electrode with a simple capacitor suffices. The value of the capacitance is
dependent on the electrode surface area and if some surface treatment technique
is used in the electrode to increase this impedance. 1 pF/µm2 is a good number to
remember when calculating this electrode capacitance.
LNA
One of the most critical blocks of such a system is the low noise amplifier (LNA).
LNAs must be low noise, low power and low area. The amplifier should be able to
reject large dc offsets that may arise due to dc electrode current (∼ 100 pA) and
high impedance at electrode-electrolyte interface [28]. The challenge is to achieve
a high pass pole around a few Hertz, to pass low field potentials (LFP), without
using very large passive devices due to area constraint. The design of such large
time constants in integrated circuit technology is difficult. In order to be able to
monitor extracellular action potential (EAPs) separately from LFPs [44], the high
pass cut-off frequency of the amplifier should be tunable.
Neural signals are typically low frequency signals (100 Hz-5 kHz) and are cor-
rupted by the narrow-band flicker noise in addition to the wide-band thermal noise.
Correct sizing and biasing of the devices is very important to mitigate the effect of
electronic noise on the weak neural signals. The neural amplifier should also benefit
from noise-power trade-off.
Neural amplifiers, other than being the most power hungry block, are the most
area consuming block too (Fig. 2.4). Very large input transistor sizes are often used
to reduce flicker noise below thermal noise. Large input capacitance Cin have also
been used in the amplifiers (∼ 15 − 50pF ). The input pair of the amplifier should
be optimally sized to reduce the size of the input capacitance (Cin ) to reduce the
area, without compromising with the high pass cut off frequency.
Gain Stage Av
The role of this block is basically to give additional amplification to the neural sig-
nal. Being an intermediate block in the NRFE, the specifications of this block are
relaxed on both noise and distortion. However, the adaptivity in gain and band-
width are required in this block too, similar to that in a LNA.
VGA
The amplitude of the maximum detectable signal varies with neuron-electrode dis-
tance and probe impedance which is frequency dependent. A fixed gain in NRFE
will either under-utilize the ADC dynamic range or causes clipping of the peaks.
Hence the VGA should possess large programmable range in voltage gain. It will
ensure that the signal will traverse the full scale range (FSR) of the ADC and will
cause complete utilization of the ADC. Any gain error in preceding blocks can also
be corrected by using a VGA before the ADC.
ADC
Analog-to-digital converter (ADC) is another very important block in a NRFE. It

typically utilizes a SAR ADC due to moderate resolution requirement (8-10 bit) and
its high energy efficiency [8, 15, 45, 46]. Till now the ADCs in NRFEs have followed
a traditional design methodology except in [45]. The resolution of the ADC is
usually determined based on the dynamic range requirement (SNR) which is the
ratio of the maximum and minimum detectable signal. The maximum detectable
signal in the NRFE can vary a lot depending on the distance between electrode and
the neuron which is not well controlled. The minimum detectable signal is limited
by the background noise. Hence an energy-efficient NRFE must have the ability to
adapt the resolution of the ADC.
SAR ADCs have become very popular with the the technology scaling owing to
its digital nature. Researchers have been exploiting this to continuous push the
speed of the operation of the ADC and also lower the power consumption. But
the DAC is not scaling like the digital portion as capacitors do not follow Moore’s
law. The energy consumption in the DAC is a significant part of the total energy
consumption in the ADC and an energy-efficient solution of the ADC should try to
reduce the energy consumption in the DAC.
More detailed discussion on the design constraint of each block of NRFE is pre-
sented in the subsequent chapters.
2.5 Summary
This chapter presented an introduction to a neural recording system. The origin and
characteristics of neural signals are briefly discussed which indicates towards prob-
lems and specifications in designing a neural recording system. Sodium-Potassium
channels are the main source of the origin of the action potentials. The discussion
was more focused on EAPs compared to LFPs as they are more important source of
information from the brain. EAPs have higher frequency content than LFPs whereas
LFPs are stronger than EAPs. The amplitude of the EAPs varies from ∼ 10 µV to
500 µV and bandwidth is ∼ 100 Hz to 5 kHz. A small discussion on the attenuation
of the action potential for chronic recording is also made.
The main challenges in the design of a NRS are introduced. More detailed dis-
cussion on them can be found in the subsequent chapters. A NRS must necessarily
have low power consumption. This requirement arises as a moderate heat flux of
only 80 mWatt/mm2 can lead to necrosis of the muscle tissue. It boils down to
each channel not consuming more than a few hundreds of µW att. A NRS must
be low noise so that the weak neural signals can be detected reliably. This be-
comes more difficult due to the presence of the flicker noise in addition to the
thermal noise in the low frequency band. The problem of the unknown dc-offsets at
electrode-electrolyte interface is introduced which acts as a big problem in design
of an area-efficient fully integrated NRS.
Another requirement that is imposed on NRS is due to dynamic nature of input
signal and input noise in these systems. The exploitation of power-noise trade-
off can be an essential tool in designing a power efficient just-good-enough NRS.
The transmission of the tremendous amount of data generated in a power-efficient
way pose serious threat to the scalability of NRS. Simple thresholding ans spike
feature extraction are two popular way in which researchers have tried to tackle
this problem. However the former is prone to loss of information whereas the later
needs complicated DSP or circuitry which is not power-efficient.
The block diagram of a typical NRFE is briefly discussed. A NRFE basically con-
sists of MEA, LNAs, gain-stages, an analog multiplexer, a VGA and an ADC. A brief
discussion on each block of NRFE is presented. The electrical modeling of multi-
electrode array is introduced. The problem with even a very small dc-current in
these electrodes is discussed which demands the use of a very high input impedance
LNA. Detailed discussion on these blocks is presented in subsequent chapters.
Chapter 3
Neural Low Noise Amplifier Design
3.1 Introduction
NE of the most critical blocks of such a system is the low noise amplifier
O (LNA). Neural LNAs must be low noise, especially in presence of flicker
noise, to reliably sense and amplify weak EAPs. It should consume lowest power
and smallest area to design a large channel NRFE. Out of various neural LNAs avail-
able in the literature, very few LNAs meet all these requirements.
Fig. 3.1 shows a neural LNA, with input impedance Za , sensing the neural
activity en . Being the first stage, there are various requirements to be fulfilled by
the LNA. Firstly, the amplifier should be able to reject large dc-offsets that may arise
due to dc electrode current (∼ 100 pA) and high impedance at electrode-electrolyte
interface [28]. Researchers have come up with many techniques to mitigate this
problem. Some have tried dc-coupling by accommodating the voltage swing at the
input of the amplifier [28, 29]. However it is difficult to use it in lower technology
nodes, with lower supply voltages and smaller input common mode range. AC
coupling or DC stabilization has achieved more popularity and acceptance over
the years [21, 24, 42, 47]. The challenge is to achieve a high pass pole around
a few Hertz, to pass low field potentials (LFP), without using very large passive
devices. The design of such large time constants in integrated circuit technology is
difficult. Researchers have used off-chip components for this purpose earlier [30].
But the use of off-chip components increases the system size which is problematic
for a fully implantable solution. The situation exacerbates when recording from
a large number of neurons. Many of the previously published designs have used
28
Chapter 3. Neural Low Noise Amplifier Design 29
Figure 3.1: Neural LNA is the first stage of a NRFE which senses and amplifies weak
neural signals.
MOS-bipolar pseudo-resistors [21] [24] or MOS in weak inversion [42] to get high
resistance in tera-ohm range [28]. Our first contribution is the use of NMOS in
deep-depletion region, as pseudo-resistor, to get incremental resistance in the tera-
ohm range with less distortion.
Neural signals are typically low frequency signals (1 Hz-7 kHz) and are mainly
corrupted by the narrow-band flicker noise in addition to the wide-band thermal
noise. Correct sizing and biasing of the devices is very important to mitigate the
effect of electronic noise on weak neural signals. The background noise at the input
of such system is dynamic and varies typically between 10 µV to 30 µV [32,33,37].
The background noise is dependent on firing activity of the distant neurons and the
effective electrode-neuron distance [48]. It is disadvantageous to design a system
with 2 µV input referred noise, when background noise is 30 µV . Our second
contribution is the design of a neural amplifier that benefits from noise-power trade-
off. In order to be able to monitor extracellular action potential (EAPs) separately
from LFPs [44], the high pass cut-off frequency of the amplifier is made tunable.
Neural amplifiers, other than being the most power hungry block, are the most
area consuming block too (Fig. 12 in [11]). The importance of area efficient design
has increased with time, due to continuous increase in demand for data from more
number of recording sites. But previous works have not really focused on reducing
the area of the amplifier except [29]. Very large input transistor sizes are often used
(a) (b)
Figure 3.2: Architectures of Neural LNA. (a) Closed Loop Neural LNA. (b) Open
Loop Neural LNA. Cp,in represents the input parasitic capacitance in both cases.
Large resistance R is emulated using pseudo-resistors.
to reduce flicker noise below thermal noise. Large input capacitance Cin have also
been used in the amplifiers (∼ 15 − 50pF ), to compensate for noise accentuation
due to parasitic capacitance Cp (Fig. 3.2), which takes a lot of area [11, 21, 24, 49].
Our third contribution is the optimum sizing of the input pair of the amplifier to
reduce the size of the input capacitance (Cin ) and hence reduce the area, without
compromising with the high pass cut off frequency.
The intricacies of the application have to be weighed upon to choose the correct
amplifier architecture. We find that an open loop architecture is more suitable here
due to its potential advantages. The absence of a stable dc supply [19, 50] neces-
sarily asks for a fully differential architecture with high PSRR for a robust system.
Section 3.2 discusses the design and implementation of the neural amplifier. Sec-
tion 3.3 describes the proposed concept of optimum sizing of input transistors for a
given input capacitance and input referred noise. Section 3.4 presents experimental
results from a UMC 130nm test chip and Section 3.5 concludes the chapter.
3.2 Neural Amplifier Design
3.2.1 Closed Loop vs Open Loop Neural Amplifier
The architecture of the neural amplifier employed in [21] (Fig. 3.2(a)) is popu-
lar and is accepted by many researchers [11, 24, 47, 51]. It employs a capacitive
feedback for ac signals and dc feedback through MOS-bipolar pseudo-resistor. The
mid-band gain is given by the ratio of input and feedback capacitance. However the
output is taken single ended which might suffer from power supply noise. In addi-
tion, a two stage amplifier is used for large open loop voltage gain which consumes
additional power.
The proposed architecture of the neural amplifier is shown in Fig. 3.2(b). We
have used an open loop configuration over closed-loop configuration (Fig. 3.2(a))
for the application, keeping into view its potential advantages:
1. Many neuroscientists have proven that the information is essentially encoded

in the spike time-stamps and inter-spike intervals [8, 40]. Hence a small gain
error due to process-voltage-temperature (PVT) variations is not detrimental
to the information. Also the amplitude of the EAP is strongly dependent on
the electrode-neuron distance which is not well-controlled [52]. So having a
highly deterministic gain in the neural amplifier does not really contribute.
2. Typically an electrode picks up signals from a number of neighboring neurons

(∼ 6). These signals are discriminated using special algorithms known as
spike sorting algorithms. These algorithms use spike shapes to distinguish dif-
ferent neuronal sources and hence constrain distortion that can be introduced
by the amplifier. Pseudo-resistors show good linearity and large resistance for
small swings only [21, 51]. In feedback configuration (Fig. 3.2(a)), pseudo-
resistor experiences larger signal swing across it and can cause more signal
distortion.
3. Open loop amplifiers consume lower power than closed loop configurations
for same accuracy requirements [53]. For same steady state error, an amplifier
in closed loop configuration needs large open loop gain which requires more
than one stage in deep sub-micron technologies. It may also need compensa-
tion for stable operation.
4. In pass-band, the transfer function from signal source to the input of the OTA
(Gm in Fig. 3.2) can be calculated as,
Cin
Hatt,closed (s) = (3.1)
Cin + Cp + Cf b
Cin
Hatt,open (s) = (3.2)
Cin + Cp
Input referred noise of the amplifier is accentuated by the inverse of the trans-
fer function Hatt (s) [21]. Closed loop configurations have larger Cp,ef f =
Cp + Cf b . However the difference is small as Cf b << Cin . But it is imperative
to note that any feedback loop at the input of the LNA for offset or inter-
ference cancellation [26, 54] increases Cp,ef f . Hence noise increases more in
such configurations over open loop configurations. This also demands the use
of larger Cin as explained in Section 3.3.
Looking at the above reasons, the use of an open loop architecture for neural
recording application looks very advantageous. However, open loop architecture
does suffer from inaccuracy in gain due to PVT variations. But if the error is not
large, this can be compensated for by using a VGA in subsequent stages. Open loop
architecture also introduces larger offset than closed loop amplifiers. Fortunately,
both these errors can be calibrated and corrected digitally [53]. Open loop ampli-
fiers also cause larger distortion than closed loop amplifiers. But this is not a serious
issue for this stage as the voltage swings encountered by it are very small. CMRR is
only determined by the matching of the input AC coupling capacitance and hence
it is independent of the architecture, whether open loop or closed loop.
3.2.2 MOS in Deep Depletion as Pseudo-resistor
It is challenging to achieve large time constants (∼ 10sec) due to small specific

capacitance (∼ 2 − 3f F/um2 in 130 nm technology ) and resistance of the passive
devices supported in integrated technology. Fortunately this application does not
need high accuracy in the position of the high pass pole. The presence of a high
pass pole between dc and lowest input frequency suffices.
Pseudo-resistors are largely used to emulate tera-ohm resistance for the rejection
of dc offsets at cell-electrode interface [21, 24]. Fig. 3.3(a)(ii) shows the MOS-
bipolar pseudo-resistor used by many previous designs. It has worked well in larger
technology nodes due to smaller leakage currents. But it is less efficient in deep sub-
micron technologies where leakage currents are higher. Simulations (Fig. 3.3(b))
show a cut-off frequency of 100 Hz for C = 10 pF. Moreover the swing that can be
supported across it is only 0.2 Volts [21]. Usually 2-4 MOS-bipolar devices are used
in series to limit distortion introduced by them by reducing effective swing across
each of them.
We have proposed NMOS (Fig. 3.3(a)(i)) in deep-depletion region (V gs << 0
& V gb ≥ 0 ) to emulate very high resistance. It works as two reversed biased diodes
in series (Fig. 3.4). Simulations indicate a cut-off frequency around 10 mHz for
Cin = 10 pF, which was 100 Hz for a MOS-bipolar pseudo-resistor. It also supports
larger swing (∼ 0.6V ) than MOS-bipolar pseudo-resistor with a distortion of only
0.3% THD. Fig. 3.3(b) shows the comparison between the two pseudo-resistors
with VBIAS = 0 V for Cin = 10 pF. Lower distortion in the pseudo-resistor is due to
symmetric behavior of the device for both positive and negative swings (Fig. 3.4)
whereas MOS-bipolar pseudo-resistor behaves differently for two swings [21]. Also
inversion charge is a more non-linear function of gate voltage than depletion charge
Normalized Magnitude (dB)

−20
Deep
−40 Depletion
MOS MOS−bipolar
−60 pseudoresistor
−80
−100
−120 −4 −2 0 2 4 6 8
10 10 10 10 10 10 10
Frequency
(a) (b)
Figure 3.3: Pseudo-Resistors used to emulate large incremental resistance to

achieve large time constant. (a) Pseudo-Resistors. (b) Comparison between MOS-
bipolar pseudo-resistor and deep depletion NMOS pseudo-resistor time constants
for Cin = 10 pF.
Figure 3.4: Equivalent circuit of the proposed pseudo-resistor. The charge density
in the depletion region is controlled by the gate which causes modulation of the
resistance with the bias.
in MOSFETs [55].
The resistance of the pseudo-resistor can be tuned through VBIAS. The charge
balance equation [55] in MOSFETs is given as,
QG + Q0 + QC = 0 (3.3)
where QG is charge on gate, Q0 is effective interface charge and QC is charge in

the semiconductor under the oxide. Taking Q0 as constant and inversion charge as
negligible,
∆QG = −∆Qdep (3.4)
where Qdep is the charge in depletion region. The gate terminal controls the
charge density in the depletion region which in turn controls minority carrier diffu-
sion current. It helps us modulate the value of the resistance (Fig. 3.4) emulated
by the pseudo-resistor. Device level simulations were also performed to study this
phenomenon using Sentaurus Device [56].
The high pass cut-off frequency can be increased to reject LFPs and only pass
EAPs. It is also helpful in attenuating the interference due to power line. Fig. 3.5
shows the tunable high pass pole for different VBIAS. As VBIAS is increased, the
high pass cut-off frequency increases due to reduction in the incremental resistance
of the pseudo-resistor. The high pass cut-off frequency can be varied from 10 mHz
at VBIAS = 0 V to 1.4 kHz at VBIAS = 800 mV. Amplifiers employing MOS-bipolar
pseudo-resistors need an additional filter stage for tunability purpose and increase
system cost.
3.2.3 Low Noise OTA Design
Neural amplifiers are one of the the most power hungry blocks [11] in a NRFE
as they are large in number (one amplifier per recording site) and consume static
50
0
0V
Magnitude (dB)
−50
800mV
−100
−150
−5 0 5
10 10 10
Frequency
Figure 3.5: Tunability in high pass pole by varying VBIAS. An increase in VBIAS
increases the high pass pole position.
power. The input referred noise must be very small for efficient acquisition of the
signal which demands larger power consumption. Typically the cortical EAPs mag-
nitude varies from 10 µV to 500 µV . The input referred noise of such amplifiers
must be sufficiently lower than smallest input signal. The low noise design needs
careful sizing and biasing of the input transistors and the load. The basics of the
noise optimization techniques is explained in Section A.1.
Noise Optimization
As derived in Section A.1, the input referred thermal noise voltage PSD and input
referred flicker noise voltage PSD of a common source amplifier (Fig. 3.6) is given
by [57],
2 4 · kB · T · γ· 4 · kB · T · γ · gm,load
vn,in,th = + (3.5)
gm,in (gm,in )2
| {z } | {z }
Input Load
Figure 3.6: Noise Contribution by input and load transistors at the input. The input
2
referred noise PSD (Vn,in ) is given as total output noise current PSD (In2 ), flowing
into the output impedance (Rin ||Rload ), divided by the square of the transconduc-
tance (gm, in) of the input transistor.
2
2 KF 1 KF 1 gm,load
vn,in, 1 = + · 2 (3.6)
f Cox · W · L f Cox · W · L f gm,in
| {z } | {z }
Input Load
where γ is the thermal noise coefficient which depends on the effective mobility
and channel length modulation. It is 2/3 for older technology nodes but is reported
to be larger for sub-micron technologies. kB is Boltzmann Constant, T is the temper-
ature in Kelvin [55, 58]. KF is technology dependent flicker noise co-efficient and
is lower for PMOS. It is found to be increasing with technology scaling. Cox is oxide
capacitance per unit gate area, f is the frequency and W , L are width and length of
the transistor respectively. Eqn. 3.5 and Eqn. 3.6 provides key insight in reducing
the noise contribution of the load and input transistors in the input-referred-noise.
OTA architecture
The schematic of the OTA is shown in Fig. 3.7. PMOS with large gate area is used
as the differential input pair to reduce flicker noise contribution by it [59]. The
Figure 3.7: Schematic of the proposed neural amplifier. Gm − Gm architecture

is used. Isteal is used to reduce the transconductance of the load transistors and
achieve voltage gain.
noise contribution of different transistors can be reduced by referring to Eqn. 3.5

and Eqn. 3.6. Flicker noise contribution of input transistor pair can only be reduced
by increasing the gate area. Both Win · Lin product and Win /Lin ratio of the input
pair has to be increased, to increase gate area and transconductance respectively.
This essentially pushes input transistor pair into the weak inversion region where,
fortunately, it possesses maximum current efficiency (gm/Id) [60].
The specific current Is is given by,
2 · η · µ · Cox · VT2 · W
IS = (3.7)
L
where η is sub-threshold slope coefficient, VT is thermal voltage [60] [55].

Inversion coefficient (IC) is defined by the ratio ID /IS where ID is the drain
current. Specific Current IS for input transistor pair is 11.4 µA giving IC = 0.0874
for ISS = 2µA. Other than the input transistor pair, all transistors have IC > 0.1
where current efficiency is inferior than that of weak inversion region [60]. This is
a definite requirement for a low noise design.

The thermal noise analysis of the amplifier (Fig. 3.7) gives input referred ther-
mal noise as,
2
vn,in,th 1 gm,5 gm,9
= 4 · kB · T · γ · + 2 + 2 V 2 /Hz (3.8)
BW gm,in gm,in,ef f gm,in,ef f
The flicker noise analysis of the amplifier (Fig. 3.7) gives input flicker referred
noise as,
2
vn,in, 1
K 1 2
gm,5 2
gm,9
f
= · + 2
+ 2
V 2 /Hz
BW Cox · f Win · Lin W5 · L5 · gm,in,ef f W9 · L9 · gm,in,ef f
(3.9)
where BW is the bandwidth and gm,in,ef f = gm,in · Rx /(Rx + Ry ) (Section A.2).
Transistors M3,4 and M7,8 , being cascode transistors, don’t add significant noise at
low frequency [57].
Referring to Eqn.3.8 and Eqn.3.9, the noise contribution of transistors other
than that of the input transistors can be removed by making gm5 , gm9 << gm,in .
It is usually done by decreasing their W/L ratio for a given bias current. But a
limit is superimposed on this method by the maximum device length possible in a
technology and output swing availability.
In this work, the transconductance of load transistors is further reduced by de-
creasing bias current through them. Fig. 3.7 shows Isteal used for this purpose. This
leads to drastic reduction in transconductance of the load, giving large gm,in /gm,load
value. The values of W/L, gm, gm/Id for different transistors, for ISS = 2 µA, are
given in Table. 3.1. Input transistors have gm/Id = 26.24 which is nearly equal
to that in the weak inversion region (1/η · VT ). The input-referred noise for ISS
= 2 µA is found to be 3.9uV . The dominant noise contributors in this are listed
in Table. 3.2. Input pair is really the dominant noise contributor (77%) which
Table 3.1: Sizing, gm, gm/Id for all devices

Device W/L (µm/µm) gm gm/Id (V −1 )
M0 16/2 37.5 µS 18.6
M1,M2 100/2 26.26 µS 26.24
M3,M4 1/20 263 nS 17.44
M5,M6 1/20 263 nS 17.44
M7,M8 5/20 24 µS 25.1
M9.M10 5/30 10 µS 10.9
Ma, Mb 4/4 - -
Table 3.2: Dominant Noise Contributors in the OTA

Device Contribution Type of Noise
M1,M2 41.26% Flicker
M1,M2 35.38% Thermal
M9,M10 14% Thermal
M9.M10 6.72% Flicker
supports our design technique. An ideal current source Isteal would have made the
input-referred noise solely limited to that of the input transistor pair. Simulations
indicate that the pseudo-resistors Ma and Mb add negligible noise. The dominant
noise source in a diode (Section. 3.2.2) is shot noise. The shot current noise PSD is
given as: In2 = 2 · q · Idiode A2 /Hz where q is the charge of an electron and Idiode is
the average current flowing through the diode. The current through diode Idiode is
small in the amplifier as it is connected to the gate of the input transistor. Hence it
adds negligible noise.
The advantage of this noise reduction technique is two-fold. Apart from the
noise reduction, a moderate voltage gain can also be achieved using Gm − Gm
architecture in the amplifier. The voltage gain AV can be calculated as (Fig. 3.7),
V −V
op om
AV = (3.10)
VIN − VREF
Taking gm5,6 >> gds3,4 , gds5,6 ,
gm,in,ef f
AV = (3.11)
gm5
Eqn. 3.11 depicts that the voltage gain for the amplifier is given by the ratio
of the transconductances of two PMOS devices. It partially cancels the detrimental
effect of PVT variations on AV . It also shows that whole input transconductance
doesn’t translate to the voltage gain as some of the small signal current is lost
in Isteal branch. Effective input transconductance can be calculated as gm,in,ef f =
gm,in ·Rx /(Rx +Ry ) where Rx and Ry are small signal impedances shown in Fig. 3.7.
Note that except for Isteal branch, only PMOS transistors are used in the amplifier
that reduces flicker noise content in the total output noise. Cascode architecture
is used due to its superior current efficiency over the folded cascode architecture.
Transistors M7−10 are used to implement Isteal , as shown in Fig. 3.7.
3.2.4 Noise-Power Trade-off
As shown in the Section. 3.2.3, the input referred noise of an OTA can be limited
solely to the noise of input transistor using proper sizing and biasing. But other than
intrinsic electronic noise of transistor devices, the background noise [32, 33] of the
system also limits the dynamic range. The background noise primarily consists of
firing activity of the neighboring neurons. The maximum detectable signal strength
can also vary due to change in electrode-neuron spacing.
For an amplifier limited by thermal noise, the power consumption (PD ) and
input referred noise (vni,thermal ) are related as,
1
PD ∝ 2
(3.12)
vni,thermal
Eqn. 3.12 clearly states that to lower input referred noise, more power must
be consumed and vice versa. Hence for smaller SNR case, the power dissipation
Noise−Power Trade Off

10
Input Referred Noise (uV)

8
4
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Bias Current (uA)
Figure 3.8: Noise-power trade-off. Input referred noise of the amplifier reduces
with increase in power consumption.
of the amplifier can be reduced by using a lower bias current. It increases the
input referred noise of the amplifier, but does not hamper the dynamic range of the
system. The amplifier proposed can be biased from 200 nA to 2 µA, based on the
dynamic range requirement, modulating input referred noise from 9.92 µV to 3.9
µV respectively. In Fig. 3.7, Iss and Isteal are controlled to vary the bias current.
Fig. 3.8 shows how input referred noise varies with different bias currents.
3.3 Cin Optimization
Neural LNAs are traditionally ac-coupled amplifiers to reject large dc-offsets at the
electrode-electrolyte interface [21, 28]. The high pass pole introduced by this ca-
pacitor has to be large enough to pass signals as low as few hertz where LFPs reside.
Earlier researchers have used off-chip capacitors in the range of a few nano-farads
for this purpose. The present generation of NRFEs use on-chip coupling capacitors
in the range of tens of picofarads for this purpose. The area of the LNA and NRFE
is dominated by these coupling capacitors [11] due to their large size and large
number. Any reduction in the size of these capacitors can save a lot of area which
can be potentially utilized for other purpose in the system.
Typically large gate area PMOS input transistors are used in neural LNAs to
mitigate flicker noise which causes large input parasitic capacitance. This large
input parasitic capacitance plays an important role in defining the size of these
coupling capacitors. In this section, it is shown that the careful sizing of the input
differential pair can result in significant reduction in the input capacitance size
without deteriorating their noise performance.
3.3.1 Noise Analysis in ac-coupled LNAs
In this section, the effect of input parasitic capacitance on the noise performance
of ac-coupled LNAs is investigated. Both open-loop and closed-loop amplifiers are
analyzed for the completeness of the problem. It is shown that the input parasitic
capacitance deteriorates the noise performance in both amplifiers in similar fashion.
Open Loop Amplifier
Fig. 3.9(a) represents an open-loop ac-coupled amplifier with open loop voltage
gain A(s). The input-referred noise PSD (vn2 ), of the amplifier, is taken uncorrelated
with the input and hence modeled as additive. Cin is the input coupling capacitor
and Cp represents the parasitic input capacitance of the amplifier.
The effective input to the amplifier A(s), vg (s), is given by,
Cin
vg (s) = .vin (s) + vn (s) (3.13)
Cin + Cp
From Fig. 3.9(b),
vg (s) = Ho (s).vin (s) + vn (s) (3.14)
Hence,
vn(s)
Cin +
vin(s) + vo(s)
A(s)
vg(s)
Cp
(a)
vn(s)
+ +
vin(s) Ho(s) A(s) vo(s)
vg(s)
(b)
Figure 3.9: Effect of parasitic capacitance on effective input referred noise in open-
loop amplifiers.
Cin
Ho (s) = <1 (3.15)
Cin + Cp
which represents input signal attenuation.

From Eqn. 3.14, the effective input-referred noise PSD of the ac-coupled ampli-
fier can be calculated as,
2 vn2
vn,in = (3.16)
Ho2
which says that noise PSD is effectively amplified due to the input parasitic
capacitance Cp , by the factor Ho2 .
Closed Loop Amplifier
Fig. 3.10(a) represents a closed-loop ac-coupled amplifier with open loop voltage
gain A(s). The input-referred noise PSD (vn2 ), of the amplifier, is taken uncorrelated
with the input and hence modeled as additive. Cin is the input coupling capacitor,
Cf is the feedback capacitance and Cp represents the parasitic input capacitance of
the amplifier.
The effective input to the amplifier A(s), vg (s), can be calculated as,
1 Cin
vg (s) = .vin (s) + vn (s) (3.17)
Cf Cin + Cf + Cp
1 + A(s).
Cin + Cf + Cp
This can be equivalently represented by Fig. 3.10(b) as,
1
vg (s) = Hc (s).vin (s) + vn (s) (3.18)
1 + A(s).F
where,
Cf
vn(s)
Cin + vg(s)
vin(s) + vo(s)
A(s)
Cp
(a)
vn(s)
+ + vg(s)
vin(s) Hc(s) A(s) vo(s)
F
(b)
Figure 3.10: Effect of parasitic capacitance on effective input referred noise in
closed-loop amplifiers.
Cin
Hc (s) = <1 (3.19)
Cin + Cf + Cp
represents input signal attenuation.

and
Cf
F = <1 (3.20)
Cin + Cf + Cp
represents the feedback factor.

The effective input referred noise PSD can be calculated from Eqn. 3.18 as,
2 vn2
vn,in = (3.21)
Hc2
which says that noise PSD is effectively amplified due to the feedback capaci-
tance Cf and input parasitic capacitance Cp , by the factor Hc2.
3.3.2 Input Capacitance Optimization
Fig. 3.11 depicts input coupling in an ac-coupled open-loop neural amplifier. The
effective parasitic capacitance CP at the gate is given by,
CP = CGB + CGS + CGD · (1 + AV 0 ) (3.22)
Assuming the transistor is operating in weak inversion region [61],
1
CP ≈ .W.L.Cox + W.Lov .Cox + W.Lov .Cox .(1 + Av0 ) (3.23)
3
1
CP ≈ .W.L.Cox + W.Lov .Cox (2 + Av0 ) (3.24)
3
where Lov is the overlap length, W is the width of the transistor, L is length of
the transistor and Cox is the oxide capacitance [62]. First term in Eqn. 3.24 shows
Figure 3.11: Input parasitic capacitance accentuates effective input referred of the
amplifier. Av0 is the voltage gain from gate to drain of the transistor.
that CP is a function of input transistor sizing and increases linearly with gate area
of the input transistor. Remaining terms in Eqn. 3.24 increase with the width of the
transistor and illustrates the detrimental effect of Miller capacitance in ac coupled
neural LNAs.
The transfer function Hin (s) is defined as,
Vg (s) s.R.Cin
Hin (s) = = (3.25)
Vin (s) 1 + s.R.(Cin + Cp )
In pass-band, ω > 1/(R.(Cin + Cp )),
Cin
Hin (s) = (3.26)
Cin + Cp
which is the attenuation that input signal has to go through to reach gate of
2
the input transistor. Hence the effective input referred noise voltage Vn,in,ef f of
2
the amplifier employing an OTA with input referred noise PSD Vn,in,OT A can be
calculated as,
Z FH 2
2
Vn,in,OT A
Vn,in,ef f = .df (3.27)
FL |Hin (s)|2
C + C 2 Z FH
2 in p 2
Vn,in,ef f = Vn,in,OT A .df (3.28)
Cin FL
1 Gout
where FL = , FH = , R is the resistance emulated by
2.π.R.(Cin + CP ) 2.π.CL
the pseudo-resistor, Gout is the effective output conductance and CL is the load
capacitance for the amplifier.
2
The input referred noise PSD vn,in,OT A for an amplifier dominated by noise from
input pair is given by,
2 2 2
vn,in,OT A = vn,in,1/f + vn,in,th V 2 /Hz (3.29)
The input-referred thermal noise PSD and input-referred flicker noise PSD are
given by,
2 4.K.T.γ
vn,in,th = V 2 /Hz (3.30)
gm
2 KF 1
vn,in,1/f = · V 2 /Hz (3.31)
Cox · W · L f
And for input transistors operating in subthreshold region, gm = Id /ηVT ,
2 4.K.T.γ.η.VT
vn,in,th = V 2 /Hz (3.32)
Id
From Eqn. 3.28 and Eqn. 3.29, for a constant current consumption, bandwidth
and FH >> FL ,
C + C 2 K
2 in p F 2
Vn,in,ef f = .ln(α.(CP + Cin )) + Vn,th (3.33)
Cin Cox .W.L
2
where α = R.Gout /CL , Vn,th = 4.K.T.γ.η.VT .FH /Id represents thermal noise
floor. Thermal noise just acts as a pedestal for flicker noise, which must be de-
creased by operating in highest gm /Id region and not over-designing bandwidth.
Eqn. 3.24 and Eqn. 3.33 indicates that a very aggressive increase in gate area
(W.L) of the input transistor, to tackle flicker noise, will adversely affect the low
noise design. A bigger input capacitance is required, to compensate this increase in
effective noise, which is area inefficient. Hence for a given Cin , minimize Vn,in,ef f
by finding (Win ∗ Lin )opt .
The variation of input referred noise with the gate area is shown in Fig. 3.12(a)
when flicker noise is the dominant noise (Vn,in,1/f >> Vn,in,th ). It tells that a larger
input coupling capacitance is required to achieve a lower input referred noise if the
input transistors are not optimally sized. Fig. 3.12(b) depicts that optimum sizing
of input pair becomes more important in presence of thermal noise, in addition to
flicker noise. The optimum area ((Win ∗Lin )opt ) also becomes smaller in the presence
of thermal noise as the extra thermal noise demands smaller input attenuation and
hence smaller input transistors.
Cin = 5 pF is used which is smaller than the previous state of the art neural
amplifiers [24] [11]. KF = 60 × 10−27 V 2 F , Lov = 10nm and Cox = 10f F/um2
are extracted from simulations and used in Fig. 3.12. This analysis is valid when
noise contribution of other transistors is made negligible via proper biasing and siz-
ing. The aspect ratio W/L of the input transistor should be optimized, to minimize
thermal noise Vn,th . The length is chosen based on the Vds,sat value, decided by the
swing requirement at the drain. Minimum length is not chosen due to poor output
conductance in deep sub-micron technologies.
The limit on the W.L product due to Miller capacitance can be relaxed by using
cascoding. The attractive property of cascoding for low noise design is that cascode
transistor doesn’t contribute to the output noise at low frequencies [57]. But it
does eat into the available output swing which is critical for submicron technologies
employing lower supply voltage. Hence cascoding is used in one side only (M3,4 ) as
a trade-off between input signal attenuation and output swing. Table 3.3 compares
15
(Cin=1 pF)
(Cin=2 pF)
10
(uV)
(Win*Lin)opt
(C =3 pF)
in
n,in,1/f
(C =4 pF)
in
V
5
(C =5 pF)
in
0
0 1000 2000 3000 4000 5000
Gate Area (um2)
(a)
20
15 Flicker + Thermal Noise

(uV)
10
n,in
V
5 Only Flicker Noise
0
0 1000 2000 3000 4000 5000
Gate Area (um2)
(b)
Figure 3.12: Optimum sizing of input transistor pair minimizes input referred noise
for a given Cin . (a) Input referred flicker noise variation with the gate area of the
input pair for different input capacitance Cin . (b) Input referred noise variation
with the gate area in presence of thermal noise (Vn,th = 2µV ) for input capacitance
Cin = 5pF .
Table 3.3: Comparison of input coupling capacitance

[21] [24] [49] This work
Technology 1.5 µm 0.5 µm 1.5 µm 0.13 µm
LCF 25 mHz 45 Hz 15 mHz 5 Hz
HCF 7.2 kHz 5.32 kHz 4 kHz 7 kHz
Cin,tot 40 pF 28 pF 40 pF 10 pF
the input capacitance size with the state-of-the-art neural LNAs.
3.4 Experimental Results
The neural amplifier was fabricated in UMC 130 nm, 1P8M CMOS technology. Fig.
3.13(b) illustrates the two configurations of the amplifier that were fabricated: one
using MIMCAP as Cin and another using P-MOSCAP as Cin. Since the input signal
swing is very small, the distortion caused by putting MOSCAPs in signal path due to
their large voltage sensitivity is expected to be negligible. The area of the amplifier
was dominated by capacitors, followed by the input transistor pair. AMP block was
used as a buffer with voltage gain 5 V/V. The die micrograph of the chip is shown
in Fig. 3.13(a).
3.4.1 Electrical Characterization
LNA with MIMCAP as Cin
Fig. 3.14 shows the measured ac response of the amplifier. The lower cut-off fre-
quency and higher cut-off frequency are found to be 5 Hz and 7 kHz respectively for
Vbias= 0 V. The lower cut-off frequency is found higher than the simulated result
which can be attributed to inaccurate modeling of the transistor and the leakage
currents in the deep depletion region. But the cut-off is still lower than that of a
MOS-bipolar pseudo-resistor. The mid-band gain is found to be 37 dB. Fig. 3.15
shows the PSD of the LNA output for Fin = 500 Hz and Vin = 100 µVp−p .
(a)
Cin,mim
Vin Vo1+
M
Vref LNA AMP U Vo+
Vo1-
X
Cin,mim
CMFB C load
Cin,mos Vcm
M
LNA Vo2+ U Vo-
AMP
X
Vo2-
Cin,mos
LNAbias AMPbias
(b)
Figure 3.13: Chip fabricated in UMC 130 nm, 1P8M CMOS technology. (a) Die
micrograph of the chip. (b) Block Diagram of the system fabricated.
Measured AC response of LNA (mid−band gain = 37dB)

5
−5
−10
Output (dB)
−15 Vbias= 0 V
−20
Vbias= Vdd
−25
−30
−35
−40 −1 0 1 2 3 4 5
10 10 10 10 10 10 10
Input Frequency
Figure 3.14: Measured ac response of the amplifier for Vbias = 0 V and Vbias =
Vdd.
Low frequency noise in Fig. 3.15 contains 50 Hz power line interference and
flicker noise. Even a small pick up of 50 Hz power line [27], capacitively or induc-
tively, is manifested in the output due to large voltage gain. Large input impedance
of the amplifier worsens this condition. A makeshift Faraday cage is made using
aluminum foil, minimized wire loop sizes and used twisted pair to reduce the inter-
ference by power line signal. It has reduced the amount of interference but still its
not negligible. The remaining interference is removed while processing the data.
PSRR is found to be 67 dB. The input referred offset is measured as 65 µV . This
small value is due to the large size of the input transistor pair (with common cen-
troid layout) and better matching in 130 nm technology. One drawback of using
more advanced technology (small Vdd ) and open loop architecture is limited output
swing and the amplifier achieves 1 % THD for input swing of 400 µV .
−2
10
Output PSD (Volt/sqrt(Hz))
−4
10
−6
10
−8
10
−10
10 −1 0 1 2 3 4
10 10 10 10 10 10
Frequency (Hz)
Figure 3.15: PSD for LNA output employing MIMCAPs as Cin. Vin = 100 uVp−p, Fin
= 500 Hz.
LNA with MOSCAP as Cin
This configuration of LNA was fabricated keeping area advantage in the mind.
MOSCAPs have higher specific capacitance than MIMCAPs. But it is not showing
voltage gain as much as LNA employing MIMCAPs. It could be because of the small
capacitance emulated by the MOSCAP due to some biasing problem. Hence there
is a possibility of large attenuation of the signal from the source to the gate of
the input pair. A dc offset is applied at the input to modulate Cin,mos and noticed
improvement in the response. But the gain is still not appreciable.
Noise
Fig. 3.16(a) shows input referred noise PSD of the amplifier for ISS = 1µA. Power
line interference and its third harmonic can be seen in the plot. The integration of
the PSD till π/2 ∗ FH = 11KHz gives Vin,rms = 5.5 µVrms which is very close to the
√
expected value (Fig. 3.8). The thermal noise floor is 48 nV/ Hz. Fig. 3.16(b)
−4
Input referred Noise PSD (Volt/sqrt(Hz)) 10
50 Hz
−6
10 150 Hz
−8
10
−10
10
−12
10 0 1 2 3 4
10 10 10 10 10
Frequency (Hz)
(a)
(b)
Figure 3.16: Noise characterization. (a) Input referred noise PSD. The power line,
its odd harmonics and flicker noise can be seen in it. (b) Input referred noise
(output noise divided by the voltage gain). The rms value is Vin,rms = 5.5 µVrms .
Table 3.4: Summary and comparison of the measured results
[21] [42] [24] [49] [29] This work

Technology 1.5 µm 1.5 µm 0.5 µm 1.5 µm 0.18 µm 0.13 µm
Power 80 µW 115 µW 7.56 µW 27.2 µW 8.6 µW 1.5 µW
VDD ±2.5 V ±1.5 V 2.8 V ±1.7 V 1.8 V 1.5 V
AV 39.5 dB 39.3 dB 40.85 dB 39.3 dB, 45.6 dB 50 dB 37 dB
LCF 25 mHz dc (±250 mV) 45 Hz 15 mHz 105 Hz 5 Hz
Cin,tot 40 pF - 28 pF 40 pF - 10 pF
HCF 7.2 kHz 9.1 kHz 5.32 kHz 4 kHz 9.2 kHz 7 kHz
THD (1%) 16.7 mVp−p 5 mVp−p 7.3 mVp−p 17.4 mVp−p 2.4 mVp−p 400 µVp−p
PSRR 85 dB N/A 75dB - 52 dB 67 dB
Vni,rms 2.2 µVrms 7.8 µVrms 3.96 µVrms 3.6 µVrms 5.6 µVrms 5.5 µVrms
N.E.F 2.9 19.4 2.67 4.9 4.6 2.58
shows measured input referred noise waveform.

Noise efficiency factor (N.E.F) has been largely used to compare different neural
LNA architectures. It is basically a figure of merit based on power-noise trade-off.
It is defined as,
r
2 · Itot
N.E.F = Vni,rms · (3.34)
π · UT · 4kT · BW
For Itot = 1 µA, Vni,rms = 5.5 µV & BW = 7 kHz, N.E.F = 2.58 which is better
than the present state of the art neural LNAs. NEF 2 .Vdd [54] comes out to be 9.98.
3.4.2 In vitro experiment
Performance of the proposed LNA is also validated using an in vitro experiment that
emulates a neuron-electrode interface in a NRFE. Fig. 3.17 explains the test setup
used for the experiment. Epoxy-coated Tungsten electrode (UEWLFCSEEN1E from
FHC [63]) was used as the recording electrode B and saline solution as the elec-
trolyte. The impedance of the electrode is 5 MΩ at 1 kHz. Artificial spike signals
were generated as linear combination of rising and decaying exponential wave-
forms by programming Agilent 33250A arbitrary waveform generator using Agilent
33503A BenchLink Waveform Builder software and fed to aluminum electrode A.
Figure 3.17: Test set-up for in vitro testing of the chip. The PCB is shielded using
thin aluminum foils to protect from interference from 50 Hz power line.
Figure 3.18: In vitro acquisition of artificial EAP signal. Input (Fig. 3.17) is ∼
8mVpp .
An additional attenuation of 20 dB is introduced using SUHNER 6610.19.AA atten-

uators to bring the LNA input into the dynamic range of the amplifier. Fig. 3.18
depicts the faithful retrieval of the action potential from the saline solution. Table.
3.4 shows the comparison of the measured results with previous state of the art
works.
3.5 Summary
In this chapter, we focused on the design of a neural LNA. An emphasis on the

employment of the open loop architecture is made and it is advocated due to its
potential advantages over closed loop architecture for the application. A novel so-
lution for pseudo-resistor is proposed for the rejection of unknown dc-offsets at
electrode-electrolyte interface. An NMOS transistor in deep-depletion region is
made to work as the pseudo-resistor which presents high incremental resistance
and can withstand larger swing than MOS-bipolar pseudo-resistor. Lower distor-
tion in the proposed pseudo-resistor comes from the inherent symmetric structure
of the pseudo-resistor for both positive and negative signal swings.
A low noise design technique to reduce noise contribution of transistors other
than the input pair is proposed. This technique is well suited for higher technology
nodes where supply voltage is not large. Hence the traditional method to reducing
the trans-conductance by sacrificing the signal swing is not very effective. In the
proposed technique, the trans-conductance of the load transistors of the LNA is
reduced by stealing current through them. This technique also enables in achieving
a moderate voltage gain from Gm − Gm and helps in reducing the gain error due
to PVT variations by first order. The input transistor pair is selectively operated in
weak inversion to achieve maximum current efficiency for low noise design.
An analysis, for optimum sizing of the input transistors, to minimize input cou-
pling capacitance size in ac-coupled neural amplifiers is presented. The sizing of
the coupling capacitor in found to be dependent on the sizing of the input transis-
tor pair. It becomes very important in low frequency ac-coupled low noise amplifiers
as they they are corrupted by flicker noise too which is often tackled by using large
gate area input transistors. It is shown that by properly sizing the input transistor,
in a region with both flicker noise and thermal noise, the requirement on the size
of the input coupling capacitance can be relaxed. This significantly reduces area of
the amplifier and will enable more number of recording channels for a given area.
A novel low-noise fully-integrated neural amplifier is designed in UMC 130 nm,
1P8M CMOS technology. It can be biased adaptively from 2 µA to 200 nA, modu-
lating the input referred noise, based on the dynamic range requirement. The am-
plifier can reject dc offsets at electrode-electrolyte interface. The amplifier shows
a band-pass response with lower cut-off frequency being tunable. In vitro experi-
ments, to record action potentials from saline solution, were performed which val-
idates the usefulness of the amplifier in NRFE. The amplifier proposed consumes
lowest power compared to the published designs till the date and has achieved
large time constant of ∼ 0.2sec which makes it useful for other low frequency and
low noise applications as ECoG, EEG etc. The amplifier presented in this paper
achieves N.E.F = 2.58 which is smaller than the present state of the art designs.
Chapter 4
Energy-Efficient DAC Switching

Techniques
4.1 Introduction
AR ADCs [64] [65] are very popular in moderate speed and moderate reso-
S lution applications due to their low energy consumption [66–68]. The en-
ergy consumption is very crucial for applications that are predominantly battery-
operated e.g wireless sensor nodes [69–71] and implantable biomedical devices
[10, 11, 15, 39, 40, 46]. The energy consumption in the SAR ADC improves with
CMOS scaling due to its digital nature. However the DAC power consumption does
not scale well because passive components (capacitors) do not follow Moore’s law
and is also limited by the swing requirement. In this chapter, we illustrate two
novel DAC switching techniques, FlipDAC switching and QCS, which reduce the
energy consumption in the capacitive DAC (CDAC) without sacrificing speed.
The chapter is organized as follows. Section 4.1.1 gives an introduction to SAR
ADC. Section 4.1.2 brings the focus to energy-efficient DAC switching techniques
and its importance in deep sub-micron CMOS technology. Section 4.2 and Sec-
tion 4.3 explains two proposed techniques, FlipDAC switching and QCS respectively.
Some of the practical considerations of QCS scheme are presented in Section 4.4.
The chapter in concluded in Section 4.5.
61
Chapter 4. Energy-Efficient DAC Switching Techniques 62
D
D 1
B B
E 1 0
E
FSR
A Vin A
F
F 0 1
C C
G 0
G
LSB
Figure 4.1: Binary search algorithm for quantization of an input.
4.1.1 SAR ADC
The goal of a ADC is to quantize an input Vin to one of the various levels in the full
scale range (FSR) of the ADC. For an N-bit ADC, there are 2N − 1 levels in the ADC.
These levels are equidistant from each other with difference equal to the resolution
of the ADC. The ADC adds error to the output due to this quantization process
which is known as quantization error. Of various ways to quantize an analog input,
SAR ADC is one popular choice.
SAR ADCs basically work on the principle of binary search process. Fig. 4.1
explains this process for a 3-bit ADC. To quantize an input Vin to one of levels among
A-G, the magnitude of the input can be compared to these levels. In binary search
process, the input is first compared to half of the ADC FSR i.e level A (= Vref /2). If
the input is found higher than level A, it is compared with level B (= 3.Vref /4), else
with with level C (= Vref /4). Similarly the process is carried on based on the result
of the previous comparison. Each comparison step gives one bit information of the
input from most significant bit (MSB) to least significant bit (LSB).
To implement a SAR ADC, you need the capability: to compare the input with
a reference level, to generate these reference levels and to control these reference
Comparator
Vin +
Reference
Buffer Data
Vdac −
decision
Vref DAC
Qdac
clk
Up/Down SAR
LOGIC
Figure 4.2: Block diagram of a conventional SAR ADC.
levels based on the result of the previous comparison. Fig. 4.2 shows the block
diagram of a conventional SAR ADC. A comparator [72] is used to compare input Vin
with the reference level Vdac . Digital-to-analog converter (DAC) generates various
reference levels and is controlled, by a successive approximation register (SAR)
logic, based on the previous decision. If the output of the comparator in logic
HIGH, an UP control signal is enabled which increases Vdac , else a DOWN control
signal is enabled to decease Vdac . Each output of the comparator is stored in a
data register. Various kind of DACs can be used in a SAR ADC but capacitive DAC
are predominantly employed due to the advantage of no static power dissipation.
Reference buffer is used to generate a clean and stable voltage reference (Vref ) with
good output drive capability.
4.1.2 Energy-efficient DAC Switching
Fig. 4.3 shows the role of a reference buffer in SAR ADCs which provides charge
to the CDAC during the binary search process. This charge (Idac ) is taken from the
supply and pose a limit on the time for which the system can be operated from
it. The energy consumption in the DAC is a significant part of the total energy
consumption in the ADC and an energy-efficient solution of the ADC should try to
Vdd Capacitive DAC Comparator
Vref Ro Idac
-+
Vss
switch control Digital
Logic
Figure 4.3: Reference Buffer in a SAR ADC.
reduce the energy consumption in the DAC.

Of late, there has been a lot of interest in energy-efficient DAC switching tech-
niques for CDAC [73–77]. These works were basically focused on increasing the
monotonicity, or making DOWN transitions more energy efficient, in the implemen-
tation of the binary search algorithm. The splitting of the 1st MSB capacitor is
employed in [73] for this purpose but it complicates the digital logic and layout
due to increase in the number of the independent switches in the CDAC. Stepwise
charging of the CDAC was employed in [78] which is a trade-off between energy
consumption and the speed of operation of the ADC.
It has been shown that the DOWN transitions takes more energy than UP transi-
tions in the digitization process [79]. This is the reason that the energy consump-
tion for a code nearer to the center of the ADC dynamic range is greater than that
of a code towards the extremes. For a 10 bit ADC, code 511 and code 512 takes
maximum energy where as code 0 and code 1023 takes minimum energy [76]. The
energy drawn from the reference can be reduced if it is possible to resolve an in-
put through fewer DOWN transitions. Even if the number of DOWN transitions are
not smaller than that of UP transitions, the energy consumption can be lowered by
pushing the DOWN transitions towards the LSBs.
Figure 4.4: Energy inefficiency in CDAC.
4.2 FlipDAC Switching
Fig. 4.5(a) shows the switching scheme proposed in [76] for a 3-bit SAR ADC for
Vip > Vin . Although it consumes the lowest energy when compared to the previous
techniques, it is not energy efficient for some of the switching steps. Fig. 4.4
explains the reasons for this. Fig. 4.4 (a) and (b) represents two ways of charging a
pre-charged capacitor in which (b) is energy inefficient and is usually encountered
in SAR ADCs. Fig. 4.4 (c) and (d) represents a DOWN transition causing Vx2 < Vx1 ,
achieved by switching 2C from Vcm to Vref m . In this, energy inefficiency arises due
to 4C which was already connected to Vref p . Splitting of 1st MSB capacitor saves the
energy wastage in the second case by minimizing the total capacitance connected to
the reference voltage during DOWN transitions. In Fig. 4.5(a), the DOWN transition
draws 5 times more energy from the reference compared to the UP transition.
Fig. 4.5(a) shows the switching scheme proposed in [76] for a 3-bit SAR ADC.
The DOWN transition draws 5 times more energy from the reference compared to
the UP transition. Fig. 4.5(b) presents the proposed switching technique. For the
DOWN transition step, the energy drawn from the reference is 5 times smaller than
that in Fig. 4.5(a). This step is performed by switching C and manipulating DAC
V V
2C C Vdac=3V/4
Vcm+3V/8 C +
Vcm
V −
2C Vcm-3V/8 C
Vcm Vcm+V/4 2C C
2C C C +
C C +
P
E=1/8
U
Vcm Vcm
− − V
D
O
2C C C C C
W
Vdac=0 Vdac=V/2 2C C Vdac=V/4
N
Vcm Vcm-V/4
2C Vcm+V/8 C +
E=0 E=0.5
Vcm
−
Vcm-V/8 C
2C C
E=5/8
(a) V
V V
2C C
Vdac=3V/4
Vcm+3V/8 C +
Vcm
−
V
Vcm-3V/8 C
2C 2C C
Vcm Vcm+V/4
2C C C +
C C + E=1/8
P
U
Vcm Vcm
− −
D
O
2C C C Vdac=0 C C
Vdac=V/2 2C C Vcm-V/8
W
Vcm
N
Vcm-V/4
+-Vdac=V/4
C
2C
E=0 E=0.5 V
Vcm
−
C FlipDac
2C C Vcm+V/8
(b) E=1/8
Figure 4.5: CDAC switching in a 3 bit ADC (a) [76] (b) FlipDAC switching. Capaci-
tors switched in each step are shown in blue color. In the figure, V = 2 · Vcm = Vref
2
and the unit of energy consumption is C.Vref .
Vip-Vin Vref-(Vip-Vin)
Vdacp-Vdacm Vdacm-Vdacp
purge
FlipDac
1 1 1 0 1 0 0 1
Flip
sign b2 b1 b0 sign b2 b1 b0
Strobe
Figure 4.6: Input digitization through the proposed FlipDAC switching technique. In
the second case, output 1001 is resolved indirectly by tracking 1110 by Vdacp -Vdacm .
reference rails so as not to degrade digital switching energy and is explained in

detail in Section 6.2.2. The proposed scheme is overall 33 % more energy efficient
than Fig. 4.5(a). Note that the DAC voltage achieved in the DOWN transition is
negative of the desired value (Vdac = −V /4). The sign of the DAC voltage can
be is corrected by either interchanging the two DAC inputs to the comparator or
by comparing this negative DAC voltage with the negative of the sampled input
voltage. The former approach is preferred as the latter will flip the offset of the
comparator which can affect the linearity of the ADC. It is explained in detail in
Section 4.2.
This reduction in the energy consumption is achieved by mapping the input
voltage to a digital code which is more energy efficient than the actual code for the
input. Fig. 4.6 explains this for a 4 bit SAR ADC. If b2 is detected as logic HIGH,
Vdacp -Vdacm tracks Vip -Vin in the conventional way. However if b2 is detected as logic
LOW, Flip goes high and, Vdacp and Vdacm interchange their roles. The remaining
tracking of the input Vip -Vin is then carried out by Vdacm -Vdacp . It is equivalent to re-
solving Vref -(Vip -Vin ) by Vdacp -Vdacm in remaining bit cycles. This maps the input to a
higher digital code and helps in reducing the number of times CDAC is discharged,
Figure 4.7: Proposed FlipDAC switching scheme for a 4 bit SAR ADC and energy
cost comparison with [76] for each step in the binary search tree.
especially during MSBs. As shown in Fig. 4.6, output code 1001 is resolved indi-
rectly by tracking code 1110 by the CDAC. This results in fewer discharging steps
than the case when CDAC resolves 1001 directly.
Fig. 4.7 represents the switching scheme for a 4-bit ADC for Vip > Vin . Note
that 2nd MSB capacitor (2C) is the replica of the remaining two LSB capacitors.
First DOWN transition in Fig. 4.7 again illustrates the concept of FlipDAC switching
technique. The FlipDAC step does not take any extra clock cycle and hence speed
is not compromised. The flipping of the CDAC is done only for the first DOWN
transition by making use of the symmetric structure of the CDAC, for both UP and
DOWN transitions, from this node. The splitting of (MSB − 1)th capacitor helps in
implementing binary search algorithm, after flipping, without incurring extra time
1=Up and 0=Down outp

0
1
outm
Flip
1
+ Vip
DACp 0 + LATCH
-
Av
DACm 0
- Vin
1
Flip
0
outm
0=Up and 1=Down 1
outp
Figure 4.8: Conceptual diagram of FlipDAC switching scheme.
and switching. The energy consumption during various steps for a 4-bit ADC is
also compared with [76] in Fig. 4.7. The number in the circle represents the total
number of unit capacitors connected to Vref . The relative energy costs are shown
on the arrows.
Fig. 4.8 shows the conceptual implementation diagram of the FlipDAC switching
technique. Once Flip goes high due to DOWN transition after the estimation of 1st
MSB, the DACp and DACm blocks take over each others role. The output of DACp
and DACm blocks start to work as the negative and positive DAC voltage respec-
tively. The output of the comparator is also complemented for correct binary search
implementation. The energy drawn from the reference for each UP (∆VDAC > 0)
and DOWN (∆VDAC < 0) transitions can be calculated as,
EU P = (Csw .(Vref − Vcm ) − (Cref + Csw ).(∆VDAC )).Vref (4.1)
EDOW N = ((Cref − Csw ) · |∆VDAC |).Vref (4.2)

220
[zhu]
200 [Zhu] This work
[anand]
)
ref
2
Energy consumed (C.V
180 E =170
avg
160 [Anand]
E =142
avg
140
[This work] 37.5 %
25.3 %
120
100 E =106
avg
100 200 300 400 500 600 700 800 900 1000
Output Code (in LSB)
Figure 4.9: Comparison of CDAC switching energy for a 10 bit SAR ADC.
Comparison of CDAC switching energy with [76] and [77] for a 10 bit SAR ADC.
Table 4.1: DAC Switching Energy Comparison for 10 bit SAR ADC
Spec. [77] [75] [76] This scheme
2
Energy (C.Vref ) 142 255.5 170 106
Saving 25.3 % 58.6 % 37.5 % -
where Csw is the capacitance switched, Cref is the total capacitance connected
to Vref before this step, ∆VDAC is the change in CDAC reference voltage in that step.
Energy Consumption
Fig. 4.9 depicts the comparison of the energy drawn from the reference for each
code in a 10 bit SAR ADC in [76], [77] and FlipDAC switching scheme. Note that
the proposed switching technique achieves minima at code 511 and 512 compared
to maxima in [76]. This happens because code 511 and code 512 are resolved
by tracking code 0 and code 1023 respectively which have no DOWN transitions.
Table. 4.1 compares the proposed scheme with the present state-of-the-art CDAC
Vip
Vip -+ +
-+
Vdacp
+ Vdacm +
+ CDAC
CDAC -
Vdacm
- Vdacp
-
Vim
- Vim
(c) Vip-Vim > Vdacm-Vdacp
(a) Vip-Vim > Vdacp-Vdacm
Vim Voff
-+ + Vdacp Flip +
+
−
Vdacp
+
CDAC CDAC Flip
- −
Vdacm Vdacm
- Flip
Vip
(b) Vim-Vip < Vdacp-Vdacm (d) Vip-Vim>Vdacm-Vdacp
Figure 4.10: Offset sensitive and offset insensitive FlipDAC switching.
switching schemes for a 10 bit ADC and shows energy savings achieved by the pro-
posed scheme over them. This scheme necessitates the use of separate sampling
capacitors which upon investigation is found favorable in reducing the power con-
sumption in the VGA and is explained in Section 5.3.
Effect of Comparator Offset
The FlipDAC switching technique causes the DAC voltage to change its polarity as
shown in Fig. 4.5(b). For a correct binary search implementation, this needs to
be corrected. This can be corrected by comparing this negative DAC voltage with
the negative of the input voltage (Vim − Vip ≤ Vdacp − Vdacm ). This can also be
corrected by interchanging the two DAC inputs to the comparator to correct the
polarity of the DAC voltage (Vip − Vim ≥ Vdacm − Vdacp ). Note that fully differential
architecture of the comparator with 4 input gives the freedom to do either. Fig.
4.10 illustrates both these situations when the effective offset is modeled in Vip
input to the comparator. In Fig. 4.10(b), the inputs are interchanged to compare
the negative of the sampled input voltage with the negative DAC voltage whereas
A Ideal B
Offset
Flipped
Constant
Offset
l
ua
ct
d
A
cte
rre
Co
2*Voff/LSB
C D
Constant Ideal
Offset
ed
Offset
ct
rre
Flipped
Co
l
ua
ct
A
Figure 4.11: Effect of flipping the offset on the linearity of a SAR ADC.
in Fig. 4.10(c) the DAC outputs are interchanged to revert the polarity of the DAC
voltage. The offset for the input voltage flips its sign in Fig. 4.10(b) but the offset
remains the same in Fig. 4.10(c). Next we analyze the effect of flipping the offset
on the linearity of the ADC.
Fig. 4.11 presents the effect of the offset on the ADC transfer characteristics.
Fig. 4.11(A) and Fig. 4.11(C) shows the transfer characteristics of a 3-bit ADC.
The ideal code transitions are the center of each code width. Fig. 4.11(A) shows
the case of a positive offset when code transitions move to the right by the amount
of the offset where as Fig. 4.11(C) shows the case of a negative offset when code
transitions move to the left. This can be corrected later by simply subtracting and
adding the offset from the output code for positive and negative offset respectively.
However when the offset flips in between the digitization process, as in the Flip-
DAC switching, the code transitions for codes below the mid-code move opposite to
that of the code transitions for codes above mid code. The red curve in Fig. 4.11(A)
and Fig. 4.11(C) shows this behavior. Fig. 4.11(B) and Fig. 4.11(D) shows the
phenomenon for an ADC of very high resolution and demonstrate the non-linearity
introduced due to the change in the polarity of the offset. The offset corrected ADC
transfer characteristics has missing codes and their number is equal to 2.Vof f /LSB.
Hence the flipping of the offset should be avoided. Fig. 4.10(d) shows the imple-
mentation of Fig. 4.10(c) which keeps the polarity of the comparator offset intact
and does not compromise the linearity. The scheme of Fig. 4.10(b) can be used
only when offset correction methods are employed in the comparator [72] which
makes sure that the offset Vof f is smaller than the LSB of the ADC.
4.3 Quaternary Capacitor Switching Scheme
Over the last decade, a lot of research has been done on improving energy efficiency
of the CDAC [74–79]. It has been shown that the DOWN transitions consumes more
energy than UP transitions [73] in the implementation of binary search tree. The
difference in the energy consumption between DOWN transitions and UP transitions
basically arise because higher MSB capacitors interfere during the extraction of LSBs
[73]. This makes the energy consumption in CDAC dependent on the output code.
MSB capacitors are benign during UP transitions but degrade energy consumption
during DOWN transitions. As a consequence, the energy consumption of codes near
to the center of the ADC dynamic range is greater than that of a code towards
extremes. For a 10 bit ADC, code 511 and code 512 consume maximum energy
where as code 0 and code 1023 consume minimum energy [76].

In this section, we propose an energy efficient switching scheme which reduces
the energy drawn from the reference by reducing the switching capacitance, com-
pared to conventional switching schemes. The proposed scheme makes the energy
consumption in the CDAC independent of the output digital code by avoiding the
interference of MSB capacitors during the estimation of the LSBs. This makes the
average energy consumption in the DAC independent of the input dynamic range.
Section 4.3.1 motivates the requirement of code-independent energy consump-
tion in CDAC for a SAR ADC. Section 4.3.2 explains the proposed switching tech-
nique. Section 4.4.1 addresses errors caused due to mismatch in charge injection by
top-plate switches. Section 4.4.2 presents the linearity implication of the switching
technique.
4.3.1 Code-independent Energy Consumption
This section introduces two benefits of having a code-independent energy consump-

tion in CDAC of a SAR ADC.
Energy consumption degradation
As the energy consumption is larger for digitization of small signals, the average
energy consumption in a CDAC can increase if the input does not traverse the com-
plete dynamic range of the ADC. Fig. 4.12 depicts the variation of CDAC energy
consumption with output code in a conventional SAR ADC for two different input
swings. For smaller input signal swings, the average energy consumption in the
DAC will increase from E1 to E2 . The average energy consumption in CDAC de-
grades from 170 CV 2 to 202 CV 2 in [76] if the input signal traverses only half the
ADC dynamic range. Hence, small input swing not only reduces achievable ENOB
but also increases the effective power consumption in the ADC. This motivates the
need for a code-independent energy consumption in CDAC.
Code
-V -V/2 0 V/2 V
E2
Energy
E1
p ut
n
I ing
Sw
Figure 4.12: Code dependent energy consumption increases average energy con-
sumption in CDAC for smaller input swings.
This phenomenon of energy consumption degradation is more prevalent for in-

puts having large peak-to-average ratio. Variable gain amplifier (VGA) is often
employed before ADC in an automatic gain control (AGC) loop to fully utilize the
ADC dynamic range. The gain of the VGA is usually decided based on the peak
of the input signal. However if the input has large peak-to-average ratio, the non-
uniform distribution of the input degrades the energy consumption in the CDAC.
The important signals with large peak-to-average ratio are biomedical signals (EAP,
ExG), RF signals with large out-of-band blockers [80] [81] etc. To verify this, neural
data recorded in vitro from the Hippocampal culture of a Wistar rat is used as the
input to the ADC. The average energy consumption in CDAC degrades to 209 CV 2
0.5
Amplitude (V) 0
Input
−0.5
2 2.5 3
Sample 4
x 10
200
Energy (CV2)
150
100 Energy Consumption
2 2.5 3
Sample 4
x 10
Figure 4.13: Energy consumption in CDAC for neural data recorded in vitro from
the Hippocampal culture of a Wistar rat. Eavg = 209 CV 2
from 170 CV 2 for Vcm -based switching [76]. Fig. 4.13 shows the variation in CDAC
energy consumption with neural data input.
Harmonic Injection
Fig. 4.14 shows the variation in the charge drwan from the supply by CDAC for a
sinusoidal input for two different swings in [76]. Fig. 4.14(b) and Fig. 4.14(d)
again illustrate the concept of FoM degradation with smaller input swing. Fig.
4.14(a) and Fig. 4.14(b) show the charge consumption in [76] for a full swing
sinusoidal input. For an input vin (t) = Vp · sin(ωin t), the charge supplied by the
reference buffer in Vcm -based switching technique [76] can be approximated by,
Qmax − Qmin π
Qdac (t) ≈ Qavg + · sin(2 · ωin t + ) (4.3)
2 2
0.6
(a) (c)
Amplitude (V) 0.4 Input 0.2 Input
Amplitude
0.15
0
−0.1
−0.35 −0.2
−0.6
200 400 600 800 1000 200 400 600 800 1000
Sample Sample
250 220
(b) (d)
Charge (CV)
Charge (CV)
200
Q =148 Qavg=196
avg
150 200
100
50 180
200 400 600 800 1000 200 400 600 800 1000
Sample Sample
Figure 4.14: Code dependent energy consumption in CDAC induces harmonic noise
into the supply.
where Qavg , Qmax , Qmin are average, maximum and minimum charge taken
by CDAC from the reference. Eqn. 4.3 depicts that code-dependent energy con-
sumption in CDAC injects 2nd harmonic in the reference buffer whose amplitude is
dependent on the difference between Qmax and Qmin . The strength of this noise
increases with the resolution of the ADC. This noise will adversely affect the design
of voltage regulator used for the supply. It can also limit the SFDR of the ADC. A
code-independent energy consumption in CDAC avoids harmonic noise injection.
4.3.2 QCS Scheme
Fig. 4.15(a) shows a binary weighted CDAC for a 5 bit SAR ADC. In the approach
presented in [76], the sign bit is extracted without any switching and then other 4
MSBs are found out by successively switching of 8C, 4C, 2C and C (C = unit capac-
itance) from Vcm to V or GND (Vcm = V /2) based on the comparison of input with
the CDAC output. Also the capacitors that were switched for the extraction of the
higher MSBs affect the energy consumption during the extraction of the remaining
LSBs. These MSB capacitors are found helpful in UP transitions but are the main
cause of the energy inefficiency in the DOWN transitions [73].

Fig. 4.15 shows the scheme proposed by us which reduces the effective capac-
itance in the CDAC by 50 %, after each bit extraction, by floating the last MSB
capacitor. Hence MSB capacitors do not affect the energy consumption during the
extraction of the remaining bits. The amount of energy delivered by the reference
to the CDAC is then only dependent on the capacitance to be switched from Vcm
to V . The smaller size of the effective CDAC also enables us to reduce the size
of switching capacitance (Csw ) which draws smaller amount of energy from the
reference.
Fig. 4.15(c) and Fig. 4.15(d) represents UP and DOWN steps respectively for
the estimation of the 2nd MSB. For this, 1st MSB capacitor (= 8C) is made to float
which enables switching of only 2C for a step change of V /8 in the CDAC output,
compared to 4C in [76]. The energy drawn from the reference is 3/4.C.V 2 for both
UP and DOWN transitions in this step. The energy consumption for these steps
in [76] are: Eup = 1/2.C.V 2 and Edown = 5/2.C.V 2 , i.e. Eavg,msb,2 = 3/2.C.V 2 .
Hence the proposed technique achieves a 50 % reduction in the average energy
consumption for this step. Similarly, Fig. 4.15(e-h) shows that floating the 2nd MSB
capacitor (= 4C) requires switching of only 0.5C, compared to 2C in [76, 77], for
the estimation of the 3rd MSB. The size of the switching capacitor for the estimation
of the ith MSB (excluding sign bit) can be calculated as,
Cdac
Csw (i) = (4.4)
4i
where Cdac is the total DAC capacitance and is equal to 2n C for an n-bit DAC.
The size of the switching capacitor reduces in a quaternary fashion in the proposed
scheme. Fig. 4.16 represents the comparison of the switching capacitance size for
each MSB with [76, 77] for a 10 bit ADC.
The net charge is always zero on the CDAC output rail in a traditional charge
redistribution DAC [82] but not in the proposed technique. The removal of MSB
E=0.22 E=0.22
V V V V V
Cdac=4C Cdac=4C
8C 2C C/2 Vcm+V/4+V/8-V/16 8C 2C C/2
Vcm+V/4+V/8+V/16
2C C C 2C C C
1.5C 1.5C
Vcm Vcm
1.5C 1.5C
2C C C 2C C C
P
Vcm-V/4-V/8+V/16 Vcm-V/4-V/8-V/16
O
8C 2C C/2
U
8C 2C C/2
W
(g) (f)
N
V
E=0.75
V V
Cdac=8C
8C 2C
Vcm+V/4+V/8
2C 2C C C
Vcm
2C 2C C C
8C 2C Vcm-V/4-V/8
(c)
UP
E=0 V E=2
Cdac=16C 8C Cdac=16C
Vcm Vcm+V/4
8C 4C 2C C C 4C 2C C C
Vcm Vcm
8C 4C 2C C C 4C 2C C C
Vcm 8C Vcm-V/4
(b)
(a)
DOWN
E=0.75
V
Cdac=8C
8C 2C
Vcm+V/4-V/8
2C 2C C C
Vcm
2C 2C C C
8C 2C Vcm-V/4+V/8
(d)
V
N
W
U
O
P
D
E=0.22 E=0.22
V V V
Cdac=4C Cdac=4C
8C 2C C/2 8C 2C C/2
Vcm+V/4-V/8-V/16 Vcm+V/4-V/8+V/16
2C C C 2C C C
1.5C 1.5C
Vcm Vcm
1.5C 1.5C
2C C C 2C C C
8C 2C C/2 Vcm-V/4+V/8+V/16 8C 2C C/2 Vcm-V/4+V/8-V/16

(h) (e)
V V V
Figure 4.15: Proposed Switching technique with quaternary switching capacitors

for a 5 bit ADC. Figure shows the extraction of first 4 bits.
3
10
Proposed
Switching Capacitor Size (C) 2 Conventional
10
1
10
0
10
−1
10
−2
10
−3
10
1 2 3 4 5 6 7 8 9
Bit Cycling Phase
Figure 4.16: Comparison of the switching capacitance sizes with [76] and [77] for
a 10 bit ADC.
capacitors creates a net residual charge on the CDAC output rail which preserves the
previous value of the CDAC output. Hence the switching of the LSB capacitors needs
to do only the incremental work. Also in this scheme only one set of capacitors is
switched at a time, from Vcm to V or GND, which keeps the design of the digital
logic simple and energy efficient.
Energy Consumption
The average energy consumption for an n-bit ADC for the proposed switching
scheme can be calculated using the expression,
n−1
X 1
Eavg (n) = 2(n−2i−1) . 1 − i .CV 2 (4.5)
i=1
2
Fig. 4.17 compares the proposed switching scheme with that of [76] and [77]
for a 10 bit SAR ADC. The average energy consumption is 97.5.C.V 2 compared to
170.C.V 2 in [76] and 142.C.V 2 in [77] which saves 42.5 % and 31.5 % energy
220
[Zhu]
200 [Zhu] [Anand]
Proposed
Energy Drawn (C.V2)
180 Eavg=170
160
Eavg=142
140
[Anand]
42.5%
120
31.3%
Eavg=97.5
100
200 400 600 800 1000

Output Code (in LSB)
Figure 4.17: Comparison of the proposed technique with [76] and [77] for a 10 bit
ADC.
over [76] and [77] respectively. As the higher MSB capacitors do not affect the
energy consumption during the estimation of the LSBs, the energy consumed for
UP and DOWN transitions are always equal which makes the energy consumption
independent of the output code.
DAC Settling
One bit cycling phase is usually dominated by the settling time given for the DAC
which in turn depends on the time constant (Ro,ref + Rsw ).Cef f (Fig. 4.18) where
Ro,ref is the output impedance of the reference buffer, Rsw is the switch resistance,
Cef f is the effective DAC capacitance and is equal to series combination of Csw and
Cdac − Csw . The proposed switching scheme reduces both Csw and Cdac for the next
MSB extraction, hence it improves the DAC time-constant and speeds up the DAC
charging and discharging process. Parasitic extracted simulations are performed to
validate this.
Vdac
Csw
Cdac-Csw
Rsw
Vref
+
−
Ro,ref
Figure 4.18: DAC settling equivalent model in a SAR ADC.
4.4 Practical Considerations of QCS Scheme
This section analyzes some of the practical considerations and implications of the
proposed QCS scheme.
4.4.1 Top-plate switch Mismatch
The gradual reduction in the size of CDAC can be performed by using switches
either at bottom plates or top plates of MSB capacitors. The drawback of using
bottom plate switch for this purpose is that the parasitic capacitance at the DAC
output rail becomes more appreciable compared to the effective CDAC size in each
step causing large gain errors. Moreover the gain error changes with each bit cycle
which can affect the linearity of the ADC. Hence it is beneficial to use switches at
the top plate [45] as parasitic capacitance scale linearly with the CDAC size and
gain error remains constant.
However, the mismatch in the charge injection by top plate switches in two
differential paths can cause errors in the output. This section presents an analysis
for the error caused due to charge injection mismatch in the top plate switches. This
analysis is also useful for SAR ADCs which employ top-plate switches in the CDAC
for variable resolution purpose [45, 83].
Ci Ci
Vdac
Q/2
negative Ci positive
xR
charge charge
Qmis
Q/2
Vdacp
+
(1-x)R Clsb
Vdac Qn Qp
-
Q/ Vdacn
2
Qmis
Ci
Q/2
Ci Ci
Figure 4.19: Charge injection mismatch in top-plate switches.
Fig. 4.19 shows the charge injection on the residual DAC capacitance when the
last MSB capacitor is removed. The figure also shows the unit element of the DAC
which is replicated to implement the complete DAC structure. The resistance of DAC
switches can be divided in top plate and bottom plate switches based on the ratio
x (x < 1). CMOS switches are typically employed as top plate switches for lower
charge injection and linearity. When NMOS and PMOS are on, they have charge Qp
and Qn stored in them.
Qp = W.L.Cox · (VSG − |VT P |) (4.6)
= W.L.Cox · (Vdac − VSS − |VT P |)
Qn = −W.L.Cox · (VGS − VT N ) (4.7)
= −W.L.Cox · (VDD − Vdac − VT N )
This charge flows out of them once they are turned off. As the DAC capacitance
is reduced to half in each step, equal impedance is seen by this charge on two sides.
It causes half the charge flow into the residual DAC and other half into the capacitor
which is disconnected. Considering only half of the total charge flows in the DAC,
the total charge injection Qmis in the ith step is given by,
1
Qmis (i) = · (Qp (i) + Qn (i))
2
= Wsw (i).Lmin .Cox · Vdac (i)
Vdd + Vss VT N − |VT P |
− ( )+
2 2
The mismatch in the charge injection in positive and negative DAC, with voltages
Vdacp and Vdacn , is given by,
∆Qmis (i) = Qmis,p (i) − Qmis,n (i)
= Wsw (i).Lmin .Cox .Vdac (i)

∆V
T N,p − ∆VT N,n
+ Wsw (i).Lmin .Cox .
2
∆VT P,p − ∆VT P,n
−
2
where Vdac (= Vdacp -Vdacn ) is the effective DAC voltage at that step. First term
in the above equation represents the error due to mismatch in VGS of NMOS and
PMOS in a CMOS switch. Second term arises due to threshold voltage mismatch
between NMOS and PMOS in CMOS switches in positive and negative DAC.
The analysis of both effects is presented in following two sections. The length
used in the DAC switches is assumed to be the minimum length (Lmin ) in a tech-
nology and DAC switches are assumed to be sized in a binary way for layout con-
sideration. The PMOS and NMOS transistors in each CMOS switch are assumed to
be have same widths and lengths for charge injection cancellation and small clock
feed-through. The sizing of LSB capacitor (Clsb) of the DAC can be found in Ap-
pendix B.2. The sizing of the unit switch of the DAC can be found in Appendix
B.1.
CMOS switch VGS mismatch
The charge injection mismatch error due to VGS mismatch in NMOS and PMOS is
dependent on the value of the instantaneous DAC voltage and is given by,
∆Qvgs (i) = Wsw (i).Lmin .Cox .Vdac (i)
= 2(N −i−1) .Wu .Lmin .Cox .Vdac (i)
(4.8)
where Wsw (i) = 2(N −i−1) .Wu and Wu is the size of the unit DAC switch (Eqn.
B.5) and is dependent on the resolution and the speed of the ADC.
The DAC voltage error due to this charge injection mismatch depends on the size
of the residual DAC (Cdac (i) = Cdac (i + 1)/2 = 2(N −i−1) .Clsb) and is given by,
∆Qvgs (i)
∆Vdac,vgs (i) =
Cdac (i)
Wu .Lmin .Cox .Vdac (i)
=
Clsb
(4.9)
The above error is dependent on the digital output code of the ADC and is small
for smaller codes. Considering the worst case which happens at the largest code,
the instantaneous DAC voltage is given by,
1
Vdac (i) = Vref · 1 − i
2
5
10
∆Vdac,vgs /∆lsb
0
10
1 MS/s
−5 10 MS/s
10 100 MS/s
1 GS/s
0 2 4 6 8 10 12 14 16 18 20
Resolution (in bits)
Figure 4.20: Comparison of the charge injection error due to Vgs mismatch normal-
ized to the quantization error.
The total charge injection error due to Vgs mismatch in each step can be calcu-
lated as,
∆Vdac,vgs = ∆Vdac,vgs (1) + ∆Vdac,vgs (2)
+ .... + ∆Vdac,vgs (N − 2)
1 Wu .Lmin .Cox .Vref
= N − 3 + N −2 ·
2 Clsb
(4.10)
The ratio ∆Vdac,vgs /∆lsb , where ∆lsb = Vref /2N , can be used as a metric to com-
pare the magnitude of this charge injection error with the quantization error. For
large N, this is given by,
∆Vdac,vgs N.Wu .Lmin .Cox .Vref 2N

≈ · (4.11)
∆lsb Clsb Vref
where Wu is the size of the unit DAC switch (Eqn. B.5) and is dependent on the
resolution and the speed of the ADC.
Fig. 4.20 shows the variation of this metric with resolution for different sampling
speeds. It tells that this error dependent on both resolution and speed of the ADC.
It also tells that the charge injection error due to VGS mismatch of CMOS switch
becomes more important at higher resolution and higher speed. Fig. 4.20 is plotted
for UMC 0.13 µm CMOS technology with µ = 270 cm2 /V s, Cox = 10 f F/µm2 and
Vdd = 3.VT H = 1 V.
Threshold voltage mismatch
The charge injection mismatch error due to threshold voltage mismatch in NMOS
and PMOS is given by,
∆V
T N,p − ∆VT N,n
∆Qvt (i) = Wsw (i).Lmin .Cox .
2
∆VT P,p − ∆VT P,n
−
2
The variance of this error is given by,
2 2
σV2T N + σV2T P
σQ,vt (i) = (Wsw (i).Lmin .Cox ) · (4.12)
2
where Wsw (i) = 2(N −i−1) .Wu and Wu is the size of the unit DAC switch (Eqn.
B.5) and is dependent on the resolution and the speed of the ADC.
From the Pelgrom’s model [84],
2 2
A2VT N + A2VT P
σQ,vt (i) = Wsw (i) · Lmin · Cox · (4.13)
2
Hence the variance of the DAC voltage error can be calculated as,
2 2
σQ,vt (i) σQ,vt (i)
σV2dac,vt (i) = 2
= N −i−1
(Cdac (i)) (2 · Clsb)2
2
Wu · Lmin · Cox · (A2VT N + A2VT P )
= 2
(4.14)
2 · 2(N −i−1) .Clsb
2
10
σV2 dac /σN

2 0
10
q
−2
10 1 MS/s
10 MS/s
100 MS/s
1 GS/s
0 2 4 6 8 10 12 14 16 18 20
Resolution (in bits)
Figure 4.21: Comparison of the charge injection error due to threshold voltage
mismatch normalized to the quantization error.
Assuming charge injection errors due to threshold voltage mismatch from dif-
ferent top plate switches to be uncorrelated,
σV2dac,vt = σV2dac (1) + σV2dac (2) + .... + σV2dac (N − 2) (4.15)
The total error due to charge injection is given by,
2
1 Wu · Lmin · Cox
· (A2VT N + A2VT P )
σV2dac,vt = 1 − N −2 . 2
(4.16)
2 2 · Clsb
The variance of the quantization error for a N-bit ADC with step size ∆lsb =
Vref /2N is given by,
2
2 ∆2lsb Vref
σQN = = 2N (4.17)
12 2 · 12
q
For this error, 2
σV2dac /σN can be used as a metric to compare the magnitude of
the charge injection error with the quantization error. For large N, this is given by,
s
2
Wu · Lmin · Cox · (A2VT N + A2VT P ) 22N · 12
2
· 2
(4.18)
2 · Clsb Vref
where Wu is the size of the unit DAC switch (Eqn. B.5) and is dependent on the
resolution and the speed of the ADC.

Fig. 4.21 shows the variation of the above metric (Eqn. 4.18) with ADC res-
olution for different sampling speeds. It tells that this error dependent on both
resolution and speed of the ADC. It also tells that the charge injection error due
to threshold voltage mismatch becomes more important at higher resolution and
higher speed. Fig. 4.21 is plotted for UMC 0.13 µm CMOS technology with µ =
270 cm2 /V s, Cox = 10 f F/µm2 , AVT N = 6.6 mV.µm, AVT P = 4.4 mV.µm and Vdd =
3.VT H = 1 V.
Based on analysis presented in the section, charge injection mismatch error is

found to be less critical for moderate resolution and moderate speed SAR ADCs.
Charge injection mismatch error due to VGS mismatch of CMOS switch is found to
be more critical than that due to threshold voltage mismatch between PMOS and
NMOS. Charge injection cancellation techniques [85] will prove to be helpful in
extending the range of the applicability of QCS technique.
4.4.2 Linearity Analysis
Appendix.B.3 gives an introduction to the linearity analysis of a binary weighted

capacitive DAC. In this section, we analyze the linearity aspect [86] of QCS scheme.
If the unit (LSB) capacitance has a value of Clsb with standard deviation σc , the
switching capacitance size for the estimation of k th LSB is given by,
22k−(N−1)
X
2k−(N −1)
Csw,k = 2 · Clsb + ǫk (4.19)
i=1
where ǫk is the deviation in the k th unit capacitor from the expected value with
√
variance σc and σc /Clsb = Ac / Clsb where Ac is a process dependent constant.
PN −1
The output of CDAC, employing QCS, for an input y = i=0 bi · 2i , where bi can
be 1 or 0, is given by,
N P 2k−(N−1)
· Clsb + 2i=1
−1 2k−(N −1)
Vdac,qcs (y) X 2 ǫi
= P2k+1 bk
Vref k=0 2 k+1 · C
lsb + ǫi i=1
(4.20)
Neglecting the 2nd term in the denominator of each of above terms,
N P 2k−(N−1)
· Clsb + 2i=1
−1 2k−(N −1)
Vdac,qcs (x) X 2 ǫi
= k+1
bk
Vref k=0
2 · C lsb
(4.21)
The error from the expected output is calculated as,
N −1 P22k−(N−1)
∆Vdac,qcs (y) X
i=1 ǫi
= k+1
bk (4.22)
Vref 2 · Clsb
k=0
which can be represented equivalently as,
N −1 P 2k−(N−1)
∆Vdac,qcs (y) X 2N −k−1 · 2i=1 ǫi · bk
= N
(4.23)
Vref k=0
2 · Clsb
If the errors in different unit capacitors are independent identically distributed,

the variance of this error is given by,
2 N
σ∆Vdac,qcs
(y) X −1
22(N −k−1) · (22k−(N −1) · σc2 ) · bk
2
= 2
(4.24)
Vref k=0
22N · Clsb
2 N
σ∆Vdac,qcs
(y) X −1
bk · 2N −1 · σc2
2
= 2
(4.25)
Vref k=0
22N · Clsb
which is worse than that of a conventional binary-weighted DAC [79]. The ratio
of variances of this error for the QCS scheme and the conventional binary weighted
scheme (BW) is given by,
2 PN −1 N −1
σQCS (y) k=0 bk · 2
2
= PN −1 (4.26)
σBW (y) k=0 bk · 2
N −1−k
A behavioral simulation was performed for both binary weighted (BW) DAC and
QCS DAC for a 10-bit ADC [79, 86]. The standard deviation in unit capacitors and
the size of unit capacitors (Clsb) are calculated based on 3-σ matching requirement.
Fig. 4.22 compares the standard deviation of the INL and DNL for a 10 bit CDAC. The
QCS scheme does look inferior to the binary weighted DAC on the linearity aspect.
This seems obvious as due to continual reduction in the size of the DAC with every
MSB extraction, the amount of averaging of the mismatch error decreases which in
turn makes this technique more non-linear.
However with the continuous increase in the matching of capacitors [87] with
technology scaling, the scheme could become more useful to reduce energy con-
sumption in SAR ADCs. To achieve same linearity as in BW DAC, Clsb has to be
doubled which doubles the average energy consumption. But the advantage due to
the code-independence in the technique remains.
Implementation
The proposed switching scheme requires switching of the capacitance smaller than
the unit capacitance for the estimation of the LSBs due to continuous reduction
in the effective DAC size. As it is difficult to implement well-matched switching
capacitors lower than unit capacitance Clsb in a CMOS technology. So we may
want to use the switching technique for first few MSBs and then proceed to the
conventional binary weighted capacitor switching techniques [76, 77]. As the total
energy consumption is dominated only by first few MSBs, the energy consumption
will not degrade significantly.
σIN L of BW DAC σDN L of BW DAC
0.1 0.2
Error (in LSB)
Error (in LSB)

0.15
0.05 0.1
0.05
0 0
0 128 256 384 512 640 768 896 0 128 256 384 512 640 768 896
σIN L of QCS DAC σDN L of QCS DAC

0.6
0.5
Error (in LSB)
Error (in LSB)

0.4 0.4
0.3
0.2
0.2
0 0.1
0 128 256 384 512 640 768 896 0 128 256 384 512 640 768 896
Code (in LSB) Code (in LSB)
Figure 4.22: Comparison of standard deviation of INL and DNL error in binary
weighted (BW) and QCS DAC.
4.5 Summary
This chapter discussed energy-efficient DAC switching techniques for a SAR ADC.
An energy efficient FlipDAC switching scheme for capacitive DAC in SAR ADCs
is proposed. The scheme obviates the energy-inefficient DOWN transitions at the
higher MSBs by flipping the positive and negative DAC inputs to the comparator
during the decision of the 2nd MSB. It consumes small energy in the CDAC without
using extra capacitors or sacrificing speed of the ADC. The DAC switching schemes
is compared with the state-of-the-art DAC switching techniques and was found more
energy efficient from all of them. The DAC switching technique consumes 37 % less
energy than the present state-of-the-art.
Another energy-efficient switching technique for a capacitive digital-to-analog
converter, QCS, is presented which employs switching capacitors that vary, instead
of binary, in a quaternary manner. In this technique, the MSB capacitors do not
influence the energy consumption during the extraction of the remaining bits which
makes the energy consumption independent of the output code. The reduction in
size of the switching capacitance is also helpful in achieving a faster settling in the
DAC and hence improves the speed of the successive approximation register (SAR)
ADC. The proposed technique, compared to the Vcm -based switching technique,
consumes 42.5 % less switching energy for a 10-bit SAR ADC.
The limitation of this technique due to the the errors due to top plate switch
charge injection mismatch is analyzed. Charge injection error due to mismatch in
VGS of PMOS and NMOS of a CMOS switch is found to be more critical compared to
that due to threshold voltage mismatch. An analysis on the linearity for this scheme
is also presented. The QCS scheme is found to be inferior to the schemes employing
binary switching capacitors as due to continual reduction in the size of the DAC, the
amount of averaging of the mismatch error decreases. To achieve same linearity as
in BW DAC, Clsb has to be doubled which doubles the average energy consumption.
But the advantage due to the code-independence in the technique remains.
Chapter 5
SAR ADC design for NRFE
5.1 Introduction
NALOG -TO - DIGITAL converter (ADC) is another very important block in a NRFE.
A It typically utilizes a SAR ADC [64] due to its moderate resolution require-
ment (8-10 bit) and its high energy efficiency [8, 45, 46]. Till now the ADCs in
NRFEs have followed a traditional design methodology except in [45] which was
focused on the design of a variable resolution ADC array for an implantable neural
sensor. Motivated by the need for energy-efficient solutions for each block in NRFE,
we present a solution for the ADC and the VGA for a NRFE in this chapter. However
the design techniques and concepts can be used in the analog front-end for other
applications (EEG, ECoG etc) too.
Fig. 5.1 represents a N-channel NRFE where a single k-bit ADC is employed
to digitize N-channels in a time division multiplexed fashion. The input buffer
Figure 5.1: VGA and ADC in a N-channel neural recording front end.
94
Chapter 5. SAR ADC design for NRFE 95
(VGA) and ADC need to support larger bandwidth than the other blocks due to the
processing of the time division multiplexed data.
Typically the VGA (Fig. 5.1) needs to track the input on the CDAC in a very small
time (2-3 bit cycles) which demands large bandwidth. In this chapter it is shown
that employing a ping-pong input sampling architecture [88] enables full ADC sam-
pling period for the input tracking. It reduces the bandwidth requirement and hence
power consumption in the VGA. The amplitude of the maximum detectable signal
varies with neuron-electrode distance and probe impedance which is frequency de-
pendent. A fixed gain in NRFE will either under-utilize the ADC dynamic range or
causes clipping of the peaks. Hence we emphasize on a large programmable range
in voltage gain of the VGA.
NRFE generate tremendous amount of data due to chronic recording from a
number of neurons. Spike feature extraction [8] and simple thresholding [15] are
two popular ways through which researchers have tried to reduce output data rate.
However the former needs extra hardware and power whereas later can cause loss
of information. The present low ODR NRFE typically needs an extra spike detection
block, e.g one DAC per channel [15], which consumes large area. In this work, we
merge spike detection logic into the SAR ADC, utilizing the CDAC, to mitigate the
processing of the background noise and reduce ODR.
The chapter is organized as following. Section 5.2 illustrates the architecture
of the ADC designed for the NRFE. The technique used to relax the bandwidth of
the VGA is explained in Section 5.3. A brief discussion on the variable resolution
scheme can be found in Section 5.4. Section 5.5 addresses the concept of the activity
dependent A/D to mitigate the processing of the background noise to reduce ODR
and energy consumption. The chapter in concluded in Section 5.6.
CDAC comparator
REFP Vinp
+ Vop
LATCH
outp
Vdacp
REFBFR
Vcm -
Vdacm
+ Av outm
Vinm Vom
REFM -
Data Register
NEXT
Vip0 STB
Cin0
Cin1
clk
Vim0 Flip
Vip
VGA
Vip1 Vim clk=Fs/2

Vim1 Switch Control
Asynchronous
SAR Logic
Pingpong
Sampling
DR
Sth
Threshold N[2:0] Digital Output
and Noise noise Sth
Estimation
Figure 5.2: Block diagram of the proposed SAR ADC.
5.2 SAR ADC Architecture
The block diagram of the proposed SAR ADC is shown in Fig. 5.2. Fully differential
input and DAC voltage are used for immunity against the common mode noise
[89, 90]. The residual difference between the DAC voltage and the input voltage
is amplified by the preamplifier (AV ) whose sign is detected by the latch upon STB
signal. The ADC employs an asynchronous architecture using the concept of self-
timing [65, 71] to relax the clock requirement. Two pairs of sampling capacitors
are employed to use ping-pong input sampling. A master clock of only half the
sampling speed is used due to it, saving power in clock buffers by 2X and reducing
total system power consumption. The CDAC and sampling capacitors are segregated
to gain advantages as explained in Section 5.3.
An on-chip voltage reference buffer is implemented to provide clean and stable
voltage reference to the ADC. The Vcm rail is not buffered as ideally no charge is re-
quired from this rail owing to the symmetric DAC switching scheme similar to [76].
Energy-efficient switching scheme, FlipDAC (Section 4.2), is employed to reduce
Ts
1 2 3 4 5 6 7 8 9 10
Tracking 8 bit cycles
Tvga Tref
Sampling
Instant (a)
Ts Ts
Tracking odd sample and Tracking even sample and
Digitizing even sample Digitizing odd sample
Sampling Sampling Sampling

Instant Instant Instant
(b)
Figure 5.3: Input sampling in a SAR ADC. (a) Conventional sampling (b) Ping-pong
input sampling.
CDAC power consumption. The dynamic range (DR) decides the resolution setting
(N2 -N0 ) of the ADC. Spike threshold ST H is calculated based on the background
noise and is stored in registers dedicated to each channel. This is explained more
in Section 5.5.
5.3 Ping-Pong input sampling
Fig. 5.3(a) depicts the timing diagram in a conventional 8 bit SAR ADC. Typically
2-3 bit cycles or equivalent delay (Tvga ) is dedicated to the tracking of the input
on the CDAC (CDAC ). It is then followed by 8 bit-cycles for the digitization of the
sample. It demands large bandwidth (current) in the input buffer (VGA) as it has
small time to track the input from the previous state. The power consumption in
the VGA can be reduced by giving more time for the input tracking but it contradicts
with the design of the reference buffer in this sampling approach.
In this ADC, ping-pong sampling scheme [88] is employed which relaxes the
0
clk0 clk1
1
1 1 0
Cin1 Ts Ts
1
Vip 0 0 ADCp
Cin0
VGA Vin,cm Vcm ADC
Cin0
Vim 0 0 ADCm
Cin1 1
1 1
0
1
Figure 5.4: Architecture of ping-pong input sampling scheme to relax the band-
width requirement of VGA and reference buffer. Vin,cm is the output common mode
voltage of the VGA.
design of both VGA and the reference buffer. Fig. 5.3(b) and Fig. 5.4 illustrate
the sampling scheme employed in the ADC. In this scheme, inputs are sampled
on capacitors (Cin0 and Cin1 ) rather than CDAC . There are two sets of sampling
capacitors of which when one tracks the input, the other is used to digitize the
previous sample. This enables the use of the complete sample period (TS in Fig.
5.3(b)) for the input tracking which relaxes the bandwidth requirement of the VGA.
It also reduces the power consumption in the reference buffer as comparatively
more time is available for bit cycling. Ping-pong sampling in the ADC enables the
use of two half rate clocks for even and odd-numbered channels. It alleviates the
clock requirement by 2X, over asynchronous schemes employing clocks equal to
that of the sampling rate, which reduces power consumption in clock buffers. The
following section quantitatively shows the advantage due to the sampling scheme.
The settling mechanism is assumed to be of first order and the analysis is done for
settling error of 1 LSB = Vref /2N .
Power Saving in VGA
If Tvga = αvga · TS , the N bit settling error can be given by,

Vref −Tvga
Verr1 = N = Vref · exp (5.1)
2 Req · CDAC
Assuming output resistance Req = β/ID where β is a constant dependent on the

architecture of the driver and ID is the current consumed in the driver,
N · ln(2) · βvga · CDAC

ID,vga,1 = (5.2)
αvga · TS
Now for ping-pong input sampling αvga = 1,
N · ln(2) · βvga · CDAC

ID,vga,2 = (5.3)
TS
The percentage power saving can be calculated as,
ID,vga,1 − ID,vga,2
= (1 − αvga ) · 100% (5.4)
ID,vga,1
Power Saving in reference buffer
If Tref = αref · TS , the N bit settling error due to the reference buffer can be given
by,

Vref −(Tref )/2N
Verr2 = N = Vref · exp (5.5)
2 Req · Ceq
where Ceq is the equivalent capacitance seen by the reference buffer and 50 %
of each bit cycle (Tref /N) is given for CDAC settling.
N · ln(2) · βref · Ceq

ID,ref,1 = · 2N (5.6)
αref .TS
For ping-pong input sampling αref = 1,

N · ln(2) · βref · Ceq

ID,ref,2 = · 2N (5.7)
TS
The percentage power saving can be calculated as,
ID,ref,1 − ID,ref,2
= (1 − αref ) · 100% (5.8)
ID,ref,1
Hence for an 8 bit ADC, with 2 cycles given for sampling in the conventional
approach, αvga = 0.2 and αref = 0.8. Hence 80 % power can be saved in the VGA
and 20 % power can be saved in the reference buffer by using ping-pong sampling
scheme. Actually the power saving in the VGA is more as the sampling capacitors
(Fig. 5.4) are much smaller than CDAC which is used as sampling capacitors in SAR
ADCs with conventional sampling approach.
The drawback of this architecture is of course the use of extra sampling capac-
itors. But as their sizes are determined by thermal noise, not matching, the area
penalty is not significant for moderate resolution ADCs. This architecture also re-
quires good matching between two sampling paths for a single channel application
and may need calibration [91, 92]. But no such requirement is imposed for multi-
channel input, as in NRFE, where each channel (even-numbered or odd-numbered)
traverses same path every time. It also alleviates the concern of duty cycle distor-
tion due to the half-rate clocking as even and odd numbered channels are sampled
by two different non-overlapping clocks.
5.4 Variable resolution
The resolution of the ADC is usually determined based on the dynamic range re-
quirement (SNR) which is the ratio of the maximum and minimum detectable sig-
nal. The maximum detectable signal in the NRFE can vary a lot depending on the
distance between electrode and the neuron which is not well controlled. The min-
imum detectable signal is limited by the background noise. The background noise
in these systems is predominantly due to the spiking activity of the distant neurons
and can vary a lot. Hence an energy-efficient NRFE must have the ability to adapt
the resolution of the ADC. Also, an electrode can pick up signals from a number of
neuron (∼ 6) in a NRFE and the discrimination of these signals is done using spike
sorting algorithms. To preserve this information, signal-to-signal ratio (SSR) also
determines the resolution [45] along with the SNR.
The ADC is designed with reconfigurable resolution to mitigate unnecessary pro-
cessing in case of smaller dynamic range. The previous state-of-the-art variable res-
olution ADCs [45,83] reconfigured resolution by switching out MSB capacitors with
the reduction in resolution using switches at the top plates. This saves power expo-
nentially with the resolution, as power consumption was dominated by the CDAC,
but increases layout-cum-logic complexity.
However we have made the CDAC power consumption small compared to the
digital switching power by using the FlipDAC switching scheme. Hence, the resolu-
tion is reduced by simply halting the binary search algorithm in between based on
the resolution requirement. It enables the resolution reconfiguration from 8 bit to
1 bit at 1 bit step. This scheme of variable resolution saves power linearly with the
resolution and is finally limited by the static power consumption in the ADC.
5.5 Activity dependent A/D
There is a great need to reduce the amount of data to be transmitted to enable

chronic recording from a number of channels [7, 40]. A 100 channel NRS with
sampling frequency 20 KS/s and digitizing using a 10-bit ADC needs a wireless link
to supports 20 Mbps of data rate. Transmitting this data in a low power way is
challenging. The next generation of these systems must incorporate more on-chip
Input −
1 bit/spike
Tx
DAC +
Sth
Threshold
(a)
Free
running Spike
Features
Input ADC DSP Tx
clk
(b)
Figure 5.5: Data rate reduction in a NRFE. (a) Simple Thresholding. (b) Spike
Feature Extraction.
processing capability to record from thousands of neurons and reduce the amount
of data to be transmitted. And a power-efficient solution should use small overhead
for it.
Fig. 5.5(a) presents a scheme used in [7]. In this scheme, an array of spike
detectors is used to detect and encode a spike event in one bit. The spike thresh-
old can be set adaptively based on the background noise [37]. The information in
neural EAPs is essentially encoded in spike time-stamps but the amplitude informa-
tion in EAPs is also important for spike sorting purpose. However representing a
spike as a point event causes loss of information required for spike sorting which is
indispensable in a practical NRFE.
Spike feature extraction [39,40] is another way of reducing output data rate and
is depicted in 5.5(b). It is found that out of many features of a spike if we keep only
Spike
ADC Sorting
Input −
DSP Tx
CDAC +
Sth
SAR
Figure 5.6: Data rate reduction through proposed activity dependent A/D scheme.
some of the spike features in the data, it does not causes any loss of information
required for the spike sorting [93]. In this technique, an on-chip DSP processes the
raw signal from NRFE and extracts the required spike features. Then only these
spike features are transmitted via the RF telemetry. It does save energy in the RF
telemetry block but there is no reduction in power consumption of the NRFE. The
ADC is still free running and is doing unnecessary conversions of the background
noise. Moreover, its needs complicated circuitry for spike detection using energy
operators, noise-shaping filters and feature extractors [8].
For this reason we have employed an activity dependent A/D conversion scheme
to obviate the processing of the background noise. Fig. 5.6 presents the proposed
scheme. In the proposed scheme, the digitization process is only enabled when the
input is found larger than the spike detection threshold ST H (Fig. 5.2). The spike
detection threshold ST H is decided based on the magnitude of the background noise
(σn ), ST H = k.σn where k = 3-4 so that the probability of the false detection of the
noise as a spike is very small [7, 38].
Using this technique, the spike features that are kept intact are maximum ampli-
tude (Amax ), minimum amplitude (Amin ) and time separation between them (Tpp).
In [93], these three spike feature are shown to be the most important ones to char-
acterize a spike. This was earlier used in [94] where the scheme is implemented
in the DSP block and hence does not optimize the power consumption in the ADC.
Figure 5.7: Effective Activity Factor.(a) Spike approximated as a triangular wave-

form. (b) Important spike features that should be preserved. [94]
Our scheme reuses blocks from the SAR ADC (Fig. 5.6) as DAC and comparator to
implement the logic which in-built in the ADC.
Fig. 5.7(a) depicts the conceptual diagram of the activity dependent A/D. The
spike is approximated by a triangular waveform with maximum amplitude Amax
and spike duration Tspike . The slope the spike (Fig. 5.7(a)) can be calculated as,
dV 2.Amax k.σn
m= = = (5.9)
dt Tspike x
Hence,
k.σn .Tspike
x= (5.10)
2.Amax
The total number of spikes in a given measurement time (Texp ) is α = SR · Texp

where SR is the spike rate in spikes/sec. Then the effective time (Tef f ) for which
the N bit ADC operates is given by,
(Texp − α(Tspike − 2.x))

Tef f = α(Tspike − 2.x) + (5.11)
N +1
The second term in the above equation indicates that the ADC operates only for
one cycle for spike detection and is idle for remaining N bit cycles if the spike is not
detected. The effective activity factor (EAF) of as N bit ADC working on activity
based A/D scheme can be given by,
Tef f 1 N ST H
EAF = = + .SR .Tspike . 1 − (5.12)
Texp N +1 N +1 Amax
Eqn. 5.12 represents the effective time for which an activity dependent ADC will
be working when compared to a free running ADC. It represents the reduction in
both power consumption in the ADC and output data rate (ODR) of the system.
The typical values of Tspike and SR are 1 msec and 100 spikes/sec respectively.
Assuming ST H /Amax = 0.2, EAF for an 8 bit ADC can be calculated from Eqn. 5.12
as ∼ 0.18 which saves 82 % energy and ODR over a free running ADC.
The spike detection threshold (ST H ) can be increased to reduce EAF and to
provide more immunity against the background noise but may cause loss of infor-
mation. Hence the value of ST H should be decided based spike sorter’s requirement
in addition to the background noise [45]. The designed SAR ADC is programmable
to operate either in this mode or free running mode to transmit raw data.
5.6 Summary
This chapter discussed the design considerations of SAR ADC for a NRFE. For mul-
tichannel input, the use of ping-pong input sampling structure is emphasized. It
enables full sampling period for bit cycling and tracking. It saves power in both
VGA and reference buffer by providing more time for settling and relaxing their
output resistance. This sampling scheme also helps in employing master clock of
half of the sampling speed. It reduces the power consumption in the clock buffers
which makes the system more energy efficient. The matching requirement for the
two paths is relaxed for multi-channel input as in NRFE whereas it becomes impor-
tant for a single channel application.
Owing to large dynamic range and varying background noise, the resolution
of the ADC can be varied to avoid unnecessary processing and save power. The
variable resolution scheme is very simple and is incorporated in the digital logic.
The relative power of the CDAC does not scale well the resolution compared to
the digital switching power. However the power consumption in the CDAC is quite
small compared to the digital switching power due to a novel energy efficient DAC
switching technique. The power consumption reduces linearly with the resolution.
Output data rate is a serious threat neural recording application due to the
tremendous amount of data that is generated by them. The transmission of the
raw data over a wireless link in an energy-efficient way is challenging. The pro-
cessing of the background noise is mitigated by using an activity dependent A/D
scheme which reduces both power consumption and output data rate of the NRFE.
The savings in power consumption and ODR are analyzed for a spike input to the
ADC and is expressed in term of EAF .
Chapter 6
Neural Recording Front End Design
HE block diagram of the 16-channel neural recording system is shown in Fig.

T 6.1. The system consists of 16 AC-coupled low-noise amplifiers (LNA) and
gain stages (A2). Open loop architectures were employed for these two blocks as
a power-efficient solution for this application. LNA and A2 blocks are controlled
using a sliding window power-on control by channel controller which periodically
puts them in sleep mode. It reduces the static power consumption of the system
and make the system energy-efficient.
The 16-channels are time division multiplexed in a variable gain amplifier (VGA)
followed by a variable resolution SAR ADC. The ADC is programmable to operate
in a free running mode or activity-dependent mode as explained in Section 5.5.
The resolution (N) and spike threshold (ST H ) are decided based on the dynamic
range requirement (DR) of the system which depends on maximum detectable
spike amplitude (Amax ) and background noise (Noise). The input dynamic range
(DR) also controls the gain of the V GA, through channel controller, to match it
with that of the ADC. V GA also mitigates gain error in LNA and A2 due to
PVT variations as open loop architectures were used [95]. All channels can be
monitored separately to set spike thresholds (ST H ) and resolution (N) which are
stored in dedicated registers for each channel.
Sliding window power-on control
The 16-channels are time division multiplexed and when the ADC is catering to one
channel, other channels are unnecessarily wasting power [8, 96]. Fig. 6.2 depicts
107
Chapter 6. Neural Recording Front End Design 108
Figure 6.1: Block Diagram of the 16-channel neural recording system.
CLK 0 1 2 3 14 15 0 1 2 3 14 15
CH0 Active Sleep Boot Active Sleep Boot
CH1 Boot Active Sleep Boot Active Sleep
CH2 Sleep Boot Active Sleep Sleep Boot Active Sleep
CH15 Sleep Boot Active Sleep Boot Active
Figure 6.2: Sliding Window Power-on control. Only two channels consume power
at a time.
Cbias
Off
M5 M0
On
Iout
Iref
Figure 6.3: ON/OFF control employed for power scheduling in the amplifiers.
the sliding window power-on control used to reduce average power consumption in
LNA and A2 stages. Only 2 channels are enabled at a time of which one is in active
state and another is booting to be active in the next cycle. Hence each channel
consumes power only for 2 out of 16 cycles and this effectively reduces static power
consumption by 8X in these stages. It also helps in reducing the crosstalk between
different channels.
The number of channels that can be put into sleep mode at a time is decided
based on the recovery time of the active blocks and the sampling rate (Fs ) of the
ADC. The number of LNAs that should be ON at a time Non can be found by [96],
Non > Fs · tT (6.1)
where tT is the transient time for the recovery of the LNA. The sampling rate Fs
is related to the bandwidth of the input signal. For an N-channel system, the over-
sampling ratio (∝ Fs /Fnyquist ) must be carefully decided as it will demand faster re-
covery from the LNAs and hence more power. The transient time tT is dependent on
the parasitic capacitance on the various nodes and slewing of large MOS-capacitors
at the bias nodes [97]. The ON/OFF scheme used is shown in Fig. 6.3. The recov-
ery time for this scheme is limited by the charging of parasitic capacitance at the
various nodes in the amplifier but not the bias nodes.
Vx2 Vx1
VCM VCM
Mx Bias M0 My Bias M13
Req Req
Vg1 Vg2
VIP M1 M2 VIM
Vg1 Vg2
Bias
Cin = 2 pF Cin = 2 pF M14
Vx1 Vx2 VOP1 M15 M16 VOM1
Cbias M8
Bias1 M7 M3 M4 Bias1 M11 M12
VOM VOP
VOM1 VOP1
Bias2 M9 M5 M6 M10 Bias2 M17 M18
Figure 6.4: Schematic of Neural LNA.
6.1 Low Noise Amplifier
A detailed discussion on the design of neural LNA is already given in Chapter 3.

This section presents the LNA designed as a part of the neural recording front end
(Fig. 6.1). The schematic of the LNA designed for the system is depicted in the Fig.
6.4. It consists of two stages with the first stage being a low noise and second stage
providing additional voltage gain.
The LNA stage uses PMOS input pair (M1−2 ) with large gate area for low flicker
noise and are operated selectively in weak inversion region for high current effi-
ciency [60]. Transistors M7−10 are used to degrade the transconductance of the
load transistors (M5−6 ) to reduce their noise contribution in the effective input-
referred-noise of the LNA. This current stealing technique also helps in attaining a
moderate voltage gain using gm -gm topology. The load transistors are also PMOS to
decrease flicker noise in the total noise. The lower cut-off frequency of the amplifier
is tunable to reject LFPs and pass only EAPs and is controlled by varying the pseudo-
resistor Req . The pseudo-resistor Req along with input capacitance Cin presents a
high pass pole which rejects large dc offsets at electrode-electrolyte interface. The
amplifier employs only 2 pF of input coupling capacitance using the Cin optimiza-
tion technique explained in chapter 3 and [95]. The detrimental effect of Cgd due
to Miller effect is further reduced by using capacitive neutralization technique [98].
Transistors Mx and My in Fig. 6.4 are used for this purpose and are sized half of
the input transistors.
The second stage also uses PMOS input pair (M15−16 ) and employs partial posi-
tive feedback (M11−12 ) to decrease effective output conductance at the output node
and hence achieve a voltage gain. The current in the main branch and the positive
feedback branch is controlled by the width of transistors M13−14 which prevent the
effective conductance at the output node from becoming negative. This stage can
also be bypassed if the input signal is found strong and large gain is not required in
the front end.
The amplifier is also made noise-adaptive to trade input-referred-noise with the
power consumption. The amplifier has two modes of operation: ’low-noise’ and
’not-so-low-noise’ with input referred noise of 5.5 µVrms and 11 µVrms respectively.
This is achieved by controlling width of transistors M0 , M7−10 with one bit digital
control. The current consumption in the two modes are 1 µA and 0.5 µA respec-
tively in the LNA stage.
6.1.1 Gain Stage
The schematic of the gain stage (A2) is shown in Fig. 6.5. It is again an open
loop amplifier employing gm .Rd architecture. The gain error of this stage is also
corrected by the VGA. This block can be put in sleep mode by cutting the bias to
the tail transistor. This block consumes 1 µA of current from 1.2 V supply and the
expected voltage gain from this stage is ∼ 20 dB. 6 − σ Monte-Carlo simulations
were performed to make sure that error in voltage gain is not large. It achieved a
THD of 56 dB for output swing of Vp−p = 200 mV.
Sleep
Vip Vim
Vom 0.5 u Vop
1.25M 1.25M
Figure 6.5: Schematic of an open loop gain stage (A2).
6.2 SAR ADC
The block diagram of the proposed SAR ADC is shown in Fig. 6.6. Fully differential
input (Vinp , Vinm ) and DAC voltages (Vdacp , Vdacm ) are used for immunity from the
common mode noise [89, 90]. The residual difference between the DAC voltage
and the input voltage is amplified by the preamplifier (AV ) whose sign is detected
by the latch using the STB signal which is generated in the SAR logic block. The
ADC employs an asynchronous architecture using the concept of self-timing [71]
which alleviates the requirement of a high speed clock in the ADC. The reference
DAC and sampling capacitors are segregated to gain advantages by ping-pong input
sampling. Two pairs of sampling capacitors are employed to use ping-pong input
sampling which relaxed the bandwidth requirement of the VGA and reference buffer
(Section 5.3). A master clock of only half the sampling speed is required due to it
which saves power in clock buffers and reduces total system power.
An on-chip voltage reference buffer is implemented to provide clean and stable
voltage reference (REFP, REFM) to the ADC. The Vcm rail is not buffered as ideally
no charge is required from this rail owing to the symmetric switching scheme [76].
CDAC comparator
REFP Vinp
+ Vop
LATCH
outp
Vdacp
REFBFR
Vcm -
Vdacm
+ Av outm
Vinm Vom
REFM -
Data Register
NEXT
Vip0 STB
Cin0
Cin1
clk
Vim0 Flip
Vip
VGA
Vip1 Vim clk=Fs/2

Vim1 Switch Control
Asynchronous
SAR Logic
Pingpong
Sampling
DR
Sth
Threshold N[2:0] Digital Output
and Noise noise Sth
Estimation
Figure 6.6: Block diagram of the proposed SAR ADC.
Energy efficient switching scheme, FlipDAC, is employed to make DAC power con-
sumption small. QCS scheme is not used in the implemented ADC. Spike threshold
ST H is calculated based on the background noise and is stored in registers. The dy-
namic range (DR) decides the resolution setting (N2-N0) of the ADC. The variable
resolution logic is implemented in the SAR logic to reduce the complexity.
6.2.1 Comparator
The comparator consists of two blocks, preamplifier and latch. Unlike many of
the previous publications on SAR ADC where preamplifier is not used before the
clocked latch, the use of a preamplifier is preferred by us for offset and kickback
noise mitigation. Kickback noise is an important concern in this architecture due
to the use of small sampling capacitors to save power in the VGA using ping-pong
input sampling architecture.
Preamplifier
The preamplifier in SAR ADC is subjected to step input only and needs to amplify
the error just enough for the detection of the sign by the latch. It relaxes the settling
s
requirement in the preamplifier. If Av (s) = Av0 /(1 + ωp
), for an input Vin .u(t) and
initial condition at output as Vo (0−), the output vo is given by,
vo (t) = Av0 .Vin .(1 − e−ωp t ) + Vo (0−).e−ωp t (6.2)
The second term in Eqn. 6.2 can be eliminated by resetting output before en-
abling CDAC output which becomes important when successive voltage difference
are of opposite signs. The output of the preamp, after a delay Td from CDAC output,
can be calculated and effective amplification Av,ef f is given by,
Av,ef f = Av0 (1 − e−ωp Td ) (6.3)
Above equation represents the effective amplification provided by the preampli-

fier and must be chosen based on the accuracy requirement (Av0 ), speed (Td ) and
the power consumption (ωp ).
The schematic of the preamplifier is shown in Fig. 6.7. The amplifier con-
sists of two pair of input transistors each for Vin and Adac . A partial positive feed-
back is employed to reduce the effective output conductance using transistors of
width W2 . The load transistors are sized (W1 > W2 ) to prevent the effective output
conductance from becoming negative, even in presence of mismatch [99, 100]. If
W2 = η.W1 where η < 1, the dc voltage gain Av0 and the bandwidth ωp [101], for a
load capacitance CL , can be calculated as,
gm,in 1
Av0 = (6.4)
gm,w1 1 − η
W1 W2 W2 W1
Vom Vop
Vinp Adacp Adacm Vinm
BIAS
Figure 6.7: Schematic of the 4-input preamplifier. Preamplifier is employed to mit-

igate the effect of kickback noise on small sampling capacitors. A partial positive
feedback reduces the output conductance.
gm,w1 · (1 − η)
ωp = (6.5)
CL
By increasing η towards unity, more voltage gain can be achieved but it makes
the preamplifier more sluggish which is a typical gain-bandwidth trade-off. We
have chosen η = 0.8 as a trade-off between voltage gain, speed and stability. The
simulated values are Av0 = 14 and fp = ωp /(2π) = 8 MHz. The inputs Adacp and
Adacm are interchangeable to implement the FlipDAC logic as explained in Section
6.2.2.
Latch
Clocked latch are very popular in SAR ADCs as they do not consume static power
and and are digital in nature. They typically employ a positive feedback structure
through a cross-coupled inverter. Fig. 6.8 shows one such structure. Two inverters
are biased around their trip-point using two voltage sources Va and Vb with CLKa
-Gm CLKb
CLKa CLKa
B Cp A
Vb Cp Va
CLKb -Gm
Figure 6.8: Functionality of latch employing cross-coupled inverters.
= 1 and CLKb = 0.
Va = Vtrip + ∆/2 (6.6)
Vb = Vtrip − ∆/2 (6.7)
Now with CLKa = 0 and CLKb = 1, based on the transconductance Gm of each

inverter and the parasitic capacitance Cp at the output of each inverter, the inverter
outputs undergo regenerative positive feedback giving voltages at nodes A and B
as,
∆ t.G −t.G
m m
VA (t) = Vtrip + .exp + VA (0−)exp (6.8)
2 Cp Cp
∆ t.G −t.G
m m
VB (t) = Vtrip − .exp + VB (0−)exp (6.9)
2 Cp Cp
Hence the voltage at node A increase with time towards Vdd and voltage at
Cp
node B decrease with time towards Vss . The time constant is given by τ =
Gm
and can be used to calculate speed and the resolution of the latch. Gm should
be maximized and Cp should be minimized for a fast latch. Note that increasing
the size of the transistors to increase Gm will not result in increasing the speed as
parasitic capacitance also increases proportional. Preamplifier helps in increasing
CLK CLK
Va Vb
CLK
A B
CLK
Figure 6.9: Schematic of the sense amplifier based latch.
the speed of the latch by presenting larger differential input to the latch. Resetting
the two output before the regeneration phase helps in eliminating the last term of
the above two equations which basically represents hysteresis. This also helps in
increasing the accuracy and speed of the latch. If Vtrip = Vdd /2, the time to resolve
∆ differential voltage is given by,
Cp,ef f V
dd
Tres = .loge (6.10)
Gm 2.∆
And the resolution N, without no offset and hysteresis, can be estimated by

putting ∆ = Vdd /2N ,
1 1
∼ T (6.11)
2N res .Gm
exp
Cp,ef f
The latch employed in the ADC is a conventional sense amplifier based latch
[79]. The schematic of the latch is shown in Fig. 6.9. The latch employs a positive
feedback loop to resolve a error introduced by the inputs A and B in two branches.
The positive feedback is inactivated by resetting the internal nodes to Vdd when CLK
is LOW. It helps in getting rid of hysteresis in the latch. To detect the sign of the
difference between A and B, CLK is made HIGH which enables the positive feedback
loop and resolves the sign.
6.2.2 CDAC Manipulation and Sign Correction
The FlipDAC switching scheme is explained in Section 4.2. During the first DOWN
transition, flipping of the CDAC is found to reduce energy consumption in it. The flip
step comprises of two parts: switching of (MSB − 1)th capacitor and manipulating
DAC reference rails. This keeps the DAC capacitance switched in each bit cycle same
as in [76]. During the flip step, voltage reference rails in CDAC are manipulated to
achieve the desired magnitude of the DAC voltage and the logic for this is shown in
Fig. 6.10. When Flip signal (Fig. 4.6) goes HIGH, rails V and G are shorted together
to Vcm input. Based on the sign of the input, Vcm1 and Vcm2 rail is shorted to either
REF P or REF M which are outputs of the reference buffer. The proposed ADC
only has an overhead in digital switching energy over [76] due to the manipulation
of DAC reference rails otherwise equal capacitances are switched in every bit-cycle.
However as this manipulation requires a single driver (FLIP) which switches only
once in a sample period when 1st MSB is logic LOW, the overhead is small.
As discussed in Section 4.2, the flip step causes the effective DAC voltage (Vdacp -
Vdacm ) to become negative of the desired value. This is compensated by interchang-
ing Vdacp and Vdacm inputs to the preamplifier when Flip signal goes HIGH. Charge
sharing between the input parasitic capacitance of the comparator and CDAC occurs
during the flip step and introduces an error. The error caused by this charge sharing
Cp,cmp REF P − REF M
is ∼ 2 · . differential. With Cox ∼ 10f F/µm2 and W/L of
Cdac 4
input transistor as 1µm/0.2µm, Cp,cmp is approximately 2 fF. The error comes out
to be ∼ 0.26 mV which is quite smaller than the LSB of the ADC. During layout
care was taken to keep the input parasitic capacitance of the comparator as small
Flip=1
Flip=0
Sign=1 Sign=0
V REFP VCM VCM
G REFM VCM VCM
VCM1 VCM REFP REFM
VCM2 VCM REFM REFP
G
VCM2
REFM=350 mV
Flip
Adacp
Vdacp
REFBFR
Flip
Flip
Vdacm
Adacm
REFP=850 mV
Flip
G
VCM1
V
Figure 6.10: Energy-efficient implementation of the FlipDac step by manipulating
DAC reference rails. The sign of the DAC voltage is corrected by interchanging DAC
inputs to the preamplifier.
N
D0 D1 D2 D3 D4 D5 D6 D7 B6
data clk
outp
MUX
0 D Q D Q D
OVER
Q D Q D Q D Q D Q D Q
outm 1 FF FF FF FF FF FF FF FF
B00
Flip
outp SOC
HS
LATCH
CDAC Av outm PST
STB
PDL
STB
LOGIC
OVER
purge Flip
Flip STB RST
SOC NEXT
NEXT
STB
PST RST RST RST RST RST RST RST RST RST RST
FF FF FF FF FF FF FF FF FF FF FF
B00
purge
sthen
sign
B0
B2
B5
B4
B3
B1
B6
To CDAC Switch Driver Logic

Flip
Figure 6.11: Asynchronous logic. Variable resolution is implemented using the MUX
setting controlled by N.
as possible. The matching of parasitic capacitance of two paths to the comparator

is also important to keep the gain error constant.
6.2.3 Asynchronous Logic and CDAC
The asynchronous scheme employed is shown in Fig. 6.11. The individual bit
cycling phases are generated once a decision is made by the comparator after STB
and is detected by a NAND gate. A shift register of depth = 11 is used to progress a
pulse, after each decision, to enable the extraction of the next bit. The first flip-flop
is asynchronously preset by start-of-conversion (SOC) to start this. Programmable
delay line (PDL) is used to generate RST and PST signals to respectively reset and
preset STB by introducing delays tRST and tP ST (tP ST > tRST ). The STB signal
must only be applied after sufficient time has been given to DAC and preamplifier
to settle the input based on the accuracy of the ADC. The time budgeting in each
Figure 6.12: Timing diagram depicting asynchronous operation. T c consists of the

comparator and NAND gate delay.
bit cycle is very critical for the ADC. The input HS controls PDL to modulate delays
for the operation at higher speeds. The timing diagram of the logic is illustrated in
Fig. 6.12.
Once the pulse reaches the final flip-flop, OVER signal halts the conversion un-
til the next SOC. The number of bit cycles is decided based on the resolution re-
quirement (N) through a digital MUX. It implements variable resolution, without
complicating the layout and logic, and prevents unnecessary conversion steps to
happen. As the resolution is reduced by simply halting the binary search algorithm
in-between, it enables the resolution reconfiguration from 8 bit to 1 bit at 1 bit step.
This scheme of variable resolution saves power linearly with the resolution and is
finally limited by the static power consumption in the ADC. Two extra bit cycles are
used to include the logic for STH and is controlled by the signal sthen (Fig. 6.11).
This state can be bypassed for the free running mode of the ADC.
Fig. 6.13 depicts the architecture of the 8-bit CDAC used in the ADC. Separate
sub-DACs for DOWN and UP transitions are used. As the linearity of a CDAC is
determined by total capacitance connected to Vref indifferent of its position [79],
this structure does not compromise the linearity performance of the CDAC. A be-
havioral model for the switching scheme was made in the MATLAB to confirm it
and the variance of INL was found to be similar to that of a binary-weighted CDAC.
32C 32C
64C 16C 8C C C 16C 8C C C
Vdacp
Vdacm
64C 16C 8C C C 16C 8C C C
MSB Cap Down Transition Up Transition
Figure 6.13: Architecture of 8 bit CDAC with separate sub-DACs.
Vdd Capacitive DAC Comparator
Vref Ro Idac
-+
Vss
switch control Digital
Logic
Figure 6.14: Reference buffer in a SAR ADC employing CDAC as the feedback DAC.
6.2.4 Reference Buffer
Recently a number of publications [76] [78] have used supply rails, VDD and VSS , as
the reference voltage in the ADC. But any noise on the reference voltage will directly
appear at the output of the ADC and will deteriorate its dynamic performance,
especially in a system-on-chip environment.
Fig. 6.14 shows the role of a reference buffer in a SAR ADC. SAR ADC resolves
an input by comparing it with different reference voltages. These reference voltage
are generated accurately using the ratio of the capacitors in a capacitive DAC. The
basic functionality of a reference buffer it to provide clean and stable reference
voltage to this DAC. Reference buffer should also have enough drive capability to
charge the capacitive DAC within a time based on the speed requirement. Hence
the output impedance Ro should be decided based on the speed of the ADC. The
worst case situation occurs during the estimation of the first MSB when half of the
Cdac is switched to Vref to compare input against Vref /2. For an N-nit ADC operates
1
a Fs = samples/sec, with αref fraction of each bit cycle (Ts /N) given for DAC
Ts
settling, the output impedance of the reference buffer can be calculated from,
Ro .Cdac Ts
N.loge (2). = αref . (6.12)
4 N
The designed value of the output impedance is usually smaller the the value
from the above equation to accommodate the switch resistance and the parasitic
capacitance.
Large capacitors are usually used at the output of the reference buffer for ADC
operating at moderate speed. This relaxes the design of the buffer as the instanta-
neous spike current if supplied by these capacitors to the DAC and the buffer needs
to supply only the average current to the output capacitor. The schematic of the
reference buffer designed is shown in Fig. 6.15. It is load compensated and has
a built-in programmability (hs) to support higher speed of operation by increasing
2.5M
1M
700m - 50 pF
+ 850m
A0 50 pF
- 350m
500m + 50 pF
1M
2.5M
(a)
Bias1
hs Vip Vim hs
Vop Vom
hs hs
1.5u 500n
1u
Bias2
CMFB CMFB
(b)
Figure 6.15: Schematic of reference buffer.

the current in the output branch which effectively lower the output resistance. The
reference buffer consumes 4 µA of current from a 1.2 V supply.
6.3 Variable Gain Amplifier (VGA)
VGAs help tame signals that exhibit wide dynamic range. Broadly speaking, VGAs
are used in two circumstances. The first encompasses all those situations where
the circuit designer must match an input signal level to the full-scale input of a
device such as an ADC. The second addresses situations in which the designer must
scale a fixed input voltage to compensate for variable losses, for example, to adjust
the voltage level to a transmission line. In these applications, VGAs reduce bill-of-
materials cost and save space, but they also offer better performance in terms of
noise, distortion, and power consumption.
Variable gain amplifiers (VGAs) serve a critical function when an analog signal
with wide dynamic range is converted to digital format, and the ADC resolution
is insufficient to capture all useful information. For example, a 10-bit converter
with a 2 Vp−p input range has an LSB weight of 2/1024, or just under 2 mV. This
represents a dynamic range of approximately 60 dB. A VGA can be used ahead of
the ADC to amplify input signals with amplitudes less than the minimum resolution
and attenuate large signals that would otherwise saturate the ADC. VGA used in
this system also compensates for any gain error in the low-noise-amplifier LNA and
gain stage A2 due to employment of the open-loop architecture.
The architecture of the VGA is shown in Fig. 6.16. VGA comprises of two
stages, VGA1 and VGA2 in which VGA1 can be put in sleep mode if detectable
signal amplitude is large. Switch S1 and S2 are selected based on the total gain
requirement to fully traverse the ADC dynamic range. Two stages of the VGA is
chosen to provide large range in the gain programmability to cater to even a very
small detectable signal.
S2
S1
Vip VOP
VGA 1 S1 VGA 2
2.5-7.5 S1 2.5-7.5
Vim VOM
S1 sleep
S2 S2
Figure 6.16: Architecture of VGA for even or odd numbered channel.
Vcm
S Cf0 S
Even Channels
S CS0 Hp Hp H
Vcm
−
Vip0 Sp Vincm Gm
Vim0 H Sp
Vcm +
S CS1 Hp Hp H
Sp
S S Cf1 S
Vcm Vom
Hp
H Vcm ADC
Vop
H Cf2 H
clk=Fs/2
Sp
H CS2 Sp S
Vcm
Vip1 Hp Vincm
Vim1 S Hp Gm
Vcm
H CS3 Sp Sp S
Odd Channels
H Cf3 H
Vcm
Figure 6.17: OTA sharing between even and odd numbered channel.
Bias1
Vip Vim 1u
Cm Cm
Vop 0.5u Vom
Bias2
CMFB CMFB
Figure 6.18: Schematic of OTA in the VGA.
The architecture of the VGA block is elaborated in Fig. 6.17. There are two
paths for the signal to reach the ADC, one path is dedicated to all even-numbered
channels and other path for all odd-numbered channels. As an effort to reduce the
area and design time, the OTA is shared between the two sets of capacitors which
also enables the use of ping-pong sampling.
The schematic of the OTA block is shown in Fig. 6.18. The OTA is a two-stage
trans-conductance amplifier which consumes only 3 µA driving 1 MS/s 8-bit SAR
ADC. Common-mode feedback is applied to the load transistors which are operat-
ing a current sources for high output impedance. The OTA is Miller-compensated
through the capacitor Cm . Simulation of the VGA achieved a THD of 69 dB for 1
Vp−p output swing. The amplifier uses Cs = 300 fF and Cf = 40 fF (fixed) + 80 fF
(programmable in 4 steps). The voltage gain that can be achieved are 2.5, 3.75, 5,
7.5 with one VGA stage. This structure is shown more elaborately in Fig. 6.19. The
programmable voltage gain range is 2.5-56.25 V/V in 8 steps.
40 fF
20 fF
20 fF
20 fF
20 fF
300 fF
Vin+ + - Vo-
Gm
+ Vo+
Vin- -
300 fF 20 fF
20 fF
20 fF
20 fF
40 fF
Figure 6.19: Architecture of each VGA.

Figure 6.20: Block diagram of the fabricated 16-channel neural recording system.
6.4 Experimental Results
A 16-channel neural recording system is designed in UMC 0.13 µm CMOS tech-

nology. Fig. 6.20 shows the complete system fabricated. The system consist of
16-channels, each with a LNA and gain stage A2, which are time-division multi-
plexed in a single VGA followed by a SAR ADC. The channel controller block (Fig.
6.1) is not on-chip and is implemented in a FPGA. The algorithm to calculate ST H
to reject background noise and N to control resolution is also implemented in the
FPGA.
Fig. 6.21 shows a die photo of the chip fabricated in 0.13 µm CMOS technology.
Each LNA occupies considerably smaller area as only 2 pF of Cin is employed. The
area of the gain stage A2 is dominated by the poly-poly resistor RD used in the
amplifier. The ADC occupies an area of 390 µm x 420 µm. The area of the ADC
is dominated by the digital logic gates which also includes the logic for applying
spike-threshold ST H . The ADC occupies an area of 390 µm x 420 µm. The charge
redistribution DAC employs custom made unit capacitor ∼ 15 fF using MOM tech-
nology with 6 metal layers. This value of the unit capacitance is larger than the
required unit capacitance size for an 8 bit ADC with σC /C0 = 0.5 %. The total DAC
Figure 6.21: Die photograph of the chip.
capacitance is 3.84 pF. The full scale range (FSR) of the ADC is 1 Vpp differential.
The complete 16-channel system is fabricated in only 1 mm X 1 mm area which
makes it most area efficient neural recording system fabricated till now.
6.4.1 ADC Characterization
The test setup for the characterization is shown in Fig. 6.22. 2 layer PCB on FR4
substrate is designed due to low frequency application. Virtex-II Pro FPGA is pro-
grammed to work as the controller for the chip. The power supply to the chip is
provided by Agilent U2722A module which can provide 6 reference voltage/current
at a time and is fully controllable by a computer through an USB interface. The in-
put signal to the chip is provided by Agilent 81150A waveform generator.
The maximum measured INL and DNL (Fig. 6.23) are found to be 0.6 LSB/-0.7
LSB and 0.26 LSB/-0.67 LSB. These are at 0.25 FSR and 0.75 FSR due to mismatch
in the two paths (Fig. 6.10) meant for interchanging two DAC inputs to the pream-
plifier once they are flipped. Fig. 6.24 shows 16384 point FFT of the ADC output
Figure 6.22: Test Setup for the characterization.
for -1 dBFS input at Fin = 62.439 kHz. Fig. 6.25 presents the measured signal-to-
noise-and-distortion (SNDR) for different input frequencies at -1 dBFS input. The
ADC achieves a SNDR of 48.1 dB for a near Nyquist input (499.939 kHz) which
translates to effective number of bits (ENOB) of 7.7.
The ADC consumes total power of 8.8 µW with VDD = 1 V at 8 bit setting.
Based on parasitic extracted simulations, CDAC consumes only 0.4 µW and preamp
consumes 1.5 µW which is ∼ 5 % and 17 % of the total power consumption re-
spectively. The power consumption is dominated by the digital switching (∼ 78 %).
The power consumption in the digital logic is found to be larger than for a normal
SAR ADC logic primarily due to the in-built logic for the spike thresholding in the
ADC. A more efficient layout can further reduce the digital switching power and
will make the ADC more power efficient. As the power consumption is dominated
by the digital switching, it reduces linearly with the decrease in the resolution and
is shown in Fig. 6.26.
Figure-of-merit (F oM) is frequently used by researchers to compare various
ADC architectures. F oM is dependent on the power consumption (PD ), ENOB
and input frequency (Fin ), and is defined as,
DNL
0.6
0.4
0.2
0
−0.2
−0.4
0 20 40 60 80 100 120 140 160 180 200 220 240 255
INL
0.4
0.2
0
−0.2
−0.4
−0.6
0 20 40 60 80 100 120 140 160 180 200 220 240 255
Figure 6.23: Measured DNL and INL plots.
0
Output Voltage (in dBFS)
−30
−60
−90
0 1 2 3 4 5
5
Frequency (in Hz) x 10
Figure 6.24: 16384 point FFT of the ADC output for -1 dBFS input at Fin = 62.439
kHz.
50
49
48
47
SNDR (dB)
46
45
44
43
42
0 0.1 0.2 0.3 0.4 0.5
Input Frequency (MHz)
Figure 6.25: Measured SNDR vs Fin for -1 dBFS input at 1 MS/s speed.
0.9
Relative Power Dissipation
0.8
0.7
0.6
0.5
0.4
0.3
0.2
8 7 6 5 4 3 2 1
Resolution
Figure 6.26: Relative power dissipation vs resolution with Pmax = 8.8 µW

4
10
2
Power/Fs (in pJ)
10
180 nm
0 130 nm
10 90 nm
65 nm
This work
[2]
−2 [1]
10
10 20 30 40 50 60 70
SNDR (in dB)
Figure 6.27: Comparison with SAR ADCs published.
PD
F oM = (6.13)
2EN OB· 2 · Fin
The F oM is found out to be 42.3 fJ/conversion step for the free running ADC
which is excluding the reference buffer and output buffer. The FoM would be even
smaller (∼ 35.1 fJ/conversion-step) if the ADC were not to employ the preamplifier
to mitigate the effect of kickback noise on small sampling capacitors. Bigger sam-
pling capacitors could have been used to obviate the preamplifier but it defeats the
whole purpose of ping-pong sampling to reduce power consumption in the VGA.
The power consumption of the reference buffer is 4.8µW . Hence the F oM of the
ADC with reference buffer is 65.4 fJ/conversion step.
Fig. 6.27 shows the comparison with various SAR ADCs published in premier
IEEE conferences and JSSC [102]. Table 6.1 compares this work with the state-of-
the-art SAR ADCs with similar speed of operation.
Table 6.1: SAR ADC Comparison
[70] [71] [74] [45] [83] This work

Technology 0.25 µm 0.18 µm 0.18 µm 0.13 µm 65 nm 0.13 µm
Supply 1V 1V 1V 1V 0.4-1 V 1V
Power Consumption (µW ) 3.1 25 7.75 0.9 0.2 @ 0.55 V 8.8
Speed 100 KS/s 100 KS/s 500 KS/s 100 KS/s 20 KS/s 1 MS/s
ENOB 7.0 10.55 7.5 7.55 8.84 7.7
FoM (fJ/conv) 310 165 86 48 22.4 42.3
6.4.2 Activity dependent A/D
Fig. 6.28 represents the measured output of the ADC working under activity de-
pendent A/D scheme at 1 MS/s speed. For this experiment, neural data recorded in
vitro from the Hippocampal culture of a Wistar rat is fed to the ADC using Agilent
81150A Pulse Function Generator. The values of ST H and EAF are shown in Fig.
6.28 where the first bit S is the sign bit. In this mode, the ADC takes two extra
bit cycles each for spike detection and purging of the CDAC. If ST H is set as 0 in
this mode, the ADC behaves as a free running ADC and consumes 10.7 µW which
is larger due to two extra cycles required. However when ST H > 0, there in con-
siderable drop in the activity of the ADC which reduces power consumption and
ODR.
Fig. 6.29 and Fig. 6.30 show the relative reduction in power consumption and
ODR as a function of ST H under different noise (σn ) conditions. For this experi-
ment, the spike input to the ADC is approximated by a triangular waveform with
noise and is generated using Agilent 81150A Pulse Function Generator. This is
shown in Fig. 6.31.
Based on the value of input noise σn , a proper value of ST H can be found which
reduces power consumption and ODR but preserves three important spike features
(Fig. 5.7(b)), namely, Amax (the maximum positive spike amplitude), Amin (the
minimum negative spike amplitude) and Tpp (the time between Amax and Amin )
[93] [94] [38].
250 250
200 200
STH = disabled STH = "S0001000"
150 150
EAF = 1 EAF = 0.86
100 100
50 50
1 1.1 1.2 1.3 1.4 1.5 1.6 1 1.1 1.2 1.3 1.4 1.5 1.6
4 4
x 10 x 10
250 250
200 200
STH = "S0010000" STH = "S0100000"
150 150
EAF = 0.76 EAF = 0.03
100 100
50 50
1 1.1 1.2 1.3 1.4 1.5 1.6 1 1.1 1.2 1.3 1.4 1.5 1.6
4 4
x 10 x 10
Figure 6.28: Measured Digital output of the activity dependent ADC. The X-axis and
Y-axis represents the time in µsec and the output code respectively. The asymmetric
rejection of the background noise is due to the fact that only 5 bits were used to
encode ST H .
1
Relative ADC Power Consumption
0.9
0.8
0.7
0.6
0.5
σn=100 mVrms
0.4
σ =33.3 mVrms
n
0.3 σ =133.3 mVrms
n
0.2
0 50 100 150 200 250
Threshold STH (in codes)
Figure 6.29: Relative reduction in power consumption with different σn and ST H .

(Pmax = 10.7 µW )
100
Relative Output Data Rate
80
60
40
σ =100 mV
n rms
20 σn=33.3 mVrms
σn=133.3 mVrms
0
0 50 100 150 200 250
Threshold, STH (in codes)
Figure 6.30: Relative reduction in ODR with different σn and ST H .
Free running ADC

300
200
100
0
0 5000 STH = 192 10000 15000
300
200
100
0
0 5000 STH = 160 10000 15000
300
200
100
0
0 5000 STH = 224 10000 15000
300
200
100
0
0 5000 10000 15000
Figure 6.31: Measured Digital output of the activity dependent ADC. The X-axis and
Y-axis represents the sample number and the output code respectively.
Table 6.2: VGA Comparison

Spec. [8] [46] [103] This work
ADC 9b, 640 KS/s 10b, 16 KS/s 8b, 31.25 KS/s 8b, 1 MS/s
IB 40.6 µA 0.55 µA 1.45 µA 3 µA
Kef f,vga 49.5 m 91.4 m 67.7 m 1.05
6.4.3 VGA
VGA can only be characterized at low frequencies (∼ 1 kHz) as it is not designed

to drive large capacitance (∼ 5 pF for I/O pads) at higher frequencies. The low
frequency voltage gain matches the expected 8-35 dB. Also for testing the ADC,
inputs at different frequencies (till Nyquist frequency) are given to the ADC, both
directly and through the VGA. Similar performance is achieved for both these cases
which indirectly indicates that the proper functioning of the VGA till the Nyquist
frequency.
To evaluate the power efficiency of the VGA, we have used the metric Kef f,vga
defined by,
2 · π · FN · Vsw
Kef f,vga = · 10−12 pF −1 (6.14)
IB
where Vsw is the output swing, FN is the Nyquist frequency of the ADC and IB
is the current consumption in the VGA. Kef f,vga is a measure of how efficiently the
current is utilized in the VGA for a slew rate requirement and is the inverse of the
effective load capacitance that has to be charged by the VGA. Higher is the Kef f,vga ,
more power efficient is the VGA. Table. 6.2 presents the comparison of the VGA
with that in three state-of-the-art NRSs.
The front-end amplifiers could not be tested due to some problem in analog VDD
and is under troubleshooting process.
60
50
Voltage Gain (in dB)
40
30
20
10 High Gain LNA

Low Gain LNA
0 −2 0 2 4 6
10 10 10 10 10
Frequency (in Hz)
Figure 6.32: Simulated AC response of the system with two modes of gain of LNA.
6.4.4 Simulation results for NRFE
This section presents simulation results for the whole front end, except that of the
ADC. The AC response plotted are for LNA, Gain stage A2 and VGA (Fig. 6.1) in
cascade with VGA configured in smallest gain setting of 8 dB. A voltage gain of 20
dB is achieved by gain stage A2 . Fig. 6.32 shows simulated AC response for two
modes of voltage gain from the LNA as discussed in Section 6.1. Second stage of
LNA is bypassed for the smaller gain setting.
Fig. 6.33 illustrate the tuning capability of the high-pass pole of the system by
tuning Req of Fig. 6.4. Fig. 6.34 shows the output referred noise of the system
for two modes of LNA (Section 6.1): low-noise and not-so-low noise. Noise-power
trade-off is exploited to save power when the system can tolerate larger electronic
noise. The presence of flicker noise in the frequency band of interest can be seen
from the figure.
6.4.5 System Power Consumption Comparison
This section presents the power-per-channel calculation of the total NRFE, exclud-
ing that of the control circuitry implemented in FPGA. Sliding window power-on
60
40
Voltage Gain (in dB)
20
−20
Vss
−40 Vdd
600mV
−60 −4 −2 0 2 4 6 8
10 10 10 10 10 10 10
Frequency (in Hz)
Figure 6.33: Simulated AC response to illustrate tunable high pass cut-off of the
system.
−60
Low Noise
−65 not−so−low Noise
Output Noise PSD (in dB)
−70
−75
−80
−85
−90
−95
−100 0 1 2 3 4 5
10 10 10 10 10 10
Frequency (in Hz)
Figure 6.34: Simulated output referred noise for two modes of LNA: low-noise and
not-so-low noise.
control reduces the static power consumption in LNA and gain stage. Only 2 out of
16 channels consume power using this power control algorithm, with one in active
mode and other is in boot mode. The power consumed in two stage LNA (Section
6.1) is 1.5 µA from 1.2 Volt supply. Gain stage A2 consumes 1 µA from 1.2 V sup-
ply. VGA consumes 3 µW when driving 8-bit SAR operating at 1 MS/s. The ADC
consumes 8.8 µW at 1 MS/s speed. The power consumption-per-channel (pc/ch.)
for this 16-channel NRFE can be calculated from,
2 ∗ 1.2 ∗ (1.5 + 1) + 1 ∗ (3 + 8.8)

pc/ch. = ≈ 1.1µW att (6.15)
16
Eqn. 6.15 shows that power consumption-per-channel of the designed NRFE

is only 1.1 µW compared to previous best 3.77 µW [46]. Note that the ADC
(and VGA) is working at 1 MS/s which turns out as the sampling rate of 62.5
kSps/channel compared to 40 kSps/channel in [46]. A smaller sampling rate will
further improve the power-per-channel. Also this pc/ch. number is derived for ADC
in free running mode. The activity dependent A/D mode further reduces power
consumption in the ADC and hence power consumption-per-channel of the system.
Note that the power consumption of the digital control circuitry (implemented in
FPGA) is not included in the power-per-channel comparison. Power consumption
in the control circuitry is estimated to be very small compared to the static power
consumption in active blocks (LNA, VGA, ADC). Moreover maximum of the control
circuitry is only used for the configuration setting and does not switch frequently.
Leakage current is quite small in 0.13 µm CMOS technology to significantly deteri-
orate the power-per-channel number.
6.5 Summary
This chapter discussed the design of a 16-channel NRFE in UMC 0.13 µm CMOS
technology. The innovation in the architecture and system level concepts for a low
power solution are discussed. Sliding window power-on control is chosen as a

method to reduce static power consumption in LNA and gain stages. It also helps
in reducing the crosstalk from other channels as they are not operational. The
minimum number of channels that should be kept on at a time is dependent of
the recovery tine of the blocks from sleep more to active state. This scheme can’t
ne used in multi-channel system where simultaneous sampling is required across all
channel. Oversampling is a way to get over this problem but consumes more power.
The design of a programmable gain and programmable bandwidth LNA is pre-
sented. Open loop configuration is employed for the LNA due to its advantage
for the application as explained in Section 3.2. The LNA is a two stage amplifier
in which the first stage is a low noise stage and second stage adds more gain to
the input signal. Using Cin optimization technique, input coupling capacitance of
only 2 pF is used in the amplifier. The signal attenuation due to Miller capacitance
is reduced by using capacitance neutralization technique. Gm .RD architecture is
employed for the gain stage Av which is designed to provide a gain of 17 dB.
A low power variable resolution SAR ADC is designed which uses separate sam-
pling and DAC capacitors. It enabled the use of ping-pong sampling architecture
which relaxes the specification of VGA, reference buffer and clock buffers. The
ping-pong scheme enables the VGA to use full sampling period for input tracking
and hence reduces its bandwidth specification, hence the current. It also gives refer-
ence buffer more time for DAC settling as each every bit cycle is slightly longer. Also
the clock requirement reduces by two over as asynchronous SAR ADC which causes
smaller power consumption from the clock buffers. FlipDAC switching scheme
makes the power consumption in the DAC negligible compared to the digital switch-
ing power consumption. The design of a low area preamplifier is also presented
which uses a partial positive feedback to reduce the effective output load and pro-
vide a voltage gain to attenuate the effect of offset and noise of the latch. Pream-
plifier is primarily employed here to mitigate the effect of the kickback noise on the
small sampling capacitors. The architecture of the asynchronous logic based on a

shift register is elaborated and the logic to interchange DAC rails for the implemen-
tation of the FlipDac logic is explained.
A low power VGA for multi-channel application is presented which uses ping-
pong as an effective way to decrease its bandwidth specification. VGA is primarily
required to make use of the complete dynamic range of the ADC which can’t be cov-
ered by weak inputs. An emphasis is put on the requirement of large programmable
voltage gain in the VGA for NRFE due to large dynamic range of the neural signals.
VGA is also used to correct any gain error in the preceding gain stages due to the
employment of the open loop architectures in them. The presented VGA provides a
voltage gain of 8 dB-35 dB in 8 steps. It consumes only 3 µA when driving a 8-bit
ADC operating at 1 MS/s. The complete system is fabricated on silicon in UMC 0.13
µm CMOS technology.
The presented SAR ADC consumes 8.8 µW from 1 V supply and achieves ENOB
of 7.7 bit for a near Nyquist input at 1 MS/s speed. FlipDAC switching techniques
makes energy consumption in the DAC (∼ 5 %) negligible compared to digital
switching energy (∼ 78 %). The DAC switching scheme will be more beneficial
in higher resolution and higher speed SAR ADCs where the DAC switching energy
is more comparable to the digital switching energy. An experiment with the real
neural data is carried out to show the usefulness of the activity dependent A/D
scheme for NRFE application. The reduction in the power consumption and the
ODR is found to have a linear relationship with EAF in different noisy environment.
This experiment is done by modeling spikes as triangular waveforms with noise.
The ADC achieves a F oM of 42.3 fJ/conversion. ADCs with better F oM than
ours (Table 6.1) were designed in higher technology nodes where digital switching
power is lower than that in the technology used by us. The power consumption in
the ADC is dominated by digital switching and hence will only improve with voltage
and technology scaling.
Chapter 7
Conclusion
7.1 Thesis Conclusions
OWER consumption and area consumption are two serious bottlenecks for the
P scalability of present neural recording systems to a larger number of chan-
nels. Future neural recording systems must solve these critical issues for an effi-
cient brain-machine-interface for an implantable neuro-sensor. Various techniques
and considerations to reduce power-per-channel and area-per-channel in a NRFE
were presented in this thesis.
The design of a low-power noise-adaptive neural LNA is presented. A novel ar-
chitecture of the neural LNA is proposed which emphasizes the use of open-loop
LNA for a low power NRFE. A new architecture of OTA is proposed which minimizes
the noise contribution of the load transistors. The proposed architecture also helps
in achieving a moderate voltage gain in an open-loop configuration, without the
employment of common-mode feedback. Noise-power trade-off is exploited in the
LNA to optimize the power consumption under various noise conditions. The cause
of the area-inefficiency of NRFE is investigated and large input coupling capacitors
in LNAs are found to be the reason behind it. Optimum sizing of the input tran-
sistors is proposed to relax the size of the input coupling capacitance by avoiding
the input signal attenuation in an ac-coupled amplifier. The neural LNA is designed
and fabricated in UMC 0.13 µm CMOS technology. Its electrical characteristics are
validated using bench top testing and the usefulness in neural recording application
is proved via in vitro experiment. Table. 7.1 shows the comparison of the measured
results with previous state of the art works.
144
Chapter 7. Conclusion 145
Table 7.1: Neural LNA Comparison
[21] [42] [24] [49] [29] This work

Technology 1.5 µm 1.5 µm 0.5 µm 1.5 µm 0.18 µm 0.13 µm
Power 80 µW 115 µW 7.56 µW 27.2 µW 8.6 µW 1.5 µW
VDD ±2.5 V ±1.5 V 2.8 V ±1.7 V 1.8 V 1.5 V
AV 39.5 dB 39.3 dB 40.85 dB 39.3 dB, 45.6 dB 50 dB 37 dB
LCF 25 mHz dc (±250 mV) 45 Hz 15 mHz 105 Hz 5 Hz
Cin,tot 40 pF - 28 pF 40 pF - 10 pF
HCF 7.2 kHz 9.1 kHz 5.32 kHz 4 kHz 9.2 kHz 7 kHz
THD (1%) 16.7 mVp−p 5 mVp−p 7.3 mVp−p 17.4 mVp−p 2.4 mVp−p 400 µVp−p
PSRR 85 dB N/A 75dB - 52 dB 67 dB
Vni,rms 2.2 µVrms 7.8 µVrms 3.96 µVrms 3.6 µVrms 5.6 µVrms 5.5 µVrms
N.E.F 2.9 19.4 2.67 4.9 4.6 2.58
The design considerations of a low power VGA and SAR ADC for a NRFE are
addressed. Architectural changes in the VGA and SAR ADC is proposed to reduce
the power consumption in both. For multichannel input, the use of ping-pong in-
put sampling structure is emphasized to save power in both VGA and reference
buffer. It also helps in relaxing the clock requirement in the NRFE which reduces
power consumption in clock buffers. A novel activity dependent A/D scheme is
proposed to mitigate the processing of the background noise It reduces both power
consumption in the ADC and output data rate (ODR) of the NRFE while preserving
the essential spike-features for robust spike-sorting. The savings in power consump-
tion and ODR due to this scheme are analyzed and presented for a spike input to
the ADC.
An energy efficient FlipDAC switching scheme is proposed for CDAC in SAR
ADCs. The scheme obviates energy-inefficient DOWN transitions at higher MSBs
which reduces energy consumption in the CDAC, without using extra capacitors or
sacrificing speed of the ADC. The implication of flipping the comparator offset due
to the technique is discussed. The DAC switching technique consumes 37 % less
energy than the present state-of-the-art.
Another energy-efficient CDAC switching technique, QCS, is described which
employs switching capacitors that vary in a quaternary manner. The reduction in
4
10
2
Power/Fs (in pJ)
10
180 nm
0 130 nm
10 90 nm
65 nm
This work
[2]
−2 [1]
10
10 20 30 40 50 60 70
SNDR (in dB)
Figure 7.1: Comparison with SAR ADCs published.
the size of switching capacitors helps in reducing energy consumption in the DAC.
A novel concept of code-independent energy is proposed to obviate energy con-
sumption degradation at smaller input signal dynamic range and to mitigate har-
monic noise injection into the supply. The proposed technique consumes 42.5 % less
switching energy for a 10-bit SAR ADC when compared to the Vcm -based switching
technique. Analysis of errors due to top plate switch charge injection mismatch is
presented. An analysis on the linearity implication for this scheme is also presented
and discussed.
An 8-to-1 bit 1 MS/s SAR ADC with VGA is fabricated in UMC 0.13 µm CMOS
technology. The measured results are presented and discussed for both free run-
ning ADC mode and activity dependent A/D mode. Real neural data is used for
validating the usefulness of the activity dependent A/D mode to reduce power con-
sumption and ODR. Fig. 7.1 shows the comparison with various SAR ADCs pub-
lished in premier IEEE conferences and JSSC [102]. Table 7.3 compares this work
Table 7.2: VGA Comparison

Spec. [8] [46] [103] This work
ADC 9b, 640 KS/s 10b, 16 KS/s 8b, 31.25 KS/s 8b, 1 MS/s
IB 40.6 µA 0.55 µA 1.45 µA 3 µA
Kef f,vga 49.5 m 91.4 m 67.7 m 1.05
Table 7.3: SAR ADC Comparison
[70] [71] [74] [45] [83] This work

Technology 0.25 µm 0.18 µm 0.18 µm 0.13 µm 65 nm 0.13 µm
Supply 1V 1V 1V 1V 0.4-1 V 1V
Power Consumption (µW ) 3.1 25 7.75 0.9 0.2 @ 0.55 V 8.8
Speed 100 KS/s 100 KS/s 500 KS/s 100 KS/s 20 KS/s 1 MS/s
ENOB 7.0 10.55 7.5 7.55 8.84 7.7
FoM (fJ/conv) 310 165 86 48 22.4 42.3
with the state-of-the-art SAR ADCs with similar speed of operation. It shows that
the ADC compares favorably with many of previous works. Table. 7.2 presents the
comparison of the VGA with that in three state-of-the-art NRSs. Separate sampling
capacitance and the employment of ping-pong input sampling makes the designed
VGA most power-efficient in a NRFE.
7.2 Future Directions
Neural recording system is a hot and emerging field of research. Even after 2-3
decade of work, a lot of opportunities are available for the research in this area.
Lowest power-per-channel, among published result, is 3.77 µW [46]. This works
presents simulated power consumption-per-channel of 1.1 µW (Section 6.4.5). De-
sign of a sub-microwatt power-per-channel neural front end is indispensable for the
scalability of NRFE to thousands of channel. Efficient power management to re-
duce static power dissipation in front-end amplifiers and adaptable energy-efficient
blocks will be very important requisites for such systems. Digital-assisted-analog
techniques will be very applicable to these system especially once they are designed
in deep-submicron CMOS technologies. Output data rate (ODR) reduction also

needs more attention from researchers. Of late, many researchers have started fo-
cusing on the necessity of on-chip reduction of ODR. But the field is still very new
and has ample opportunities. Area-efficient solution of each block is equally im-
portant and it is often limited by passive devices. Techniques to reduce their size
or completely remove them will be very beneficial towards an area-efficient NRFE.
Power transmission, supply regulation and RF telemetry blocks also demand careful
design for a complete power-efficient neural recording system.
Till now, this work has not really focused on offset cancellation and power line
interference mitigation which I believe are very important issues for these systems.
In future work, blocks dedicated fro these function will be included in NRFE. The
incorporation of these blocks in NRFE will further degrade power-per-channel and
area-per-channel of the system and must be performed in a intelligent way. Time
based digitization, compared to voltage based digitization, can prove to be a more
power efficient solution in deep submicron technologies. Telemetry block will be
integrated with the analog front end to move towards a SOC solution. For CDAC
switching techniques, a lot of work has already happened. But most of these works
have focused on reducing the energy consumption in the DAC. Future works in this
area will be focused towards achieving a code-independent energy consumption
similar to that in Chapter 5, in a less error prone way.
Appendix A
Noise Analysis and Optimization
In this appendix, we present an introduction to the noise analysis of an linear am-

plifier. For this, first we will consider a common source (CS) amplifier to get an
insight into the methodology. Following this, we will carry out the noise-analysis of
the neural LNA proposed in Chapter 3.
A.1 Common Source Amplifier
In the following section, we will try to explain the noise optimization technique
to achieve a low noise design using a CS amplifier as the example. Both thermal
and flicker noise sources will be considered as flicker noise is very important for
low frequency applications. Fig. 3.6 illustrates a PMOS input CS amplifier with a
NMOS load. Both the transistors are assumed to be biased in saturation region to
achieve high output impedance, hence voltage gain. The noise sources are modeled
as current sources and consists of both flicker and thermal noise. The noise PSD are
given by,
Thermal Noise PSD = i2n,th = 4 · kB · T · gm · γ A2 /Hz (A.1)
where γ is the thermal noise coefficient which depends on the effective mobility
and channel length modulation. It is 2/3 for higher technology nodes but is re-
ported to be larger for submicron technologies, kB is Boltzmann Constant and T is
temperature in Kelvin. [55] [58].
149
Appendix A. Noise Analysis and Optimization 150
Figure A.1: Noise Contribution by input and load transistors at the input.
K 1
Flicker Noise PSD = i2n, 1 = 2
· gm · A2 /Hz (A.2)
f Cox · W · L f
where K is technology dependent Flicker noise co-efficient and is lower for

PMOS, Cox is oxide capacitance, f is the frequency and W , L are width & length of
the transistor respectively.
Assuming no correlation between thermal and flicker noise sources, the total
noise current PSD is given as:
Total Noise PSD = In2 = i2n,th + i2n, 1 (A.3)

f
The input referred noise voltage PSD can be calculated by:
2
1. Finding the output noise voltage PSD (Vn,out ) by multiplying noise current PSD
with the square of the output impedance (Rin ||Rload ).
2
2. Dividing the output noise voltage PSD (Vn,out ) by the square of the voltage
gain (AV ) of the amplifier.
The voltage gain AV of the CS amplifier in Fig. 3.6 is given by,

Voltage Gain = AV = gm,in · (Rin ||Rload ) (A.4)
Input referred Thermal Noise
2
Referring to Fig. A.1, the output thermal noise PSD (Vn,out,th ) is given by:
2
Vn,out,th = (i2n,in,th + i2n,load,th ) · (Rin ||Rload )2 V 2 /Hz (A.5)
2
Vn,out,th = 4 · kB · T · γ · (gm,in + gm,load ) · (Rin ||Rload )2 V 2 /Hz (A.6)
The input referred thermal noise can be calculated as,
2
2
Vn,out,th
vn,in,th = V 2 /Hz (A.7)
A2V
2 1 gm,load
vn,in,th = 4 · kB · T · γ · + 4 · kB · T · γ · V 2 /Hz (A.8)
gm,in (gm,in )2
The first and second term in the above equation represents thermal noise contri-
bution by the input transistor and load transistor respectively. The noise from load
transistors is reduced mainly by decreasing their transconductance, with respect to
the input transconductance. Traditionally it is done by decreasing their W/L ratio
i.e giving more overdrive voltage for a given bias current.
Input referred Flicker Noise
2
Referring to Fig. 3.6, the output flicker noise PSD (Vn,out, 1 ) is given by,
f
2 2
Vn,out, 1 = (i
n,in, 1
+ i2n,load,load, 1 ) · (Rin ||Rload )2 V 2 /Hz (A.9)
f f f
2 K 1 2 2
Vn,out, 1 = · · (gm,in + gm,load ) · (Rin ||Rload )2 V 2 /Hz (A.10)
f Cox · W · L f
The input referred flicker noise can be calculated as,
2
Vn,out, 1
2
vn,in, 1 = f
V 2 /Hz (A.11)
f A2V
2
2 K 1 K 1 gm,load
vn,in, 1 = · + · · 2 V 2 /Hz (A.12)
f Cox · W · L f Cox · W · L f gm,in
The first and second term in Eqn. 3.6 represents flicker noise contribution by
the input transistor and load transistor respectively. Note that the flicker noise due
to input transistor can only be reduced by increasing the gate area of the transistor.
The key results for optimizing noise in a linear circuit are extracted from Eqn.
A.8 and Eqn. A.12, and presented Table. A.1.
A.2 Neural Amplifier
Fig. A.2 represents the small signal equivalent of the neural LNA proposed in Chap-
ter 3 (Fig. 3.7). The DC voltages are replaced by an AC ground. The pseudo-
resistor and input capacitance Cin are removed from the schematic. The resistance
(Rx , Ry , Ru , Rd ) are small signal resistance in the direction shown in the Fig. A.2.
All transistors will be considered noisy and the noise source will be modeled
Table A.1: Input Referred Noise optimization in a linear circuit. Proper sizing of
the devices can help in achieving correct transconductance ratios and hence a low
noise design.
Input Referred Noise Input Load
2 1 gm,load
Thermal Noise vn,in ∝ gm,in
∝ 2
gm,in
2
gm,load
2 1 1
Flicker Noise vn,in ∝ Win ·Lin
∝ 2
gm,in
· Wload ·Lload
Figure A.2: Small signal equivalent schematic of the proposed neural amplifier.
as current source between drain and source. Each noise source consists of both
thermal noise and flicker noise. Transistors M3−4 and M7−8 are cascode transistors
and do not contribute to the noise at the output at low frequency [57, 98]. The
noise PSD of transistor Mx with transconductance gm,x is given by,
2 K 1
In,mx = i2n,mx,th + i2n,mx, 1 = 4 · kB · T · gm,x · γ + 2
· gm,x · (A.13)
f Cox · Wx · Lx f
Assuming, gm >> gds and neglecting the body effect (gm >> gmb ), the different
resistances can be calculated as,
Rx = rds,7 · (1 + gm,7 · rds,9 ) ≈ rds,7 · gm,7 · rds,9 (A.14)

1
1+
gm,5 · rds,3 1
Ry = ≈ (A.15)
gm,3 gm,3
Ru = rds,3 · (1 + gm,3 · rds,1 ) ≈ rds,3 · gm,3 · rds,1 (A.16)
1
Rd = (A.17)
gm,5
The voltage gain of the LNA, with Rd << Ru , is given by,
Rx
Av,lna = gm,in · · Rd = gm,in,ef f · Rd (A.18)
Rx + Ry
Now the voltage noise PSD at the output can be calculated based on the contri-
bution from noise source from each transistor and is divided by the A2v,lna to get the
input referred noise. Half circuit concept is used in calculating noise due to each
transistor.
Noise due to M5,6
The current noise in,m5 flows only in the resistance Rd . Hence the output noise is
given by,
2
vn,out,m5 = i2n,m5 · Rd2 (A.19)
2
vn,out,m5 = (i2n,m5,th + i2n,m5, 1 ) · Rd2 (A.20)
f
2 K 2 1
vn,out,m5 = (4 · kB · T · gm,5 · γ + · gm,5 · ) · Rd2 (A.21)
Cox · W5 · L5 f
The input referred noise due to transistor M5 is given by,
K
2
2
vn,out,m5 (4 · kB · T · gm,5 · γ + Cox ·W 5 ·L5
2
· gm,5 · f1 )
vn,in,m5 = = (A.22)
A2v,lna 2
gm,in,ef f
2
2 gm,5 K gm,5 1
vn,in,m5 = 4 · kB · T · 2
·γ+ · 2 · V 2 /Hz (A.23)
gm,in,ef f Cox · W5 · L5 gm,in,ef f f
Noise due to M1,2 = Min
The current noise in,m1 flows to the output through Ry based on the ratio Rx /(Rx +
Ry ). Hence the output noise is given by,
Rx 2
2
vn,out,m1 = i2n,m1 · · Rd2 (A.24)
Rx + Ry
Rx 2
2
vn,out,m1 = (i2n,m1,th + i2n,m1, 1 ) · · Rd2 (A.25)
f Rx + Ry
2 K 2 1 Rx 2
vn,out,m1 = (4 · kB · T · gm,in · γ + · gm,in · ) · Rd2 (A.26)
Cox · Win · Lin f Rx + Ry
2
2
vn,out,m1 (4 · kB · T · gm,in · γ + Cox ·WKin·Lin · gm,in
2
· f1 ) Rx 2
vn,in,m1 = =
A2v,lna 2
gm,in,ef f Rx + Ry
(A.27)
2 1 K 1
vn,in,m1 = 4 · kB · T · ·γ+ · V 2 /Hz (A.28)
gm,in Cox · Win · Lin f
Noise due to M9,10
The current noise in,m9 flows to the output through Ry based on the ratio rds,in /(rds,in +
Ry ). Assuming rds,in >> Ry , the output voltage noise is given by,
2
vn,out,m9 = i2n,m9 · Rd2 (A.29)
2
vn,out,m9 = (i2n,m9,th + i2n,m9, 1 ) · Rd2 (A.30)
f
2 K 2 1
vn,out,m9 = (4 · kB · T · gm,9 · γ + · gm,9 · ) · Rd2 (A.31)
Cox · W9 · L9 f
K
2
2
vn,out,m9 (4 · kB · T · gm,9 · γ + Cox ·W 9 ·L9
2
· gm,9 · f1 )
vn,in,m9 = = (A.32)
A2v,lna 2
gm,in,ef f
2
2 gm,9 K gm,9 1
vn,in,m9 = 4 · kB · T · 2
·γ+ · 2 · V 2 /Hz (A.33)
gm,in,ef f Cox · W9 · L9 gm,in,ef f f
From (A.23), (A.28) and (A.33), total input referred noise at the input is given
by,
2 2 2 2 2 2
vn,in = vn,in,th + vn,in, 1 = vn,in,m1 + vn,in,m5 + vn,in,m9 V 2 /Hz (A.34)
f
with
1 gm,5 gm,9
2
vn,in,th = 4 · kB · T · γ · + 2 + 2 V 2 /Hz (A.35)
gm,in gm,in,ef f gm,in,ef f
2 2
2 K 1 gm,5 gm,9
vn,in, 1 = · + 2
+ 2
V 2 /Hz
f Cox · f Win · Lin W5 · L5 · gm,in,ef f W9 · L9 · gm,in,ef f
(A.36)
Above equations tell that the input transconductance has to ne maximized when
compared to the other transistors for a low noise design. The sizing of the transis-
tors becomes very important to reduce the flicker noise contribution due to the
input transistors.
Appendix B
Capacitive DAC Energy Modeling and

Sizing
In this appendix, we estimate the digital energy consumption in driving the switches
in the CDAC in a SAR ADC. Fig. B.1 represents a CDAC in which the switches are
driven by a SAR Logic which draws energy from the supply Vdd for this purpose. The
switches are sized dependent on the ADC resolution and the speed requirement.
The load to the digital logic is dependent on the size of the switches.
B.1 DAC Digital Energy Consumption Modeling
The assumptions in the derivation are:

1. Half time of each bit cycle is given for DAC settling.
2. The buffers are sized as per Fan-out-of-4 technique.
3. The ADC is a rail-to-rail ADC i.e Vref = Vdd .
From assumption. 1,
Ts
N · log10 2 · τ = 0.5 · (B.1)
N
Ts
N · log10 2 · Rsw · Clsb = 0.5 · (B.2)
N
158
Appendix B. Capacitive DAC Energy Modeling and Sizing 159
Vdac
2^(N-1)Clsb 2^(N-2)Clsb 2.Clsb Clsb

Rsw/2^(N-1) Rsw/2^(N-2) Rsw/2 Rsw
Csw
2^(N-2)Csw
2^(N-1)Csw
2.Csw
Vdd
SAR LOGIC
Figure B.1: Digital energy consumption in a SAR ADC.
1
Rsw =
β · Wu /L · (VGS − VT H )
Ts
= 2
(B.3)
2 · N · log10 2 · Clsb
2 · N 2 · log10 2 · Clsb · L·
Wu = (B.4)
µ · Cox · (VGS − VT H ) · Ts
Now for VGS = VDD and L = Lmin ,
2 · N 2 · log10 2 · Clsb · Lmin · FS

Wu = (B.5)
µ · Cox · (VDD − VT H )
Eqn. B.5 represents the width of the unit switch used for unit DAC capacitance
Clsb for a resolution N, speed FS samples/sec in a CMOS technology with oxide
capacitance Cox and minimum channel length Lmin . Hence the unit load (Csw )
presented by this unit switch to the digital logic can be calculated as,
Csw = Cox · Wu · Lmin (B.6)

1 4 16 4^Lx
Cinv Csw,x
Figure B.2: FO4 buffer chain driving a load capacitance.
2 · N 2 · log10 2 · Clsb · L2min · FS

Csw = (B.7)
µ · (VDD − VT H )
Fig. B.2 shows a buffer chain sized as per the FO4 technique to present minimum
delay. The load to the digital logic is Csw,x = 2x · Csw for xth LSB capacitor. The
number of stages of the buffers (inverters) to drive this load is given by,
C
sw,x
Lx = log4 −1 (B.8)
Cinv
Csw,x
4Lx +1 = (B.9)
Cinv
The total capacitance in the buffer chain excluding the load Csw,x is given by,
Cbuf,x = Cinv + 4 · Cinv + 16 · Cinv + .... + 4Lx · Cinv

4Lx −1 − 1
= · Cinv
4−1
Csw,x − Cinv
= (B.10)
3
Hence, the total digital load for xth LSB switch is,
Cdig,dac (x) = Csw,x + Cbuf,x

4 Cinv
= · Csw,x −
3 3
4 x Cinv
= · 2 · Csw − (B.11)
3 3
(B.12)
The total load switched per sample of the input in resolving it is the sum of all
loads presented by these LSB capacitor switches and their respective buffer chains
PN −1
i.e Cdig,dac,tot = i=0 Cdig,dac (x),
4 N · Cinv
Cdig,dac,tot = · (2N − 1) · Csw − (B.13)
3 3
4 2 · N 2 · log10 2 · Clsb · L2min · FS N · Cinv

Cdig,dac,tot = · (2N − 1) · − (B.14)
3 µ · (VDD − VT H ) 3
The energy consumption in driving the switches of the DAC can then simply be
calculated as,
2
Edig,dac,tot = Cdig,dac,tot · VDD (B.15)
This energy does not include the energy consumed in the sampling switches.
B.2 Sizing of the LSB Capacitor
In SAR ADC, the capacitive DAC is implemented by repetition of an unit capacitor

to cancel the effect of the systematic mismatches to the first order. If the unit
capacitance has a value of Clsb which standard deviation σC , the ith LSB capacitance
in a binary-weighted DAC can be calculated as,
Ci = 2i−1 · Clsb + δi (B.16)
where δi is the effective deviation from the expected value. If the errors in
different unit capacitors are independent identically distributed, the variance of
this deviation is given by,
E[δi2 ] = 2i−1 · σC2 (B.17)
The output of the conventional binary-weighted capacitive DAC for an input

P
x= N i=1 bi .2
i−1
, where bi can be 1 or 0, is given by,
PN i−1
i=1 (2 · Clsb + δi ) · bi
Vdac,bw (x) = P · Vref (B.18)
2N · Clsb + N i=1 δi
The second term in the denominator is neglected for simplicity and the error
from the expected output is calculated as,
PN
i=1 δi · bi
∆Vdac,bw (x) = N
· Vref (B.19)
2 ·C lsb
The variance of this error is given by,
PN
2 2i−1 · bi · (σC /Clsb)2
i=1 2
σ∆V (x) = · Vref
dac,bw
22N
x · (σC /Clsb )2 2
= · VREF (B.20)
22N
The maximum value of this variance occurs at x = 2N −1 ,

2 (σC /Clsb)2 2
σ∆Vdac,bw ,max
= N +1
· Vref (B.21)
2
The mismatch in the capacitors is modeled as,
σC AC
=√ (B.22)
Clsb Clsb
where AC is the mismatch co-efficient of the capacitors and is dependent on the

capacitor implementation and the process technology.
Hence,
2 A2C
σ∆Vdac,bw ,max
≈ ·V2 (B.23)
2N +1 · Clsb ref
The variance of the quantization error in an ADC with resolution N is given by,
2
2 VREF
σQN = (B.24)
22N · 12
The variance of the error due to mismatch must be smaller then the variance
due to the quantization error,
2
A2C 2
Vref
· V ≤ (B.25)
2N +1 · Clsb ref 22N · 12
which give the gives the size of the LSB capacitor Clsb for an resolution N as,
Clsb ≥ 6 · A2C · 2N (B.26)
The value of the LSB capacitor can be calculated from (B.26) based on the yield
(number of sigma). (B.26) also tells that the the requirement on the size of the
LSB capacitance becomes more stringent with the increase in the resolution of the
ADC. The DAC size increase by 4∆N for ∆N increase in the resolution. The constant
AC for UMC 130 nm CMOS technology is found out from the process development
5
10
4
10
3
10
CLSB (in fF)
2
10
1
10
0
10
−1
10
−2
10
2 4 6 8 10 12 14 16 18 20
Resolution (in bit)
Figure B.3: Variation of LSB capacitor size with resolution.
kit as 2 %(f F )0.5. Fig. B.3 shows the variation of the LSB capacitor size with the
resolution for 3 σ yield.
B.3 Linearity Analysis of binary weighted CDAC
This section gives an introduction to the linearity analysis of a binary weighted

capacitive DAC. If the unit (LSB) capacitance has a value of Clsb with standard
deviation σC , the switching capacitance size for the k th MSB is given by,
Csw,k = 2N −k · Clsb + δN −k (B.27)
P2m
where δm = i=1 ǫi , ǫi is the deviation in the ith unit capacitor from the expected
value. The standard deviation in the unit capacitors is σC which is given by (B.22).
If the errors in different unit capacitors are independently identically distributed
[79], the variance of this effective deviation is given by,
2
E[δm ] = 2m · σC2 (B.28)
PN i−1
The output of the binary-weighted capacitive DAC for an input x = i=1 bi .2 ,
where bi can be 1 or 0, is given by,
PN
Vdac,bw (x) i=1 bi · Csw,i
= P N
(B.29)
Vref i=1 Csw,i
P
Vdac,bw (x) x · Clsb + xi=1 ǫi
= P (B.30)
Vref 2N · CDAC + N i=1 ·ǫi
Above equation, neglecting the 2nd term of the denominator, tells that the effec-
tive error due to mismatch in the size of the switching capacitor from the expected
value is only dependent on the total amount of the capacitance switched. Note
that this is only valid when the errors are independently identically distributed.
Hence proper layout is very important of the capacitive DAC to cancel errors due to
gradient and fringe capacitance is very important.
The error due to mismatch in the capacitors is given by,
P
Verr,bw (x) x · Clsb + xi=1 ǫi x
= PN − N (B.31)
Vref 2 · Clsb + i=1 ·ǫi 2
N
P P
Verr,bw (x) (x · Clsb + xi=1 ǫi ) · 2N − x · (2N · Clsb + Ni=1 ·ǫi )
= P (B.32)
Vref (2N · Clsb + N i=1 ·ǫi ) · 2
N
Neglecting the term representing the deviation in the denominator and taking
the variance,
2
E[Verr,bw (x)] x · (2N − x) σc2
2
= 2
(B.33)
Vref 23N Clsb
Hence the standard deviation of the INL for a binary-weighted DAC is given by,
s s
2
E[Verr,bw (x)] x · (2N − x) σc2
σIN L (x) = 2
= 2
(B.34)
Vref 23N Clsb
The standard deviation of the INL for a binary-weighted DAC, in LSBs, is given
by,
r
x · (2N − x) σc
σIN L,lsb (x) = σIN L (x) · 2N = (B.35)
2N Clsb
For larger resolution, σIN L,lsb has to be smaller which requires smaller σc /Clsb i.e
larger Clsb (B.22). For no missing codes in the ADC,
LSB
3 · σIN L,lsb,max < (B.36)
2
Fig. B.4 shows the result of the behavioral simulation in MATLAB of a binary-
weighted DAC. The value of the LSB capacitance is decided as 3-σ value from
(B.22). As expected, the mid-code shows maximum INL and DNL for the binary
weighted DAC.
σIN L (in LSB)
0.1
0.05
0
0 128 256 384 512 640 768 896
Code
σDN L (in LSB)
0.2
0.15
0.1
0.05
0
0 128 256 384 512 640 768 896
Code
Figure B.4: Behavioral simulation results for standard deviation of INL and DNL in
a binary weighted DAC.
Bibliography
[1] K. Chen, Z. Yang, L. Hoang, J. Weiland, M. Humayun, and W. Liu, “An Inte-
grated 256-Channel Epiretinal Prosthesis,” Solid-State Circuits, IEEE Journal
of, vol. 45, no. 9, pp. 1946 –1956, sept. 2010.
[2] J. Fayad, S. Otto, R. Shannon, and D. Brackmann, “Cochlear and Brainstem

Auditory Prostheses ”Neural Interface for Hearing Restoration: Cochlear and
Brain Stem Implants”,” Proceedings of the IEEE, vol. 96, no. 7, pp. 1085 –
1095, july 2008.
[3] J. He, C. Ma, and R. Herman, “Engineering Neural Interfaces for Rehabilita-
tion of Lower Limb Function in Spinal Cord Injured,” Proceedings of the IEEE,
vol. 96, no. 7, pp. 1152 –1166, july 2008.
[4] M. Liker, D. Won, V. Rao, and S. Hua, “Deep Brain Stimulation: An Evolving
Technology,” Proceedings of the IEEE, vol. 96, no. 7, pp. 1129 –1141, july
2008.
[5] A. Amar, M. Levy, C. Liu, and M. Apuzzo, “Vagus Nerve Stimulation,” Pro-
ceedings of the IEEE, vol. 96, no. 7, pp. 1142 –1151, july 2008.
[6] I. Obeid and P. D. Wolf, “Evaluation of spike-detection algorithms for a brain-

machine interface application.” IEEE Trans. Biomed. Eng., vol. 51, no. 6,
JUNE 2004.
168
BIBLIOGRAPHY 169
[7] R. Harrison, R. Kier, C. Chestek, V. Gilja, P. Nuyujukian, S. Ryu, B. Greger,

F. Solzbacher, and K. Shenoy, “Wireless Neural Recording With Single Low-
Power Integrated Circuit,” Neural Systems and Rehabilitation Engineering,
IEEE Transactions on, vol. 17, no. 4, pp. 322 –329, aug. 2009.
[8] M. S. Chae, Z. Yang, M. Yuce, L. Hoang, and W. Liu, “A 128-channel 6 mW

wireless neural recording IC with spike feature extraction and UWB trans-
mitter,” Neural Systems and Rehabilitation Engineering, IEEE Transactions on,
vol. 17, no. 4, pp. 312 –321, aug. 2009.
[9] V. Chaturvedi and B. Amrutur, “An area-efficient noise-adaptive neural am-

plifier in 130 nm CMOS technology,” Emerging and Selected Topics in Circuits
and Systems, IEEE Journal on, vol. PP, no. 99, pp. 1 –10, 2011.
[10] M. S. Chae, W. Liu, and M. Sivaprakasam, “Design optimization for in-

tegrated neural recording systems,” Solid-State Circuits, IEEE Journal of,
vol. 43, no. 9, pp. 1931 –1939, sept. 2008.
[11] M. Azin, D. Guggenmos, S. Barbay, R. Nudo, and P. Mohseni, “A battery-

powered activity-dependent intracortical microstimulation IC for brain-
machine-brain interface,” Solid-State Circuits, IEEE Journal of, vol. 46, no. 4,
pp. 731 –745, april 2011.
[12] M. A. L. Nicolelis, “Actions from thoughts.” Nature, 2001.
[13] U. Frey, F. Heer, R. Pedron, S. Hafizovic, F. Greve, J. Sedivy, K.-U. Kirstein,

and A. Hierlemann, “An 11k-electrode 126-channel high-density microelec-
trode array to interact with electrogenic cells,” in Solid-State Circuits Confer-
ence, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International, feb.
2007, pp. 158 –593.
BIBLIOGRAPHY 170
[14] J. Aziz, K. Abdelhalim, R. Shulyzki, R. Genov, B. Bardakjian, M. Derchansky,

D. Serletis, and P. Carlen, “256-channel neural recording and delta compres-
sion microsystem with 3d electrodes,” Solid-State Circuits, IEEE Journal of,
vol. 44, no. 3, pp. 995 –1005, march 2009.
[15] R. R. Harrison, P. T. Watkins, R. J. Kier, R. O. Lovejoy, D. J. Black, B. Greger,

and F. Solzbacher, “A low-power integrated circuit for a wireless 100-
electrode neural recording system,” Solid-State Circuits, IEEE Journal of,
vol. 42, no. 1, pp. 123 –133, January 2007.
[16] C. Chestek, V. Gilja, P. Nuyujukian, R. Kier, F. Solzbacher, S. Ryu, R. Harrison,

and K. Shenoy, “Hermesc: Low-power wireless neural recording system for
freely moving primates,” Neural Systems and Rehabilitation Engineering, IEEE
Transactions on, vol. 17, no. 4, pp. 330 –338, aug. 2009.
[17] H. Miranda, V. Gilja, C. Chestek, K. Shenoy, and T. Meng, “Hermesd: A high-

rate long-range wireless transmission system for simultaneous multichannel
neural recording applications,” Biomedical Circuits and Systems, IEEE Trans-
actions on, vol. 4, no. 3, pp. 181 –191, june 2010.
[18] M. Roham, D. Covey, D. Daberkow, E. Ramsson, C. Howard, B. Heidenreich,

P. Garris, and P. Mohseni, “A wireless ic for time-share chemical and electrical
neural recording,” Solid-State Circuits, IEEE Journal of, vol. 44, no. 12, pp.
3645 –3658, dec. 2009.
[19] M. Ghovanloo and S. Atluri, “A wide-band power-efficient inductive wireless

link for implantable microelectronic devices using multiple carriers,” Circuits
and Systems I: Regular Papers, IEEE Transactions on, vol. 54, no. 10, pp. 2211
–2221, oct. 2007.
[20] T. M. Seese, H. Harasaki, G. M. Saidel, and C. R. Davies, “Characterization of

tissue morphology, angiogenesis, and temperature in the adaptive response
BIBLIOGRAPHY 171
of muscle tissue to chronic heating,” Lab. Invest., vol. 78, no. 12, pp. 1553–
1562, 1998.
[21] R. Harrison and C. Charles, “A low-power low-noise CMOS amplifier for neu-
ral recording applications,” IEEE J. Solid-State Circuits, vol. 38, no. 6, pp.
958–965, June 2003.
[22] F. Shahrokhi, K. Abdelhalim, D. Serletis, P. Carlen, and R. Genov, “The 128-

channel fully differential digital integrated neural recording and stimula-
tion interface,” Biomedical Circuits and Systems, IEEE Transactions on, vol. 4,
no. 3, pp. 149 –161, june 2010.
[23] B. Gosselin, A. Ayoub, J.-F. Roy, M. Sawan, F. Lepore, A. Chaudhuri, and

D. Guitton, “A mixed-signal multichip neural recording interface with band-
width reduction,” Biomedical Circuits and Systems, IEEE Transactions on,
vol. 3, no. 3, pp. 129 –141, june 2009.
[24] W. Wattanapanitch, M. Fee, and R. Sarpeshkar, “An energy efficient microp-

ower neural recording amplifier.” IEEE Trans. Biomed. Circuits Sys., vol. 1,
no. 2, pp. 136–147, June 2007.
[25] B. Gosselin, M. Sawan, and C. Chapman, “A low-power integrated bioampli-

fier with active low-frequency suppression,” Biomedical Circuits and Systems,
IEEE Transactions on, vol. 1, no. 3, pp. 184 –192, sept. 2007.
[26] J. Bohorquez, M. Yip, A. Chandrakasan, and J. Dawson, “A biomedical sensor

interface with a sinc filter and interference cancellation,” Solid-State Circuits,
IEEE Journal of, vol. 46, no. 4, pp. 746 –756, april 2011.
[27] C. Qian, J. Parramon, and E. Sanchez-Sinencio, “A micropower low-noise

neural recording front-end circuit for epileptic seizure detection,” Solid-State
Circuits, IEEE Journal of, vol. 46, no. 6, pp. 1392 –1405, june 2011.
BIBLIOGRAPHY 172
[28] T. Jochum, T. Denison, and P. Wolf, “Integrated circuit amplifiers for multi-
electrode intracortical recording,” J. Neural Eng., January 2009.
[29] B. Gosselin, A. Ayoub, and M. Sawan, “A low-power bioamplifier with a new

active dc rejection scheme,” IEEE Int. Symp. Circ. Syst., 2006.
[30] K. W. Chew, S. Yeo, and S. F. Chu, “Effect of technology scaling on the 1/f
noise of deep submicron PMOS transistors,” Solid-State Electronics, vol. 48,
no. 7, pp. 1101–1109, July 2004.
[31] K. Hung, P. Ko, C. Hu, and Y. Cheng, “Flicker noise characteristics of ad-
vanced mos technologies,” in Electron Devices Meeting, 1988. IEDM ’88. Tech-
nical Digest., International, 1988, pp. 34 –37.
[32] N. Joye, A. Schmid, and Y. Leblebici, “An electrical model of the cell-electrode
interface for high-density microelectrode arrays.” IEEE EMBS Conf., August
2008.
[33] R. Sarpeshkar, W. Wattanapanitch, S. K. Arfin, B. I. Rapoport, S. Mandal,

M. W. Baker, M. S. Fee, S. Musallam, and R. A. Andersen, “Low-power cir-
cuits for brain machine interfaces,” Biomedical Circuits and Systems, IEEE
Transactions on, vol. 2, no. 3, pp. 173 –183, sept. 2008.
[34] S. Rai, J. Holleman, J. Pandey, F. Zhang, and B. Otis, “A 500 µW neural tag
with 2 µVrms AFE and frequency-multiplying MICS/ISM FSK transmitter,” in
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009.
IEEE International, feb. 2009, pp. 212 –213,213a.
[35] C. Chestek, V. Gilja, P. Nuyujukian, R. Kier, F. Solzbacher, S. Ryu, R. Harrison,

and K. Shenoy, “Hermesc: Low-power wireless neural recording system for
freely moving primates,” Neural Systems and Rehabilitation Engineering, IEEE
BIBLIOGRAPHY 173
[36] R. Harrison, “The Design of Integrated Circuits to Observe Brain Activity,”

Proceedings of the IEEE, vol. 96, no. 7, pp. 1203 –1216, july 2008.
[37] ——, “A low-power integrated circuit for adaptive detection of action poten-
tials in noisy signals,” Proc. lnt. Conf. IEEE EMBS, September 2003.
[38] H. Semmaoui, J. Drolet, A. Lakhssassi, and M. Sawan, “Setting adaptive

spike detection threshold for smoothed-teo based on robust statistics theory,”
Biomedical Engineering, IEEE Transactions on, vol. PP, no. 99, p. 1, 2011.
[39] M. Chae, W. Liu, Z. Yang, T. Chen, J. Kim, M. Sivaprakasam, and M. Yuce, “A

128-channel 6mW wireless neural recording ic with on-the-fly spike sorting
and uwb tansmitter,” in Solid-State Circuits Conference, 2008. ISSCC 2008.
Digest of Technical Papers. IEEE International, feb. 2008, pp. 146 –603.
[40] A. Sodagar, G. Perlin, Y. Yao, K. Najafi, and K. Wise, “An implantable 64-
channel wireless microsystem for single-unit neural recording,” Solid-State
Circuits, IEEE Journal of, vol. 44, no. 9, pp. 2591 –2604, sept. 2009.
[41] V. Karkare, S. Gibson, and D. Markovic and, “A 130- µw, 64-channel neural
spike-sorting dsp chip,” Solid-State Circuits, IEEE Journal of, vol. 46, no. 5,
pp. 1214 –1222, may 2011.
[42] P. Mohseni and K. Najafi, “A fully integrated neural recording amplifier with
input dc stabilization.” IEE Trans. Biomed. Eng., vol. 51, no. 5, pp. 832–837,
May 2004.
[43] D. Robinson, “The electrical properties of metal microelectrodes,” Proceed-

ings of the IEEE, vol. 56, no. 6, pp. 1065 – 1071, june 1968.
[44] J. Ji and K. D. Wise, “An implantable CMOS circuit interface for multiplexed
micro-electrode recording arrays,” IEEE J. Solid-State Circuits, vol. 27, pp.
433–443, March 1992.
BIBLIOGRAPHY 174
[45] S. O’Driscoll, K. Shenoy, and T. Meng, “Adaptive resolution ADC array for
an implantable neural sensor,” Biomedical Circuits and Systems, IEEE Trans-
actions on, vol. 5, no. 2, pp. 120 –130, april 2011.
[46] W.-S. Liew, X. Zou, L. Yao, and Y. Lian, “A 1-V 60-µW 16-channel interface
chip for implantable neural recording,” in Custom Integrated Circuits Confer-
ence, 2009. CICC ’09. IEEE, sept. 2009, pp. 507 –510.
[47] V. Majidzadeh, A. Schmid, and Y. Leblebici, “Energy efficient low-noise neu-

ral recording amplifier with enhanced noise efficiency factor,” Biomedical Cir-
cuits and Systems, IEEE Transactions on, vol. 5, no. 3, pp. 262 –271, june
2011.
[48] D. Henze, Z. Borhegyi, J. Csicsvari, A. Mamiya, K. Harris, and G. Buzsaki, “In-

tracellular features predicted by extracellular recordings in the hippocampus
in vivo,” J. Neurophysiol., vol. 84, 2000.
[49] M. Yin and M. Ghovanloo, “A low-noise preamplifier with adjustable gain and
bandwidth for biopotential recording applications,” in Circuits and Systems,
2007. ISCAS 2007. IEEE International Symposium on, may 2007, pp. 321
–324.
[50] N. Neihart and R. Harrison, “Micropower circuits for bidirectional wireless

telemetry in neural recording applications,” Biomedical Engineering, IEEE
Transactions on, vol. 52, no. 11, pp. 1950 –1959, nov. 2005.
[51] X. Zou, X. Xu, L. Yao, and Y. Lian, “A 1-v 450-nw fully integrated pro-
grammable biomedical sensor interface chip,” Solid-State Circuits, IEEE Jour-
nal of, vol. 44, no. 4, pp. 1067 –1077, april 2009.
[52] W. Grill, Indwelling Neural Implants: Strategies for Contending with the In
Vivo Environment, W. Reichert, Ed. CRC Press, 2007.
BIBLIOGRAPHY 175
[53] B. Murmann and B. Boser, “A 12-bit 75-MS/s pipelined ADC using open-loop
residue amplification,” Solid-State Circuits, IEEE Journal of, vol. 38, no. 12,
pp. 2040 – 2050, dec. 2003.
[54] R. Muller, S. Gambini, and J. M. Rabaey, “A 0.013 mm2 , 5 µw , dc-coupled

neural signal acquisition ic with 0.5 v supply,” Solid-State Circuits, IEEE Jour-
nal of, vol. PP, no. 99, p. 1, 2011.
[55] Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nd, Ed. McGraw-
Hill, 1998.
[56] [Online]. Available: http://www.synopsys.com/Tools/TCAD
[57] B. Razavi, Design of Analog CMOS Integrated Circuits. McGraw-Hill, 2000.
[58] D. A. Johns and K. Martin, Analog Integrated Circuit Design, Wiley, 1997.
[59] Y. Nemirovsky, I. Brouk, and C. G. Jakobson, “1/f noise in CMOS transistors

for analog applications,” IEEE Trans. Electron Devices, vol. 48, no. 5, May
2001.
[60] E. A. Vittoz and J. Fellrath, “CMOS analog integrated circuits based on weak
inversion operation.” IEEE J. Solid-State Circuits, vol. 12, pp. 224–231, 1977.
[61] D. M. Binkley, Tradeoffs and optimization in analog CMOS design. WILEY,

2008.
[62] R. Gregorian and G. C. Temes, Analog mos integrated circuits for signal pro-
cessing. Wiley.
[63] [Online]. Available: http://www.fh-co.com/
[64] J. McCreary and P. Gray, “All-mos charge redistribution analog-to-digital con-

version techniques. i,” Solid-State Circuits, IEEE Journal of, vol. 10, no. 6, pp.
371 – 379, dec 1975.
BIBLIOGRAPHY 176
[65] G. Promitzer, “12-bit low-power fully differential switched capacitor noncal-

ibrating successive approximation ADC with 1 MS/s,” Solid-State Circuits,
IEEE Journal of, vol. 36, no. 7, pp. 1138 –1143, jul 2001.
[66] C.-C. Liu, S.-J. Chang, G.-Y. Huang, Y.-Z. Lin, and C.-M. Huang, “A 1V
11fJ/conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18 µm
CMOS,” in VLSI Circuits (VLSIC), 2010 IEEE Symposium on, june 2010, pp.
241 –242.
[67] A. Agnes, E. Bonizzoni, P. Malcovati, and F. Maloberti, “A 9.4-ENOB 1V 3.8

µ w 100kS/s SAR ADC with time-domain comparator,” in Solid-State Circuits
Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International,
feb. 2008, pp. 246 –610.
[68] S. Gambini and J. Rabaey, “A 1.5MS/s 6-bit ADC with 0.5V supply,” in Solid-
State Circuits Conference, 2006. ASSCC 2006. IEEE Asian, nov. 2006.
[69] I. Akyildiz, W. Su, Y. Sankarasubramaniam, and E. Cayirci,

“Wireless sensor networks: a survey,” Computer Networks,
vol. 38, no. 4, pp. 393 – 422, 2002. [Online]. Available:
http://www.sciencedirect.com/science/article/pii/S1389128601003024
[70] M. Scott, B. Boser, and K. Pister, “An ultralow-energy adc for smart dust,”
Solid-State Circuits, IEEE Journal of, vol. 38, no. 7, pp. 1123 – 1129, july
2003.
[71] N. Verma and A. Chandrakasan, “An ultra low energy 12-bit rate-resolution
scalable SAR ADC for wireless sensor nodes,” Solid-State Circuits, IEEE Jour-
nal of, vol. 42, no. 6, pp. 1196 –1205, june 2007.
[72] B. Razavi and B. Wooley, “Design techniques for high-speed, high-resolution

comparators,” Solid-State Circuits, IEEE Journal of, vol. 27, no. 12, pp. 1916
–1926, dec 1992.
BIBLIOGRAPHY 177
[73] B. Ginsburg and A. Chandrakasan, “An energy-efficient charge recycling ap-

proach for a SAR converter with capacitive DAC,” in Circuits and Systems,
2005. ISCAS 2005. IEEE International Symposium on, may 2005, pp. 184 –
187 Vol. 1.
[74] Y.-K. Chang, C.-S. Wang, and C.-K. Wang, “A 8-bit 500-KS/s low power SAR
ADC for bio-medical applications,” in Solid-State Circuits Conference, 2007.
ASSCC ’07. IEEE Asian, nov. 2007, pp. 228 –231.
[75] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10-bit 50-MS/s SAR
ADC with a monotonic capacitor switching procedure,” Solid-State Circuits,
IEEE Journal of, vol. 45, no. 4, pp. 731 –740, april 2010.
[76] Y. Zhu, C.-H. Chan, U.-F. Chio, S.-W. Sin, S.-P. U, R. Martins, and F. Maloberti,
“A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS,” Solid-State
Circuits, IEEE Journal of, vol. 45, no. 6, pp. 1111 –1121, june 2010.
[77] T. Anand, V. Chaturvedi, and B. Amrutur, “Energy efficient asymmetric bi-

nary search switching technique for SAR ADC,” Electronics Letters, vol. 46,
no. 22, pp. 1487 –1488, 28 2010.
[78] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and

B. Nauta, “A 1.9 uW 4.4fJ/conversion-step 10b 1MS/s charge-redistribution
ADC,” in Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Techni-
cal Papers. IEEE International, feb. 2008, pp. 244 –610.
[79] B. Ginsburg and A. Chandrakasan, “500-MS/s 5-bit ADC in 65-nm CMOS

with split capacitor array DAC,” Solid-State Circuits, IEEE Journal of, vol. 42,
no. 4, pp. 739 –747, april 2007.
BIBLIOGRAPHY 178
[80] T. Werth, C. Schmits, R. Wunderlich, and S. Heinen, “An active feedback

interference cancellation technique for blocker filtering in rf receiver front-
ends,” Solid-State Circuits, IEEE Journal of, vol. 45, no. 5, pp. 989 –997, may
2010.
[81] H. Darabi, “A blocker filtering technique for saw-less wireless receivers,”

Solid-State Circuits, IEEE Journal of, vol. 42, no. 12, pp. 2766 –2773, dec.
2007.
[82] Y. Tsividis, “Principles of operation and analysis of switched-capacitor cir-

cuits,” Proceedings of the IEEE, vol. 71, no. 8, pp. 926–940, Aug 1983.
[83] M. Yip and A. Chandrakasan, “A resolution-reconfigurable 5-to-10b 0.4-to-1V

power scalable SAR ADC,” in Solid-State Circuits Conference Digest of Techni-
cal Papers (ISSCC), 2011 IEEE International, feb. 2011.
[84] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching Proper-

ties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, pp. 1433–1440,
1989.
[85] C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effects of op-
amp imperfections: autozeroing, correlated double sampling, and chopper
stabilization.” Proc. IEEE, 1996.
[86] M. Saberi, R. Lotfi, K. Mafinezhad, and W. Serdijn, “Analysis of power con-

sumption and linearity in capacitive digital-to-analog converters used in suc-
cessive approximation adcs,” Circuits and Systems I: Regular Papers, IEEE
[87] P. J. A. Harpe, C. Zhou, Y. Bi, N. P. van der Meijs, X. Wang, K. Philips, G. Dol-
mans, and H. de Groot, “A 26 µW 8 bit 10 MS/s asynchronous SAR ADC for
low energy radios,” Solid-State Circuits, IEEE Journal of, vol. 46, no. 7, pp.
1585 –1595, july 2011.
BIBLIOGRAPHY 179
[88] B. Malki, T. Yamamoto, B. Verbruggen, P. Wambacq, and J. Craninckx, “A

70dB DR 10b 0-to-80MS/s current-integrating SAR ADC with adaptive dy-
namic range,” in Solid-State Circuits Conference Digest of Technical Papers
(ISSCC), 2012 IEEE International, feb. 2012, pp. 470 –472.
[89] L. Sumanen, M. Waltari, and K. Halonen, “A mismatch insensitive CMOS

dynamic comparator for pipeline A/D converters,” in Electronics, Circuits and
Systems, 2000. ICECS 2000. The 7th IEEE International Conference on, vol. 1,
2000, pp. 32 –35 vol.1.
[90] V. Katyal, R. L. Geiger, and D. J. Chen, “A new high precision low offset
dynamic comparator for high resolution high speed ADCs,” in Circuits and
Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on, dec. 2006, pp.
5 –8.
[91] K. Dyer, D. Fu, S. Lewis, and P. Hurst, “An analog background calibration
technique for time-interleaved analog-to-digital converters,” Solid-State Cir-
cuits, IEEE Journal of, vol. 33, no. 12, pp. 1912 –1919, dec 1998.
[92] A. Petraglia and S. Mitra, “Analysis of mismatch effects among A/D convert-
ers in a time-interleaved waveform digitizer,” Instrumentation and Measure-
ment, IEEE Transactions on, vol. 40, no. 5, pp. 831 –835, oct 1991.
[93] J. Vibert and J. Costa, “Spike separation in multiunit records: A multivariate

analysis of spike descriptive parameters,” Electroencephalography and Clinical
Neurophysiology, vol. 47, no. 2, pp. 172 – 182, 1979. [Online]. Available:
http://www.sciencedirect.com/science/article/pii/0013469479902190
[94] I. Olsson, R.H. and K. Wise, “A three-dimensional neural recording microsys-

tem with implantable data compression circuitry,” Solid-State Circuits, IEEE
Journal of, vol. 40, no. 12, pp. 2796 – 2804, dec. 2005.
BIBLIOGRAPHY 180
[95] V. Chaturvedi and B. Amrutur, “A low-noise low-power noise-adaptive neural

amplifier in 0.13um CMOS technology,” in VLSI Design (VLSI Design), 2011
24th International Conference on, jan. 2011, pp. 328 –333.
[96] M. Yin and M. Ghovanloo, “A flexible clockless 32-ch simultaneous wireless

neural recording system with adjustable resolution,” in Solid-State Circuits
Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International,
feb. 2009, pp. 432 –433,433a.
[97] I. Ahmed and D. Johns, “A 50-MS/s (35 mW) to 1-KS/s (15 µW) power
scaleable 10-bit pipelined adc using rapid power-on opamps and minimal
bias current variation,” Solid-State Circuits, IEEE Journal of, vol. 40, no. 12,
pp. 2446 – 2455, dec. 2005.
[98] P. R. Gray, R. G. Meyer, P. J. Hurst, and S. H. Lewis, Analysis and Design of

Analog Integrated Circuits, 4th ed. New York, NY, USA: John Wiley & Sons,
Inc., 2001.
[99] K. Lakshmikumar, R. Hadaway, and M. Copeland, “Characterisation and

modeling of mismatch in MOS transistors for precision analog design,” Solid-
State Circuits, IEEE Journal of, vol. 21, no. 6, pp. 1057 – 1066, dec 1986.
[100] P. Kinget, “Device mismatch and tradeoffs in the design of analog circuits,”
Solid-State Circuits, IEEE Journal of, vol. 40, no. 6, pp. 1212 – 1224, june
2005.
[101] P. Gray and R. Meyer, “MOS operational amplifier design-a tutorial

overview,” Solid-State Circuits, IEEE Journal of, vol. 17, no. 6, pp. 969 –982,
dec. 1982.
[102] B. murmann, ”adc performance survey 1997-2011. [Online]. Available:

http://www.stanford.edu/ murmann/adcsurvey.html.
BIBLIOGRAPHY 181
[103] W. Wattanapanitch and R. Sarpeshkar, “A Low-Power 32-Channel Digitally

Programmable Neural Recording Integrated Circuit,” Biomedical Circuits and
Systems, IEEE Transactions on, vol. 5, no. 6, pp. 592 –602, dec. 2011.

Vikram PHD Thesis PDF

Загружено:

Сведения о документе

Оригинальное название

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

Vikram PHD Thesis PDF

Загружено:

Авторское право:

Доступные форматы

Low Power and Low Area Techniques

For Neural Recording Application

(Dr. Bharadwaj Amrutur) Principal Advisor

Chronic recording of neural signals is indispensable in designing efficient brain

• Vikram Chaturvedi and Bharadwaj Amrutur, ”An energy-efficient FlipDac switch-

Peer-Reviewed Journal Articles

• Vikram Chaturvedi, Bharadwaj Amrutur, An Area Efficient Noise-Adaptive Neu-

• Tejasvi Anand, Vikram Chaturvedi, Bharadwaj Amrutur, An energy efficient

• Vikram Chaturvedi, Tejasvi Anand, Bharadwaj Amrutur, An 8-to-1 bit 1 MS/s

• Vikram Chaturvedi and Bharadwaj Amrutur, A Low-Noise Low-Power Noise-

• Student Research Preview in International Solid State Circuit Conference 2011,

• 24th International Conference on VLSI Design, January 2011, Chennai, India.

Publications from the thesis work and contributing works iii

2 Neural Recording System 10

3 Neural Low Noise Amplifier Design 28

4 Energy-Efficient DAC Switching Techniques 61

5 SAR ADC design for NRFE 94

6 Neural Recording Front End Design 107

A Noise Analysis and Optimization 149

B Capacitive DAC Energy Modeling and Sizing 158

3.1 Sizing, gm, gm/Id for all devices . . . . . . . . . . . . . . . . . . . . 40

4.1 DAC Switching Energy Comparison for 10 bit SAR ADC . . . . . . . . 70

6.1 SAR ADC Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . 135

7.1 Neural LNA Comparison . . . . . . . . . . . . . . . . . . . . . . . . . 145

A.1 Input Referred Noise optimization in a linear circuit. Proper sizing

2.1 Origin of an action potential due to sodium and potassium channels

4.1 Binary search algorithm for quantization of an input. . . . . . . . . . 62

5.1 VGA and ADC in a N-channel neural recording front end. . . . . . . . 94

6.1 Block Diagram of the 16-channel neural recording system. . . . . . . 108

7.1 Comparison with SAR ADCs published. . . . . . . . . . . . . . . . . . 146

B.1 Digital energy consumption in a SAR ADC. . . . . . . . . . . . . . . . 159

1.1 Brain Machine Interface

• Process the information to reduce the amount of data to be transmitted.

• Decode the information by processing the information and convert it to a form

Figure 1.2: A typical N-channel neural recording system.

1.2 Neural Recording System

Figure 1.3: A typical N-channel neural recording front end.

1.3 Neural Recording Front End

created in the electrolyte through a multi-electrode array (MEA) and amplifies it

1.4 Thesis Contribution and Organization

• The design of a low-power noise-adaptive neural LNA is presented. An em-

and makes the NRFE system more energy-efficient.

• A novel activity dependent A/D scheme is proposed to mitigate the processing

• An energy efficient FlipDAC switching scheme is proposed for capacitive DAC

• Another energy-efficient switching technique for a capacitive DAC, QCS, is

injection mismatch is presented. An analysis on the linearity for this scheme

Neural Recording System

HRONIC recording of neural signals from a large number of neurons [12] is

2.2 Neural Signal Characteristics

2.3 Challenges in NRS Design

Figure 2.3: Block diagram of a typical neural recording system.

Figure 2.4: Power and Area Breakdown in a SoC presented in [11].

Figure 2.5: DC offset rejection scheme in LNA.

Figure 2.6: Background noise and electronic noise in NRFE.

Figure 2.7: Various schemes of data transmission in a neural recording system.

Output Data Rate

2.4 Neural Recording Front End

Figure 2.8: A typical N-channel neural recording front end.

Figure 2.10: Electrical model of ac-impedance of an electrode.

frequencies and consists of interconnect resistance, spreading resistance etc. RCT

Analog-to-digital converter (ADC) is another very important block in a NRFE. It

Neural Low Noise Amplifier Design

3.2 Neural Amplifier Design