Вы находитесь на странице: 1из 19

# Optimization of Sequential Networks

## Step in Synthesis: We focus here on minimizing

states for:
Problem
1. Completely Specified
Sequential Machines –
Flow Table
specified by flow tables
Reduce States with no don’t cares

## Minimum-State Table 2. Incompletely Specified

Sequential Machines –
State Assignment specified by flow tables
with don’t cares
Transition Table

## Excitation Table or Functions

Circuit
State Reduction Goal
Given a flow table, to find an indistinguishable, minimum-
state flow table.
Note: this leads to a circuit with fewest possible memory
elements & usually a minimum cost (but not always)
Indistinguishable Flow Tables - flow tables that specify
identical output sequences for the same input sequence.
Inaccessible States – states not reached from initial state
or from desired pattern
• We want to eliminate inaccessible states by state reduction or by
making them accessible.
• We assume this is done before other state reduction techniques
are employed.
Table Reduction for
Completely Specified Networks
Consider two flow tables:
Table T Table T*
Present Next state, output
state x=0 x=1 Present Next state, output
state x=0 x=1
A B,1 C,0
B B,1 C,0 E E,1 F,0
C A,0 D,1 F E,0 F,1
D A,0 D,1

## If the same input sequence is applied to T or T*, they

produce the same output sequences
Example: for sequence x = 011, z(T,A)=101, z(T*,E)=101
Distinguishability
Two states of a FSM si and sj are distinguishable if they
produce different output sequences for the same input
sequence. Such an input sequence is a distinguishing
sequence of (si, sj)

## Two states of a FSM si and sj are equivalent or

indistinguishable if they produce the same output
sequences for the same input sequence and are members
of an indistinguishable class.

## If there is a distinguishing sequence with length k for (si, sj),

the (si, sj) is k-distinguishable

## Goal: to merge all equivalent states to obtain the minimum

number of states.
Partition and Array Techniques to
Produce Minimum-State Tables
Partition Test
Steps:

## Present Next state, output Present Next state, output

state state
x=0 x=1 x=0 x=1
Q0 Q2,0 Q1,1 Q0 A Q2 A,0 Q1 B,1
Q1 Q2,1 Q0,1 Q1 B Q2 A,1 Q0 A,1
Q2 Q4,0 Q1,1 Q2 A Q4 A,0 Q1 B,1
Q3 Q5,0 Q0,0 Q3 C Q5 B,0 Q0 A,0
Q4 Q0,0 Q6,1 Q4 A Q0 A,0 Q6 B,1
Q5 Q3, 1 Q2,1 Q5 B Q3 C, 1 Q2 A,1
Q6 Q4,1 Q2,1 Q6 B Q4 A,1 Q2 A,1

Partition Test
Steps:

## Present Next state, output

state
x=0 x=1
Q0 A Q2 A,0 Q1 B,1
Q1 B Q2 A,1 Q0 A,1
Q2 A Q4 A,0 Q1 B,1
Q3 C Q5 BD,0 Q0 A,0
Q4 A Q0 A,0 Q6 B,1
Q5 BD Q3 C, 1 Q2 A,1
Q6 B Q4 A,1 Q2 A,1

Partition Test

Steps:

## Present Next state, output

state
x=0 x=1
Q0 A Q2 A,0 Q1 B,1
Q1 B Q2 A,1 Q0 A,1
Q3 C Q5 BD,0 Q0 A,0
Q5 BD Q3 C, 1 Q2 A,1

## A[Q0Q2Q4] B[Q1Q6] BD[Q5] C[Q3]

Array Technique
Steps:
1. Form Pair Chart with ½(S)(S-1) entries. Place X in cells that
correspond to state pairs having different outputs.
2. Each remaining pair examined, place
asterisk in cells with identical next state
entries. Place pairs of states that must be
Present Next state, output
state indistinguishable in order that pair
x=0 x=1 represented by cell be indistinguishable
Q0 Q2,0 Q1,1
Q1 X
Q1 Q2,1 Q0,1
Q2 Q2Q4 X
Q2 Q4,0 Q1,1
Q3 X X X
Q3 Q5,0 Q0,0 Q0Q2 Q1Q6
Q4 Q1Q6 X Q0Q4 X
Q4 Q0,0 Q6,1 Q2Q3
Q5 X Q0Q2 X X X
Q5 Q3, 1 Q2,1
Q2Q4
Q6 Q4,1 Q2,1 Q6 X Q0Q2 X X X Q3Q4

Q0 Q1 Q2 Q3 Q4 Q5
Array Technique
3. Make successive passes through array Xing out cells
having pair entries that are distinguishable (marked by X
elsewhere in Table)
Q1 X
Q2 Q2Q4 X
Q3 X X X
Q0Q2 Q1Q6
Q4 Q1Q6 X Q0Q4 X
Q2Q3
Q5 X Q0Q2 X X X
Q2Q4
Q6 X Q0Q2 X X X Q3Q4

Q0 Q1 Q2 Q3 Q4 Q5

Result:
[Q0Q2Q4] [Q1Q6] ] [Q3] [Q5]
Optimization of Incompletely
Specified Machines
Some definitions:
Two states are I-Equivalent IFF
1. Outputs are identical, if specified
2. Matching d-outputs occur
3. Matching unspecified next states occur or specified next states
must be equivalent.

## Two states are Compatible IFF

1. Outputs are identical, if specified
2. Compatible next-states occur, if both are specified.
Maximal Compatible Classes - classes that are not subsets of any
other compatibility class.
Optimization of Incompletely
Specified Machines
Flow Table I-Equivalent States Removed

Compatible State

Pair Chart
Maximal Compatibility Classes

Minimum-State Table
Optimization of Incompletely
Specified Machines

## Steps in finding Reduced Table:

1. Remove I-Equivalence states
2. Find Maximal Compatibility Classes
3. Form Flow Table in which each state
corresponds to a maximal compatibility class
subject to satisfying the closure property and all
states of the original table are represented, that
is satisfying the covering property.
Optimization of Incompletely Specified
Machines – Array Technique
Example:

## Present Next state, output

state B X
I1 I2 I3 I4
D BE AE DE
A -- -- E,1 --
B C,0 A,1 B,0 -- E CE BC AB. BC
BC
C C,0 D,1 -- A,0 A B C D

## D -- E,1 B,- -- Compatibility State Set:

E B,0 -- C,- B,0 [AC], [AD], [CD], [ACD], [BC], [BE], [ED]

## Maximal compatibility classes

Optimization of Incompletely
Specified Machines – Merger Graph
Complete Subgraph
Example:
A
(DE) (BC) B
Present Next state, output
E (AE)
state
(BE) (BC)
I1 I2 I3 I4 (AB)

A -- -- E,1 -- D (DE)
C
B C,0 A,1 B,0 --
C C,0 D,1 -- A,0
D -- E,1 B,- -- Compatibility State Set:
E B,0 -- C,- B,0 [AC], [AD], [CD], [ACD], [BC], [BE], [ED]

## Maximal compatibility classes

State Compatibility Graph
State Compatibility Graph is a directed graph satisfying the
conditions:
1. Each node corresponds to a compatible state set.
2. When a state set implies another state set S, attach OR
directed edges from the nodes corresponding to the
original state set to the node corresponding to the state
sets containing S.
3. When a state set implies two or more state sets: S0, ….,
Sk-1, Sk, Attach AND directed edges from the node
corresponding to the original state set to the nodes that
correspond to S0, …., S k-1, Sk
Finding Minimum Number of
States Using State
Compatibility Graph
Must Satisfy Two Conditions:
1. Covering Property – Each state of the FSM is contained by
at least one compatible set V
2. Closure Property: If vi  V, then Vi  V, where Vi is the set
of implied compatible sets. Vi satisfies the following
condition: for the OR directed edges that emerge from vi ,
Vi contains the nodes for at least one edge. For the AND
directed edges that emerge from vi , Vi contains the nodes
for all the AND directed edges.
(DE) (BC) B
E (AE)

(BE) (BC)
(AB)

D (DE)

V1 : [BE]
Present Next state, output V3 : [CD]
V7
state V3 V4 : [BC]
I1 I2 I3 I4 V8 V1 V5 : [ACD]
V6
V9 AND V6 : [DE]
V7 : [AC]
A -- -- E,1 -- V10 V5 V8 : [A]
B C,0 A,1 B,0 -- V11 V2 V9 : [B]
OR V10 : [C]
C C,0 D,1 -- A,0 V12 V11 : [D]
V4 V12 : [E]
D -- E,1 B,- --
E B,0 -- C,- B,0
Optimization Example
Covering Property

State A: v2 + v5 + v7 + v8 = 1
State B: v1 + v4 + v9 = 1
State C: v3 + v4 + v5 + v7 + v10 = 1
State D: v2 + v3 + v5 + v6 + v11 = 1
State E: v1 + v6 + v12 = 1
Closure Property Example
From the state compatibility graph

v1  v4 , so v1 + v4 = 1
v2  v1 , so v2 + v1 = 1
v3  v6 , so v3 + v6 = 1
v4  (v2 + v5 ), so v4 + v2 + v5 = 1
v5  v1v6, so (v5 + v1 )(v5 + v6) = 1
v6  v4 , so v6 + v4 = 1