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Tutorial on

Chemical Mechanical Polishing (CMP)

Ara Philipossian

Intel Corporation

© 1999 Arizona Board of Regents for The University of Arizona

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
1
Outline of the Tutorial
• Section A: Overview
– Generalized schematics of CMP and Post-CMP Clean
– Current CMP environment
– Evolution of CMP
– The CMP Module
– The CMP Infrastructure
• Section B: Polishing equipment trends
• Section C: Polishing process issues
• Section D: Consumables (pads & slurries)
– Quality issues
– Factors affecting productivity
– Critical pad and slurry parameters

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
2
Outline of the Tutorial

• Section E: Industry - University Gaps


• Section F: Environmental Health and Safety (EHS)
considerations
• Section G: Slurry fluid dynamics
• Section H: Slurry re-use
• Section I: Post-CMP cleaning

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
3
Section A: Overview

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
4
Schematic Diagram of
Chemical Mechanical Polishing Process
Downforce

Carrier

Pad Conditioner

Retaining Slurry
Ring Pad

Polish Platen

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
5
Schematic Diagram of
Post-CMP Scrubbing

PVA brush

wafer

Cleaning Fluid
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
6
CMP Environment
• CMP has become the widely accepted planarization method of choice
for < 0.5 micron technologies
• The overall CMP market is growing at a rate of ~ 50% per year
• The current momentum in process integration and scaling far exceeds
the fundamental understanding of complex interactions among:
– Equipment
– Consumables (i.e. slurry, pad, carrier film)
– Process parameters
– IC type and density
• Processes and consumables are formulated to provide optimum
performance for a given equipment and IC product set
• For a 4 metal layer process with STI, ILD and W CMP steps,
approximately 20 polishers are needed ( 60% utilization, 20 wafers
per hour, 5000 wafer starts per week factory)

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
7
CMP Environment

• Protection of intellectual property hinders shared learning among IC,


equipment and consumables manufacturers, but also provides a
technological advantage:
– Internally developed equipment, precision parts and
sub-systems
• Morimoto & Patterson, US Patent No. 5,104,828 (1992)
• Breivogel, Blanchard & Prince, US Patent No. 5,216,843 (1993)
• Breivogel, Louke, Oliver, Yau & Barns, US Patent No. 5,554,064
(1996)
– Internal slurry formulations licensed to suppliers for exclusive use
– Customized pads
– 3rd party modifications of off-the-shelf consumables and
equipment

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
8
Evolution of CMP

12

10
Number of Polish Steps

6 Tungsten

4
Oxide

0
1994 (0.25 1997 (0.25
to 0.50 to 0.35
micron) micron)

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
9
Evolution of CMP

Generation Application CMP Post-CMP Clean


Attributes Attributes

First ILD Single platen, single head, Wet station,


one step polish scrubber, DI water
(0.8 to 0.5
um)
Second ILD, Doped ILD, Multiple platens, multiple Scrubber, DI water
STI & W heads, buffing, end-point & NH4OH
(0.5 to 0.25 detection & on-board
um) metrology
Third ILD, Doped ILD, Integrated Dry-In Dry-Out, Integrated Dry-In
STI, W, Low K multiple platens, multiple Dry-Out, scrubbing,
(0.25 to 0.18 ILD, Cu, Al & heads, non-rotary (i.e. orbital DI water, NH4OH,
um) polysilicon and linear), multiple step HF, novel cleaning
polish, end point detection methods and
and on-board metrology chemistries

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
10
Total Cost
Chemical Expenditure per fully Processed Product Wafer
(Disposal and Treatments Costs are Included)
a - Negotiate Price
b - Insert competition
c - Reduce disposal volume
d - reclaim and re-use
Normalized Cost per Wafer

a - Negotiate Price
b - Insert competition
c - Increase pad life via better QC
d - Increase pad life via better chemistry

ILD Slurry
W Slurry

ILD Top
2

8
Pad
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
11
The CMP Module
Product and Test Wafers

Measure & Inspect


Filter

Water Polish
Energy
Energy Re-work
In-Situ Measure
Solid Waste
Slurry
Clean
Pad Liquid Waste

Carrier Film Measure & Inspect

Product and Test Wafers


Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
12
The CMP Infrastructure
• Polishing:
✓ Rotary (single or multiple heads and platens)
– Orbital (single or multiple heads and platens)
– Linear (multiple heads)
• Cleaning:
✓ Mechanical scrubbing (with & without chemistry or megasonics)
✓ Wet cleaning (with and without megasonics)
• Measurement and inspection:
✓ Removal Rate
– Thickness uniformity (wafer-to-wafer, within-die, die-to-die)
– Defect density
– Dishing
– Erosion
– Plug recess
✓ Planarity
– Surface Roughness
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
13
The CMP Infrastructure
• In-situ Measurement:
– End-point detection
• Consumables:
✓ Pad (polyurethane, impregnated felt, fixed abrasive)
✓ Slurry (silica, alumina or ceria abrasives, organic and inorganic
additives)
– Filter (point-of-use or post-slurry-blending)
– Conditioning (diamonds)
• Slurry delivery
• Water delivery
• Waste treatment:
– Off-site disposal
– Recycling
✓ Re-use
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
14
Section B: Polishing Equipment Trends

Philipossian, Morimoto and Cadien, CMP-MIC,


Santa Clara, CA (1996)

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
15
Equipment Environment

• In high-volume manufacturing, the balance between high throughput,


size and complexity needs to be maintained

Polisher Number of Number of


Polish Heads Polish Plattens

A 1 1
B 2 1
C 3 3
D 4 4
E 5 1
F 6 1

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
16
Equipment Environment
• Development of automated dry-in-dry-out systems that:

• Improve throughput
• Reduce footprint
• Reduce total cost
Polish 1 Polish 2
• Reduce ergonomic issues
• Reduce number of people

Polish Clean Robot

I/O I/O Clean

• Ability to polish 300-mm wafers


• In-situ metrology for device wafers with closed-loop control
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
17
Section C: Polishing Process Issues

Philipossian, Morimoto and Cadien, CMP-MIC,


Santa Clara, CA (1996)

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
18
Process Issues
• Within-Wafer Non-Uniformity (WIWNU):
– Wafer flatness
– Carrier film, pad & slurry type (discussed earlier)
– Carrier design
– Pad conditioning method
– Platen & carrier speeds
– Retaining ring design (i.e. extent of pressure discontinuity between wafer
edge and retaining ring)
– Slurry injection scheme

• Removal rate: • Defect density:


– Carrier film, pad & slurry – Pad & slurry type
type (discussed earlier) – Use of secondary platen
– Downforce – Post-CMP cleaning
– Platen & carrier speeds method

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
19
Process Issues
• Planarity:
– Pad type
– Circuit density & structure size
– Extent of ILD removed
– Downforce, platen speed & carrier speeds

Pre
Polish

Post

Planarization Distance (PD)

– Step Height Ratio (SHR) = Post Step Height / Pre Step Height
– The goal is to minimize SHR and maximize PD thereby
minimizing Within-Die Non-Uniformity (WIDNU)
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
20
Effect of Structure Size & Density
on Post Step Height
8000 2000

Post Step Height (A)


Post Step Height (A)

6000 1500

4000 1000

2000 500

0 0
0 4 8 12 16 0 20 40 60 80 100
Structure Size (mm) Structure Density (%)

• SHR is greater on metal pads compared to isolated narrow lines


• Areas with lower circuit density polish faster than areas with dense underlying topography
• Each circuit design will have a different WIDNU due to variations in size and density of
interconnects
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
21
Effect of Downforce on Removal Rate &
Planarity
2500 1
Removal Rate (A/min)

0.8
2000
0.6

SHR
1500
0.4
1000
0.2

500 0
0 2 4 6 8 10 0 2 4 6 8 10
Downforce (psi) Downforce (psi)
• Increase in downforce (wafer pressure applied to the polishing pad) results in a linear
increase in removal rate (i.e. Preston’s Equation)
• Increase in downforce degrades planarity due to pad deformation and subsequent
increase in local pressure at the ‘valley’ regions (i.e. Hook’s Law)
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
22
Effect of Platen Speed on Removal Rate &
Planarity
3000 1
Removal Rate (A/min)

0.8
2500
0.6

SHR
2000
0.4
1500
0.2

1000 0
0 20 40 60 80 100 0 20 40 60 80 100
Platen Speed (RPM) Platen Speed (RPM)
• Increase in platen speed increases removal rate linearly (i.e. Preston’s Equation)
• Increase in platen speed improves planarity
• At higher speeds the pad contacts mainly the ‘hill’ regions since it does not have
sufficient time to conform to the ‘valley’ regions
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
23
Effect of Carrier Speed on
Wafer Center & Edge Removal Rates
3000
Removal Rate (A/min)
2500
Edge

2000
Center

1500

1000
0 20 40 60 80 100
Carrier Speed (RPM)
• Platen speed is maintained at 70 RPM
• Center-to-edge removal rate difference increases with increasing carrier speed
• Carrier diameter << platen diameter & at low carrier speeds, the linear velocity vector
created by the carrier is much smaller than that created by the platen
• As carrier speeds approach & exceed platen speed, the linear velocity vector created by the
carrier becomes significant
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
24
Effect of Pad Hardness on
Post Step Height and Planarization Distance
8000
Post Step Height (A)
Soft Pad
6000
Hard Pad
4000

2000

0
0 0.5 1 1.5 2 2.5 3 3.5 4
Horizontal Distance (mm)

• Harder pads deform less under pressure thus leading to:


- Lower SHR, higher PD, and improved WIDNU (i.e in mm range)
- Poorer WIWNU (i.e. in cm range)
• Harder pads also result in higher removal rates and higher defect densities
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
25
Effect of Pad Compressibility
on Electrical Integrity of ILD
Kaufman, Proceedings of Spring MRS, CA (1995)
E-Field at 50% Fails 11

10
(MV/cm)

6
As Deposited
Glass Bead / Polymer
Polymer
Stacked Polymer
Felt
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
26
Section D: CMP Consumables

Philipossian, Sanaulla, and Moinpour,


Semicon West Technical Session on CMP, CA (1998)

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
27
CMP Slurries and Pads
Areas of Concern

Manufacturability

Design
Supplier

Total Cost
Availability
EHS

Quality & Reliability


Legal

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
28
Quality Issues
Intel Corporation
All Chemicals

Delivery &
Intrinsic Warehousing
Material 15%
27%

Packaging
24%

Procedural
34%

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
29
Quality Issues
Intel Corporation
CMP Slurries
Delivery &
Warehousing
19%

Packaging
19%
Intrinsic
Material
43%

Procedural
19%
70% Abrasive Issues
20% Foreign Matter
10% Other
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
30
Quality Issues
Intel Corporation
CMP Pads
Delivery &
Warehousing
10%

Procedural
15%

Intrinsic
Material
75%
40% Texture
30% Foreign Matter
20% Adhesive
10% Other
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
31
Impact of Quality Issues
The Quality Indicator (QI)

QI = 100 - (2) [(a) + (2) (b) + (4) (c) + (8) (d) + (16) (e)]
e = No. of factory interrupts (i.e. issues resulting in tool or
factory downtime, or product loss)

d = No. of near misses (i.e. issues requiring extra


Intel resources to keep the factory running)
c = No. of repeat SCARs

b = No. of SCARs (i.e. issues caused by


gross supplier negligence)

a = No. of issues (i.e. all issues


regardless of impact to Intel)

SCAR: Supplier Corrective Action Request


Note: The Quality Indicator is measured on a quarterly basis for each supplier
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
32
Supplier Comparison
CMP Suppliers vs. Photoresist and Wet Chemical Suppliers
(Data Collected Since 1Q96)
100
Average Quality Indicator

80

60 Challenge

40

20

0
Pad & Slurry Photoresist Wet Chemical
Suppliers Suppliers Suppliers

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
33
Factors Influencing Productivity
Process Stability & Manufacturability
- RR
- WIWNU, WTWNU, WIDNU
- Defects
- Planarity
- Pad life
- Pad & slurry quality

Productivity

Equipment Labor
- Availability - EHS
- Reliability - Ergonomics
- Integrated Run Rate - Automation
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
34
Tool Integration and Automation
Integrated Run Rate
R2 Robot Limited
CMP#1

Robot Robot Cleaner


Wafers Wafers

R1 R1 R4

CMP#2
R3
Cleaner Limited
CMP#1
R2

Robot Robot Cleaner


Wafers CMP#2 Wafers

R1 R3 R1 R5

CMP#3
R4
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
35
Polishing Pad Life
Frequency of Changing Pads as a Function of Pad Life
• Changing pads in high-volume
manufacturing poses a serious
ergonomic issue:
– Frequency of change
– Difficulty of change 60

• A compromise must be reached 50

# of pad changes per week


between adhesive strength and 40

its effect on the polishing


30
process:
– Hardness 20

– Compressibility 10

– Corrosion resistance 0
0 2000 4000 6000 8000 10000 12000
– Use of chemicals to remove WSPW

adhesive residues
• Mechanical pad-pullers are
becoming a requirement in
factories
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
36
Polishing Pad Life
Effect of Pad Life on Tool Availability
• Availability (%) = 100 - Scheduled Downtime - Unscheduled Downtime
• Scheduled Downtime:
– Tool PM, facilities PM, monitors, tool qualification and consumables changeout
• Unscheduled Downtime:
– Out-of-control conditions, repairs

95
Tool Availability (%)

90

85

80
100 200 300 400 500 600
Pad Life
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
37
No. of Polishers vs. Tool Availability
Effect of Pad Change Duration
(Pad Life & Scheduled and Unscheduled Downtime are Fixed)

• 5000 WSPW
• 5 oxide polish steps
• Pad life of 500 (i.e. number
of wafers polished before 5 Layers
pad change)
120
• Pad change duration:
100
– Complexity of process
80
qualification on fresh

% Availability
0.5 hours
pad (i.e. pad break-in) 60 1 hour
2 hours
– Other consumable 40 4 hours
6 hours
changes (i.e. wafer 20

carrier & pad 0

conditioner) 0 5 10
# of Polishers
15 20 25

– Ergonomics of pad
change (i.e. pad size and
adhesive strength)
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
38
No. of Polishers vs. Tool Availability
Effect of Un-Scheduled Downtime
(Pad Life, Pad Change Duration and Scheduled Downtime are Fixed)

5 Layers

120

100

80
% Availability

60 1 hour
6 hours
40 12 hours

20

0
0 5 10 15 20 25
# of Polishers

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
39
Oxide Polisher Downtime Pareto Chart
C = Consumables
C+P P = Process
T = Tool

C+P+T
Normalized Time

C+P+T
C+P
Scheduled Qual

Unscheduled
Tool PM

Facilities PM
OOC

Other
Repair

Qual
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
40
Oxide Polisher Downtime Pareto Chart
average pad life
average POU filter life

variability in pad and slurry properties (PSD)

average filter life


Normalized Time

variability in slurry properties (PSD)


Scheduled Qual

Unscheduled
Tool PM

Facilities PM
OOC

Other
Repair

Qual
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
41
Effect of pH and Abrasive Content on ILD
Removal Rate
Scherber et al., Proceedings of the Symposium on Planarization Technology:
CMP, Semicon West (1994)
110
100
Removal Rate

90
80
70
60
50
9.5 10.5 11.5
pH

9% 12% 15%
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
42
Effect of Trace Metals on
ILD Polish Performance

Slurry [Al] [Ca] [Cr] [Fe] [Ni] Normalized


Defect Density

F < 0.2 < 0.2 0.7 1 < 0.2 1

G 99 1.2 3 18 3.2 3 to 11

- All units in ppm


- Slurries F & G are identical except for the metal content
- Comparable removal rate and uniformity
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
43
Effect of Hydrocarbons on
ILD Polish Performance

Slurry Normalized Normalized


Hydrocarbon Defect
Content Density

H 1 1

I 14 3 to 6

- Slurries H & I are identical except for the hydrocarbon


content
- Hydrocarbon contained a polar group
- Comparable removal rate and uniformity
- Majority of defects were ‘scratches’
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
44
Abrasive Geometry

Aggregate

Primary Particle

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
45
Effect of Abrasive Geometry
on ILD Polish Performance

Slurry Appx. Primary Appx. Mean Normalized Normalized


Particle Aggregate Mean WIWNU
Size Size Removal (3-sigma)
(nm) (nm) Rate

A 29 122 86 --
B 29 110 100 100
C 19 95 82 83
D 20 110 79 154
E 50 200 94 104

- Fumed silica abrasive


- Constant pH and abrasive content
- Comparable defect density and planarity
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
46
Effect of Abrasive Geometry
on ILD Removal Rate
110

100
Removal Rate

90

80

70
0.15 0.2 0.25 0.3
PPS / MAS (unitless)

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
47
Section E: Industry - University Gaps

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
48
Development of Core Competencies
(Industry - University Gaps)
Core Subject Funded Universities
Pad synthesis
Pad deformation studies SUNY, Saitama Univ, RPI,
Nagoya Inst of Tech
Brush synthesis
Adhesive development
Abrasive powder synthesis
Abrasive powder and slurry morphology, PSD, Univ of Minnesota, Univ of
geometry and type Central Florida
Abrasive powder metrology
Slurry and pad fluid mechanics (empirical) Tufts, Georgia Inst of Tech
Slurry and pad fluid mechanics (modeling) Tufts
Slurry consumption reduction Tufts
Consumable - tool - process interactions Berkeley, MIT, Tufts, ASU
Electrochemistry Univ of NM, Sandia, RPI,
Univ of Arizona
Slurry dispersion and mixing
Slurry filtration IMEC
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
49
Development of Core Competencies
(Industry - University Gaps)

Core Subject Funded Universities


Reaction kinetics RPI, Sandia, Clarkson,
Univ of NM
CMP process development & modeling IMEC, MIT, Tohoku Univ,
Stevens Institute
Slurry, pad and brush shelf-life studies
Additives to enhance or retard removal rates Clarkson, RPI, Tohoku
Univ
Additives to modulate removal rate selectivity RPI, Clarkson
Dispersion and colloidal stability Clarkson, Univ of Arizona
Anti-caking agent development
Slurry reclaim and re-use Univ of Arizona
Dissolution, passivation, adhesion and roughening Univ of Florida, Clarkson
Surfactants Univ of Arizona, Clarkson
Pad and slurry interactions SUNY
Enhanced Pourbaix diagrams
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
50
Section F: EHS Hierarchy and Considerations

Philipossian, Moinpour and Poliak,


Proceedings of VMIC, Santa Clara, CA (1998)

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
51
EHS Hierarchy & Issues
Replace > Reduce > Re-use > Recycle > Abate

• Environmental regulations are growing at an amazing rate:


– Federal and local initiatives & regulations
– International initiatives
• Recycling regulations are extremely complex and require detailed
understanding and follow-through
• Many new materials are not designed with EHS in mind. In many
cases, suppliers do not even know the potential EHS impact of these
materials
• To find out late in the process that a material has a serious EHS
impact can delay technology introduction or increase cost
• Most chemical suppliers have committed to ownership from cradle-
to-grave, but follow-through is poor
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
52
Growth of US Environmental Legislation
(Cumulative No. of Environmental Laws)
160
CERFA EPA
OPA
Technology & Environment, PPA GCRA
140

Washington DC, National Academy CAAA


Press, p. 101 (1989)
120

GCPA SPA
EPCRA WQA
HSWA SARA
100

APA NWPA
UORA CERCLA
SWDAA
EAWA
80

NCPA
CWA
RCRA SWDA
TSCA
60

HMTA
CZMA SDWA
ODA
EQIA
CAA
40

MVAPCA NPAA NEPA


AQA
FWPCA NESA
FMLA WRA WA
20

IA WL FWCA FIFRA WA
RHAA PHSA
RA FCA TGA RHA
1890 1900 1910 1920 1930 1940 1950 1960 1970 1980 1990 2000
0

Year
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
53
EHS in CMP
(Level - I Considerations)

chemical inputs
energy outputs

EHS energy inputs


ergonomics

chemical outputs

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
54
EHS in CMP
(Level - II Considerations)

chemical blending & delivery system


publicly owned treatment works
post-polish tool
slurry type
energy outputs pad type
film type
post-polish consumable
chemical inputs
IC type
energy inputs
IC density EHS
ergonomics UPW system

wafer size chemical outputs process recipe

wafer starts per week


polish tool
fab location
in-fab discharge treatment method

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
55
EHS in CMP
(Level - III Considerations)
film type chemical outputs
pH
IC type chemical inputs
abrasive type
abrasive size IC density energy outputs
abrasive shape slurry type energy inputs
abr. morphology pad type ergonomics
solids content UPW system
oxidizer type chemical blending & delivery system
additive type wafer size
buffer type polish tool
base type
post-polish tool
acid type
post-polish consumable
zeta potential
ionic strength process recipe
viscosity wafer starts per week
color fab location
shelf life in-fab discharge treatment method
pot life publicly owned treatment works
dispersability
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
56
EHS in CMP
(Level - III Considerations)
film type chemical outputs
size
IC type chemical inputs
material
stack IC density energy outputs
thickness slurry type energy inputs
texture pad type ergonomics
morphology UPW system
hardness chemical blending & delivery system
specific gravity wafer size
compressibility polish tool
hole pattern
post-polish tool
groove pattern
post-polish consumable
adhesive strength
life process recipe
shelf life wafer starts per week
fab location
in-fab discharge treatment method
publicly owned treatment works

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
57
EHS in CMP
automation (Level - III Considerations)
film type
footprint
conditioner IC type
endpoint detection IC density
water inj. scheme slurry type
slurry inj. scheme pad type
effluent segregation UPW system
POU filtration chemical blending & delivery system
flow dynamics post-polish tool
re-use compatibility chemical
chemical outputs
inputs
polish tool
carrier design energy outputs
wafer size
platen design energy inputs
ring design post-polish consumable
process recipe ergonomics
number of platens
rotation scheme wafer starts per week
vent design fab location
parts clean req. in-fab discharge treatment method
PPE req. publicly owned treatment works
ease of maint.
run rate
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
58
EHS in CMP
(Level - III Considerations)
film type
IC type
IC density
water flow rate slurry type
slurry flow rate pad type
chemical flow rate UPW system
dilution chemical blending & delivery system
flow overlap wafer size
automation polish tool
carrier speed chemical outputs
post-polish consumable
platen speed chemical inputs
post-polish tool
down-force energy outputs
back-pressure process recipe
energy inputs
number of platens fab location
ergonomics
conditioning recipe wafer starts per week
in-fab discharge treatment method
publicly owned treatment works

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
59
Section G: CMP Fluid Dynamics

Coppeta, Roger, Racz, Kaufman & Philipossian, Pad effects on slurry transport
beneath a wafer during polishing,
CMP-MIC, Santa Clara (1998)

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
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Fluid Dynamics
• Goal:
– Reduce slurry dispense volume
– Increase slurry utilization efficiency
– Entrain a uniform layer of new slurry beneath the wafer
– Prevent polished material from being re-entrained beneath the
wafer
• Key issues which need to be comprehended:
– Chemical & mechanical factors which influence polishing
– Slurry film thickness between wafer and the pad
– Slurry transport mechanism, and factors that influence slurry
transport
• Slurry injection scheme
• Slurry flow rate
• Pad type, conditioning and topography
• Platen and carrier speed
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61
Dual-Emission Laser-Induced Fluorescence

Camera Laser

Glass Wafer

Polish Platen

Slurry with Fluorescence dye Slurry


Pad

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NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
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http:\\www.tuftl.tufts.edu

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NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
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Slurry Transport

Wafer

Examining:
- Mean slurry age
Post - Residence time
- Slurry Gradients

(flat pads)
- Drag on wafer
- Fluid thickness
Interrogation
measurements
Region

Pad

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NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
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Slurry Flow Rate
Percent New Slurry

Manufacturer: Rodel
Grooved Pad Slurry Flow Rate: x cc/min
Wafer Down Force: 4 psi
Platen Speed: 60 rpm
X-Y Groove Depth: 20 mils

Flat Pad

Time (sec)

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
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Platen Speed

Grooved Pad Manufacturer: Freudenberg


Percent New Slurry

Slurry Flow Rate: 35 cc/min


Wafer Down Force: 4 psi
Platen Speed: x rpm
X-Y Groove Depth: 20 mils

Flat Pad

Time (sec)
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NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
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Static Case
Pad deformation: (4 psi, 0 rpm)

Image of a single pad Thickness profile as determined


by ratiometric technique
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
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Section H: Slurry Reuse

Kodama, A reclaim use of CMP slurry, 29th Symposium on ULSI Ultra Clean
Technology, Tokyo, Japan (1996)

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NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
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Slurry Re-Use
Experimental Setup

Secondary Platen Primary Platen

Pump & Filter

Slurry Capture Tub

Spent Slurry Reservoir

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NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
69
RR & WIWNU vs. Slurry Reclaim
2000 fumed 50 / 200 nm 10
colloidal 102 / 212 nm
9

1750 8
Removal Rate (A/min)

WIWNU (% 1-sigma)
7

1500 6

1250 4

1000 2

750 0
1 2 3 4 5 6 1 2 3 4 5 6
No. of Reclaims No. of Reclaims Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
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Surface Roughness & pH vs. Slurry Reclaim
0.4 fumed 50 / 200 nm 11.5
11.4
0.35 colloidal 102 / 212 nm 11.3
11.2
0.3 11.1
11
0.25
10.9
Ra (nm)

10.8

pH
0.2
10.7
10.6
0.15
10.5
0.1 10.4
10.3
0.05 10.2
10.1
0 10
1 6 1 6
No. of Reclaims No. of Reclaims Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
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Mean Aggregate Size vs. Slurry Reclaim
220 fumed 50 / 200 nm
colloidal 102 / 212 nm
215
Mean Aggregate Size (nm)
210

205

200

195

190

185

180
1 6
No. of Reclaims Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
72
Section I: Post-CMP Cleaning

Moinpour & Burke, Keynote Address, CMP-MIC, Santa Clara (1998)

Jankovsky, 3rd CMP Workshop, Lake Placid, NY (1998)

Busnaina, 3rd CMP Workshop, Lake Placid, NY (1998)

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NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
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Post-CMP Clean
• Requirements:
• Defects & Contamination:
– Quick and repeatable
– Abrasive particle residues
(i.e. silica, alumina or ceria) – Cause do damage to devices
or films (i.e. change
– Chemicals on surface (i.e.
roughness or planarity)
surfactants, or slurry
additives) – No residue or redeposition
– Alkali metal contaminants – Low cost of ownership
(i.e. K or Na) (COO)
– Heavy metals (i.e. Fe) • Environment:
– Pad residues – Mechanical scrubbing (with
& without chemistry or
– Pad conditioner (i.e.
megasonics)
diamond) residues
– Wet cleaning (with and
without megasonics)
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
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Post-CMP Clean
(Defect Reduction Strategies)

• Step - I … Reduce defects


during the CMP process:
– Use slurry additives
• Step - II … Reduce defects Application Process Chemical
further by performing an
Oxide NH4OH & HF
additional buffing process: W NH4OH & HF
– Use chemicals on the STI NH4OH
secondary platen polysilicon APM & HCl
Copper Proprietary
• Step - III … Reduce defects Chemicals
even further during the post-
CMP cleaning process:
– Use chemicals in the post-
CMP cleaning tool

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NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
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Post-CMP Clean
(A Sampling of Chemicals or Methods
Cited in the Literature)
18

15

12

0
NH4OH

KOH

NH4F
HCl
HF

H2O2
APM
DI Water

Hot DI Water
TMAH

Ice
Citric Acid

Surfactant
Megasonics

Proprietery
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NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
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Post-CMP Clean
(Process Improvement)

• 0.35 um, 200mm technology


• Effect of post ILD CMP clean 1

chemistry on end-of-line yield


0.8

Cumulative Probability
• Process 1 and Process 2 are
0.6
identical polish processes
• Process 2 uses a different 0.4

Post-CMP Clean chemistry 0.2

• Improved consumable lifetime 0

Yield Impact
• No impact on overall run rate

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
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Cleaning Theory
• Particles in liquids:
– Primary cause of adhesion is van der Walls forces (DLVO
Theory)
– Secondary cause of adhesion is Electric Double Layer (EDL)
forces (however, they are usually repulsive and can help in
particle removal)
• Particles in solution become charged
• Stern Layer + Diffuse Layer = EDL
• Potential at shear plane = Zeta Potential
• EDL thickness varies as inverse square root of the ionic strength
(i.e. 4X increase in ionic strength will reduce EDL thickness by
2X)
• EDL and the Zeta Potential are a function of pH

Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
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Cleaning Theory

• ELECTRIC DOUBLE LAYER

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NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
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Cleaning Theory

• DLVO THEORY

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NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
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Post-CMP Cleaning

Al2O3 Pure

6
M obility (m 2/V /S)

0 Mobility
-2
-4

-6
2 4 6 8 10 12

pH

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NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
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Brush Cleaning
• Advantages:
• Disadvantages:
– Most common cleaning – Contact with wafers may be
methodology harmful
– Double-side and edge – Brush loading with particle
cleaning capability and re-deposition
– High energy scrub capability – Low throughput
– The contact mechanism can – High COO (chemicals, DI
help clean wafers with water, consumables parts)
topography – Static build-up which may
increase particle adhesion
– Simple integration with dry- forces
in-dry-out processing
– Tough for brushes to contact
– Compatible with wet high aspect ratio topography
chemistry – Brush shedding
– Compatible with the recent – Brush break-in required
advances in ‘smart-brushes’
(zeta-potential engineering)
Philipossian
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
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Wet Chemical Cleaning
• Advantages: • Disadvantages:
– More chemically intensive compared – Particle saturation in the
to brush cleaning recirculating tank
– Residues and foreign matter can be – Difficult to integrate
readily dissolved and removed from with dry-in-dry-out
the surface processing
– Ability to manipulate zeta potential to – Cleaning process must
be tailored to each
remove particles
device layer and
– Low COO material
– High throughput – Uncontrolled cavitation
– Controlled cavitation (formation of gas may cause wafer surface
bubbles by ultrasound) and acoustic damage
streaming (steady flow induced by
sound field) can be used to detach and
remove particles from the surface
– Formation of acoustic boundary layer
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NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
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