Implementation of Inter-Integrated Circuit(I2C) Multiple Bus Controller for interfacing with

Avalon Memory Mapped Interface on FPGA Using VHDL.

Mrs. Jaya Malviya Mr. Arif Mohammad

M Tech (VLSI Design) Dept. of Electronics and Communications
Gyan Ganga Institute of Technology and Sciences Gyan Ganga Institute of Technology and Sciences
Jabalpur,Madhya Pradesh Jabalpur,Madhya Pradesh
E-mail E-mail

Abstract— The Inter - Integrated Circuit bus respectively, is called the Master device in the bus.
commonly called as I2C (I squared C) or I2C bus is Master is the device which will be generating the
a serial bus invented by Philips Semiconductors clock also.
during early 80’s for interconnecting integrated
circuits. In this paper, the design and 2. Literature Survey
implementation of a I2C Multiple Bus Controller
(IICMB) core is presented. 1) Prototyping of Dual Master I2C Bus
Controller, Anagha A , M. Mathurakani,
Keywords—I2CMB, I2C Protocol, Avalon Memory mapped International Conference on Communication
Interfaces, I2C Communication (key words) and Signal Processing, April 6-8, 2016, India.
In this project work, the multi-master facility of
I. INTRODUCTION I2C protocol is implemented successfully. Address
resolution is the major concern while using
I2C bus was developed by Philips Semiconductors
multiple masters in I2C bus. Arbitration procedure
during 1980’s for connecting computer peripherals
must be perfect for the bus to work properly when
together using a common protocol. It is a widely
dual masters are present. A dual master I2C bus
accepted serial communication protocol having only
controller system with an EEPROM 24CXX series
two wires called serial data line and serial clock
as the slave devices has been developed for
line. I2C bus is used as a de facto standard for
realizing both the read and write cycles of the I2C
connecting low speed devices like microcontrollers,
bus and tested. The design has got successfully
EEPROM’s,ADC,DAC etc. It will be having
implemented in Spartan 3A FPGA and the outputs
different speeds particularly, a normal mode of 100
are verified. Also DS1307 RTC is connected as the
kbps, fast mode of 400 kbps and a high speed mode
slave device and performed the WRITE and READ
of 3.4 mbps.
operations following I2C protocol. This design can
be used in systems where multiple devices needs to
In this project work, a I2C Master bus controller
be interconnected by ensuring with low complexity
with are designed and implemented which can be
and efficient resource utilization.
interface with the Avalon Memory mapped
Interface efficiently. A special kind of START and
2) I2C Hardware Master Serial Interface for
STOP conditions are available in I2C. START
Asynchronous ADCs. Wojciech
condition is happened when SDA will be having a
Andrysiewicz, Dariusz Ko´scielnik, Marek
transition from HIGH to LOW keeping the SCL line
Mi´skowicz AGH University of Science and
HIGH. Similarly, STOP condition is happened
Technology. 2015 IEEE.
when SDA will be having a LOW to HIGH
The implementation of the I2C-compatible serial
transition by keeping the SCL line HIGH [1].The
interface for asynchronous ADCs that output data
device which can initiate and terminate a transfer by
irregularly in time is reported in the paper. The
sending the START condition and STOP condition
 device contains I2C hardware master-transmitter
functionality and is capable of operating fully
autonomously in I2C bus communication system.
In particular, the asynchronous ADC with
proposed I2C interface is able to initiate data
transfer on the bus when new data are available on
the converter output.
The CMOS implementation of the I2C-compatible
interface for asynchronous ADCs is presented in the
present paper. The device contains I2C hardware
master-transmitter functionality and is capable of
operating fully autonomously in I2C bus
communication system. Future work can address
the design improvements related to further
reduction of power consumption: FIFO clocking
when idle at the price of slightly more complex shift
logic, and a mechanism stopping the clock
generator when device is idle.
3) Implementation of I2C Master Bus
Controller on FPGA, Bollam Eswari,
N.Ponmagal, K.Preethi, S.G.Sreejeesh,
International conference on Communication
and Signal Processing, April 3-5, 2013,
India.
This paper implements serial data communication
using I2C (Inter-Integrated Circuit) master bus
controller using a field programmable gate array
(FPGA). This project demonstrates how I2C Master
Controller (Master) transmits and receives data to
and from the DS 1307 (Slave). So that any low
speed peripheral devices can be interfaced using
I2C bus protocol as master. In future, this can be
implemented as real time clock in networks that
contains multiple masters and multiple slaves to co-
ordinate the entire system by clock synchronization
techniques.
4) Interfacing of digital TPH sensors with
FPGA using I2C interface. Muhammed
Raees PC, Anand Lokapure, Saraf Mandar
N, B.Satyanarayana. 2016 IEEE Bombay
Section Symposium.
This work involves design and prototype
implementation of an I2C interface for interfacing
digital TPH sensors to an FPGA. This work was
carried out as part of up gradation of the digital
data acquisition module used for the India-Based
Neutrino Observatory (INO) detectors.
BMP280 digital temperature and pressure sensor is
successfully interfaced with Arrow’s BeMicroCV
FPGA Board (Altera Cyclone VE) using I2C
protocol in this prototype. The sensors and interface
are now finalized as a result of this prototypic study.
The upgraded DFE module will be featuring
BME280 digital TPH sensor interfaced via I2C
protocol. The advantage of BME280 sensor is its
ability to measure temperature, pressure and relative
humidity together. So instead of using three
different sensors for TPH, we can use a single
sensor and that will save a considerable space in the
PCB. Since it is a digital sensor, we can also
eliminate the need for an ADC chip in the future
version of the module.
Proposed Work
In our Design the specification defines the
architecture, hardware interface and
parameterization options for the I2C Multiple Bus
Controller (IICMB) core.
Avalon-MM Interface
The Inter - Integrated Circuit Multiple Bus
Controller (IICMB) core provides a low-speed, two-
wire, bidirectional serial bus interfaces compliant to
industry standard I2C protocol. The key feature of
the Proposed work will be its ability to control
several connected I2C buses effectively reducing
complexity of system.
At any given moment the Inter - Integrated Circuit
Multiple Bus Controller (IICMB) will work with a
single I2C bus chosen from the range of connected
buses (throughout my thesis such bus is called from SRAM interfaces which support simple, fixed-
selected bus). When work with a particular selected cycle read and write transfers to more complex,
bus is finished, user can switch to another one to pipelined interfaces capable of burst transfers.
continue configuring other peripherals. Every
connecting I2C bus will recognize by its number, or
bus ID.
Some of the basic features on which we are working
to implement in our design will be as follows,

 Implementation of IICMB core which provides

low-speed, two-wire, bidirectional serial bus
interfaces compliant to industry standard I2C
protocol.
 “Manchester encoded UART” which enables
running small peripherals with parasitic power
derived from the TXD line, and allowing large
clock differences typical of RC oscillators.
 The key feature of the core is its ability to
effectively reducing complexity of the system
and control several connected I2C buses.
Example Slave Component
Each signal in an Avalon-MM slave corresponds to
exactly one Avalon-MM signal role. An Avalon-
MM port can use only one instance of each signal
role.
3.0 Interfaces with our design

Keeping in mind all the above specifications the key

features of our design are Signal Name I/O Description
clk Input Avalon-MM clock. Main clock for
the controller.
 Works with up to 16 distinct I2C buses s_rst Input Synchronous reset. Active high.
 Statically configurable system bus clock waitrequest Output Wait request.
frequency readdata[31:0] Output Data output.
 Statically configurable desired clock frequencies readdatavalid Output Data validity indication.
of I2C buses writedata[31:0] Input Data input.
 Multi-master clock synchronization write Input Indicates a write transfer.
 Multi-master arbitration read Input Indicates a read transfer.
 Clock stretching byteenable[3:0] Input Enables specific byte lane(s) during
transfer
 Digital filtering of SCL and SDA inputs
Avalon-MM version of the core top level has the
 Standard (up to 100 kHz) and Fast (up to 400
following signals:
kHz) mode operation
Table 1: Avalon-MM interface Signals
 Example connection as 32-bit slave on Avalon-
MM bus
There is no address signal in this group. This is
because we have only 4 bytes of registers and all of
Avalon Memory-Mapped Interfaces
them can be accessed in one single read or write.
The frequency of clk clock (in kHz) should be
Avalon Memory-Mapped (Avalon-MM) interfaces
indicated in g_f_clk parameter. For more
are used for read and write interfaces on master and
information about Avalon-MM signals please refer
slave components in a memory-mapped system.
to Avalon Interface Specifications.
These components include microprocessors,
memories, UARTs, DMAs, and timers which have
master and slave interfaces connected by an
interconnect fabric. Avalon-MM interfaces can
describe a wide variety of component interfaces,
 Hierarchy Of Modules
Hierarchy of modules with Avalon-MM top level:
 iicmb_pkg.vhd
 iicmb_int_pkg.vhd
 iicmb_m_av.vhd
o avalon_mm.vhd
o regblock.vhd
o iicmb_m.vhd
 mbyte.vhd
 mbit.vhd
 conditioner_mux.vhd
 conditioner.vhd
o filter.vhd
o bus_state.vhd
Top Level Entity for Avalon Interface Implementation Results
Device Utilization Summary
Utiliz-
Slice Logic Utilization
Used Available ation
Number of Slice Registers 182 12,480 1%
Number used as Flip Flops 182
Number of Slice LUTs 318 12,480 2%
Number used as logic 307 12,480 2%
Number using O6 output only 280
Number using O5 output only 7
Number using O5 and O6 20
Number used as exclusive route-thru 11
Number of route-thrus 18
Number using O6 output only 17
Number using O5 and O6 1
Number of occupied Slices 147 3,120 4%
Number of LUT Flip Flop pairs used 375
Number with an unused Flip Flop 193 375 51%
Number with an unused LUT 57 375 15%
Number of fully used LUT-FF pairs 125 375 33%
Number of unique control sets 15
Number of slice register sites lost 22 12,480 1%
to control set restrictions
Number of bonded IOBs 59 172 34%
IOB Flip Flops 1
Number of BUFG/BUFGCTRLs 1 32 3%
Number used as BUFGs 1
Internal Structure for Avalon Interfaces with our Average Fanout of Non-Clock Nets 4.36
design of I2CMB
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Avalon-MM interface. So that any low speed FPGA using I2C interface. Muhammed Raees
peripheral devices can be interfaced using I2C bus PC, Anand Lokapure, Saraf Mandar N,
protocol as master. In future, this can be B.Satyanarayana. 2016 IEEE Bombay Section
implemented as real time clock in networks that Symposium.
contains multiple masters and multiple slaves to co- [12] BMP280 Digital Pressure Sensor Data sheet,
ordinate the entire system by clock synchronization Bosch Sensortec, October 15th, 2015.
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Semiconductor, March 2003.
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Conference on Communication and Signal
Processing, April 6-8, 2016, India.
[7] Implementation of I2C Master Bus Controller
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K.Preethi, S.G.Sreejeesh, International
conference on Communication and Signal
Processing, April 3-5, 2013, India
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