Conventional and Improved 4-bit Ripple Carry

Adder Comparison

Bienvenido Jr., Lasaca

Department of Electrical Engineering andTechnology (DEET)
Mindanao State University – Iligan Institute of Technology
Iligan City, Philippines
bienvenidaojr.lasaca@g.msuiit.edu.ph

Abstract— A conventional 4-bit ripple carry adder 1 and 2, respectively. The basic architectures of the 4-bit
(RCA) is presented and compared to an improved RCA design is shown in Figure 3.
counterpart design performing a 4-bit addition. The
RCAs designs are implemented in a 65nm CMOS process.
This work evaluates the performance of the proposed
ripple carry adders in terms of speed and power
consumption. Moreover, the area and transistor count are
considered also. Simulation results show that the
proposed RCA design has no significant improvement in
terms of propagation delay, and lags behind significantly
in terms of power consumption. However, the number of
transistor and area of the improved design significantly
improves compared the conventional design.

I. INTRODUCTION
Adders are widely used in digital integrated circuits.
High-speed adder is the necessary component in a data path
e.g. Microprocessors and a Digital signal processor. For
Fig. 1. Gate-level circuit of a 1-bit Full Adder.
adding two binary numbers, there are several adder structures
based on different design ideas. There are many binary adder
architecture ideas to be implemented in such applications.
The easiest type of parallel adder to build is a ripple carry
adder, which uses a chain of one-bit full adder to generate its
output. The Ripple Carry Adder (RCA) gives the most
compact design but takes longer computation time. In this
paper, the propagation delay, power consumption and
transistor count in each design are compared [1].
II. RIPPLE CARRY ADDERS
The simplest way to implement the full-adder circuit is to
take the logic equation and translate them directly into circuit.
The typical full-adder function can be described as follows.
Sum = A ⊕ B⊕ Cin (1)
Fig. 2. Transistor-level diagram of a conventional 1-bit Full Adder.
Cout = A (A⊕ B) + Cin(A⊕ B) (2)
The designs of the conventional and improved RCA are
discussed below.
A. RCA using Conventional 1-bit Full Adder
Ripple Carry Adder is a basic adder that works on basic
addition principle. RCA contains series structure of Full
Adders (FA); each FA is used to add two bits along with carry Fig. 3. Structure of the 4-bit Ripple Carry Adder
bit. The carry generated from each full adder is given to next
full adder and so on [2]. Hence, the carry is propagated in a B. RCA using Improved 1-bit Full Adder [3]
serial computation. Hence, delay is more as the number of The improved 4-bit RCA utilizes a 10-transistor (10-T)
bits is increased in RCA. The gate-level and transistor-level full adder circuit. The 10-T full adder consists of 4 modules
circuit of the full adder used for the RCA is shown in Figure viz., a 3-T XOR gate, a 3-T XNOR gate, and two 2-T
multiplexer as shown in figure 5. The basic architecture of
the 4-bit RCA is shown in figure 4. The cascaded structure of
the 10-T full adders to form a 4-bit ripple carry adder is
shown in Figure 6.

Fig. 7. 4-bit Adder Input-Output combination patterns

Table 1. Area and Transistor Count Comparison of the 1-bit FAs

Transistor
1-bit FA Area, L*W (μm2)
Count
Fig. 4. Gate-level structure of the 10-T Full Adder
Conventional RCA 12.38*9.16 = 113.40 28
Improved RCA 7.9*7.9 = 62.41 18

Table 2. Area and Transistor Count Comparison of the RCAs

Transistor
RCA Area, L*W (μm2)
Count
Conventional RCA 24.98*18.35 = 458.38 112
Improved RCA 15.83*16.08 = 254.55 72

(a) (b) (c)

Fig. 5. (a) 3-T XOR. (b) 3-T XNOR. (c) 2-T Mux.

Fig. 6. 10-T FA based 4-bit RCA

III. RESULTS AND DISCUSSION

A. Simulation Environment
All the simulations have been done using Synopsys – Fig. 8. Conventional 1-bit Full Adder Layout
Custom Compiler. The calculation of power consumption
and propagation delay are carried out using the Standard
Analysis Environment (SAE) already integrated into Custom
Compiler. All the schematics and layouts are done using the
CMOS 65-nm technology process with a 1.2V supply
voltage. The designed RCAs are analyzed in terms of
propagation delay, average power consumption and area. To
establish an impartial testing environment, the simulations
have been carried out using a comprehensive input signal
pattern in Figure 7, which covers all 196 possible transitions
for a 4-bit adder circuit.
B. Simulation Results
The designed 4-bit adders have also been analyzed in
terms of area with the existing adders. The layouts of the
proposed adders have been shown in Fig.8-9 and the area
comparisons have been done in Table 1-2

Fig. 9. Conventional 4-bit Ripple Carry Adder Layout

 Power Consumption (W)
8.00E-05
6.00E-05
4.00E-05
2.00E-05
0.00E+00
Conventional Improved

Pre-Sim Post-Sim

Fig. 12. Power consumption of the different 1-bit FAs

Power Consumption (W)

1.50E-04

1.00E-04
Fig. 10. Improved 1-bit Full Adder Layout
5.00E-05

0.00E+00
RCA Conventional RCA Improved

Pre-Sim Post-Sim

Fig. 13. Power consumption of the different RCAs

The propagation delays for the adders are plotted in Fig. 14.

Propagation Delay (s)

6.00E-10

4.00E-10

2.00E-10

0.00E+00
Conventional Improved

Pre-Sim Post-Sim
Fig. 11. Improved 4-bit Ripple Carry Adder Layout
Fig. 14. Propagation delay of the different RCAs
In our experiment, frequencies have been chosen in the 1
MHz frequency. The power dissipated at this frequency by
the RCAs is plotted in Fig. 10. Propagation Delay (s)
C. Results Discussion 2.00E-09
1.50E-09
From the tabular comparisons, it is evident that the
1.00E-09
proposed RCA is inefficient in terms of power consumption
and does not show a significant improvement in terms of 5.00E-10
propagation delay. However, the design shows a promising
0.00E+00
improvement in terms of transistor count by 56%. RCA Conventional RCA Improved
Consequently, the area covered by the design is reduced also
by 80%. This analysis is summarized in Table 3-4. Pre-Sim Post-Sim

Fig. 15. Propagation delay of the different RCAs

 Table 3. Comparison summary of the FAs

Adder Power Delay Area, L*W Transistor

(μm2 ) Count
FA Conventional 1 1 1.82 1.56
FA Improved 11.9 1.34 1 1

Table 4. Comparison Summary of the RCAs

Adder Power Delay Area, L*W Transistor

(μm2 ) Count
RCA Conventional 1 1 1.80 1.56
RCA Improved 16.92 1.01 1 1

IV. CONCLUSION
In this paper, an improved 4-bit ripple carry adder cell has
been proposed. The power dissipation, delay, power-delay
product and area of the proposed adders have been compared
with the conventional ripple carry adder and is found to be
inefficient in terms of power consumption and delay
propagation. However, the area covered and transistor count
shows a significant improvement.

REFERENCES
[1] V. Gotmari and P. Agrawal, “Comparison of 32-bit Ripple Carry Adder
and Carry Look-ahead Adder in VDHL,” IJPRET, vol. 4, pp. 553–558,
January 2016.
[2] M. Saikumar and P. Samundiswary, “Deisgn and Performance
Analysis of Various Adders using Verilog” IJCSMC, vol. 2, pp. 128–
138, September 2013.
[3] S. Veeramachaneni and M. Srinivas, “New Improved 1-Bit Full Adder
Cells”, CVEST Canadian Conference on Electrical and Electronics
Engineering, 2008.