Ec6601 Notes Rejinpaul Ii PDF

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VLSI DESIGN(EC 2354)
Ms.K.Sangeethalakshmi
Assistant Professor
Department of ECE
sangeetha.lk@rmkcet.ac.in
CMOS VLSI Design 4th Ed.
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UNIT I - CMOS TECHNOLOGY
UNIT II - CIRCUIT CHARACTERIZATION AND SIMULATION
UNIT III - COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN
UNIT IV - CMOS TESTING
UNIT V - SPECIFICATION USING VERILOG HDL
TEXTBOOKS:
1. Weste and Harris: CMOS VLSI DESIGN (Third edition) Pearson
Education, 2005
2. Uyemura J.P: Introduction to VLSI circuits and systems, Wiley
2002.

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UNIT I CMOS TECHNOLOGY
 Syllabus
 A brief History
 MOS transistor
 Ideal I-V characteristics,
 C-V characteristics
 Non ideal IV effects
 DC transfer characteristics
 CMOS technologies
 Layout design Rules
 CMOS process enhancements,
 Technology related CAD issues, Manufacturing issues. 3

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CURRENT VS. VOUT, VIN
Vin0 Vin5
Vin1 Vin4
Idsn, |Idsp|
Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout
5: DC and Transient Response CMOS VLSI Design 4th Ed. 4

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LOAD LINE ANALYSIS

 For a given Vin:
 Plot Idsn, Idsp vs. Vout
 Vout must be where |currents| are equal in
Vin0 Vin5
Vin1 Vin4
Idsn, |Idsp|
VDD
Vin2 Vin3
Idsp
Vin3 Vin2 Vin Vout
Vin4 Vin1 Idsn
VDD
Vout

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LOAD LINE ANALYSIS


 VV
in in==00.2V
0V
0.4V
0.6V
0.8V
DD DD
DD
Vin0 Vin5
in5
Vin1 Vin4
dsn, |Idsp
Idsn dsp
|
Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
in0
VDD
Vout
out
DD

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DC TRANSFER CURVE
 Transcribe points onto Vin vs. Vout plot
Vin0 Vin1
VDD Vin2
Vin0 Vin5
A B
Vout
Vin1 Vin4
C
Vin2 Vin3
Vin3
Vin3 Vin2 D Vin4 Vin5
Vin4 Vin1 E
0 Vtn VDD/2 VDD+Vtp
VDD VDD
Vout Vin

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OPERATING REGIONS
 Revisit transistor operating regions VDD
Vin Vout
Region nMOS pMOS

A Cutoff Linear
VDD
B Saturation Linear A B
C Saturation Saturation Vout

C
D Linear Saturation
E Linear Cutoff
D
E
0 Vtn VDD/2 VDD+Vtp
VDD
Vin

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BETA RATIO
 If bp / bn  1, switching point will move from
VDD/2
 Called skewed gate
 Other gates: collapse

VDD into equivalent inverter
bp
 10
bn
Vout 2
1
0.5
bp
 0.1
bn
0
VDD
Vin

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NOISE MARGINS
 How much noise can a gate input see before it
does not recognize the input?
Output Characteristics Input Characteristics

VDD
Logical High
Output Range VOH Logical High
Input Range
NMH
VIH
Indeterminate
VIL Region
NML
Logical Low
Logical Low VOL Input Range
Output Range
GND

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LOGIC LEVELS
 To maximize noise margins, select logic levels at
 unity gain point of DC transfer characteristic
Vout
Unity Gain Points

VDD
Slope = -1
VOH
b p/b n > 1
Vin Vout
VOL
Vin
0
Vtn VIL VIH VDD- VDD
|Vtp|

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INTRODUCTION
 Integrated circuits: many transistors on one chip.
 Very Large Scale Integration (VLSI): bucketloads!
0: Introduction
 Complementary Metal Oxide Semiconductor
 Fast, cheap, low power transistors
 Today: How to build your own simple CMOS chip
 CMOS transistors
 Building logic gates from transistors
 Transistor layout and fabrication
 Rest of the course: How to build a good CMOS
chip
12

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NMOS TRANSISTOR
 Four terminals: gate, source, drain, body
 Gate – oxide – body stack looks like a capacitor
0: Introduction
 Gate and body are conductors
 SiO2 (oxide) is a very good insulator
 Called metal – oxide – semiconductor (MOS)
capacitor
Source Gate Drain
 Even though gate is Polysilicon
no longer made of metal SiO2
n+ n+
Body
p bulk Si
13

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NMOS OPERATION
 Body is usually tied to ground (0 V)
 When the gate is at a low voltage:
0: Introduction
 P-type body is at low voltage
 Source-body and drain-body diodes are OFF
 No current flows, transistor is OFF
Source Gate Drain

Polysilicon
SiO2
0
n+ n+
S D
p bulk Si
14

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NMOS OPERATION CONT.

 When the gate is at a high voltage:
 Positive charge on gate of MOS capacitor
0: Introduction
 Negative charge attracted to body
 Inverts a channel under gate to n-type
 Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2
1
n+ n+
S D
p bulk Si
15

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PMOS TRANSISTOR
 Similar, but doping and voltages reversed
 Body tied to high voltage (VDD)
0: Introduction
 Gate low: transistor ON
 Gate high: transistor OFF
 Bubble indicates inverted behavior
Source Gate Drain

Polysilicon
SiO2
p+ p+
n bulk Si
16

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TERMINAL VOLTAGES
Vg
 Mode of operation depends on Vg, Vd, Vs
 Vgs = Vg – Vs
+ +
Vgs Vgd
 Vgd = Vg – Vd
- -
3: CMOS Transistor Theory

 Vds = Vd – Vs = Vgs - Vgd
Vs Vd
- +
Vds
 Source and drain are symmetric diffusion terminals
 By convention, source is terminal at lower voltage
 Hence Vds  0
 nMOS body is grounded. First assume source is 0 too.
 Three regions of operation
 Cutoff
 Linear
 Saturation 17

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NMOS CUTOFF
 No channel
 Ids ≈ 0

Vgs = 0 Vgd
+ g +
- -
s d
n+ n+
p-type body
b
18

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NMOS LINEAR
 Channel forms
 Current flows from d to s

Vgs > Vt
Vgd = Vgs
 e- from s to d + g +
- -
s d
 Ids
increases with Vds Vds = 0
n+ n+
 Similar to linear resistor p-type body
b
Vgs > Vt
Vgs > Vgd > Vt
+ g +
- - Ids
s d
n+ n+
0 < Vds < Vgs-Vt
p-type body
b
19

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NMOS SATURATION
 Channel pinches off
 Ids independent of Vds

 We say current saturates
 Similar to current source
Vgs > Vt
g Vgd < Vt
+ +
- -
s d Ids
n+ n+
Vds > Vgs-Vt
p-type body
b
20

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I-V CHARACTERISTICS
 In Linear region, Ids depends on
 How much charge is in the channel?

 How fast is the charge moving?
21

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CHANNEL CHARGE
 MOS structure looks like parallel plate capacitor
while operating in inversions
Gate – oxide – channel


 Qchannel = CV
Cox =
 C = Cg = eoxWL/tox = CoxWL
eox / tox
 V = Vgc – Vt = (Vgs – Vds/2) – Vt
polysilicon gate
gate Vg
W + +
tox source Vgs Cg Vgd drain
Vs - - Vd
n+
L
n+
SiO2 gate oxide channel
(good insulator, eox = 3.9) n+ - + n+
Vds
p-type body
p-type body 22

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NMOS I-V SUMMARY

 Shockley 1st order transistor models


 0 Vgs  Vt cutoff

  Vds V V  V
I ds   b Vgs  Vt   ds linear
 2 
ds dsat

 b
Vgs  Vt 
2
 Vds  Vdsat saturation
2
23

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CAPACITANCE
 Any two conductors separated by an insulator
have capacitance

 Gate to channel capacitor is very important
 Creates channel charge necessary for operation
 Source and drain have capacitance to body
 Across reverse-biased diodes
 Called diffusion capacitance because it is associated
with source/drain diffusion
24

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GATE CAPACITANCE
 Approximate channel as connected to source
 Cgs = eoxWL/tox = CoxWL = CpermicronW

 Cpermicron is typically about 2 fF/mm
polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, eox = 3.9e0)
p-type body
25

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DIFFUSION CAPACITANCE
 Csb, Cdb
 Undesirable, called parasitic capacitance

 Capacitance depends on area and perimeter
 Use small diffusion nodes
 Comparable to Cg
for contacted diff
 ½ Cg for uncontacted
 Varies with process
26

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CMOS FABRICATION
 CMOS transistors are fabricated on silicon wafer
 Lithography process similar to printing press
0: Introduction
 On each step, different materials are deposited or
etched
 Easiest to understand by viewing both top and
cross-section of wafer in a simplified
manufacturing process
27

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INVERTER CROSS-SECTION
 Typically use p-type substrate for nMOS
transistors
0: Introduction
 Requires n-wellAfor body of pMOS transistors
GND VDD
Y SiO2
n+ diffusion
p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1
nMOS transistor pMOS transistor
28

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WELL AND SUBSTRATE TAPS

 Substrate must be tied to GND and n-well to VDD
 Metal to lightly-doped semiconductor forms poor
0: Introduction
connection called Shottky Diode
 Use heavily doped well and substrate contacts /
taps A
GND VDD
Y
p+ n+ n+ p+ p+ n+
n well
p substrate
well
substrate tap
tap
29

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INVERTER MASK SET

 Transistors and wires are defined by masks
 Cross-section taken along dashed line
0: Introduction
A
GND VDD
nMOS transistor pMOS transistor

substrate tap well tap
30

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DETAILED MASK VIEWS

 Six masks n well
 n-well
0: Introduction
 Polysilicon
Polysilicon
 n+ diffusion
 p+ diffusion
n+ Diffusion
 Contact
 Metal p+ Diffusion
Contact
Metal
31

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FABRICATION
 Chips are built in huge factories called fabs
 Contain clean rooms as large as football fields
0: Introduction
Courtesy of International
Business Machines Corporation.
Unauthorized use not permitted.
32

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FABRICATION STEPS
 Start with blank wafer
 Build inverter from the bottom up
0: Introduction
 First step will be to form the n-well
 Cover wafer with protective layer of SiO2 (oxide)
 Remove layer where n-well should be built
 Implant or diffuse n dopants into exposed wafer
 Strip off SiO2
p substrate
33

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OXIDATION
 Grow SiO2 on top of Si wafer
 900 – 1200 C with H2O or O2 in oxidation furnace
0: Introduction
SiO2
p substrate
34

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PHOTORESIST
 Spin on photoresist
 Photoresist is a light-sensitive organic polymer
0: Introduction
 Softens where exposed to light
Photoresist
SiO2
p substrate
35

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LITHOGRAPHY
 Expose photoresist through n-well mask
 Strip off exposed photoresist
0: Introduction
Photoresist
SiO2
p substrate
36

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ETCH
 Etch oxide with hydrofluoric acid (HF)
 Seeps through skin and eats bone; nasty stuff!!!
0: Introduction
 Only attacks oxide where resist has been exposed
Photoresist
SiO2
p substrate
37

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STRIP PHOTORESIST
 Strip off remaining photoresist
 Use mixture of acids called piranah etch
Necessary so resist doesn’t melt in next step
0: Introduction

SiO2
p substrate
38

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N-WELL
 n-well is formed with diffusion or ion

implantation
0: Introduction
 Diffusion
 Place wafer in furnace with arsenic gas
 Heat until As atoms diffuse into exposed Si
 Ion Implanatation
 Blast wafer with beam of As ions
 Ions blocked by SiO2, only enter exposed Si
SiO2
n well
39

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STRIP OXIDE
 Strip off the remaining oxide using HF
 Back to bare wafer with n-well
0: Introduction
 Subsequent steps involve similar series of steps
n well
p substrate
40

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POLYSILICON
 Deposit very thin layer of gate oxide
 < 20 Å (6-7 atomic layers)
0: Introduction
 Chemical Vapor Deposition (CVD) of silicon layer
 Place wafer in furnace with Silane gas (SiH4)
 Forms many small crystals called polysilicon
 Heavily doped to be good conductor
Polysilicon
Thin gate oxide
n well
p substrate
41

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POLYSILICON PATTERNING
 Use same lithography process to pattern
polysilicon
0: Introduction
Polysilicon
Polysilicon
Thin gate oxide
n well
p substrate
42

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SELF-ALIGNED PROCESS
 Use oxide and masking to expose where n+
dopants should be diffused or implanted
0: Introduction
 N-diffusion forms nMOS source, drain, and n-
well contact
n well
p substrate
43

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N-DIFFUSION
 Pattern oxide and form n+ regions
 Self-aligned process where gate blocks diffusion
0: Introduction
 Polysilicon is better than metal for self-aligned
gates because it doesn’t melt during later
processing
n+ Diffusion
n well
p substrate
44

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N-DIFFUSION CONT.
 Historically dopants were diffused
 Usually ion implantation today
0: Introduction
 But regions are still called diffusion
n+ n+ n+
n well
p substrate
45

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N-DIFFUSION CONT.
 Strip off oxide to complete patterning step
0: Introduction
n+ n+ n+
n well
p substrate
46

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P-DIFFUSION
 Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact
0: Introduction
p+ Diffusion
p+ n+ n+ p+ p+ n+
n well
p substrate
47

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CONTACTS
 Now we need to wire together the devices
 Cover chip with thick field oxide
0: Introduction
 Etch oxide where contact cuts are needed
Contact
Thick field oxide

p+ n+ n+ p+ p+ n+
n well
p substrate
48

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METALIZATION
 Sputter on aluminum over whole wafer
 Pattern to remove excess metal, leaving wires
0: Introduction
Metal
Metal
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate
49

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LAYOUT
 Chips are specified with set of masks
 Minimum dimensions of masks determine
0: Introduction
transistor size (and hence speed, cost, and power)
 Feature size f = distance between source and
drain
 Set by minimum width of polysilicon
 Feature size improves 30% every 3 years or so
 Normalize for feature size when describing
design rules
 Express rules in terms of l = f/2
 E.g. l = 0.3 mm in 0.6 mm process 50

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SIMPLIFIED DESIGN RULES

 Conservative rules to get you started
0: Introduction
51

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INVERTER LAYOUT
 Transistor dimensions specified as Width /
Length
0: Introduction
 Minimum size is 4l / 2l, sometimes called 1 unit
 In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm long
52

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CURRENT VS. VOUT, VIN
Vin0 Vin5
Vin1 Vin4
Idsn, |Idsp|
Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

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DC TRANSFER CURVE
 Transcribe points onto Vin vs. Vout plot
Vin0 Vin1
VDD Vin2
Vin0 Vin5
A B
Vout
Vin1 Vin4
C
Vin2 Vin3
Vin3
Vin3 Vin2 D Vin4 Vin5
Vin4 Vin1 E
0 Vtn VDD/2 VDD+Vtp
VDD VDD
Vout Vin

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OPERATING REGIONS
 Revisit transistor operating regions VDD
Vin Vout
Region nMOS pMOS

A Cutoff Linear
VDD
B Saturation Linear A B
C Saturation Saturation Vout

C
D Linear Saturation
E Linear Cutoff
D
E
0 Vtn VDD/2 VDD+Vtp
VDD
Vin

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BETA RATIO
 If bp / bn  1, switching point will move from
VDD/2
 Called skewed gate
 Other gates: collapse

VDD into equivalent inverter
bp
 10
bn
Vout 2
1
0.5
bp
 0.1
bn
0
VDD
Vin

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NOISE MARGINS
 How much noise can a gate input see before it
does not recognize the input?
Output Characteristics Input Characteristics

VDD
Logical High
Output Range VOH Logical High
Input Range
NMH
VIH
Indeterminate
VIL Region
NML
Logical Low
Logical Low VOL Input Range
Output Range
GND

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LOGIC LEVELS
 To maximize noise margins, select logic levels at
 unity gain point of DC transfer characteristic
Vout
Unity Gain Points

VDD
Slope = -1
VOH
b p/b n > 1
Vin Vout
VOL
Vin
0
Vtn VIL VIH VDD- VDD
|Vtp|

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Assistant Professor
Department of ECE

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UNIT II
CIRCUIT CHARACTERIZATION AND
SIMULATION
Syllabus
Delay estimation
Logical effort and Transistor sizing,
Power dissipation
Interconnect
Design margin,
Reliability
Scaling
SPICE tutorial, Device models, Device characterization,
Circuit characterization, Interconnect simulation.

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INTRODUCTION
 Chip designers face a bewildering array of choices
 What is the best circuit topology for a function?
???
 How many stages of logic give least delay?
 How wide should the transistors be?
 Logical effort is a method to make these decisions

 Uses a simple model of delay
 Allows back-of-the-envelope calculations
 Helps make rapid comparisons between alternatives
 Emphasizes remarkable symmetries

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EXAMPLE
 Ben Bitdiddle is the memory designer for the Motoroil
68W86, an embedded automotive processor. Help Ben
A[3:0] A[3:0]
design the decoder for a register file. 32 bits
4:16 Decoder
16 words
 Decoder specifications: 16
Register File
 16 word register file

 Each word is 32 bits wide
 Each bit presents load of 3 unit-sized transistors
 True and complementary address inputs A[3:0]
 Each input may drive 10 unit-sized transistors
 Ben needs to decide:
 How many stages to use?
 How large should each gate be?
 How fast can decoder operate? 4

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DELAY IN A LOGIC GATE

d
 Express delays in process-independent unit d  abs

 Delay has two components: d = f + p   3RC
 f: effort delay = gh (a.k.a. stage effort)  3 ps in 65 nm process
 Again has two components 60 ps in 0.6 mm process
 g: logical effort
 Measures relative ability of gate to deliver current
 g  1 for inverter
 h: electrical effort = Cout / Cin
 Ratio of output to input capacitance
 Sometimes called fanout
 p: parasitic delay
 Represents delay of gate driving no load
 Set by internal parasitic capacitance 5

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DELAY PLOTS
d =f+p 2-input
= gh + p 6
NAND Inverter
g = 4/3
Normalized Delay: d
5 p=2
 What about d = (4/3)h + 2
4 g=1
NOR2? p=1
3 d=h+1
2 Effort Delay: f
1
Parasitic Delay: p
0
0 1 2 3 4 5
Electrical Effort:
h = Cout / Cin
6: Logical Effort CMOS VLSI Design 4th Ed. 6

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COMPUTING LOGICAL EFFORT
 DEF: Logical effort is the ratio of the input

capacitance of a gate to the input capacitance of
6: Logical Effort
an inverter delivering the same output current.
 Measure from delay vs. fanout plots
 Or estimate by counting transistor widths
2 2 A 4
Y
2 B 4
A 2
A Y Y
1 B 2 1 1
Cin = 3 Cin = 4 Cin = 5

g = 3/3 g = 4/3 g = 5/3
7

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CATALOG OF GATES
 Logical effort of common gates
6: Logical Effort
Gate type Number of inputs
1 2 3 4 n
Inverter 1
NAND 4/3 5/3 6/3 (n+2)/3
NOR 5/3 7/3 9/3 (2n+1)/3
Tristate / mux 2 2 2 2 2
XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8
8

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CATALOG OF GATES
 Parasitic delay of common gates
In multiples of pinv (1)
6: Logical Effort
Gate type Number of inputs
1 2 3 4 n
Inverter 1
NAND 2 3 4 n
NOR 2 3 4 n
Tristate / mux 2 4 6 8 2n
XOR, XNOR 4 6 8
9

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EXAMPLE: RING OSCILLATOR

 Estimate the frequency of an N-stage ring
oscillator
6: Logical Effort
31 stage ring oscillator in
0.6 mm process has
Logical Effort: g=1 frequency of ~ 200 MHz
Electrical Effort: h=1
Parasitic Delay: p=1
Stage Delay: d=2
10
Frequency: fosc = 1/(2*N*d) = 1/4N

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EXAMPLE: FO4 INVERTER

 Estimate the delay of a fanout-of-4 (FO4) inverter
d
6: Logical Effort
Logical Effort: g=1
The FO4 delay is about
Electrical Effort: h=4
300 ps in 0.6 mm process
Parasitic Delay: p=1
15 ps in a 65 nm process
Stage Delay: d=5
11

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MULTISTAGE LOGIC NETWORKS
 Logical effort generalizes to multistage networks

 Path Logical Effort G gi 
6: Logical Effort
Cout-path
 Path Electrical Effort H
Cin-path
 Path Effort F   f i   gi hi
10
x z
y
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z
12

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MULTISTAGE LOGIC NETWORKS
 Logical effort generalizes to multistage networks

 Path Logical Effort G 
gi
6: Logical Effort
Cout  path
 Path Electrical Effort H
Cin  path
 Path Effort F   f i   gi hi
 Can we write F = GH?
13

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PATHS THAT BRANCH

 No! Consider paths that branch:
15
6: Logical Effort
90
G =1
5
H = 90 / 5 = 18
GH = 18 15
90
h1 = (15 +15) / 5 = 6
h2 = 90 / 15 = 6
F = g1g2h1h2 = 36 = 2GH
14

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BRANCHING EFFORT
 Introduce branching effort
 Accounts for branching between stages in path
6: Logical Effort
Con path  Coff path
b
Con path
B   bi
Note:
 Now we compute the path effort

 h  BHi
 F = GBH
15

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MULTISTAGE DELAYS
 Path Effort Delay DF   f i
P   pi
6: Logical Effort
 Path Parasitic Delay
 Path Delay D   d i  DF  P
16

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DESIGNING FAST CIRCUITS

D   d i  DF  P
6: Logical Effort
 Delay is smallest when each stage bears same effort
fˆ  gi hi  F
1
N
 Thus minimum delay of N stage path is

1
D  NF  P N
 This is a key result of logical effort

 Find fastest possible delay
 Doesn’t require calculating gate sizes
17

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GATE SIZES
 How wide should the gates be for least delay?
fˆ  gh  g CCoutin
6: Logical Effort
gi Couti
 Cini 
fˆ
 Working backward, apply capacitance
transformation to find input capacitance of each
gate given load it drives.
 Check work by verifying input cap spec is met.
18

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EXAMPLE: 3-STAGE PATH

 Select gate sizes x and y for least delay from A to
B
x
6: Logical Effort
y
x
45
A 8
x
y B
45
19

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x
y
x
45
A 8
x
6: Logical Effort
y B
45
Logical Effort G = (4/3)*(5/3)*(5/3) =

100/27
Electrical Effort H = 45/8
Branching Effort B=3*2=6
Path Effort F fˆ=  3
GBH F =125
5
Best Stage Effort
Parasitic Delay P=2+3+2=7
20
Delay D = 3*5 + 7 = 22 = 4.4 FO4

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 Work backward for sizes
y = 45 * (5/3) / 5 = 15
x = (15*2) * (5/3) / 5 = 10
y
x
45
45
A P:
84 P:
x 4
N: 4 P:
y 12 B
B
N: 6 45
N: 3 45
6: Logical Effort CMOS VLSI Design 4th Ed. 21

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BEST NUMBER OF STAGES

 How many stages should a path use?
 Minimizing number of stages is not always fastest
6: Logical Effort
 Example: drive 64-bit datapath with unit
inverter Initial Driver 1 1 1 1
8 4 2.8
16 8
D = NF1/N + P
23
= N(64)1/N + N
Datapath Load 64 64 64 64
N: 1 2 3 4
f: 64 8 4 2.8
D: 65 18 15 15.3
Fastest 22

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DERIVATION
 Consider adding inverters to end of path
 How many give least delay? N - n1 ExtraInverters
Logic Block:
6: Logical Effort
n1 n1Stages
D  NF   pi   N  n1  pinv
1
N Path Effort F
i 1
D 1 1 1
  F N ln F N  F N  pinv  0
N
 Define best stage effort
F
1
N
pinv   1  ln    0
23

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BEST STAGE EFFORT

 pinv   1  ln   has
0 no closed-form
solution
6: Logical Effort
 Neglecting parasitics (pinv = 0), we find  = 2.718
(e)
 For pinv = 1, solve numerically for  = 3.59
24

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SENSITIVITY ANALYSIS
 How sensitive is delay to using exactly the best
number of stages? 1.6
1.51
D(N) /D(N)
1.4
1.26
6: Logical Effort
1.2 1.15
1.0
(=6) ( =2.4)
0.0
0.5 0.7 1.0 1.4 2.0
N/ N
 2.4 <  < 6 gives delay within 15% of optimal

 We can be sloppy!
 I like  = 4
25

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EXAMPLE, REVISITED
 Ben Bitdiddle is the memory designer for the Motoroil
68W86, an embedded automotive processor. Help Ben
A[3:0] A[3:0]
design the decoder for a register file. 32 bits
6: Logical
4:16 Decoder
16 words
 Decoder specifications: 16
Register File
Effort
 16 word register file
 Each word is 32 bits wide
 Each bit presents load of 3 unit-sized transistors
 True and complementary address inputs A[3:0]
 Each input may drive 10 unit-sized transistors
 Ben needs to decide:
 How many stages to use?
 How large should each gate be?
 How fast can decoder operate? 26

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NUMBER OF STAGES
 Decoder effort is mainly electrical and branching
Electrical Effort: H = (32*3) / 10 = 9.6
6: Logical Effort
Branching Effort: B=8
 If we neglect logical effort (assume G = 1)

Path Effort: F = GBH = 76.8
Number of Stages: N = log4F = 3.1
 Try a 3-stage design

27

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GATE SIZES & DELAY

Logical Effort: G = 1 * 6/3 * 1 = 2
Path Effort: F = GBH = 154
ˆ   5.36
6: Logical Effort
1/ 3
Stage Effort: f F
Path Delay: D  3 fˆ  1  4  1  22.1
Gate sizes: z = 96*1/5.36 = 18 y = 18*2/5.36 = 6.7
A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0]
10 10 10 10 10 10 10 10
y z word[0]
96 units of wordline capacitance
y z word[15]
28

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COMPARISON
 Compare many alternatives with a spreadsheet
 D = N(76.8 G)1/N + P
6: Logical Effort
Design N G P D
NOR4 1 3 4 234
NAND4-INV 2 2 5 29.8
NAND2-NOR2 2 20/9 4 30.1
INV-NAND4-INV 3 2 6 22.1
NAND4-INV-INV-INV 4 2 7 21.1
NAND2-NOR2-INV-INV 4 20/9 6 20.5
NAND2-INV-NAND2-INV 4 16/9 6 19.7
INV-NAND2-INV-NAND2-INV 5 16/9 7 20.4
NAND2-INV-NAND2-INV-INV-INV 6 16/9 8 21.6
29

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REVIEW OF DEFINITIONS
Term Stage Path
number of stages 1 N
6: Logical Effort
logical effort g G   gi
H
Cout-path
electrical effort h  CCoutin Cin-path
Con-path Coff-path
branching effort b Con-path B   bi
effort f  gh F  GBH
effort delay f DF   f i
parasitic delay p P   pi
delay d f p D   di  DF  P
30

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METHOD OF LOGICAL EFFORT

1) Compute path effort F  GBH
2) Estimate best number of stages N  log4 F
6: Logical Effort
3) Sketch path with N stages 1
4) Estimate least delay D  NF  P N
5) Determine best stage effort ˆf  F N1
gi Couti
Find gate sizes Cini 
fˆ
6)
31

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LIMITS OF LOGICAL EFFORT

 Chicken and egg problem
 Need path to compute G
But don’t know number of stages without G
6: Logical Effort

 Simplistic delay model

 Neglects input rise time effects
 Interconnect
 Iteration required in designs with wire
 Maximum speed only
 Not minimum area/power for constrained delay
32

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SUMMARY
 Logical effort is useful for thinking of delay in
circuits
6: Logical Effort
 Numeric logical effort characterizes gates
 NANDs are faster than NORs in CMOS
 Paths are fastest when effort delays are ~4
 Path delay is weakly sensitive to stages, sizes
 But using fewer stages doesn’t mean faster paths
 Delay of path is about log4F FO4 inverter delays
 Inverters and NAND2 best for driving large caps
 Provides language for discussing fast circuits
 But requires practice to master
33

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6: Logical Effort
POWER DISSIPATION
34

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POWER DISSIPATION SOURCES
7: Power
 Ptotal = Pdynamic + Pstatic
 Dynamic power: Pdynamic = Pswitching + Pshortcircuit
 Switching load capacitances
 Short-circuit current
 Static power: Pstatic = (Isub + Igate + Ijunct +
Icontention)VDD
 Subthreshold leakage
 Gate leakage
 Junction leakage
 Contention current
35

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SHORT CIRCUIT CURRENT
7: Power
 When transistors switch, both nMOS and pMOS
networks may be momentarily ON at once
 Leads to a blip of “short circuit” current.
 < 10% of dynamic power if rise/fall times are

comparable for input and output
 We will generally ignore this component
36

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DYNAMIC POWER REDUCTION
 Pswitching   CVDD 2 f
 Try to minimize:
 Activity factor
 Capacitance
 Supply voltage
 Frequency
7: Power CMOS VLSI Design 4th Ed. 37

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STATIC POWER REDUCTION
7: Power
 Leakage and delay trade off
 Aim for low leakage in sleep and low delay in active
mode
 To reduce leakage:
 Increase Vt: multiple Vt
 Use low Vt only in critical circuits
 Increase Vs: stack effect
 Input vector control in sleep
 Decrease Vb
 Reverse body bias in sleep
 Or forward body bias in active mode
38

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Assistant Professor
Department of ECE
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UNIT III
COMBINATIONAL AND SEQUENTIAL
CIRCUIT DESIGN
Syllabus
 Circuit families
 Low power logic design
 comparison of circuit families
 Sequencing static circuits
 circuit design of latches and flip flops
 Static sequencing element methodology
 sequencing dynamic circuits
 synchronizers

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COMBINATIONAL CIRCUIT
 What makes a circuit fast?
◦ I = C dV/dt -> tpd  (C/I) DV B 4
◦ low capacitance A 4
Y
◦ high current 1 1
◦ small swing
 Logical effort is proportional to C/I
 pMOS are the enemy!
◦ High capacitance for a given current
 Can we take the pMOS capacitance off the
input?
 Various circuit families try to do this…
10: Circuit Families 3
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Pseudo-nMOS
 In the old days, nMOS processes had no
pMOS
◦ Instead, use pull-up transistor that is always
ON
 In CMOS, use a pMOS that is always ON
◦ Ratio issue
◦ Make pMOS about ¼ effective strength of
load
P/2
1.8
Ids
pulldown network 1.5
Vout
16/2 1.2
P = 24
Vin Vout 0.9
0.6
CMOS VLSI Design 4th Ed. P = 14
0.3
4 P=4
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Pseudo-nMOS Gates
 Design for unit current on output
to compare with unit inverter. Y
inputs
 pMOS fights nMOS f
Inverter NAND2 NOR2
gu = gu = gu =
gd = g = gd =
gavg = Y gd = gavg =
avg
pu = A pu =
Y Y pu =
A pd = B pd = A B pd =
pavg = pavg = pavg =

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Pseudo-nMOS Gates
 Design for unit current on output
to compare with unit inverter. Y
inputs
 pMOS fights nMOS f
Inverter NAND2 NOR2
gu = 4/3 gu = 8/3 gu = 4/3

gd = 4/9 2/3 g = 8/9 gd = 4/9
gavg = 8/9 Y gd = 16/9 gavg = 8/9
2/3 avg 2/3
pu = 6/3 A 8/3 pu = 10/3
Y Y pu = 10/3
A 4/3 pd = 6/9 B 8/3 pd = 10/9 A 4/3 B 4/3 pd = 10/9
pavg = 12/9 pavg = 20/9 pavg = 20/9

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Pseudo-nMOS Design
 Ex: Design a k-input AND gate using
pseudo-nMOS. Estimate the delay driving
a fanout of H Pseudo-nMOS
In1 1
Y
 G = 1 * 8/9 = 8/9 In 1 k
H
 F = GBH = 8H/9
 P = 1 + (4+8k)/9 = (8k+13)/9
N=2
1/N 4 2 H 8k  13
 D = NF +P= 3  9

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Pseudo-nMOS Power
 Pseudo-nMOS draws power whenever Y
=0
◦ Called static power P = IDDVDD
◦ A few mA / gate * 1M gates would be a
problem
◦ Explains why nMOS went extinct
 Use pseudo-nMOS
en sparingly
Y
for wide
NORs A B C
 Turn off pMOS when not in use
8
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Dynamic Logic
 Dynamic gates uses a clocked pMOS
pullup
 Two modes: precharge and evaluate
2 
2/3 1
A Y Y Y
1 A 4/3 A 1
Static Pseudo-nMOS Dynamic
 Precharge Evaluate Precharge

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The Foot
 What if pulldown network is ON during
precharge?
 Use series evaluation transistor to
 
precharge transistor
 prevent
Y
fight. Y Y
inputs inputs
A f f
foot
footed unfooted

10
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Logical Effort
Inverter NAND2 NOR2
 1
Y
 1  1
A 2
unfooted Y Y
A 1 B 2 A 1 B 1
gd = 1/3 gd = 2/3 gd = 1/3
pd = 2/3 pd = 3/3 pd = 3/3
 1
Y
 1  1
A 3
Y Y
footed A 2 B 3 A 2 B 2
gd = 2/3 gd = 3/3 gd = 2/3
2 pd = 3/3 3 pd = 4/3 2 pd = 5/3

11
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Monotonicity
 Dynamic gates require monotonically rising
inputs during evaluation

◦ 0 -> 0 A
◦ 0 -> 1
◦ 1 -> 1 violates monotonicity
during evaluation
◦ But not 1 A-> 0

Output should rise but does not

12
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Monotonicity Woes
 But dynamic gates produce
monotonically falling outputs
during evaluation
 Illegal for one dynamic gate to
drive another!
A=1
  Precharge Evaluate Precharge

Y
X
A
X
X monotonically falls during evaluation
Y
Y should rise but cannot

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Domino Gates
 Follow dynamic stage with inverting static
gate
◦ Dynamic / static pair is called domino gate
◦ Produces monotonic outputs
domino AND
W
W X Y Z X
A
Y
B C

Z
dynamic static
 
NAND inverter  
A W X A X
H Y =
B H Z B Z
C C

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Domino Optimizations
 Each domino gate triggers next one, like a
string of dominos toppling over
 Gates evaluate sequentially but precharge
in parallel
 Thus evaluation is more critical than

precharge
S0
D0
S1
D1
S2
D2
S3
D3
 HI-skewed static stages can perform logic

Y
H

S4 S5 S6 S7
D4 D5 D6 D7

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Dual-Rail Domino
 Domino only performs noninverting
functions:
◦ AND, OR but not NAND, NOR, or XOR
 Dual-rail domino solves this problem
◦ Takes true and complementary inputs
sig_h sig_l Meaning
◦ Produces true and complementary
Y_l 
outputsY_h
0 0 Precharged
‘0’
inputs
0 1 f f
1 0 ‘1’ 
1 1 invalid

16
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Example: AND/NAND
 Given A_h, A_l, B_h, B_l
 Compute Y_h = AB, Y_l = AB
 Pulldown networks are conduction
complements
Y_l  Y_h
= A*B A_h = A*B
A_l B_l B_h

17
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Example: XOR/XNOR
 Sometimes possible to share transistors
Y_l  Y_h
= A xnor B A_h A_l A_l A_h = A xor B
B_l B_h

18
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Leakage
 Dynamic node floats high during
evaluation
◦ Transistors are leaky (IOFF  0)
◦ Dynamic value will leak away over time
◦ Formerly miliseconds, now nanoseconds
 Use keeper to hold dynamic
weak keeper node

◦ Must be weak enough
1 k
X
H not
Y to fight evaluation
A 2
2

19
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Charge Sharing
 Dynamic gates suffer from charge sharing


Y A
A x CY
Y
B=0 Cx Charge sharing noise
CY
Vx  VY  VDD
Cx  CY

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Secondary Precharge
 Solution: add secondary precharge
transistors
◦ Typically need to precharge every other node
 Big load capacitance CY helps as well
secondary
 precharge
Y transistor
A x
B

21
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Noise Sensitivity
 Dynamic gates are very sensitive to noise
◦ Inputs:VIH  Vtn
◦ Outputs: floating output susceptible noise
 Noise sources
◦ Capacitive crosstalk
◦ Charge sharing
◦ Power supply noise
◦ Feedthrough noise
◦ And more!
22
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Power
 Domino gates have high activity factors
◦ Output evaluates and precharges
 If output probability = 0.5, a = 0.5
 Output rises and falls on half the cycles
◦ Clocked transistors have a = 1
 Leads to very high power consumption

23
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Domino Summary
 Domino logic is attractive for high-speed
circuits
◦ 1.3 – 2x faster than static CMOS
◦ But many challenges:
 Monotonicity, leakage, charge sharing, noise
 Widely used in high-performance
microprocessors in 1990s when speed was
king
 Largely displaced by static CMOS now that
power is the limiter
 Still used in memories for area efficiency

24
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Pass Transistor Circuits

 Use pass transistors like switches to do
logic
 Inputs drive diffusion terminals as well as
gates
 CMOS + Transmission Gates:
S ◦ 2-input multiplexer S
A ◦ Gates should be restoring A

S Y
S Y
B
B
S
S
25
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LEAP
 LEAn integration with Pass transistors
 Get rid of pMOS transistors
◦ Use weak pMOS feedback to pull fully high
◦ Ratio constraint
S
A
S L Y
B

26
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CPL
 Complementary Pass-transistor Logic
◦ Dual-rail form of pass transistor logic
◦ Avoids need for ratioed feedback
◦ Optional cross-coupling for rail-to-rail swing
S
A
S L Y
B
S
A
S L Y
B

27
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Pass Transistor Summary

 Researchers investigated pass transistor
logic for general purpose applications in
the 1990’s
◦ Benefits over static CMOS were small or
negative
◦ No longer generally used
 However, pass transistors still have a
niche in special circuits such as memories
where they offer small size and the
threshold drops can be managed
28
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STATIC CMOS
 Bubble Pushing
 Compound Gates
 Logical Effort Example
 Input Ordering
 Asymmetric Gates
 Skewed Gates
 Best P/N ratio

29
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Bubble Pushing
 Start with network of AND / OR gates
 Convert to NAND / NOR + inverters
 Push bubbles around to simplify logic
◦ Remember DeMorgan’s Law
Y Y
(a) (b)
Y Y
D
(c) (d)

30
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Compound Gates
 Logical Effort of compound gates
unit inverter AOI21 AOI22 Complex AOI
YA Y  A BC Y  A BC D Y  A B  C  D E

D
A A E
Y
B B A
A Y Y Y
C C B
D C
A 4 B 4 A 4 B 4 B 6
2 C 4 C 4 D 4 C 6 A 3
A Y Y Y
1 A 2 A 2 C 2 D 6 E 6
C 1 Y
B 2 B 2 D 2 E 2 A 2
D 2 B 2 C 2
gA = 3/3 gA = 6/3 gA = 6/3 gA = 5/3

p = 3/3 gB = 6/3 gB = 6/3 gB = 8/3
gC = 5/3 gC = 6/3 gC = 8/3
p = 7/3 gD = 6/3 gD = 8/3
p = 12/3 gE = 8/3
p = 16/3

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Input Order
 Our parasitic delay model was too simple
◦ Calculate parasitic delay for Y falling
 If A arrives latest? 2t
 If B arrives latest? 2.33t
2 2 Y
A 2 6C
B 2x 2C

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Inner & Outer Inputs

 Inner input is closest to output (A)
 Outer input is closest to rail (B) 2 2 Y
A 2
 If input arrival time is known B 2
◦ Connect latest input to inner terminal

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Asymmetric Gates
 Asymmetric gates favor one input over another
 Ex: suppose input A of a NAND gate is most
critical
◦ Use smaller transistor on A (less capacitance)
◦ Boost size of noncritical input resetA Y
◦ So total resistance is same
 gA = 10/9 2 2
Y
 gB = 2 A 4/3
 gtotal = gA + gB = 28/9 reset 4
 Asymmetric gate approaches g = 1 on critical

input
 But total logical effort goes up
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Symmetric Gates
 Inputs can be made perfectly symmetric
2 2
Y
A 1 1
B 1 1

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Skewed Gates
 Skewed gates favor one edge over another
 Ex: suppose rising output of inverter is most
critical
◦ Downsize noncritical nMOS transistor
HI-skew unskewed inverter unskewed inverter
inverter (equal rise resistance) (equal fall resistance)
2 2 1
A Y A Y A Y
1/2 1 1/2
 Calculate logical effort by comparing to unskewed

inverter with same effective resistance on that
edge.
◦ gu = 2.5 / 3 = 5/6
◦ gd = 2.5 / 1.5 = 5/3
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HI- and LO-Skew

 Def: Logical effort of a skewed gate for a
particular transition is the ratio of the input
capacitance of that gate to the input capacitance
of an unskewed inverter delivering the same
output current for the same transition.
 Skewed gates reduce size of noncritical

transistors
◦ HI-skew gates favor rising output (small nMOS)
◦ LO-skew gates favor falling output (small pMOS)
 Logical effort is smaller for favored direction
 But larger for the other direction

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Catalog of Skewed Gates

Inverter NAND2 NOR2
2 2 B 4
Y
2 A 4
A 2
unskewed A Y Y
Inverter 1 guNAND2=1 B NOR2 2 gu = 4/3 1 1 gu = 5/3
gd 2 = 12 B 4
gd = 4/3 gd = 5/3
2 gA avg = 12 Y
A 4 gavg = 4/3 gavg = 5/3
unskewed A Y Y
1 gu = 1 B 2 gu = 4/3 1 1 gu = 5/3
gd = 1
gavg = 1
gd = 4/3
gavg = 4/3 2 gd = 5/3
2
gavg = 5/3 B 4
4 Y
2 2 2
Y
B
A 4
2 AA 4 1
HI-skew
HI-skew A
A Y
1/2 g = 5/6
u
YAB 1
1 g u
=1 1/2 1/2
Y
gu = 3/2
Y
1/2 gu = 5/6gg
gd = 5/3
gavg = 5/4
d
=2
= 3/2
B gd = 3 1
gavg = 9/4 gu = 1/2 1/2 gu =
avg
gd 1 = 5/3
1
Y
B 2 gd = gd =
1 A 2
LO-skew A
1
Y gB avg = 5/4
A 2
2 1 1
Y gavg = gavg =
gu = 4/3 gu = 2 gu = 2
gd = 2/3 gd = 1 gd = 1
gavg = 1 gavg = 3/2 1 1
gavg = 3/2 B 2
Y
1 A 2
A 2
LO-skew A Y Y
1 gu = 4/3 B 2 gu = 1 1 gu =
gd = 2/3 gd = gd =
gavg = 1 gavg = gavg =

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Asymmetric Skew
 Combine asymmetric and skewed gates
◦ Downsize noncritical transistor on
unimportant input
◦ Reduces parasitic delay for critical input
A
Y
reset
1 2
Y
A 4/3
reset 4

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Best P/N Ratio

 We have selected P/N ratio for unit rise and
fall resistance (m = 2-3 for an inverter).
 Alternative: choose ratio for least average
delay
 Ex: inverter P
◦ Delay driving identical inverter A
1
◦ tpdf = (P+1)
◦ tpdr = (P+1)(m/P)
◦ tpd = (P+1)(1+m/P)/2 = (P + 1 + m + m/P)/2
◦ dtpd / dP = (1- m/P2)/2 = 0
◦ m
Least delay for P =

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P/N Ratios
 In general, best P/N ratio is sqrt of equal
delay ratio.
◦ Only improves average delay slightly for
inverters
◦ But significantly decreases area and power
Inverter NAND2 NOR2
2 2 B 2
Y
fastest 1.414 A 2
A 2
A Y Y
P/N ratio 1 gu = B 2 gu = 1 1 gu =
gd = gd = gd =
gavg = gavg = gavg =

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Observations
 For speed:
◦ NAND vs. NOR
◦ Many simple stages vs. fewer high fan-in stages
◦ Latest-arriving input
 For area and power:
◦ Many simple stages vs. fewer high fan-in stages

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Sequencing
 Combinational logic
◦ output depends on current inputs
 Sequential logic
◦ output depends on current and previous inputs
◦ Requires separating previous, current, future
◦ Called state or tokens
◦ Ex: FSM, pipeline
clk clk clk clk
in out
CL CL CL
Finite State Machine Pipeline

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Sequencing Cont.
 If tokens moved through pipeline at constant
speed, no sequencing elements would be
necessary
 Ex: fiber-optic cable
◦ Light pulses (tokens) are sent down cable
◦ Next pulse sent before first reaches end of cable
◦ No need for hardware to separate pulses
◦ But dispersion sets min time between pulses
 This is called wave pipelining in circuits
 In most circuits, dispersion is high
◦ Delay fast tokens so they don’t catch slow ones.

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Sequencing Overhead
 Use flip-flops to delay fast tokens so they
move through exactly one stage each cycle.
 Inevitably adds some delay to the slow
tokens
 Makes circuit slower than just the logic delay
◦ Called sequencing overhead
 Some people call this clocking overhead
◦ But it applies to asynchronous circuits too
◦ Inevitable side effect of maintaining sequence

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Sequencing Elements
 Latch: Level sensitive
◦ a.k.a. transparent latch, D latch
 Flip-flop: edge triggered
◦ A.k.a. master-slave flip-flop, D flip-flop, D register
 Timing Diagrams
◦ Transparent
clk clk
Latch
Flop
D Q D Q
◦ Opaque
◦ Edge-trigger clk
Q (latch)
Q (flop)

11: Sequential Circuits 46
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Latch Design
 Pass Transistor Latch
 Pros 
+ Tiny
+ Low clock load D Q
 Cons Used in 1970’s
◦ Vt drop
◦ nonrestoring
◦ backdriving
◦ output noise sensitivity
◦ dynamic
◦ diffusion input
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Latch Design
 Transmission gate

+ No Vt drop
D Q
- Requires inverted clock


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Latch Design
 Inverting buffer 
+ Restoring D
X
Q
+ No backdriving 

+ Fixes either
D Q
 Output noise sensitivity
 Or diffusion input 
◦ Inverted output

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Latch Design
 Tristate feedback

+ Static X
D Q
◦ Backdriving risk 

 Static latches are now essential 
because of leakage

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Latch Design
 Buffered input

+ Fixes diffusion input D
X
Q
+ Noninverting 


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Latch Design
 Buffered output  Q
+ No backdriving D
X



 Widely used in standard cells
+ Very robust (most important)
- Rather large
- Rather slow (1.5 – 2 FO4 delays)
- High clock loading
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Latch Design
 Datapath latch  Q
+ smaller D
X
+ faster 

- unbuffered input


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Flip-Flop Design
 Flip-flop is built as pair of back-to-back
latches 
X
D Q
 
  Q
X
D Q
 
 
 

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Enable
 Enable: ignore clock when en = 0
◦ Mux: increase latch D-Q delay
◦ Clock Gating: increase en setup time, skew
Symbol Multiplexer Design Clock Gating Design
 en
 
D 1
Latch
Latch
Latch
D Q Q D Q
0
en en
 en

 D 1
Flop
Q
0
Flop
Flop
D Q D Q
en
en

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Reset
 Force output low when reset asserted
 Synchronous vs. asynchronous  
Symbol
Latch
Flop
D Q D Q
reset reset
Synchronous Reset
 Q   Q
reset reset
Q
D D
 

  
 

Q
Q 
Asynchronous Reset
 
reset
reset
D
D 
 

 
reset
reset




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Set / Reset
 Set forces output high when enabled
 Flip-flop with asynchronous


set and reset

reset
set Q
D




set
reset



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Sequencing Methods
Tc
 Flip-flops
Flip-Flops
clk
 2-Phase Latches clk clk
Flop
Flop
Combinational Logic
 Pulsed Latches
2-Phase Transparent Latches

1
tnonoverlap tnonoverlap
Tc/2
2
1 2 1
Latch
Latch
Latch
Combinational Combinational
Logic Logic
Half-Cycle 1 Half-Cycle 1
Pulsed Latches
p tpw
p p
Latch
Latch
Combinational Logic

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Timing Diagrams
Contamination and
Propagation Delays A tpd
Combinational
A Y
tpd Logic Prop. Delay Logic
Y tcd
tcd Logic Cont. Delay

clk clk tsetup
thold
tpcq Latch/Flop Clk->Q Prop. Delay
Flop
D Q D
tccq Latch/Flop Clk->Q Cont. Delay tpcq
Q tccq
tpdq Latch D->Q Prop. Delay
tcdq Latch D->Q Cont. Delay clk tsetup thold

clk
tccq tpcq
tsetup Latch/Flop Setup Time

Latch
D Q D tpdq
tcdq
thold Latch/Flop Hold Time Q

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Max-Delay: Flip-Flops
t pd  Tc   tsetup  t pcq 
clk clk
Q1 D2
F1
F2
sequencing overhead Combinational Logic
Tc
tsetup
clk
tpcq
Q1 tpd
D2

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Max Delay: 2-Phase Latches

1 2 1
t pd  t pd 1  t pd 2  Tc   2t 
pdq D1 Q1 Combinational D2 Q2 Combinational D3 Q3
L1
L2
L3
sequencing overhead Logic 1 Logic 2
1
2
Tc
D1 tpdq1
Q1 tpd1
D2 tpdq2
Q2 tpd2
D3

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Max Delay: Pulsed Latches

t pd  Tc  max  t pdq , t pcq  tsetup  t pw  p p
D1 Q1 D2 Q2
L1
L2
Combinational Logic
sequencing overhead
Tc
D1 tpdq
(a) tpw > tsetup

Q1 tpd
D2
p
tpcq Tc tpw
Q1 tpd tsetup
(b) tpw < tsetup
D2

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Min-Delay: Flip-Flops
clk
tcd  thold  tccq Q1
F1
CL
clk
D2
F2
clk
Q1 tccq tcd
D2 thold

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Min-Delay: 2-Phase Latches

1
tcd 1,tcd 2  thold  tccq  tnonoverlap Q1
L1
CL
2
Hold time reduced by D2
L2
nonoverlap
tnonoverlap
1
Paradox: hold applies
tccq
2
twice each cycle, vs.
only once for flops. Q1 tcd
D2 thold
But a flop is made of

two latches!

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Min-Delay: Pulsed Latches

p
tcd  thold  tccq  t pw Q1
L1
CL
p
Hold time increased
D2
by pulse width
L2
p
tpw
thold
Q1 tccq tcd
D2

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Time Borrowing
 In a flop-based system:
◦ Data launches on one rising edge
◦ Must setup before next rising edge
◦ If it arrives late, system fails
◦ If it arrives early, time is wasted
◦ Flops have hard edges
 In a latch-based system
◦ Data can pass through latch while transparent
◦ Long cycle of logic can borrow time into next
◦ As long as each loop
CMOS VLSI completes in one cycle
4th Ed.
Design
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Time Borrowing Example

1
2
1 2 1
Latch
Latch
Latch
Combinational
(a) Combinational Logic
Logic
Borrowing time across Borrowing time across

half-cycle boundary pipeline stage boundary
1 2
Latch
Combinational Logic Latch Combinational

(b) Logic
Loops may borrow time internally but must complete within the cycle

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How Much Borrowing?

2-Phase Latches 1 2
 c   tsetup  tnonoverlap 
D1 Q1 D2 Q2
T
L1
L2
Combinational Logic 1
tborrow
2
1
2 tnonoverlap
Pulsed Latches Tc
tsetup
tborrow  t pw  tsetup Tc/2
Nominal Half-Cycle 1 Delay
tborrow
D2

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Clock Skew
 We have assumed zero clock skew
 Clocks really have uncertainty in arrival
time
◦ Decreases maximum propagation delay
◦ Increases minimum contamination delay
◦ Decreases time borrowing

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Skew: Flip-Flops
clk clk
t pd  Tc   t pcq  tsetup  tskew 

Q1 D2
F1
F2
Combinational Logic
Tc
sequencing overhead
clk
tcd  thold  tccq  tskew

tpcq
tskew
Q1 tpdq tsetup
D2
clk
Q1
F1
CL
clk
D2
F2
tskew
clk
thold
Q1 tccq
D2 tcd

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Skew: Latches
2-Phase Latches 1 2 1
 2t 
D1 Q1 Combinational D2 Q2 Combinational D3 Q3
L1
L2
L3
t pd  Tc  pdq
Logic 1 Logic 2
sequencing overhead 1
tcd 1 , tcd 2  thold  tccq  tnonoverlap  tskew 2
  tsetup  tnonoverlap  tskew 

Tc
tborrow 
2
Pulsed Latches
t pd  Tc  max  t pdq , t pcq  tsetup  t pw  tskew 
sequencing overhead
tcd  thold  t pw  tccq  tskew
tborrow  t pw   tsetup  tskew 

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Two-Phase Clocking
 If setup times are violated, reduce clock speed
 If hold times are violated, chip fails at any speed
 In this class, working chips are most important
◦ No tools to analyze clock skew
 An easy way to guarantee hold times is to use 2-
phase latches with big nonoverlap times
 Call these clocks f1, f2 (ph1, ph2)

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Safe Flip-Flop
 Past years used flip-flop with
nonoverlapping clocks
◦ Slow – nonoverlap adds to setup time
◦ But no hold times
 In industry, use a better timing analyzer
◦ Add buffers

to slow

signals if hold
Q
time is at
 
risk X
D Q
 
 
 
 4th Ed.
CMOS VLSI Design
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Adaptive Sequencing
p
 Designers include timing margin X
◦ Voltage
ERR
D Q
◦ Temperature
◦ Process variation 
D
p
◦ Data dependency Q
X
◦ Tool inaccuracies ERR
 Alternative: run faster and check for near failures

◦ Idea introduced as “Razor”
 Increase frequency until at the verge of error
 Can reduce cycle
11: Sequential Circuits
time
CMOS by ~30%
4th Ed.
VLSI Design
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Summary
 Flip-Flops:
◦ Very easy to use, supported by all tools
 2-Phase Transparent Latches:
◦ Lots of skew tolerance and time borrowing
 Pulsed Latches:
◦ Fast, some skew tol & borrow, hold time risk

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UNIT IV
CMOS TESTING
Ms.K.Samgeethalakshmi
Assistant Professor
Department of ECE
Sangeetha.lk@rmkcet.ac.in

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SYLLABUS
Need for testing
Testers, Text fixtures and test programs
Logic verification
Silicon debug principles
Manufacturing test
Design for testability
Boundary scan

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TESTING
 Testing is one of the most expensive parts of
chips
 Logic verification accounts for > 50% of design effort
for many chips
 Debug time after fabrication has enormous
opportunity cost
 Shipping defective parts can sink a company
 Example: Intel FDIV bug (1994)

 Logic error not caught until > 1M units shipped
 Recall cost $450M (!!!)
3

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LOGIC VERIFICATION
 Does the chip simulate correctly?
 Usually done at HDL level
 Verification engineers write test bench for HDL
 Can’t test all cases
 Look for corner cases
 Try to break logic design
 Ex: 32-bit adder

 Test all combinations of corner cases as inputs:
 0, 1, 2, 231-1, -1, -231, a few random numbers
 Good tests require ingenuity

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SILICON DEBUG
 Test the first chips back from fabrication
 If you are lucky, they work the first time
 If not…
 Logic bugs vs. electrical failures
 Most chip failures are logic bugs from inadequate
simulation
 Some are electrical failures
 Crosstalk
 Dynamic nodes: leakage, charge sharing
 Ratio failures
 A few are tool or methodology failures (e.g. DRC)

 Fix the bugs and fabricate a corrected chip
5

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SHMOO PLOTS
 How to diagnose failures?
 Hard to access chips
 Picoprobes
 Electron beam
 Laser voltage probing
 Built-in self-test
 Shmoo plots
 Vary voltage, frequency
 Look for cause of
electrical failures

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MANUFACTURING TEST
 A speck of dust on a wafer is sufficient to kill chip
 Yield of any chip is < 100%
 Must test chips after manufacturing before delivery
to customers to only ship good parts
 Manufacturing testers are
very expensive
 Minimize time on tester
 Careful selection of
test vectors

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MANUFACTURING FAILURES
SEM images courtesy Intel Corporation 8

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STUCK-AT FAULTS
 How does a chip fail?
 Usually failures are shorts between two conductors
or opens in a conductor
 This can cause very complicated behavior
 A simpler model: Stuck-At
 Assume all failures cause nodes to be “stuck-at” 0 or
1, i.e. shorted to GND or VDD
 Not quite true, but works well in practice

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EXAMPLES
10

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OBSERVABILITY & CONTROLLABILITY

 Observability: ease of observing a node by
watching external output pins of the chip
 Controllability: ease of forcing a node to 0 or 1 by
driving input pins of the chip
 Combinational logic is usually easy to observe

and control
 Finite state machines can be very difficult,
requiring many cycles to enter desired state
 Especially if state transition diagram is not known to
the test engineer
11

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TEST PATTERN GENERATION

 Manufacturing test ideally would check every
node in the circuit to prove it is not stuck.
 Apply the smallest sequence of test vectors
necessary to prove each node is not stuck.
 Good observability and controllability reduces

number of test vectors required for
manufacturing test.
 Reduces the cost of testing
 Motivates design-for-test
12

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TEST EXAMPLE
SA1 SA0 A3 n1
A2
 A3 Y
 {0110} {1110} A
n2
1
n3
A
 A2 {1010} {1110} 0
 A1 {0100} {0110}
 A0 {0110} {0111}
 n1 {1110} {0110}
 n2 {0110} {0100}
 n3 {0101} {0110}
Y {0110} {1110}
 Minimum set: {0100, 0101, 0110, 0111, 1010,
13
1110}

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DESIGN FOR TEST

 Design the chip to increase observability and
controllability
 If each register could be observed and controlled,

test problem reduces to testing combinational
logic between registers.
 Better yet, logic blocks could enter test mode

where they generate test patterns and report the
results automatically.
14

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SCAN
CLK
 Convert each flip-flop to a scan register SCAN
Flop
 Only costs one extra multiplexer SI Q
D
 Normal mode: flip-flops behave as usual
 Scan mode: flip-flops behave as shift register
scan-in
Flop
Flop
Flop
 Contents of flops
Flop
Flop
Flop
can be scanned Logic Logic
inputs Cloud Cloud outputs
out and new

Flop
Flop
Flop
values scanned
Flop
Flop
Flop
in scanout
15

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SCANNABLE FLIP-FLOPS
12: Design for Testability

SCAN
SCAN CLK
  Q
D
D 0 X
Flop
Q Q
SI 1 SI  
(a)  
(b)
 
d
 D
d  Q
SCAN
d X
Q
s  
s 
SI
(c)
s
 
16

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ATPG
 Test pattern generation is tedious
 Automatic Test Pattern Generation (ATPG) tools
produce a good set of vectors for each block of
combinational logic
 Scan chains are used to control and observe the
blocks
 Complete coverage requires a large number of
vectors, raising the cost of test
 Most products settle for covering 90+% of
potential stuck-at faults
17

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BUILT-IN SELF-TEST
 Built-in self-test lets blocks test themselves
 Generate pseudo-random inputs to comb. logic
 Combine outputs into a syndrome
 With high probability, block is fault-free if it
produces the expected syndrome
18

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PRSG
 Linear Feedback Shift Register
 Shift register with input taken from XOR of state
 Pseudo-Random Sequence Generator
Step Y
CLK Y 0 111
Q[0] Q[1] Q[2]
Flop
Flop
Flop
D D D
1 110
2 101
3 010
Flops reset to 111 4 100
5 001
6 011
7 111 (repeats)
19

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BILBO
 Built-in Logic Block Observer
 Combine scan with PRSG & signature analysis
D[0] D[1] D[2]
C[0]
C[1]
Q[2] / SO
Flop
Flop
Flop
SI 1
0 Q[0]
Q[1]
MODE C[1] C[0]

Scan 0 0
Logic Signature
PRSG Test 0 1
Cloud Analyzer
Reset 1 0
Normal 1 1
20

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BOUNDARY SCAN
 Testing boards is also difficult
 Need to verify solder joints are good
 Drive a pin to 0, then to 1
 Check that all connected pins get the values
 Through-hold boards used “bed of nails”

 SMT and BGA boards cannot easily contact pins
 Build capability of observing and controlling pins

into each chip to make board test easier
21

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BOUNDARY SCAN EXAMPLE

PackageInterconnect
CHIP B CHIP C
Serial Data Out
CHIP A CHIP D
IO pad and Boundary Scan

Cell 22
Serial Data In

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BOUNDARY SCAN INTERFACE

 Boundary scan is accessed through five pins
 TCK: test clock
 TMS: test mode select
 TDI: test data in
 TDO: test data out
 TRST*: test reset (optional)
 Chips with internal scan chains can access the

chains through boundary scan for unified test
strategy.
23

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SUMMARY
 Think about testing from the beginning
 Simulate as you go
 Plan for test after fabrication
 “If you don’t test it, it won’t work! (Guaranteed)”
24

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VERILOG HDL

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VERILOG FUNDAMENTALS

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WHAT IS VERILOG
 Hardware Description Language (HDL)
 Developed in 1984
 Standard: IEEE 1364, Dec 1995

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APPLICATION AREAS OF VERILOG

System Specification Suitable for all level
Behavioral level
Not suitable
HW/SW
Partition
Hardware Softwre
Spec Spec
ASIC
FPGA Boards
&
Software
PLD Systems
Std Parts

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BASIC LIMITATION OF VERILOG
Description of digital systems only

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ABSTRACTION LEVELS IN VERILOG
Behavioral
RTL Our focus
Gate
Layout (VLSI)

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MAIN LANGUAGE CONCEPTS (I)
 Concurrency
 Structure

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MAIN LANGUAGE CONCEPTS (II)
 Procedural
Verilog HDL Basics

Statements
 Time

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USER IDENTIFIERS
 Formed from {[A-Z], [a-z], [0-9], _, $}, but ..
 .. can’t begin with $ or [0-9]
 myidentifier 
 m_y_identifier 
 3my_identifier 
 $my_identifier 
 _myidentifier$ 
 Case sensitivity
 myid  Myid

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COMMENTS
 // The rest of the line is a comment
 /* Multiple line
comment */
 /* Nesting /* comments */ do NOT work */

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VERILOG VALUE SET

 0 represents low logic level or false condition
 1 represents high logic level or true condition
 x represents unknown logic level
 z represents high impedance logic level

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NUMBERS IN VERILOG (I)

<size>’<radix> <value>
No of Binary  b or B Consecutive chars

bits Octal  o or O 0-f, x, z
Decimal  d or D
 8’h ax = 1010xxxx
Hexadecimal  h or H
 12’o 3zx7 = 011zzzxxx111

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NUMBERS IN VERILOG (II)

 You can insert “_” for readability
 12’b 000_111_010_100
 12’b 000111010100
 12’o 07_24 Represent the same number
 Bit extension
 MS bit = 0, x or z  extend this
 4’b x1 = 4’b xx_x1
 MS bit = 1  zero extension
 4’b 1x = 4’b 00_1x

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NUMBERS IN VERILOG (III)

 If size is ommitted it
 is inferred from the value or
 takes the simulation specific number of bits or
 takes the machine specific number of bits
 If radix is ommitted too .. decimal is assumed

 15 = <size>’d 15

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NETS (I)
 Can be thought as hardware wires driven by logic

 Equal z when unconnected
 Various types of nets

 wire
 wand (wired-AND)
 wor (wired-OR)
 tri (tri-state)
 In following examples: Y is evaluated,
automatically, every time A or B changes

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NETS (II)
A wire Y; // declaration
Y assign Y = A & B;
B
wand Y; // declaration
assign Y = A;
A assign Y = B;
Y
B
wor Y; // declaration
assign Y = A;
assign Y = B;
dr
tri Y; // declaration
A Y
assign Y = (dr) ? A : z;

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REGISTERS
 Variables that store values
 Do not represent real hardware but ..
 .. real hardware can be implemented with registers

 Only one type: reg
reg A, C; // declaration
// assignments are always done inside a procedure
A = 1;
C = A; // C gets the logical value 1
A = 0; // C is still 1
C = 0; // C is now 0
 Register values are updated explicitly!!

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VECTORS
 Represent buses
wire [3:0] busA;
reg [1:4] busB;
reg [1:0] busC;
 Left number is MS bit
 Slice management
busC[1] = busA[2];
busC = busA[2:1];  busC[0] = busA[1];
 Vector assignment (by position!!)
busB[1] = busA[3];
busB[2] = busA[2];
busB[3] = busA[1];
busB = busA; 
busB[4] = busA[0];

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INTEGER & REAL DATA TYPES

 Declaration
integer i, k;
real r;
 Use as registers (inside procedures)
i = 1; // assignments occur inside
procedure
r = 2.9;
k = r; // k is rounded to 3
 Integers are not initialized!!
 Reals are initialized to 0.0

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TIME DATA TYPE

 Special data type for simulation time measuring
 Declaration
time my_time;
 Use inside procedure

my_time = $time; // get current sim time
 Simulation runs at simulation time, not real time

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ARRAYS (I)
 Syntax
integer count[1:5]; // 5 integers
reg var[-15:16]; // 32 1-bit regs
reg [7:0] mem[0:1023]; // 1024 8-bit regs
 Accessing array elements
 Entire element: mem[10] = 8’b 10101010;
 Element subfield (needs temp storage):
reg [7:0] temp;
..
temp = mem[10];
var[6] = temp[2];

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ARRAYS (II)
 Limitation: Cannot access array subfield or
entire array at once
var[2:9] = ???; // WRONG!!
var = ???; // WRONG!!
 No multi-dimentional arrays
reg var[1:10] [1:100]; // WRONG!!
 Arrays don’t work for the Real data type
real r[1:10]; // WRONG !!

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STRINGS
 Implemented with regs:
reg [8*13:1] string_val; // can hold up to 13 chars
..
string_val = “Hello Verilog”;
string_val = “hello”; // MS Bytes are filled with 0
string_val = “I am overflowed”; // “I ” is truncated
 Escaped chars:
 \nnewline
 \ttab
 %%%
 \\\
 \““

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LOGICAL OPERATORS
 &&  logical AND
 ||  logical OR
!  logical NOT
 Operands evaluated to ONE bit value: 0, 1 or x
 Result is ONE bit value: 0, 1 or x
A = 6; A && B  1 && 0  0
B = 0; A || !B  1 || 1  1
C = x; C || B  x || 0  x
but C&&B=0

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BITWISE OPERATORS (I)

 &  bitwise AND
|  bitwise OR
~  bitwise NOT
^  bitwise XOR
 ~^ or ^~  bitwise XNOR
 Operation on bit by bit basis

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BITWISE OPERATORS (II)

c = ~a; c = a & b;
Verilog HDL Basics

 a = 4’b1010;
b = 4’b1100;
c = a ^ b;
 a = 4’b1010;
b = 2’b11;

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REDUCTION OPERATORS
 &  AND
 |  OR
 ^  XOR
 ~&  NAND
 ~|  NOR
 ~^ or ^~  XNOR
 One multi-bit operand  One single-bit result

a = 4’b1001;
..
c = |a; // c = 1|0|0|1 = 1

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SHIFT OPERATORS
 >>  shift right
 <<  shift left
 Result is same size as first operand, always zero
filled
a = 4’b1010;
...
d = a >> 2; // d = 0010
c = a << 1; // c = 0100

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CONCATENATION OPERATOR
 {op1, op2, ..}  concatenates op1, op2, .. to single
number
 Operands must be sized !!
reg a;
reg [2:0] b, c;
..
a = 1’b 1;
b = 3’b 010;
c = 3’b 101;
catx = {a, b, c}; // catx = 1_010_101
caty = {b, 2’b11, a}; // caty = 010_11_1
catz = {b, 1}; // WRONG !!
 Replication ..
catr = {4{a}, b, 2{c}}; // catr = 1111_010_101101

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RELATIONAL OPERATORS
 >  greater than
<  less than
 >=  greater or equal than
 <=  less or equal than
 Result is one bit value: 0, 1 or x

1 > 0 1
’b1x1 <= 0 x
10 < z x

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EQUALITY OPERATORS
 ==  logical equality
Return 0, 1 or x
 !=  logical inequality
 ===  case equality
 !==  case inequality Return 0 or 1
 4’b 1z0x == 4’b 1z0x x

 4’b 1z0x != 4’b 1z0x x
 4’b 1z0x === 4’b 1z0x  1
 4’b 1z0x !== 4’b 1z0x  0

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CONDITIONAL OPERATOR
 cond_expr ? true_expr : false_expr
 Like a 2-to-1 mux ..
A
1
Y
Y = (sel)? A : B;
B
0
sel

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ARITHMETIC OPERATORS (I)

 +, -, *, /, %
 If any operand is x the result is x
 Negative registers:
 regs can be assigned negative but are treated as unsigned
reg [15:0] regA;
..
regA = -4’d12; // stored as 216-12 = 65524
regA/3 evaluates to 21861

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ARITHMETIC OPERATORS (II)

 Negative integers:
 can be assigned negative values
 different treatment depending on base specification or not
reg [15:0] regA;
integer intA;
..
intA = -12/3; // evaluates to -4 (no base spec)
intA = -’d12/3; // evaluates to 1431655761 (base spec)

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OPERATOR PRECEDENCE
Use parentheses to
enforce your
priority

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HIERARCHICAL DESIGN
Top Level
E.g.
Module
Full Adder
Sub-Module Sub-Module
1 2
Half Adder Half Adder

Basic Module Basic Module Basic Module
1 2 3

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MODULE
module my_module(out1, ..,
inN);
in1 my_module out1 output out1, .., outM;
in2 out2 input in1, .., inN;
f
.. // declarations
inN outM .. // description of f (maybe
.. // sequential)
endmodule
Everything you write in Verilog must be inside a module

exception: compiler directives

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EXAMPLE: HALF ADDER
A module half_adder(S, C, A, B);

S
output S, C;
B input A, B;
C
wire S, C, A, B;
assign S = A ^ B;
A S
Half assign C = A & B;
B Adder C
endmodule

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EXAMPLE: FULL ADDER

in1 A Half S I1 A Half S sum
Adder 1 Adder
in2 B C I2 B C I3
ha1 ha2 cout
cin
module full_adder(sum, cout, in1, in2, cin);
output sum, cout;
input in1, in2, cin;
wire sum, cout, in1, in2, cin;

Module wire I1, I2, I3; Instance
name name
half_adder ha1(I1, I2, in1, in2);
half_adder ha2(sum, I3, I1, cin);
assign cout = I2 || I3;
endmodule

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HIERARCHICAL NAMES
ha2.A
in1 A Half S I1 A Half S sum

Adder 1 Adder
in2 B C I2 B C I3
ha1 ha2 cout
cin
Remember to use instance names,

not module names

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PORT ASSIGNMENTS
module
 Inputs reg or net net
module
 Outputs reg or net net
module
net net
 Inouts
41
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CONTINUOUS ASSIGNEMENTS
A CLOSER LOOK
 Syntax:
assign #del <id> = <expr>;
optional net type !!

 Where to write them:
 inside a module
 outside procedures
 Properties:
 they all execute in parallel
 are order independent
 are continuously active

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STRUCTURAL MODEL (GATE LEVEL)

 Built-in gate primitives:
and, nand, nor, or, xor, xnor, buf, not, bufif0,
bufif1, notif0, notif1
 Usage:
nand (out, in1, in2); 2-input NAND without delay
and #2 (out, in1, in2, in3); 3-input AND with 2 t.u.
delay
not #1 N1(out, in); NOT with 1 t.u. delay and instance
name
xor X1(out, in1, in2); 2-input XOR with instance name
 Write them inside module, outside procedures

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EXAMPLE: HALF ADDER,

2ND IMPLEMENTATION
A module half_adder(S, C, A, B);

S
output S, C;
B input A, B;
C
wire S, C, A, B;
xor #2 (S, A, B);

and #1 (C, A, B);
Assuming:
• XOR: 2 t.u. delay endmodule
• AND: 1 t.u. delay

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BEHAVIORAL MODEL - PROCEDURES (I)
 Procedures = sections of code that we know they

execute sequentially
 Procedural statements = statements inside a
procedure (they execute sequentially)
 e.g. another 2-to-1 mux implem:
begin
if (sel == 0)
Y = B;
Execution else
Flow Procedural assignments:
Y = A; Y must be reg !!
end

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BEHAVIORAL MODEL - PROCEDURES (II)
 Modules can contain any number of procedures

 Procedures execute in parallel (in respect to each
other) and ..
 .. can be expressed in two types of blocks:
 initial  they execute only once
 always  they execute for ever (until simulation finishes)

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“INITIAL” BLOCKS
 Start execution at sim time zero and finish when
their last statement executes
module nothing;
initial
$display(“I’m first”);
Will be displayed
at sim time 0
initial begin
#50;
$display(“Really?”); Will be displayed
end at sim time 50
endmodule

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“ALWAYS” BLOCKS
 Start execution at sim time zero and continue until
sim finishes

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EVENTS (I)
 @
always @(signal1 or signal2 or ..) begin
..
end
execution triggers every
time any signal changes
always @(posedge clk) begin
..
execution triggers every
end
time clk changes
from 0 to 1
always @(negedge clk) begin
.. execution triggers every
end
time clk changes
from 1 to 0

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EXAMPLES
 3rd half adder implem  Behavioral edge-triggered

module half_adder(S, C, A, B); DFF implem
output S, C; module dff(Q, D, Clk);
input A, B; output Q;
input D, Clk;
reg S,C;
wire A, B; reg Q;
wire D, Clk;
always @(A or B) begin
S = A ^ B; always @(posedge Clk)
C = A && B; Q = D;
end
endmodule
endmodule

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EVENTS (II)
 wait (expr)
always begin
wait (ctrl)
#10 cnt = cnt + 1; execution loops every
#10 cnt2 = cnt2 + 2;
time ctrl = 1 (level
end
sensitive timing control)
 e.g. Level triggered DFF ?

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EXAMPLE
always @(res or posedge clk) begin

res
if (res) begin
a
Y Y = 0;
b W = 0;
end
else begin
c W Y = a & b;
W = ~c;
clk end
end

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TIMING (I)
d
initial begin
#5 c = 1; c
#5 b = 0;
#5 d = c; b
end
0 5 10 15
Time
Each assignment is
blocked by its previous one

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TIMING (II)
d
initial begin
fork c
#5 c = 1;
#5 b = 0; b
#5 d = c;
join 0 5 10 15
end Time
Assignments are
not blocked here

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PROCEDURAL STATEMENTS: IF
E.g. 4-to-1 mux:
module mux4_1(out, in, sel);
output out;
if (expr1) input [3:0] in;
true_stmt1; input [1:0] sel;
reg out;
else if (expr2) wire [3:0] in;
wire [1:0] sel;
true_stmt2;
.. always @(in or sel)
if (sel == 0)
else out = in[0];
def_stmt; else if (sel == 1)
out = in[1];
else if (sel == 2)
out = in[2];
else
out = in[3];
endmodule

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PROCEDURAL STATEMENTS: CASE
E.g. 4-to-1 mux:

module mux4_1(out, in, sel);
case (expr) output out;
input [3:0] in;
input [1:0] sel;
item_1, .., item_n: stmt1; reg out;
item_n+1, .., item_m: stmt2; wire [3:0] in;
.. wire [1:0] sel;
default: def_stmt; always @(in or sel)

case (sel)
0: out = in[0];
endcase 1: out = in[1];
2: out = in[2];
3: out = in[3];
endcase
endmodule

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PROCEDURAL STATEMENTS: FOR

for (init_assignment; cond;
step_assignment)
stmt;
E.g.
module count(Y, start);
output [3:0] Y;
input start;
reg [3:0] Y;
wire start;
integer i;
initial
Y = 0;
always @(posedge start)

for (i = 0; i < 3; i = i + 1)
#10 Y = Y + 1;
endmodule

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PROCEDURAL STATEMENTS: WHILE
E.g.
output [3:0] Y;
input start;
reg [3:0] Y;
wire start;
while (expr) integer i;
stmt; initial
Y = 0;
always @(posedge start) begin

i = 0;
while (i < 3) begin
#10 Y = Y + 1;
i = i + 1;
end
end
endmodule

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PROCEDURAL STATEMENTS: REPEAT
E.g.
output [3:0] Y;
input start;
repeat (times) stmt; reg [3:0] Y;

wire start;
initial
Can be either an Y = 0;
integer or a variable
always @(posedge start)
repeat (4) #10 Y = Y + 1;
endmodule

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STRUCTURAL VS PROCEDURAL
Structural Procedural
 textual description of  Think like C code
circuit
 order does not matter  Order of statements are
important
 Starts with assign  Starts with initial or
statements always statement
 Harder to code  Easy to code

 Need to work out logic  Can use case, if, for
wire c, d; reg c, d;
assign c =a & b; always@ (a or b or c) begin
assign d = c |b; assign c =a & b;
assign d = c |b; end

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STRUCTURAL VS PROCEDURAL
Procedural Structural
wire [3:0]Q;
reg [3:0] Q;
wire [1:0]y;
wire [1:0] y;
assign
always@(y) Q[0]=(~y[1])&(~y[0]),
begin Q[1]=(~y[1])&y[0],
Q=4’b0000; Q[2]=y[1]&(~y[0]),
case(y) begin Q[3]=y[1]&y[0];
2’b00: Q[0]=1;
2’b01: Q[1]=1;
2’b10: Q[2]=1;
Q[0]
2’b11: Q[3]=1;
endcase
end Q[1]
y[0] You don’t Q[0]

Q[2]
have to Q[1]
y[1] work out Q[2] y[0]
Q[3]
logic Q[3] Elshafei y[1]
Nov 16, 2006 Abdul-Rahman 61
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BLOCKING VS NON-BLOCKING
Blocking Non-blocking
 <variable> =  <variable> <=
<statement> <statement>
 Similar to C code  The inputs are stored once

the procedure is triggered
 The next assignment
waits until the present  Statements are executed
one is finished in parallel
 Used for combinational  Used for flip-flops, latches

logic and registers
Do not mix both assignments
in one procedure
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BLOCKING VS NON-BLOCKING
Initial
begin
#1 e=2;
#1 b=1;
#1 b<=0;
e<=b; // grabbed the old b
f=e; // used old e=2, did not wait e<=b

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PROCEDURAL STATEMENTS: FOREVER
Typical example:
clock generation in test modules
module test;
reg clk; Tclk = 20 time units

forever stmt; initial begin
clk = 0;
forever #10 clk = ~clk;
Executes until sim end
finishes
other_module1 o1(clk, ..);
other_module2 o2(.., clk, ..);
endmodule

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MIXED MODEL
Code that contains various both structure and behavioral style

module simple(Y, c, clk, res);
output Y;
input c, clk, res;
reg Y;
wire c, clk, res;
res wire n;
c n Y not(n, c); // gate-level
clk
always @(res or posedge clk)
if (res)
Y = 0;
else
Y = n;
endmodule

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SYSTEM TASKS
Always written inside procedures
 $display(“..”, arg2, arg3, ..);  much like printf(), displays

formatted string in std output when encountered
 $monitor(“..”, arg2, arg3, ..);  like $display(), but .. displays string
each time any of arg2, arg3, .. Changes
 $stop;  suspends sim when encountered
 $finish;  finishes sim when encountered
 $fopen(“filename”);  returns file descriptor (integer); then, you can
use $fdisplay(fd, “..”, arg2, arg3, ..); or $fmonitor(fd, “..”, arg2, arg3,
..); to write to file
 $fclose(fd);  closes file
 $random(seed);  returns random integer; give her an integer as a
seed

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COMPILER DIRECTIVES
 `include “filename”  inserts contents of file into current file;

write it anywhere in code ..
 `define <text1> <text2>  text1 substitutes text2;

 e.g. `define BUS reg [31:0] in declaration part:`BUS
data;
 `timescale <time unit>/<precision>

 e.g. `timescale 10ns/1ns later: #5 a = b;
50ns

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PARAMETERS
in[3:0] p_in[3:0]
out[2:0]
wu
A. Implelementation
without parameters
wd
clk
module dff4bit(Q, D, clk); module dff2bit(Q, D, clk);

output [3:0] Q; output [1:0] Q;
input [3:0] D; input [1:0] D;
input clk; input clk;
reg [3:0] Q; reg [1:0] Q;

wire [3:0] D; wire [1:0] D;
wire clk; wire clk;
always @(posedge clk) always @(posedge clk)

Q = D; Q = D;
endmodule endmodule

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(II)
module top(out, in, clk);
output [1:0] out;
input [3:0] in;
A. Implelementation input clk;
without parameters (cont.)
wire [1:0] out;
wire [3:0] in;
wire clk;
wire [3:0] p_in; // internal

nets
wire wu, wd;
assign wu = p_in[3] & p_in[2];

assign wd = p_in[1] & p_in[0];
dff4bit instA(p_in, in, clk);

dff2bit instB(out, {wu, wd}, clk);
// notice the concatenation!!
endmodule

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(III)
module top(out, in, clk);
B. Implelementation output [1:0] out;
with parameters input [3:0] in;
input clk;
wire [1:0] out;
module dff(Q, D, clk); wire [3:0] in;
wire clk;
parameter WIDTH = 4;
output [WIDTH-1:0] Q; wire [3:0] p_in;
input [WIDTH-1:0] D; wire wu, wd;
input clk;
assign wu = p_in[3] & p_in[2];
reg [WIDTH-1:0] Q; assign wd = p_in[1] & p_in[0];
wire [WIDTH-1:0] D;
wire clk; dff instA(p_in, in, clk);
// WIDTH = 4, from declaration
always @(posedge clk) dff instB(out, {wu, wd}, clk);
Q = D; defparam instB.WIDTH = 2;
// We changed WIDTH for instB only
endmodule
endmodule

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TESTING YOUR MODULES

module top_test;
wire [1:0] t_out; // Top’s signals
reg [3:0] t_in;
reg clk;
top inst(t_out, t_in, clk); // Top’s instance
initial begin // Generate clock

clk = 0;
forever #10 clk = ~clk;
end
initial begin // Generate remaining inputs

$monitor($time, " %b -> %b", t_in, t_out);
#5 t_in = 4'b0101;
#20 t_in = 4'b1110;
#20 t_in[0] = 1;
#300 $finish;
end
endmodule

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LOGIC
 Combination logic function can be expressed as:
logic_output(t) = f(logic_inputs(t))
Combinational
logic_inputs(t) logic_outputs(t)
Logic
 Rules
 Avoid technology dependent modeling; i.e. implement
functionality, not timing.
 The combinational logic must not have feedback.
 Specify the output of a combinational behavior for all
possible cases of its inputs.
 Logic that is not combinational will be synthesized as
sequential.

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LOGIC
 Synthesizable combinational can have following

styles
 Netlist of gate instances and Verilog primitives (Fully

structural)
 Combinational UDP (Some tools)
 Functions
 Continuous Assignments
 Behavioral statements
 Tasks without event or delay control
 Interconnected modules of the above

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NETLIST
 Synthesis tools further optimize a gate netlist specified
in terms of Verilog primitives
 Example:
module or_nand_1 (enable, x1, x2, x3, x4,

y);
input enable, x1, x2, x3, x4;
output y;
wire w1, w2, w3;
or (w1, x1, x2);
or (w2, x3, x4);
or (w3, x3, x4); // redundant
nand (y, w1, w2, w3, enable);
endmodule

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SYNTHESIS OF COMBINATIONAL LOGIC –

GATE NETLIST (CONT.)
 General Steps:
 Logic gates are translated to Boolean equations.
 The Boolean equations are optimized.
 Optimized Boolean equations are covered by library
gates.
 Complex behavior that is modeled by gates is not
mapped to complex library cells (e.g. adder,
multiplier)
 The user interface allows gate-level models to be
preserved in synthesis.

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CONTINUOUS ASSIGNMENTS
Example:
module or_nand_2 (enable, x1, x2, x3, x4, y);
output y;
assign y = !(enable & (x1 | x2) & (x3 | x4));
endmodule

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BEHAVIORAL STYLE
Example:
output y;
reg y;
always @ (enable or x1 or x2 or x3 or x4)
if (enable)
y = !((x1 | x2) & (x3 | x4));
else
y = 1; // operand is a constant.
endmodule
Note: Inputs to the behavior must be included in the event

control expression, otherwise a latch will be inferred.

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FUNCTIONS
Example:
output y;
assign y = or_nand(enable, x1, x2, x3, x4);
function or_nand;
begin
or_nand = ~(enable & (x1 | x2) & (x3 | x4));
end
endfunction
endmodule

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TASKS
Example:
output y;
reg y;
always @ (enable or x1 or x2 or x3 or x4)
or_nand (enable, x1, x2, x3c, x4);
task or_nand;
output y;
begin
y = !(enable & (x1 | x2) & (x3 | x4));
end
endtask
endmodule

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CONSTRUCT TO AVOID FOR

COMBINATIONAL SYNTHESIS
 Edge-dependent event control
 Multiple event controls within the same behavior
 Named events
 Feedback loops
 Procedural-continuous assignment containing event or delay
control
 fork ... join blocks
 wait statements
 External disable statements
 Procedural loops with timing
 Data dependent loops
 Tasks with timing controls
 Sequential UDPs

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SYNTHESIS OF MULTIPLEXORS
 Conditional Operator
module mux_4bits(y, a, b, c, d, sel);

input [3:0] a, b, c, d;
input [1:0] sel; a[3:0]
output [3:0] y; b[3:0]
assign y = y[3:0]
c[3:0]
(sel == 0) ? a :
d[3:0]
(sel == 1) ? b :
(sel == 2) ? c :
(sel == 3) ? d : 4'bx;
sel[1:0]
endmodule

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SYNTHESIS OF MULTIPLEXORS (CONT.)

 CASE Statement
module mux_4bits (y, a, b, c, d, sel);
input [3:0] a, b, c, d;
input [1:0] sel
output [3:0] y;
reg [3:0] y; a[3:0]
always @ (a or b or c or d or sel) b[3:0]
case (sel) y[3:0]
c[3:0]
0: y = a;
1: y = b; d[3:0]
2: y = c;
3: y = d;
default: y = 4'bx;
endcase sel[1:0]
endmodule

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SYNTHESIS OF MULTIPLEXORS (CONT.)

 if .. else Statement
module mux_4bits (y, a, b, c, d, sel);
input [3:0] a, b, c, d;
input [1:0] sel
output [3:0] y;
reg [3:0] y; a[3:0]
always @ (a or b or c or d or sel) b[3:0]
if (sel == 0) y = a; else y[3:0]
c[3:0]
if (sel == 1) y = b; else
if (sel == 2) y = c; else d[3:0]
if (sel == 3) y = d;
else y = 4'bx;
endmodule
sel[1:0]
Note: CASE statement and if/else statements are more preferred and
recommended styles for inferring MUX

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UNWANTED LATCHES
 Unintentional latches generally result from

incomplete case statement or conditional branch
 Example: case statement
always @ (sel_a or sel_b or data_a or data_b)
case ({sel_a, sel_b})
2'b10: y_out = data_a;
2'b01: y_out = data_b;
endcase
The latch is enabled by the "event or" of the cases

under which assignment is explicitly made. e.g. ({sel_a,
sel_b} == 2'b10) or ({sel_a, sel_b} == 2'b01)

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UNWANTED LATCHES (CONT.)
 Example: if .. else statement

always @ (sel_a or sel_b or data_a or data_b)
if ({sel_a, sel_b} == 2’b10)
y_out = data_a;
else if ({sel_a, sel_b} == 2’b01)
y_out = data_b;

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PRIORITY LOGIC
 When the branching of a conditional (if) is not mutually

exclusive, or when the branches of a case statement are not
mutually exclusive, the synthesis tool will create a priority
structure.
 Example:
module mux_4pri (y, a, b, c, d, sel_a, sel_b, sel_c);
input a, b, c, d, sel_a, sel_b, sel_c;
output y;
reg y;
always @ (sel_a or sel_b or sel_c or a or b or c or d)
begin
if (sel_a == 1) y = a; else
if (sel_b == 0) y = b; else
if (sel_c == 1) y = c; else
y = d;
end
endmodule

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VERILOG: SYNTHESIS - SEQUENTIAL LOGIC
 General Rule: A variable will be synthesized as a flip-flop when its
value is assigned synchronously with an edge of a signal.
 Example:
module D_reg4a (Data_in, clock, reset,

Data_out);
input [3:0] Data_in;
input clock, reset;
output [3:0] Data_out;
reg [3:0] Data_out;
always @ (posedge reset or posedge clock)
if (reset == 1'b1) Data_out <= 4'b0;
else Data_out <= Data_in;
endmodule

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REGISTERED COMBINATIONAL LOGIC
 Combinational logic that is included in a synchronous

behavior will be synthesized with registered output.
 Example:
module mux_reg (a, b, c, d, y, select, clock);
input [7:0] a, b, c, d;
output [7:0] y;
input [1:0] select;
reg [7:0] y;
always @ (posedge clock)
case (select)
0: y <= a; // non-blocking
1: y <= b; // same result with =
2: y <= c;
3: y <= d;
default y <= 8'bx;
endcase
endmodule

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VERILOG SHIFT REGISTER
 Shift register can be implemented knowing how the flip-

flops are connected
always @ (posedge clock) begin

if (reset == 1'b1) begin
reg_a <= 1'b0;
reg_b <= 1'b0;
reg_c <= 1'b0;
reg_d <= 1'b0;
end
else begin
reg_a <= Shift_in;
reg_b <= reg_a;
reg_c <= reg_b;
reg_d <= reg_c;
end
end

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VERILOG SHIFT REGISTER
 Shift register can be implemented using concatenation

operation referencing the register outputs
module Shift_reg4 (Data_out, Data_in, clock, reset);

input Data_in, clock, reset;
output Data_out;
reg [3:0] Data_reg;
assign Data_out = Data_reg[0];
always @ (negedge reset or posedge clock) begin
if (reset == 1'b0) Data_reg <= 4'b0;
else Data_reg <= {Data_in, Data_reg[3:1]};
end
endmodule

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VERILOG RIPPLE COUNTER
4-bit Ripple Counter

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VERILOG RIPPLE COUNTER
module ripple_counter (clock, toggle, reset, count);

input clock, toggle, reset;
output [3:0] count;
reg [3:0] count;
Synthesis Result
wire c0, c1, c2;
assign c0 = count[0], c1 = count[1], c2 = count[2];
always @ (posedge reset or posedge clock)

if (reset == 1'b1) count[0] <= 1'b0;
else if (toggle == 1'b1) count[0] <= ~count[0];
always @ (posedge reset or negedge c0)

if (reset == 1'b1) count[1] <= 1'b0;

if (reset == 1'b1) count[2] <= 1'b0;

if (reset == 1'b1) count[3] <= 1'b0;
endmodule

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VERILOG UP/DOWN COUNTER
Functional Specs.
 Load counter with Data_in when load = 1

 Counter counts when counter_on = 1
counts-up when count_up = 1
Counts-down when count_up = 0

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VERILOG UP/DOWN COUNTER (CONT.)
module up_down_counter (clk, reset, load, count_up, counter_on, Data_in,

Count);
input clk, reset, load, count_up, counter_on;
input [2:0] Data_in;
output [2:0] Count;
reg [2:0] Count;
always @ (posedge reset or posedge clk)

if (reset == 1'b1)
Count = 3'b0;
else if (load == 1'b1)
Count = Data_in;
else if (counter_on == 1'b1) begin
if (count_up == 1'b1)
Count = Count +1;
else Count = Count –1;
end
endmodule

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FINITE STATE MACHINE (FSM)
 When the sequence of actions in your design depend on

the state of sequential elements, a finite state machine
(FSM) can be implemented
 FSMs are widely used in applications that require

prescribed sequential activity
 Example:
 Sequence Detector
 Fancy counters
 Traffic Light Controller
 Data-path Controller
 Device Interface Controller
 etc.

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FINITE STATE MACHINE (FSM) (CONT.)
 All state machines have the general feedback structure consisting of:
 Combinational logic implements the next state logic
• Next state (ns) of the machine is formed from the current
state (cs) and the current inputs
 State register holds the value of current state
Next State
Inputs Current
Next-State State
Memory
Logic

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TYPES OF STATE MACHINES

Moore State Machine
ns cs
Inputs Next-State State Output Outputs
Logic Register Logic
 Next state depends on the current state and the inputs but the output
depends only on the present state
 next_state(t) = h(current_state(t), input(t))

 output = g(current_state(t))

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TYPES OF STATE MACHINES (CONT.)

Mealy State Machine
Output Outputs
ns cs Logic
Inputs Next-State State
Logic Register
 Next state and the outputs depend on the current state and the inputs
 next_state(t) = h(current_state(t), input(t))

 output(t) = g(current_state(t), input(t))

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TYPICAL STRUCTURE OF A FSM

module mod_name ( … );
input … ;
output … ;
parameter size = … ;
reg [size-1: 0] current_state;
wire [size-1: 0] next_state;
// State definitions
`define state_0 2'b00
`define state_1 2b01
always @ (current_state or the_inputs) begin
// Decode for next_state with case or if statement
Next State
// Use blocked assignments for all register transfers to ensure Logic
// no race conditions with synchronous assignments
end
always @ (negedge reset or posedge clk) begin
if (reset == 1'b0) current_state <= state_0; State
else current_state <= next_state; Register
end
//Output assignments
endmodule

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SEQUENCE DETECTOR FSM
Functionality: Detect two successive 0s or 1s in the serial input bit stream
reset
reset_state out_bit = 0
0 1
1
FSM
out_bit = 0 read_1_zero read_1_one out_bit = 0
Flow-Chart
0
0 0 1 1
0 read_2_zero read_2_one 1
out_bit = 1 out_bit = 1

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SEQUENCE DETECTOR FSM (CONT.)

module seq_detect (clock, reset, in_bit, out_bit);
input clock, reset, in_bit; always @ (state_reg or in_bit)
output out_bit; case (state_reg)
reset_state:
reg [2:0] state_reg, next_state; if (in_bit == 0)
next_state = read_1_zero;
// State declaration else if (in_bit == 1)
parameter reset_state = 3'b000; next_state = read_1_one;
parameter read_1_zero = 3'b001; else next_state = reset_state;
parameter read_1_one = 3'b010; read_1_zero:
parameter read_2_zero = 3'b011; if (in_bit == 0)
parameter read_2_one = 3'b100; next_state = read_2_zero;
else if (in_bit == 1)
// state register
next_state = read_1_one;
always @ (posedge clock or posedge reset)
else next_state = reset_state;
if (reset == 1)
read_2_zero:
state_reg <= reset_state;
if (in_bit == 0)
else
state_reg <= next_state;
// next-state logic

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SEQUENCE DETECTOR FSM (CONT.)

read_1_one:
if (in_bit == 0)
read_2_one:
if (in_bit == 0)
default: next_state = reset_state;
endcase
assign out_bit = ((state_reg == read_2_zero) || (state_reg == read_2_one)) ? 1 : 0;

endmodule

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VLSI DESIGN(EC 2354)

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VLSI DESIGN(EC 2354)

UNIT II - CIRCUIT CHARACTERIZATION AND SIMULATION

UNIT III - COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN

UNIT IV - CMOS TESTING

UNIT V - SPECIFICATION USING VERILOG HDL

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UNIT I CMOS TECHNOLOGY

CMOS VLSI Design 4th Ed.

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CURRENT VS. VOUT, VIN

5: DC and Transient Response CMOS VLSI Design 4th Ed. 4

LOAD LINE ANALYSIS

5: DC and Transient Response CMOS VLSI Design 4th Ed. 5

LOAD LINE ANALYSIS

5: DC and Transient Response CMOS VLSI Design 4th Ed. 6

5: DC and Transient Response CMOS VLSI Design 4th Ed. 7

Region nMOS pMOS

C Saturation Saturation Vout

5: DC and Transient Response CMOS VLSI Design 4th Ed. 8

 Other gates: collapse

5: DC and Transient Response CMOS VLSI Design 4th Ed. 9

Output Characteristics Input Characteristics

5: DC and Transient Response CMOS VLSI Design 4th Ed. 10

Unity Gain Points

5: DC and Transient Response CMOS VLSI Design 4th Ed. 11

CMOS VLSI Design 4th Ed.

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no longer made of metal SiO2

CMOS VLSI Design 4th Ed.

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Source Gate Drain

CMOS VLSI Design 4th Ed.

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NMOS OPERATION CONT.

CMOS VLSI Design 4th Ed.

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Source Gate Drain

CMOS VLSI Design 4th Ed.

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3: CMOS Transistor Theory

CMOS VLSI Design 4th Ed.

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3: CMOS Transistor Theory

CMOS VLSI Design 4th Ed.

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3: CMOS Transistor Theory

CMOS VLSI Design 4th Ed.

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3: CMOS Transistor Theory

 Similar to current source

CMOS VLSI Design 4th Ed.

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3: CMOS Transistor Theory

CMOS VLSI Design 4th Ed.

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3: CMOS Transistor Theory

CMOS VLSI Design 4th Ed.

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NMOS I-V SUMMARY