De Lab-Manual PDF

DIGITAL ELECTRONICS [15ECL38] 1
R.N.SHETTY INSTITUTE OF TECHNOLOGY

Channasandra, Bangalore-560098
D EPAR TMEN T OF
E LECTRO NICS A ND C OMMUN ICATION
E NG IN EER ING
DIGITAL ELECTRONICS [15ECL38]

LABORATORY MANUAL
NAME:……………………………………………………
USN:………………………………………………………
SEMESTER:……………………………………………..
SECTION…………………………………………………
DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

PROGRAM EDUCATIONAL OUTCOMES (PEOs)

Upon successful completion of the program, the student will be able to
PEO1. Gain employment in private, public and government organizations.
PEO2. Develop knowledge required to pursue higher studies in premier
institutions.
PEO3. Acquire technical knowledge to involve in Research and Development
in the field of Electronics & Communication Engineering and multi-
disciplinary areas.
PEO4. Acquire excellence and leadership qualities to emerge as an
Entrepreneur.
PROGRAM OUTCOMES (POs)

Engineering Graduates will be able to:
1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex engineering
problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems
and design system components or processes that meet the specified needs with
appropriate consideration for the public health and safety, and the cultural, societal, and
environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and
research methods including design of experiments, analysis and interpretation of data,
and synthesis of the information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and

modern engineering and IT tools including prediction and modeling to complex

engineering activities with an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal and cultural issues and the consequent responsibilities
relevant to the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and
need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities
and norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or
leader in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and
write effective reports and design documentation, make effective presentations, and give
and receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member
and leader in a team, to manage projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to
engage in independent and life-long learning in the broadest context of technological
change.

Digital Electronics Lab -15ECL38
SYLLABUS
Sub Code: 15ECL38 IA Marks: 20

Hrs/Week: 03 Exam hours: 03
Total Hrs: 42 Exam Marks:
80
1. To verify
(a) Demorgan’s Theorem for 2 variables
(b) The sum-of product and product-of-sum expressions using universal gates.
2. To design and implement
(a) Full Adder using basic logic gates.
(b) Full subtractor using basic logic gates.
3. To design and implement 4-bit Parallel Adder/ subtractor using IC 7483.
4. Design and Implementation of 4-bit magnitude comparator using IC 7485.
5. To realize
(a) 4:1 Multiplexer using gates
(b) 3-variable function using IC 74151(8:1 MUX)
6. 1:8 Demux and 3:8 Decoder using IC74138
7. To realize the following flip-flops using NAND Gates.
(a) Clocked SR Flip-Flop (b) JK Flip-Flop
8. To realize the following shift registers using IC7474
(a) SISO (b) SIPO (c)PISO (d) PIPO
9. To realize the Ring Counter and Johnson Counter using IC7476
10. To realize the Mod-N Counter using IC7490.
11. To simulate Full-Adder using simulation tool.
12. To simulate Mod-8 synchronous UP/DOWN counter using simulation tool.

PRE-REQUISITE EXPERIMENT
VERIFICATION OF LOGIC GATES
Aim: To study about logic gates and verify their truth tables.
Components required:
SL No. COMPONENT SPECIFICATION QTY
1. 2 Input AND Gate IC 7408 1
2. 3 Input AND Gate IC 7411 1
3. 2 Input OR Gate IC 7432 1
4. NOT Gate IC 7404 1
5. 2 Input EX-OR Gate IC 7486 1
6. 2 Input NAND Gate IC 7400 1
7. 3 Input NAND Gate IC 7410 1
8 2 Input NOR Gate IC 7402 1
9. IC TRAINER KIT - 1
10. PATCH CORDS - -
Theory: Logic gates are the basic components in digital electronics. A logic gate is a general
purpose electronic device used to construct logic circuits. All logic gates have inputs and
outputs. The state of the output is set by the input states using different rules depending on
the type of gate. The different types of gates have different shaped circuit symbols.
There are three basic logic gates: AND, OR and NOT. AND, OR logic gates can have ‘n’
inputs (n≥ 2) and gives single output. NOT gate also called as “inverter”, has single input and
produces single output.
These basic logic gates are implemented as small-scale integrated circuits (SSICs) or as part
of more complex medium scale (MSI) or very large-scale (VLSI) integrated circuits. Digital
IC gates are classified not only by their logic operation, but also the specific logic-circuit
family to which they belong. Each logic family has its own basic electronic circuit upon
which more complex digital circuits and functions are developed. The following logic
families are the most frequently used.
TTL Transistor-transistor logic

ECL Emitter-coupled logic
MOS Metal-oxide semiconductor
CMOS Complementary metal-oxide semiconductor

TTL and ECL are based upon bipolar transistors. TTL has a well established popularity
among logic families. ECL is used only in systems requiring high-speed operation. MOS and
CMOS, are based on field effect transistors. They are widely used in large scale integrated
circuits because of their high component density and relatively low power consumption.
CMOS logic consumes far less power than MOS logic. There are various commercial
integrated circuit chips available. TTL ICs are usually distinguished by numerical
designation as the 5400 and 7400 series.
Each logic family is characterized by several circuit parameters.
Fan-out specifies the number of standard loads that the output of a gate can drive without
impairing its normal operation. A standard load is usually defined as the amount of current
needed by an input of another gate in the same logic family. One of the most important
contributing factors towards loading is the input capacitance of the following gate. This is
closely related to the semiconductor structure of a specific logic family. For instance, the
standard TTL gate will typically have a maximum fanout of 50. Exceeding the specified
maximum fan-out (or load) may cause a malfunction because the circuit cannot supply the
power demanded from it.
Power dissipation is the supplied power required to operate the desired logic function. This
parameter does not include the power delivered from another gate. Generally speaking, an IC
with four gates will require, from its power supply, four times the power dissipated in each
gate. Power dissipation is an important parameter. A complex electronic system may have
many thousands of gates. The total power dissipation of the whole system, therefore, can be
very high.
Propagation delay is the time delay for a signal transition to propagate from input to output
when the binary input signals change in value. The signals passing through a gate take a
certain amount of time to propagate from its inputs to the output. This interval of time is
defined as the propagation delay of the gate. When the signals travel through a series of
gates, the sum of the propagation delays through the gates is the total propagation delay of
the circuit. Both input and output signals are not ideal signals, i.e. they have non-zero rise
and fall times.
Noise margin is the maximum noise voltage added to the input signal of a digital circuit
without causing an undesirable change in the output.
DEFINITION OF LOGIC GATES
AND gate: It is a basic logic gate that produces high state output only when all the inputs are
logic high or at logic ‘1’ state. It performs logical multiplication.
OR gate: It is a basic logic gate that produces high state output if any one of the inputs is
logic high. It performs logical addition.

NOT gate: It is a basic logic gate that produces an inverted output for a given input.
There are two universal gates: NAND and NOR gates.
NAND gate: It is an universal logic gate that produces high state output if any one of the
inputs is at logic ‘1’ state. It is the complement of AND gate.
NOR gate: It is a universal logic gate that produces high output only when all the inputs are
logic high. It is the complement of OR gate.
Ex-OR gate: It is a logic gate that that produces high state output if it has odd number of
ones.
Ex-NOR gate: It is a logic gate that that produces high state output if it has even number of
ones. It is the complement of Ex-OR gate.
Procedure:
1. Identify the IC required and place on the trainer kit such that the notch of the IC is
facing towards the Vcc, where the IC pin no. 7 and 14 are connected to ground and
VCC respectively.
2. Connections are made as per the logic diagram
3. Switch on the power supply.
4. Apply suitable logical inputs as per the truth table and verify the output.
2 INPUT AND GATE :

PIN DIAGRAM:
SYMBOL:

3 AND GATE:
2 OR GATE:
NOT Gate:
SYMBOL: PIN DIAGRAM:

2 INPUT EX-OR GATE:

2 INPUT NAND GATE:

3 INPUT NAND GATE:

NOR GATE:
II Realization of basic gates using NOR and NAND gates:

NOT GATE NOT GATE:
OR GATE
AND GATE:
AND GATE
OR GATE:
NOR GATE:
NAND GATE

PROCEDURE :
 Check the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Provide the input data via the input switches and observe the output on output LEDs
VIVA QUESTIONS:
1. Why NAND & NOR gates are called universal gates?

2. Realize the EX – OR gates using minimum number of NAND gates.
3. Give the truth table for EX-NOR and realize using NAND gates?
4. What are the logic low and High levels of TTL IC’s and CMOS IC’s?
5. Compare TTL logic family with CMOS family?
6. Which logic family is fastest and which has low power dissipation?

EXPERIMENT NO. 1
IMPLEMENTATION OF DEMORGAN’S THEOREM AND SOP/POS
EXPRESSIONS
Aim: 1. To verify
(a) Demorgan’s Theorem for 2 variables
Components required: IC 7400, IC 7402, IC 7404, IC 7408, IC 7432, Patch Cords and
Trainer Kit.
Theory: Augustus De Morgan, a 19th-century British mathematician developed a pair of

important rules regarding group complementation in Boolean algebra referred to as
Demorgan’s theorems. Applications of these rules include simplification of
logical expressions in computer programs and digital circuit designs. They are as follows.
(i) AB  A  B
Statement: The complement of a product is equal to the sum of complements.
(ii) A  B  A. B
Statement: The complement of a sum term is equal to the product of complements.
In a Boolean function, the variables appear either in complemented or an uncomplemented
form. Each occurrence of a variable in either form is called a “literal”. These literals can be
grouped either as a product term or sum term. A product term is defined as either a literal or
product of literals (also called conjunction). A sum term is defined as either a literal or sum
of literals (also called disjunction). These literals and terms are arranged in two forms.
(i) Sum of Products (SoP): It is the group of product terms ORed together. If each
product term (also called minterm) in SoP contains all literals, then it is called
canonical SoP.
(ii) Product of Sum (PoS): It is the group of sum terms ANDed together. If each sum
term (also called maxterm) in PoS contains all literals, then it is called canonical
PoS.
Procedure:
VCC respectively.
2. Connections are made as per the logic diagram.
4. Apply suitable logical inputs as per the truth table and verify the output.
NOTE: If correct output is not obtained, each and every gate is to be checked separately and
even then if the output is not obtained, then IC has to be replaced.
(a) Verification of Demorgan’s theorem for two variables

Logic diagram:
Truth table:
(i) AB  A  B (ii) A  B  A. B
A B A B AB A B A B A B A B A. B
0 0 1 1 1 1 0 0 1 1 1 1
0 1 1 0 1 1 0 1 1 0 0 0
1 0 0 1 1 1 1 0 0 1 0 0
1 1 0 0 0 0 1 1 0 0 0 0
1) Sum of product (SOP): Y=BD+AD
Y=F(A,B,C,D) = ∑(5,7,9,11,13,15)
Simplification using K-map:

ii)Implementation Using NAND gates iii) Implementation Using NOR Gates
2) Product of Sum (POS): Y=(A+B)D
Y=F(A,B,C,D) = П(0,1,2,3,4,6,8,10,12,14)
Simplification using K-map:
ii) Implementation Using NAND gates iii) Implementation Using NOR Gates

Truth table:
Result: Truth Tables of the given expressions are verified.

Viva Questions:
1. State Demorgan’s theorem for three variables.
2. What is sum of product and product of sum?
3. Anything ORed with its own complement is equal to
A) 0 B) 1 C) Itself D) Its complement.
4. By using DeMorgan's theorem, X = A(B + C) is simplified to ________.
A) X = A(B + C) B) X = ABC C) X = A + B + C D) X = A + BC
5. A NOR gate with a bubble on one of its inputs is equivalent to
A) a NOR with bubbles in its inputs.
B) a NAND with bubbles on its inputs.
C) a NAND with a bubble on one input.
D) a NOR.
6. Anything that is complemented twice is equal to
A) 0. B) 1. C) Itself. D) Its complement.
7. An AND gate with inverted inputs functions as
A) OR gate. B) NAND gate. C) Inverter. D) NOR gate.
8. For a simplified Boolean expression f = AD' + AC + B'C, minimum no. of NAND
gates required is
A) 5 B) 6 C) 4 D) 8
9. The Boolean function A + BC is a reduced form of
A) AB + BC B) (A + B)(A + C) C) A’B + AB’C D) (A + C)B
10. What is Gray code? Why this code is used in K-map?

EXPERIMENT NO. 2
ADDERS AND SUBTRACTORS
Aim: To design and implement the following Adder and subtractor using logic gates.
(a) Full Adder using basic logic gates.
(b) Full subtractor using basic logic gates.
Components Required: IC 7486, IC 7432, IC 7408, Patch Cords and Trainer Kit.
Theory: A combinational circuit that performs the addition of two bits is called a half adder.
A half adder needs two binary inputs and two binary outputs. A half adder has no provision
to add a carry from the lower order bits when binary numbers are added. When two input bits
and a carry are to be added the number of input bits becomes three and the input combination
increases to eight. For this full adder is used.
A combinational circuit that performs the addition of three bits is a full adder. It consists of
three inputs and two outputs. Like half adder it also has a sum bit and a carry bit. The new
carry generated is represented by ‘Cout’ and the carry generated from the previous addition is
represented by ‘Cin’.
When two input bits and a borrow have to be subtracted the number of input bits equal to
three and the input combinations increases to eight, for this a full subtractor is used.
Procedure:
VCC respectively.
2. Connections are made as per the logic diagram
Apply suitable logical inputs as per the truth table and verify the output.
1.FULL ADDER
TRUTH TABLE BOOLEAN EXPRESSIONS:
INPUTS OUTPUTS
A B C Sum Carry Sum= A  B  C
0 0 0 0 0 Carry=A B + B C+ A C
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Logic Circuit
2. FULL SUBTRACTOR
TRUTH TABLE BOOLEAN EXPRESSIONS:
INPUTS OUTPUTS D= A  B  C
A B Cin D Br
_ _
0 0 0 0 0 Br= A B + B Cin + A Cin
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Logic Circuit
RESULT : The truth table of the above circuits are verified.
VIVA QUESTIONS:
1)What is a half adder?
2)What is a full adder?
3)What are the applications of adders?
4) What is a half subtractor?
5)What is a full subtractor?
6)What are the applications of subtractors?
7)Obtain the minimal expression for above circuits.
8)Realize a full adder using two half adders
9) Realize a full subtractors using two half subtractors

EXPERIMENT NO. 3 : PARALLEL ADDER AND SUBTRACTOR
AIM : To design and set up the following circuit using IC 7483.

i) A 4-bit binary parallel adder.
ii) A 4-bit binary parallel subtractor.
LEARNING OBJECTIVE:
 To learn about IC 7483 and its internal structure.
 To realize a subtractor using adder IC 7483
COMPONENTS REQUIRED :
IC 7483, IC 7486, Patch Cords & IC Trainer Kit.
THEORY: The Full adder can add single-digit binary numbers and carries. The largest sum
that can be obtained using a full adder is 112. Parallel adders can add multiple-digit numbers.
If full adders are placed in parallel, we can add two- or four-digit numbers or any other size
desired. Figure below uses STANDARD SYMBOLS to show a parallel adder capable of
adding two, two-digit binary numbers The addend would be on A inputs , and the augend on
the B inputs. For this explanation we will assume there is no input to C0 (carry from a
previous circuit)
To add 102 (addend) and 012 (augend), the addend inputs will be 1 on A2 and 0 on A1. The
augend inputs will be 0 on B2 and 1 on B1. Working from right to left, as we do in normal
addition, let’s calculate the outputs of each full adder. With A1 at 0 and B1 at 1, the output of
adder1 will be a sum (S1) of 1 with no carry (C1). Since A2 is 1 and B2 is 0, we have a sum
(S2) of 1 with no carry (C2) from adder1. To determine the sum, read the outputs (C2, S22,
and S1) from left to right. In this case, C2 = 0, S2 = 1, and S1 = 1. The sum, then, of 102 and
012 is 0112. To add four bits we require four full adders arranged in parallel. IC 7483 is a 4-
bit parallel adder whose pin diagram is shown.
MSB LSB
Cin
INPUTS A3 A2 A1 A0
B3 B2 B1 B0
OUTPUT Cout S3 S2 S1 S0

IC 7483 pin
i) 4-Bit Binary Adder

An Example : 7+2=11 (1001)
 7 is realized at A3 A2 A1 A0 = 0111
 2 is realized at B3 B2 B1 B0 = 0010
Sum = 1001
ADDER CIRCUIT:
PROCEDURE :
 Check all the components for their working.
 Apply augend and addend bits on A and B and cin=0.
 Verify the results and observe the outputs.
ii) 4-BIT BINARY SUBTRACTOR.

Subtraction is carried out by adding 2’s complement of the subtrahend.
Example : 8 – 3 = 5 (0101)
 8 is realized at A3 A2 A1 A0 = 1000
 3 is realized at B3 B2 B1 B0 through X-OR gates = 0011
 Output of X-OR gate is 1’s complement of 3 = 1100
 2’s Complement can be obtained by adding Cin = 1
Therefore
Cin = 1

A3 A2 A1 A0 = 1 0 0 0
B3 B2 B1 B0 = 1 1 0 0
S3 S2 S1 S0 = 0 1 0 1
Cout = 1 ( Ignored )
PROCEDURE :
 Apply Minuend and sutrahend bits on A and B and cin=1.
 Verify the results and observe the outputs
Result: Truth Tables of Parallel adder and subtrator are verified.

EXPERIMENT NO. 4
STUDY OF IC 7485 4- BIT MAGNITUDE COMPARATOR
Aim: To design and implement 4-bit magnitude comparator using IC 7485.
Components Required: IC 7485, Patch cords and Trainer kit.
Theory: A digital comparator or magnitude comparator is a hardware electronic device

that takes two numbers as input in binary form and determines whether one number is
greater than, less than or equal to the other number. Comparators are used in central
processing unit s (CPUs) and microcontrollers (MCUs).
IC 7485: The IC 7485 is a 4-bit magnitude comparator that can be expanded to almost any
length. It compares two 4 bit binary and produces three magnitude results.
Procedure:
1. Make the connections as per the Pin diagram.
2. Verify the output with the truth table.
TO COMPARE THE GIVEN DATA USING 7485 CHIP.
Truth Table
RESULT : Four bit comparator IS verified using magnitude comparator IC7485

VIVA QUESTIONS:
1) What is a comparator?
2) What are the applications of comparator?
3) Derive the Boolean expressions of one bit comparator and two bit comparators.
4) How do you realize a higher magnitude comparator using lower bit comparator
5. Design a 2 bit comparator using a single Logic gates?
6. Design a 8 bit comparator using a two numbers of IC 7485?

EXPERIMENT NO. 5
MUX - STUDY OF ICs 744051
Aim: To realize
(a) 4:1 Multiplexer using gates.
(b) 3-variable function using IC 74151(8:1 MUX).
Components required: IC 744051, IC 7404, IC 7411, IC 7432, Patch cords and Trainer kit.
Theory: A multiplexer is combinational circuit that selects binary information from one of
many input lines and directs it to a single output line. The selection of a particular input line
is controlled by a set of selection lines. Normally there are 2n input lines and n selection lines
whose bit combinations determine which input is selected. An electronic multiplexer can be
considered as a multiple-input, single-output switch. A multiplexer is also called a data
selector.
Conversely, a demultiplexer (or demux) is a device taking a single input signal and
selecting one of many data-output-lines, which is connected to the single input. A
demultiplexer has one data input, n select lines, and 2n output lines. A demultiplexer is also
called a data distributor.
Procedure:
3. Make the connections as per the logic diagram.
4. Verify the output with the truth table.
(a) 4:1 multiplexer using Logic gates.
Logic diagram:

Truth Table of 4:1 MUX
Select lines Output

S1 S0 Z
0 0 Y0
0 1 Y1
1 0 Y2
1 1 Y3
The output expression is
8:1 Multiplexer
In this experiment, 8:1 MUX is implemented using IC 74HC4051. It is a popular 16-pin DIP
IC which provides eight inputs, three select lines and an output Z. The output Z selects one
of the eight inputs Yi based on the select lines (S2,S1,S0) where S2 is the MSB. Vcc is on pin
16 and GND is on pin 8. Pin 3 is the output. The enable is on pin 6 which is active low.
Pin Details of IC 74HC4051:
Logic Symbol of 8:1 MUX Truth Table

Inputs Output
Ē S2 S1 S0 Z
1 X X X 0
0 0 0 0 Y0
0 0 0 1 Y1
0 0 1 0 Y2
0 0 1 1 Y3
0 1 0 0 Y4
0 1 0 1 Y5
0 1 1 0 Y6
0 1 1 1 Y7

b) 3-variable function using IC 744051(8:1 MUX).
Realize the following expression using IC 744051

F (A,B,C) = ∑m (1,3,5,6)
Truth table
A B C Z
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Result: (i) Truth Tables of 4:1, 8:1 MUX is verified.

(ii) Realization of 3 variable function using IC744051 is performed.

Experiment 6
Realize 1:8 Demux and 3:8 Decoder using IC 74138
Aim: To study Decoder and Demultiplexer

Components required: IC 74139, IC 74138 and digital IC trainer kit.
Theory:
Demultiplexer does the reverese operation of a multiplexer. It has one input and many
outputs.the select input lines load the input to the corresponding output pin. Demultiplexers
function as decoders also. The number at select lines gets decoded as output.
Decoders are similar to demultiplexers but without any data input. A decoder is a circuit that
changes a code into a set of signals. In other words, decoder is a combinational circuit that
converts the input of one code format into another coded format at the output side. It can
process n inputs and generate 2n outputs.
The term is often used in reference to MPEG-2 video and sound data, which must be decoded
before it is output. Most DVD players, for example, include a decoder card whose sole
function is to decode MPEG data. It is also possible to decode MPEG data in software, but
this requires a powerful microprocessor.
1) 2 to 4 line decoder (active low):
The pin configuration, logic circuit and truth table of IC 74139 (active low outputs), a
dual 2 to 4 line decoder is as shown below:
Truth table: Logic circuit for 2 to 4 line decoder

(Active low ):

2) 2 to 4 line decoder (active high):
Logic circuit for 2 to 4 line decoder Truth table:

(Active high):
3) 3 to 8 line decoder: IC 74138
The pin configuration, logic circuit and truth table of IC 74138 (active low outputs), is as
shown below:
Pin Details:
 A0 – A2 : input pins/select pins
 G1 : Active high enable pin
 G2A, G2B : Active low enable pin
 Y0-Y7 : Active low outputs

Truth table:
Demultiplexer:
The demultiplexer takes one single input data line and then switches it to any one of a
number of individual output lines one at a time.
 1-to-8 Demultiplexer
 The below figure shows the block diagram of a 1-to-8 demultiplexer that consists of
single input D, three select inputs S2, S1 and S0 and eight outputs from Y0 to Y7.
 It is also called as 3-to-8 demultiplexer due to three select input lines. It distributes
one input line to one of 8 output lines depending on the combination of select inputs.
The truth table for this type of demultiplexer is shown below. The input D is connected with
one of the eight outputs from Y0 to Y7 based on the select lines S2, S1 and S0.

1:8 Demultiplexer using IC 74138:
Truth table:
Procedure
 Connect the IC 74138 as 1:8 Demultiplexer. For this, apply data input at G1, connect
logic 0 to G2 and G3. Apply 000 through 111 at the select lines A0A1A2 and observe
the outputs and verify its demux operation.
 Observe the outputs and verify the operation as 3:8 decoder.
Result: The Function of DEMUX and DECODER is verified.

EXPERIMENT-7
FLIP-FLOPS
Aim: To realize the following flip-flops using NAND Gates.

(a) Clocked SR Flip-Flop (b) JK Flip-Flop
Components Required: IC 7400, IC trainer kit and patch cords
THEORY:
Logic circuits that incorporate memory cells are called sequential logic circuits; their output
depends not only upon the present value of the input but also upon the previous values.
Sequential logic circuits often require a timing generator (a clock) for their operation.
The latch (flip-flop) is a basic bi-stable memory element widely used in sequential logic
circuits. Usually there are two outputs, Q and its complementary value.
Some of the most widely used latches are listed below.
SR LATCH:
An S-R latch consists of two cross-coupled NOR gates. An S-R flip-flop can also be design
using cross-coupled NAND gates as shown. The truth tables of the circuits are shown below.
A clocked S-R flip-flop has an additional clock input so that the S and R inputs are
active only when the clock is high. When the clock goes low, the state of flip-flop is latched
and cannot change until the clock goes high again. Therefore, the clocked S-R flip-flop
is also called “enabled” S-R flip-flop.
A D latch combines the S and R inputs of an S-R latch into one input by adding an
inverter. When the clock is high, the output follows the D input, and when the clock
goes low, the state is latched.
A S-R flip-flop can be converted to T-flip flop by connecting S input to Qb and R to Q.
 JK flip Flop is the most widely used of all the flip-flop designs and is considered to
be a universal flip-flop circuit. The sequential operation of the JK flip flop is exactly
the same as for the previous SR flip-flop with the same “Set” and “Reset” inputs. The
difference this time is that the “JK flip flop” has no invalid or forbidden input states
of the SR Latch even when S and R are both at logic “1”.
 The JK flip flop is basically a gated SR flip-flop with the addition of a clock input
circuitry that prevents the illegal or invalid output condition that can occur when both
inputs S and R are equal to logic level “1”. Due to this additional clocked input, a JK
flip-flop has four possible input combinations, “logic 1”, “logic 0”, “no change” and
“toggle”.

CIRCUIT DIAGRAM :
1) S-R LATCH:
(A) LOGIC DIAGRAM (B) SYMBOL
TRUTH TABLE
S R Q Q b
0 0 Q Qb
0 1 0 1
1 0 1 0
1 1 0* 0*
SR LATCH: TRUTH TABLE
S R Q Q
0 0 1* 1*
0 1 1 0
1 0 0 1
1 1 Q Q

2)GATED SR FLIP FLOP:
CIRCUIT DIAGRAM :
(A) LOGIC DIAGRAM (B) SYMBOL
TRUTH TABLE
S R Q Q
0 0 Q Q
0 1 0 1
1 0 1 0
1 1 0* 0*
3. JK-FLIP FLOP
LOGIC DIAGRAM TRUTH TABLE
Q Commen
Clock J K Q
t
Q No
1 0 0 Q
Change
1 0 1 0 1 Reset
1 1 0 1 0 Set
Q
1 1 1 Q Toggle

4)JK MASTER SLAVE FLIP FLOP
LOGIC DIAGRAM
TRUTH TABLE
PRE = CLR = 1
Cloc Q
J K Q Comment
k
1 0 0 Q Q No Change
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 Toggle
PROCEDURE :
 Verify the Truth Table and observe the outputs.
Result: All the Flip-Flops has been verified.
QUESTIONS:-
1. What is the difference between Flip-Flop & latch?
2. Give examples for synchronous & asynchronous inputs?
3. What are the applications of different Flip-Flops?
4. What is the advantage of Edge triggering over level triggering?
5. What is the relation between propagation delay & clock frequency of flip-flop?
6. What is race around in flip-flop & how to over come it?

Experiment No: 8
Implementation of Shift Registers Using Flip-Flops
AIM: To implement different types of shift registers like Serial In Serial Out [SISO], Serial
In Parallel Out [SIPO], Parallel In Parallel Out [PIPO] and Parallel In Serial Out
[PISO] using D-flip flops and to verify their observation table.
.
COMPONENTS REQUIRED :
 Logic gates (IC) trainer kit.
 Connecting patch chords.
 ICs 7474, 7432
THEORY:
A register is nothing but a set of flip-flop that can be used to store a binary number. A shift
register is register which accepts a binary number and shifts it left or right.The data can be
entered to the shift register either in serial or in parallel.
Uses
Shift Registers are used for data storage or for the movement of data and are therefore
commonly used inside calculators or computers to store data such as two binary numbers
before they are added together, or to convert the data from either a serial to parallel or
parallel to serial format. Several bidirectional shift registers could also be connected in
parallel for a hardware implementation of a stack. The individual data latches that make up a
single shift register are all driven by a common clock ( Clk ) signal making them
synchronous devices.
IC of 7474 Pin diagram of 7474

FUNCTION TABLE FOR IC 7474:
Serial-in and Serial-out (SISO)
These are the simplest kind of shift registers. The data string is presented at 'Data Input', and
is shifted right one stage each time data advances. At each advance, the bit on the far left (i.e.
'Data In') is shifted into the first flip-flop's output. The bit on the far right (i.e. 'Data Out') is
shifted out and lost.
Observation Table:

Serial-in, parallel-out (SIPO)
This configuration allows conversion from serial to parallel format. Data is input serially, as
described in the SISO section above. Once the data has been clocked in, it may be either read
off at each output simultaneously, or it can be shifted out
Observation Table:
Parallel -in, parallel-out (PIPO)

Observation Table:
Parallel-in, Serial-out (PISO)
Observation Table:
Clock Inputs Output

pulse
D0 D1 D2 D3
0 1 0 0 0
0 0 1 0 0
0 0 0 1 1
0 0 0 0 0

PROCEDURE :
 Check the components for their working.
 Connect all Preset and Clear pin to Vcc.
 Provide the input data via the input switches and clock to observe the output on
output LEDs
RESULT: All the Shift registers function is verified.

Experiment No 9
RING COUNTER AND JOHNSON COUNTER
Components Required
Pin Description of 7476
Procedure:
1. Initially clear the outputs of all flip flops by setting clear=0,Pr0= Pr1= Pr2= Pr3=1.
2. Then Set clr=1, Pr0=0 ad Pr1= Pr2= Pr3=1, to load the data 1000.
3. Again Set clr=1, Pr0= Pr1= Pr2= Pr3=1.
4. Then go on applying the clock pulses and observe the output as listed in the truth table.


Procedure:
1. Initially clear the outputs of all flip flops by setting clear=0,Pr =1.
2. Then Set clr=1, Pr=1, to load the data 1000.
3. Then go on applying the clock pulses and observe the output as listed in the truth table.
RESULT:4 Bit ring counter and johnson counter are realized using IC 7476 .

EXPERIMENT- 10
MOD-N COUNTER USING IC 7490
Aim: To realize the Mod-N Counter using IC7490.
Components required: IC 7490, IC trainer kit, patch cords
Theory: Counter is a sequential circuit which is used for counting pulses. Counter is the
widest application of flip-flops. It is a group of flip-flops with a clock signal applied.
Counters are of two types. Asynchronous or ripple counters and Synchronous counters.
Depending on the way in which the counting progresses, the synchronous or asynchronous
counters are classified as follows −Up counters, Down counters and Up/Down counters
The 2-bit ripple counter is called as MOD-4 counter and 3-bit ripple counter is called as
MOD-8 counter. So in general, an n-bit ripple counter is called as modulo-N counter.
Where, MOD number = 2n. Application of counters are Frequency counters, Digital
clock, Time measurement, A to D converter, Frequency divider circuits etc.
The 7490 is a BCD/decade counter that consists of four Master-Slave JK flip-flops internally
connected to provide Mod-2 (Divide by 2 ) and Mod-5 Counter(Divide by 5). It can count
from 0 to 9 cyclically in its natural mode. It counts the input pulses and the output is received
as a 4-bit binary number through pins QA, QB, QC and QD. The binary output is reset to 0000
at every tenth pulse and count starts from 0 again. The Mod of the IC 7490 is set by
changing the RESET pins R0 (1), R0 (2), R9 (1), R9 (2). It is possible to increase the counting
capability of a Decade number by connecting more ICs n series.
Procedure:
1. Connections are made as per the logic diagram.
2. Apply the clock pulses and verify the truth table.
Pin Diagram:

(a) IC 7490 as BCD/ Decade Counter
Truth Table:
(b) IC 7490 as MOD-7 COUNTER:

Truth Table:
Clk QD QC QB QA
1 0 0 0 0
2 0 0 0 1
3 0 0 1 0
4 0 0 1 1
5 0 1 0 0
6 0 1 0 1
7 0 1 1 0
(c) IC 7490 as MOD-5 COUNTER:
Truth Table:
Result: Mod-N Counter using IC7490 is realized and verified.

INTRODUCTION TO MULTISIM SIMULATION TOOL
Multisim is an electronic schematic capture and simulation program which is part of circuit
design programs. Multisim was originally created by a company named Electronics
Workbench, which is a division of National Instruments. Multisim is an industry-standard,
best-in-class SPICE simulation environment. It is the teaching solution to build expertise
through practical application in designing, prototyping, and testing of analog, digital and
power electronic circuits. The Multisim helps in prototyping various circuits and optimize it
before realizing any circuit on printed circuit board (PCB).
Multisim can be used to simulate digital, analog and power electronics circuits based on the
application. This helps in faster realization providing graphical visualization. It is used across
all the industries for faster simulation of the circuits. Multisim has over 36,000 components
validated by leading semiconductor manufacturers. The Multisim library of has up-to-date
amplifiers, diodes, transistors, and switch mode power supplies paired with advanced
simulation makes it possible to cover a wide variety of application specific design.
Multisim includes microcontroller simulation, integrated circuits and also provide an option
to import and export features to the Printed Circuit Board layout software for further
realization of the hardware board. Multisim is widely used in academia and industry for
circuit’s education, electronic schematic design and SPICE simulation. Students can use
Multisim to optimize their circuit design performance and save prototype iterations in
different application areas such as analog design, power electronics, renewable energy, and
complete analog/digital system level designs.

STEPS FOR CONDUCTING EXPERIMENTS USING ‘MULTSIM 14.0’

SIMULATION TOOL
1. Click on ‘Multisim 12.0’ on the desktop.
2. Open/Create Schematic
A blank schematic Circuit 1 is automatically created. To create a new schematic

click on File – New – Schematic Capture. To save the schematic click on File /Save
As. To open an existing file click on File/ Open in the toolbar.
3. Place Components
To Place Components click on Place/Components. On the Select Component window, click

on Group-> All groups. Type the components needed for the circuit. Click OK to place the
component on the schematic.

4. Place the selected component on the schematic.
5. Rotate Components: To rotate the components right click on the component and click
on rotate 90 Clockwise (Ctrl +R) or rotate 90 Counter Clockwise (Ctrl+Shift+R).

6. Place Wire/Connect Components: To connect components, click on Place/Wire drag

and place the wire. Components can also be connected by clicking the mouse over the
terminal edge of one component and dragging to the edge of another component. (Refer
Figure 6).
Figure 6
7. Validation of Input and Output (Refer Figures 7a & 7b)
 To give input, Click on Place -> components-> All Groups-> Type SPDT(Single
Pole Double Throw) switch in component icon.
 Click on Place -> components-> Groups -> Select sources-> Type VCC in
component icon.
 Click on Place -> components-> Groups -> All Groups-> Type DGND(Digital
Ground) in component icon.
 To observe the output, Click on Place -> components-> Groups ->Select Indicators->
Probe.
 Connect the above components using wires.

Figure 7a
Figure 7b
8. Simulation: To simulate the completed circuit Click on Simulate/Run or F5. This feature
can also be accessed from the toolbar.

Experiment No: 11
SIMULATE FULL ADDER USING SIMULATION TOOL
AIM: To simulate full adder using basic logic gates using Multisim.
APPARATUS REQUIRED: PC, Multisim software
COMPONENTS:7486N, 7432N,7408N,Vcc,Ground,SPDT,Probe,wire
THEORY:
Multisim is the schematic capture and simulation application of National Instruments Circuit
Design Suite, a suite of EDA (Electronic Design Automation) tools that assists you in
carrying out the major steps in the circuit design flow. Multisim is designed for schematic
entry, simulation, and exporting to downstage steps, such as PCB layout.
LOGIC DIAGRAM OF FULL ADDER
TRUTH TABLE FOR VERIFICATION

INPUT OUTPUT
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

SIMULATION OUTPUT
RESULT: full adder circuit using basic logic gates is simulated using Multisim and the truth
table is verified.

Experiment No: 12
SIMULATE MOD 8 SYNCHRONOUS UP/DOWN COUNTER USING
SIMULATION TOOL
AIM: To simulate mod 8 synchronous up/down counter using Multisim.
APPARATUS REQUIRED: PC, Multisim software
THEORY
Counter is a sequential circuit. A digital circuit which is used for a counting pulses is known
counter. Counter is the widest application of flip-flops. It is a group of flip-flops with a clock
signal applied. If the "clock" pulses are applied to all the flip-flops in a counter
simultaneously, then such a counter is called as synchronous counter.
Modulus Counter (MOD-N Counter)-
A 2-bit ripple counter is called as MOD-4 counter and 3-bit ripple counter is called as
MOD-8 counter. So in general, an n-bit ripple counter is called as modulo-N counter.
Where, MOD number = 2n.
A mod-8 up counter counts from 0 to 7. It stores the initial value, and increments that value
on each clock tick, and wraps around to 0 when the count reaches 7. So, the stored value
follows a cycle: 000 001 010 011 100 101 110 111
A mod-8 down counter counts from 7 to 0. It stores the initial value, and decrements that
value on each clock tick, and wraps around to 7 when the count reaches 0. So, the stored
value follows a cycle: 111 110 101 100 011 010 001 000
OBSERVATION
For Mod 8 up counter- 0 ,1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3,……
For Mod 8 down counter- 7, 6, 5, 4, 3. 2, 1, 0, 7, 6, 5, …….
For Mod 8 up/down counter-

switch connected to Vcc- down counter 7, 6, 5, 4, 3. 2, 1, 0, 7, 6, 5, ……
switch connected to Gnd- up counter 0 ,1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3,……

MOD 8 UP COUNTER CIRCUIT
MOD 8 DOWN COUNTER CIRCUIT

MOD 8 UP/ DOWN COUNTER CIRCUIT
RESULT-
Mod 8 synchronous up counter, down counter and up/down counter are simulated using
Multisim and the output sequence is observed.

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DIGITAL ELECTRONICS [15ECL38] 1

R.N.SHETTY INSTITUTE OF TECHNOLOGY

DIGITAL ELECTRONICS [15ECL38]

DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

PROGRAM EDUCATIONAL OUTCOMES (PEOs)

PROGRAM OUTCOMES (POs)

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering

DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

modern engineering and IT tools including prediction and modeling to complex

DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

Digital Electronics Lab -15ECL38

Sub Code: 15ECL38 IA Marks: 20

DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

10. PATCH CORDS - -

TTL Transistor-transistor logic

DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

DEFINITION OF LOGIC GATES

DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

2 INPUT AND GATE :

DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

2 INPUT EX-OR GATE:

2 INPUT NAND GATE:

3 INPUT NAND GATE:

DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

II Realization of basic gates using NOR and NAND gates:

DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

1. Why NAND & NOR gates are called universal gates?

DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

Theory: Augustus De Morgan, a 19th-century British mathematician developed a pair of

(a) Verification of Demorgan’s theorem for two variables

DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

Simplification using K-map:

DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

ii)Implementation Using NAND gates iii) Implementation Using NOR Gates

2) Product of Sum (POS): Y=(A+B)D

Simplification using K-map:

DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

Result: Truth Tables of the given expressions are verified.

10. What is Gray code? Why this code is used in K-map?

DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

TRUTH TABLE BOOLEAN EXPRESSIONS:

DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

RESULT : The truth table of the above circuits are verified.

DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

EXPERIMENT NO. 3 : PARALLEL ADDER AND SUBTRACTOR

AIM : To design and set up the following circuit using IC 7483.

DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

i) 4-Bit Binary Adder

ii) 4-BIT BINARY SUBTRACTOR.

DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

Result: Truth Tables of Parallel adder and subtrator are verified.

DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

Components Required: IC 7485, Patch cords and Trainer kit.

Theory: A digital comparator or magnitude comparator is a hardware electronic device

TO COMPARE THE GIVEN DATA USING 7485 CHIP.

RESULT : Four bit comparator IS verified using magnitude comparator IC7485

DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

(a) 4:1 multiplexer using Logic gates.

DEPT. OF ELECTRONICS AND COMMUNICATION, R.N.S.I.T III SEM

Truth Table of 4:1 MUX