Table of Contents

ABSTRACT........................................................................................................................................ 2
Chapter-I Background and Introduction ......................................................................................... 3
1.1 Background ........................................................................................................................... 3
1.2 Introduction ........................................................................................................................... 3
1.2.1 Overview of CNT ........................................................................................................... 3
1.2.2 Early CNTFET devices .................................................................................................. 4
Chapter-II Structure and types of CNTFETs .................................................................................. 5
2.1 Structure of CNTFETs .......................................................................................................... 5
2.2 Types of CNTFET ................................................................................................................. 6
2.2.1 Back gate CNTFET ....................................................................................................... 6
2.2.2 Top-gated CNTFET's .................................................................................................... 6
2.2.3 Wrap-around gate CNTFETs........................................................................................ 7
2.2.4 Suspended CNTFETs ................................................................................................... 7
Chapter-III Performance and Characteristics ................................................................................. 8
3.1 Performance ................................................................................................................................ 8
3.1.1 Schottky Barriers ........................................................................................................... 8
3.1.2 Contact Resistance ......................................................................................................... 8
3.1.3 Phonon Scattering .......................................................................................................... 8
3.1.4 Hysteresis ....................................................................................................................... 9
3.1.5 Heat Dissipation ............................................................................................................. 9
3.1.6 Polarity Switching .......................................................................................................... 9
3.2 Drain Current equations for CNTFET ............................................................................... 10
3.2.1 Linear region................................................................................................................ 10
3.2.2 Saturation region ......................................................................................................... 10
3.3 MATLAB SIMULATION ................................................................................................... 10
𝑰𝒅 − 𝑽𝒈𝒔 Characteristics ............................................................................................................ 10
Trans-conductance with respect to Drain current and overdrive Voltage ................................ 11
Chapter-IV Advantage, Limitations and Future Work ................................................................. 13
4.1 Advantage of CNT over Silicon technology ........................................................................ 13
4.1.1 Application of CNTFETs ............................................................................................. 13
4.2 Limitation of CNTFETs ...................................................................................................... 13
4.3 Future Work ........................................................................................................................ 14
Conclusion ....................................................................................................................................... 14
References ....................................................................................................................................... 15
ABSTRACT
In this paper a comprehensive study regarding carbon nanotubes transistor filed effect
transistors (CNTFET) has been presented. Low power consumption, nanoscale and high
performance devices are demands of this modern era. As further development on MOSFETs
have reached at the peak so other devices like Bulk silicon FinFETs, III-IV FinFETs, Carbon
Nanotubes transistors etc. are supposed to be successor and to sustain the transistor scalability
while increasing its performance. Core difference between MOSFETs and CNTFETs is
material used for channel. Core of presented device is CNT. Structure, operation and
characteristics of different types of CNTFETs has been sated here in this paper. Operation,
DC characteristics and performances analysis have been done using MATLAB software tool
and presented.
 Chapter-I Background and Introduction

1.1 Background
From the last two decades Moore’s Law was acting as a scaling parameter for CMOS
devices, like MOSFETs. After reaching at 10nm, further development based on Moore’s law
for MOSFETs came to end due to lack of ability for further narrowing it down[1]. To match
the future requirements in term of speed, low power consumption, leakage current control,
high performance and much more, different techniques were purposed. Material used as a
channel was considered as core thing to improve performance and Nano scaling. Based on this
concept, Carbon Nano Tube Field Effect Transistor (CNTFETs), Graphene Nanoribbon Field
Effect Transistors (GNRFETs), Silicon-On-Insulator Field Effect Transistors (SOIFETs) all
are future candidate to be a successor of FETs [2]. With respect to ease of simulation, low
current consumption and small size above mentioned candidate are being tested now a days
and it is difficult to make a solid decision which device is best among them.

1.2 Introduction
This paper is organized as follow. Chapter-I cover background and introduction of Carbon
nanotubes. In later sessions, structure of CNTFET and different types of it have seen stated. A
view of about why carbon nanotubes are better than silicon and germanium as a material for
channel in field effect transistor has presented in chapter-II. Performance analysis of CNTFET
using MATLAB has been discussed in Chapter-III. Limitations and future Scope has been
given in Chapter-IV.

1.2.1 Overview of CNT

In 1991 Carbon Nanotubes were discover by S. Iijima as a carbon atoms arranged in
hexagonal structure rolled up in tube. As carbon atom utilize three of its valence electrons out
of four in 𝑠𝑝2 bonds. In this type of bonding, from the 2s-orbital an electron is promoted to p-
orbital. To generate 𝑠𝑝2 –orbitals, single electron left in the 2s-orbital is then combined with
two electrons from different 2p-orbitals. 𝑠𝑝2 –orbitals are planar with 1200 between the major
lobes, and the remaining p-orbital is perpendicular to this plane. The unused p-orbital is
vertical to the graphene. A weak 𝜋-bonds is made between electrons in this orbital and other
carbon atoms. This loosely bound electrons in the p-orbitals are responsible for the
conductance of graphite. As carbon is more likely than graphite, only have larger inner
distance, so binding in CNT almost same as in graphite.
 1.2.2 Early CNTFET devices
CNT was consider as a new way to obey Moore’s Law and utilized in field of transistor.
These. In 2004, first transistor made using this technology was named as Single wall Carbon
Nano-Tube Field Effect Transistor (SWCNTFETs) which was only able to work under low
temperature[3]. This early device had gold or platinum electrodes which served as source and
drain. Nanotubes were used as a connecting material and Silicon substrate served as a gate.
Being in early stage of development, there were several problems i.e. high gate voltage to turn
on, low trans-conductance, no current saturation etc. A schematic diagram is shown in figure-
1. For improvements metal-nanotube contact, Au, Ti and CO were used with a thermal
annealing step. All early CNTFETs were p-type, hole conductors, due to contact doping.
Thermal annealing in vacuum along with Alkali gas doping was done to achieve N-type
CNTFETs. By this thermal annealing a way to achieve threshold voltage shift when going
from p-type to n-type was observed as an intermediate state, in which both electron and hole
injection are allowed, resulting in am-bipolar conduction.

Figure-1 (Early CNTFET Structure)

 Chapter-II Structure and types of CNTFETs

2.1 Structure of CNTFETs

Physical structure of CNTFETs and MOSFETs almost same with difference of material used
for channel. In CNTFETs, semiconductor carbon nanotubes are used as a channel. Both p-
type and N-type CNTFET can be made using CNT. CNT can be shaped like cylinder as
shown in figure-2. As channel is used as a pathway for electrons from source to drain so for
this device, CNT is used for such purpose. Scaling lower than 10nm and short channel effects
were main problems in MOSFETs but in CNTFETs this channel helps to overcome such
problems due to its electrical and physical characteristics[4].

Figure-2 (Structure of Cylindrical CNT)

At the intersection of metals contacts and channel, Schottky barriers are created. Basic
structure of CNTFT is shown in figure-3. A completely different mechanism of electron
conduction is promoted when annealing of CNTFETs in vacuums is done. The way in which
charge is transferred, oxygen near the nanotubes contacts affects the local bending of the
conduction and valence bands in the nanotube. This mechanism allows injection of holes
much easier as Fermi level is pinned closer to the valence band. At the time when oxygen is
desorbed at high temperature, this Fermi level come closer to conduction band which make it
easier to inject electron. Due to this mechanism, a threshold voltage to shift from p-type to n-
type is achieved via thermal annealing. This intermediate state in which electron and holes can
be injected results in ambipolar conduction.
 Figure-3 (Structure of CNTFET)

2.2 Types of CNTFET

CNTFET has been classified into four major classes given as:

a) Back gate CNTFET

b) Top gate CNTFET
c) Wrap-around gate CNTFETs
d) Suspended CNTFETs

2.2.1 Back gate CNTFET

This architecture based upon early model of single wall carbon nanotube which act as a
channel for two metal electrodes prefabricated by lithography on an oxidized silicon wafer.
These metal electrodes act as a drain and source. In this structure, heavily doped silicon
wafers acts as a back gate. Weak Vander Waals coupling of the devices to the noble metal
electrodes in the ‘side-bonding results in high contact resistance (>1 MΩ). This larger contact
resistance led to low trans-conductance (10-9 A/V). Low drive current is also a limitation of
this model[5]. Structure is shown in figure-4.

2.2.2 Top-gated CNTFET's

To overcome limitation in back gated CNTFETs, a next generation of CNTFETs were
developed named as Top-gated CNTFETs. In this model, isolated single wall CNT are
deposited on substrate, silicon oxide. High resolution electron beam lithography is used to
pattern source and drain contacts. Adhesion between metal contact and CNT is made via high
temperature annealing which reduces high contact resistance. Evaporation or atomic layer
deposition process is used to deposit a thin top-gate dielectric layer on nanotubes, as shown in
figure-4. In final step of fabricating top-gated CNTFETs, the top gate contact is deposited on
the gate dielectric.
 Figure-4 (Back-gated (a),Top-gated (b), Wrapped-Around gate (c) and Suspended CNTFET)

Fabrication process of top-gated CNTFETs is more complex than back-gated CNTFETs but
lower gate voltage requirement, less contact resistance and fabrication of array of top-gated
CNTFETs on same wafer are some plus point over back-gate CNTFETs[5].

2.2.3 Wrap-around gate CNTFETs

In 2008 more improvement, as a gate-all-around CNTFETs, were made upon geometry of
top-gated device. To improve electrical performance and reduce leakage current, whole
circumference of nanotubes is gated in this model. Atomic layer deposition is used to wrap
CNT in gate dielectric and gate contact. These wrapped nanotubes are then deposited on
substrate and partially etched off to expose end of tubes. At the end contacts of drain and
source are deposited over ends of tubes [5]-[6]. Structure is shown in figure-4.

2.2.4 Suspended CNTFETs

To reduce scattering at CNT-substrate interface and improve performance, option of
suspending nanotubes over a trench is utilized in geometry of CNTFETs. These kind of
structures are called suspended CNTFETs. Fabrication is quite difficult and can be possible in
number of ways i.e. using catalyst particles. Because of suspended geometry, there comes
certain limitation in selection of dielectric material and apply gate bias. This architect is
acceptable for shorter nanotube but in longer tube, flex issue will emerge and this will cause
leaning towards gate, possibly touching it and shorting the device[5].
 Chapter-III Performance and Characteristics
3.1 Performance
As CNT is material used to bridge source and drain so performance of CNTFETs is related to
physical properties of CNT. So for better understanding performance of CNTFETs, properties
of CNT should be considered.

3.1.1 Schottky Barriers

At the intersection of metals contacts and channel, Schottky barriers are created. This
happened due to Fermi levels lining up and affecting channel transport. As channel
transportation is reduced due to Schottky barriers, so this much affect the performance of
CNTFET. Several solution to reduce such problem have been proposed i.e. high temperature
doping, highly doping channel, specific coatings for getting contact with intrinsic channel
Characteristics. This problem is not related to single wall CNT but also happens in multi wall
CNT due to due to the inevitable crossing of m-CNTs over s-CNTs tubes during
fabrication[7].

3.1.2 Contact Resistance

Due to intrinsic mismatch between higher-dimensional external contacts to the wires and one-
dimensional nanotube, contact resistance issue arise. Mathematically it can be written as
based on Land-Auer formula:

ℎ 𝐿
𝑅𝑁𝑇 = (1 + ) … … (𝐴 )
4𝑒 2 𝑙𝑒

Where L is length of conductor, 𝑙𝑒 is mean free path.

ℎ 𝐿
is length independent intrinsic resistance (6.5 k ohms ) and (1 + 𝑙 ) is an effect of
4𝑒 2 𝑒

mismatch between higher-dimensional external contacts to the wires and one-dimensional

nanotube. Some other factors will also increase this contact resistance are impurities,
sophisticated geometry of the contact region and temperature. Higher the value of contact
resistance lower will be trans-conductance that affecting performance of CNTFETs.

3.1.3 Phonon Scattering

This scattering mechanism is related to mean free path in high quality single wall CNT. As
mean free path increase, phonon scattering decrease which provide less thermal noise, low
self-heating, higher breakdown voltage less power dissipation and thus resulting in leaner
𝐼𝑑 − 𝑉𝐺𝑆 characteristics.

There are also some negative effects on the behavior of the carriers on the channel when
phonon interaction happens between channel and substrate i.e. lower mobility. Although this
scattering doesn’t affect DC characteristics of transistor.

3.1.4 Hysteresis
Due to localization of energy states in the band gap, also known as traps, hysteresis issue
arise in in CNTFET. This also arise due to electrically underside material present in tubes.
Due to this issue in CNTFETs, devices are not preferred in digital applications. To eliminate
hysteresis, matched and defect-free material should be used. Hydrophobic self-assembled
mono layers (SAMs) are used to cover dielectric and minimize traps adsorption before
positing tubes[6].

3.1.5 Heat Dissipation

Thermal constant for Silicon based technology is 10ns but for CNT it is 0.1ns. So this makes
CNTFETs high level of activity, less energy usage and better scaling candidate in fabrication
of memory materials. But this happened due to high electric current values for programming
thus causing heat dissipation issue.

3.1.6 Polarity Switching

A completely different mechanism of electron conduction is promoted when annealing of
CNTFETs in vacuums is done. The way in which charge is transferred, oxygen near the
nanotubes contacts affects the local bending of the conduction and valence bands in the
nanotube. This mechanism allows injection of holes much easier as Fermi level is pinned
closer to the valence band. At the time when oxygen is desorbed at high temperature, this
Fermi level come closer to conduction band which make it easier to inject electron. Due to
this mechanism, a threshold voltage to shift from p-type to n-type is achieved via thermal
annealing. This intermediate state in which electron and holes can be injected results in
ambipolar conduction.

There are still number of CNT properties which might affect performance of CNTFETs i.e.
diameter of Nanotubes, high frequency operation etc.[7]
3.2 Drain Current equations for CNTFET
Current voltage curve for CNTFET can be divided into two region which are given as;

3.2.1 Linear region

Drain current in linear region for CNTFET can be described as;
𝑊 𝑉𝑑𝑠
𝐼𝑑 = 𝜇𝐶𝑜𝑥 (𝑉𝑔 − 𝑉𝑇 − ) ∗ 𝑉𝑑𝑠 … … (𝑋)
𝐿 2
Where W is the width of CNTFET, L is the length of CNTFET, 𝜇 is mobility of carrier and
𝐶𝑜𝑥 is gate capacitance.
Or
2
𝐼𝑑 = 𝐾𝑛 [2(𝑉𝑔 − 𝑉𝑇 )𝑉𝑑𝑠 − 𝑉𝑑𝑠 ] … … (𝑌)
𝑊
Where 𝐾𝑛 = 2𝐿 𝜇𝐶𝑜𝑥

3.2.2 Saturation region

For saturation region drain current can be calculated by replacing current 𝑉𝑑𝑠 (𝑠𝑎𝑡) = 𝑉𝑔 − 𝑉𝑇
resulting in
2
𝐼𝑑(𝑠𝑎𝑡) = 𝐾𝑛 (𝑉𝑔 − 𝑉𝑇 ) … … (𝑍)

3.3 MATLAB SIMULATION

𝑰𝒅 − 𝑽𝒈𝒔 Characteristics
MATLAB simulation is done by using (Z), saturation region, to plot Drain current vs Gate to
source voltage characteristics. For this purpose, Length of CNTFET is consider as 1nm, width
10nm , gate capacitance is considered as 0.0172. 𝑉𝑇 for this model is 0.2V.

Figure-5 (𝑰𝒅 − 𝑽𝒈𝒔 for Varying mobility Carriers )

 Figure-6 (𝑰𝒅 − 𝑽𝒈𝒔 for different Length)

Trans-conductance with respect to Drain current and overdrive Voltage

When transistor is operating in saturation always produces a constant current in response to
the variation of gate source voltage. That is it always behaves like a current source. Trans
conductance is the measure of how well the MOSFET device is able to convert the voltage
into output current. The governing equations are:

𝑊
𝑔𝑚 = 𝜇𝐶𝑜𝑥 (𝑉𝑔𝑠 − 𝑉𝑇 ) 𝐴/𝑉
𝐿

Where 𝑉𝑔𝑠 − 𝑉𝑇 is overdrive voltage, W= width of the device, L=channel length

𝑊
𝑔𝑚 = √2 ∗ ∗ 𝜇 ∗ 𝐶𝑜𝑥 ∗ 𝐼𝑑
𝐿
Or
2 ∗ 𝐼𝑑 𝐴
𝑔𝑚 =
(𝑉𝑔𝑠 − 𝑉𝑇 ) 𝑉

Simulation on MATLAB is done For L=10 nm and W=10 nm and results are stated below.
Figure-7 (𝑻𝒓𝒂𝒏𝒔 − 𝒄𝒐𝒏𝒅𝒖𝒄𝒕𝒂𝒏𝒄𝒆 𝑽𝒔 𝒐𝒗𝒆𝒓𝒅𝒓𝒊𝒗𝒆 𝑽𝒐𝒍𝒕𝒈𝒆)

Figure-8 (𝑻𝒓𝒂𝒏𝒔 − 𝒄𝒐𝒏𝒅𝒖𝒄𝒕𝒂𝒏𝒄𝒆 𝑽𝒔 𝑫𝒓𝒂𝒊𝒏 𝒄𝒖𝒓𝒓𝒆𝒏𝒕)

Figure-9 (Triode Region)

Chapter-IV Advantage, Limitations and Future Work
4.1 Advantage of CNT over Silicon technology
Due to properties of CNT, as described in above section, CNTFETs have some preeminent
advantage over silicon technology. Some of these advantages are listed below[5]:

 CNTFETs can operate in ballistic regime due to their less scattering probability
property. Because of One dimensional carbon nanotubes, CNTFETs have this
advantage over Silicon technology.
 Unlikely Silicon technology, no need of careful passivation of the interface between
the nanotube channel and the gate dielectric is required because nanotubes conducts on
its surface.
 Fast switching property due to Schottkey barrier at Metal-nanotube contacts makes
CNTFET’s performance better than other technology.
 Nano scaling is possible less than 10nm using CNT as a channel between drain and
source.

4.1.1 Application of CNTFETs

Because of above mentioned advantages over Silicon technology, application of CNT and
CNTFETs are vast. Some of them are listed below.

 CNT Computers: In 2013, first programmable computer based on PMOS technology

was built using CNT. It was nonetheless capable of multitasking.
 Pharmaceutical Applications: In Process like protein binding. Streptavidin, a protein
that is isolated from bacteria CNTFETs are used as a detector because of sensitivity
property to some gases.
 Flexible Electronics: High Carrier mobility, Conductivity and flexibility are some
unique properties of CNT which makes CNTFETs application in field of transparent
electronics.

4.2 Limitation of CNTFETs

Along with certain advantages listed above, there exist some limitation or disadvantage of
CNTFETs. Some of them are listed below:
  Lifetime: Because of properties and structure of carbon nanotubes, they are sensitive
to some gases. Oxygen is one of them which cause degradation when it contact with
CNTFETs.
 Reliability: Avalanche in CNTs, unlikely in Silicon technology, is trivially
temperature dependent. When high voltage are applied further than avalanche point
Joule heating effects emerge and eventual caused breakdown in CNTs.
 Production Cost: Stiffness, Strength and tenacity are plus properties over Silicon in
CNT. But Fabrication process of CNTFETs is high production cost.

4.3 Future Work

Along with certain unique property of CNT there also exist certain limitations or
disadvantages. As listed above degradation, reliability and production cost are main issues
related to CNTFETs so in future developments will be made to improve such things and
enhancement in its performance. Scattering effects in CNT cause channel fringe capacitances,
parasitic resistance between source and drain and contact resistance. So certain efforts in
future will be made to resolve such problems

Conclusion
A comprehensive study about Carbon nanotubes and CNTFET have been done here in this
paper. CNT has some unique properties like Stiffness, Strength and tenacity. And due to these
properties their utilization in field of Pharmaceutical, flexible electronics, logic gates,
decoders etc.is present. As performance of CNTFETs has been observed at Nano scaling and
with different number of mobility carrier and it is observed that performance vise these
devices are much better than Silicon devices. But with these advantages, limitation like
reliability issue, production cost and fabrication complexity are some problems where certain
improvements are required
References
[1] M. Mehrad and M. Zareiee, ECS Journal of Solid State Science and Technology, 5, 74
(2016).

[2] M. Akbari Eshkalak and M. K. Anvarifardb, Physics Letters A, 38(1), 1379 (2017).

[3] M. Moghaddam, M. H. Moaiyeri, and M. Eshghi, IEEE Transactions on Device and

Materials Reliability, 17(1), 267 (2017).

[4] ECS Journal of Solid State Science and Technology, 6 (8) M97-M102 (2017)

[5] International Journal of Advanced Research in Engineering Technology & Science, ISSN:
2349-2819, Volume-3, Issue-12 December- 2016

[6] https://zero.sci-hub.tw/5380/630a39e8e4bc4b21c3ab2ddec86e7866/el-
naggar2016.pdf#view=FitH

[7] ECS Journal of Solid State Science and Technology, 6 (8) M97-M102 (2017)