Analog Integr Circ Sig Process (2007) 51:59–71
DOI 10.1007/s10470-007-9036-x
A 2.4 GHz low power wireless transceiver analog front-end
for endoscopy capsule system
Baoyong Chi Æ Jinke Yao Æ Shuguang Han Æ
Xiang Xie Æ Guolin Li Æ Zhihua Wang
Received: 25 September 2005 / Revised: 13 January 2007 / Accepted: 29 January 2007 / Published online: 25 May 2007

Springer Science+Business Media, LLC 2007
Abstract This work presents the design and implemen-
tation of a 2.4 GHz low power wireless transceiver analog
front-end for the endoscopy capsule system in 0.25 lm
CMOS. The prototype integrates a low-IF receiver analog
front-end (low noise amplifier, double-balanced down-
converter, band-pass-filtered AGC loop, and ASK demod-
ulator) and a direct-conversion transmitter analog front-end
(20 MHz IF PLL with well-defined amplitude control cir-
cuit, ASK modulator, up-converter, and output buffer) on a
single chip together with one integrated RF oscillator and
two LO buffers. Trade-off has been made over the design
boundaries of the different building blocks to optimize the
overall system performance. All building blocks feature the
circuit topologies that enable comfortable operation at low
power consumption. As a result, the IC works at a 2.5 V
power supply, while only consuming 15 mW in receiver
(RX) mode and 14 mW in transmitter (TX) mode. To build
a complete transceiver for the endoscopy capsule system,
only an antenna, a duplexer, and a digital controller are
needed besides the presented analog front-end chip.
Keywords Wireless transceiver
RF
CMOS

AGC
ASK modulator
ASK demodulator
Endoscopy
capsule system
Low power
B. Chi (&)
Z. Wang
Institute of Microelectronics, Tsinghua University, Beijing
100084, China
e-mail: chibylxc@tsinghua.edu.cn
J. Yao
S. Han
X. Xie
G. Li
Department of Electronic Engineering, Tsinghua University,
Beijing 100084, China
1 Introduction
Different from the conventional endoscopic technique, the
wireless endoscopy system allows us to directly study the
entire digestive tract without any anesthesia or insufflation.
The wireless endoscopy system lessens the pain the pa-
tients suffer from and lowers the risks associated with the
endoscopic examination. So, many people start to research
the wireless endoscopy system and some preliminary
developments have been achieved recently [1–3].
The presented wireless endoscopy system is shown in
Fig. 1. It consists of the wireless capsule, the portable
device, and the computer. The wireless capsule is her-
metically packaged and could be swallowed by the pa-
tients. Inside the capsule, a CMOS image sensor captures
the images of the human digestive tract, then the image
data are sent to an integrated circuit for the digital signal
processing (such as image compression, coding, and so on).
A wireless transceiver is also integrates into the same chip
to transfer the image data to the transceiver outside the
patient body and to receive the control instructions from
the outside transceiver. Batteries and illumination devices
are also installed in the capsule. Outside the patient’s body,
there is a wireless transceiver connected to a computer or a
recording device. The image data can be stored in the
recording device, and could be used by the doctor in the
future, or the capsule can be controlled by a computer and
the image data can be displayed on the computer screen in
real time. The system uses a bi-direction communication
mode, which makes it possible that the behavior of
the circuits inside the capsule could be controlled by the
transceiver outside the patients’ body. For example, the
circuits inside the capsule could be controlled to work in
sleep mode to save power consumption when the capsule
passes the uninteresting digestive tract part. Another
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Fig. 1 The presented wireless
endoscopy system
example is that the circuit inside the capsule could be
controlled to generate a micro-current to stimulate the
muscle of the digestive tract and push the capsule forward
when the doctor wants to ignore the uninteresting part, the
action could speed up the movement of the capsule inside
the patients’ body.
In the whole wireless endoscopy system, the integrated
circuit in the capsule is the most crucial part. It must be
highly integrated since the volume inside the capsule is
limited, and its power consumption must be low since the
small size battery contains limited energy and the capsule
should work for more than 24 h. The integrated circuit in-
side the capsule is an analog–digital mixed signal low
power SOC (shown in the solid frame in Fig. 2), and con-
sists of the digital controller (shown in the dashed frame in
Fig. 2) and the wireless transceiver analog front-end.
Fig. 2 Analog–digital mixed
signal SOC architecture inside
the capsule
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Analog Integr Circ Sig Process (2007) 51:59–71
1. Digital controller inside the capsule: It includes
SRAM, the image compression module, the base-band
communication processing module, the control unit,
the interface with the CMOS image sensor, the power
management module, LEDs, the micro-current drivers
and so on.
2. Wireless transceiver analog front-end: The transceiver
operates in the 2.4 GHz ISM band. The receiver link
uses ASK modulation, and could restore the digital
instructions from the weak RF signal received by the
antenna; the transmitter link also uses ASK modula-
tion, and could convert the digital image data into the
strong RF signal which will be radiated out by the
antenna.
A low power CMOS image sensor is off-chip. It could
capture the raw image data with Bayer color filter array
Analog Integr Circ Sig Process (2007) 51:59–71
(CFA) and send the image data to the SOC chip for the
digital signal processing.
The paper presents the design and implementation of the
low power wireless transceiver analog front-end for the
endoscopy capsule system in 0.25 lm CMOS. Trade-off
has been made over the design boundaries of the different
building blocks to optimize the overall system perfor-
mance. All building blocks feature circuit topologies that
enable comfortable operation at low power consumption.
This work shows the possibility of achieving the perfor-
mance required by the endoscopy capsule system in
0.25 lm CMOS.
2 Architecture description
Since A/Dc or D/Ac would consume so much power at the
present technology [4], our wireless endoscopy capsule
system could not contain A/Dc or D/Ac. The receiver in-
side the capsule must restore the original digital data in the
analog field and the transmitter must implement the digital
modulation in the analog field. Also consider the power
consumption, RF PLL could not be used since the fre-
quency divider would consume a lot of power [5–7]. It
means RF carrier frequency could not be control accurately
and ASK becomes the only feasible modulation mode.
The transceiver analog front-end inside the capsule for
the wireless endoscopy capsule system is shown in Fig. 3.
The receiver inside the capsule demodulates the re-
ceived ASK signals and sends the restored digital data to
the digital controller. In details, 2.4 GHz RF signals re-
ceived by the antenna are first amplified by the low noise
amplifier (LNA) and then mixed in the down-converter
with the local oscillating signals generated by the inte-
Fig. 3 The presented wireless
transceiver analog front-end
61
grated oscillator. The resulted 10 MHz IF signals are AC-
coupled to a band-pass-filtered automatic gain controlled
(AGC) loop which consists of a two-stage cascade variable
gain amplifier (VGA), a constant gain amplifier, a peak
detector and a feedback Gm-C low-pass filter. The AGC
loop automatically adjusts the gain based on the signal
strength to ease the demodulation of the following ASK
demodulator. The Gm-C filter in the AGC loop forms a
negative feedback from the output of the VGA to the input
of the VGA. The feedback makes the VGA function as a
high-pass filter, which could remove the low frequency
noise and the DC-offset from the RF circuits [8]. After the
AGC loop, the signals are demodulated by the ASK
demodulator and the restored digital data are buffered by
several inverters and sent to the digital controller.
The received signal strength is designed to be between –
80 dBm and –40 dBm, and the RF front-end (LNA and
Mixer) provides about +17 dB voltage gain. The signal
amplitude for the digital data ‘1’ before the ASK demod-
ulator is well defined (~22 mV) by the AGC loop so that
the demodulator could demodulate the signals correctly.
The data rate of the receiver is about 256 kbps. This data
rate is high enough since the instruction information from
the outside transmitter is simple and occasional.
The transmitter inside the capsule also uses the ASK
modulation, it modulates the digital data from the digital
controller, up-converts the signals to 2.4 GHz ISM band
and radiates the signals out with the antenna. The 20 MHz
PLL generates the IF sine carrier signal with the well-
defined amplitude, which could reduce the harmonics and
accurately control the output power of the transmitter. The
ASK modulator modulates the IF carrier signals, and the
modulated ASK signals are up-converted to RF band and
are buffered by the on-chip RF buffer. The RF buffer
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outputs 0 dBm power into 50 W load (the impedance of the
antenna). The buffered signals are finally radiated out by
the antenna. The data rate of the transmitter is 2 Mbps.
To integrate the transceiver analog front-end on the
same chip with the digital controller under the limited
cost, CMOS process is the only feasible choice. Since
the passive components (especially the inductors) in the
CMOS process have quite low quality factor and the
allowable power consumption is also quite low, it is a
big challenge to design the analog front-end, especially
the on-chip oscillator. The oscillator generates the local
oscillating signals for the down-converter and the up-
converter, its phase noise performance has a great effect
on the communication quality of the transceiver. For our
presented negative-resistance LC oscillator, the phase
noise performance mainly depends on the quality factor
of the inductors and the power consumption. In our
design, two high quality off-chip inductors are used for
the LC oscillator. Since the oscillating frequency should
be controlled with some degree accuracy, the capacitor
array is integrated into the chip. The oscillator could be
trimmed after the type-out to adjust its oscillating
frequency.
3 Circuit description
In this section, the design and the implementation of the
transceiver analog front-end is described in details. The
whole analog front-end is divided into three parts: RF
front-end, IF part and the bias circuit.
3.1 RF front-end
The RF front-end consists of LNA, the down-converter, the
up-converter, the output buffer, the LC oscillator, and
the LO buffers (Fig. 2). Figure 4 shows the schematic of
the LNA and the down-converter.
Fig. 4 The schematic of LNA
and the down-converter
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Analog Integr Circ Sig Process (2007) 51:59–71
LNA is a fully integrated LC-tuned cascode amplifier
with inductive source degeneration. L2 provides the
source-degeneration inductance to generate the real resis-
tance at the gate of M1, and the resistance looking into the
gate of M1 is transformed into 50 W (the impedance of the
antenna) by the LC impedance matching network L1, C2.
M2 is a cascode transistor to improve the reverse isolation
performance and to reduce the Miller effect of M1. L3
resonates with C3 at the operation frequency to provide the
load for LNA. To receive the possible strong signals, the
gain of LNA is adjustable by changing the voltage level at
the gate of M3.
NF of LNA is optimized under the limited power con-
sumption with Smith Chart tool. During the optimization, it
is found that the loss of the on-chip inductor L1 has the
most severe effect on NF of LNA, and the effect of the
inductor L2 on NF could be ignored. So the crucial opti-
mization goal is to reduce the loss of the inductor L1,
which could be achieved by increasing the size of M1 and
the inductance of L2. But the gain and linearity of LNA
would become worse at the limited power consumption.
There exists tradeoffs between NF, linearity and gain, some
design iterations are necessary.
The down-converter is the classical double-balanced
Gilbert mixer [9], but the mixer is biased at the low power
consumption. One input port of the mixer (B) is connected
to the output of LNA, and another input port (C) is con-
nected to AC ground by the capacitance C5. The low pass
RC load (R5, C6/R6, C7) of the mixer would attenuate the
high frequency components and further improve the RF-IF,
LO-IF isolation performance. The output signals of the
down-converter are AC-coupled to the receiver IF part.
The transmitter RF front-end consists of the up-con-
verter and the output buffer. The up-converter is the clas-
sical differential-input, differential-output double-balanced
mixer [9] with LC resonant loads, but the mixer is biased in
the low power consumption, so it is difficult to achieve
high gain. The output signals of the up-converter are sent to
Analog Integr Circ Sig Process (2007) 51:59–71
the output buffer. The buffer consists of two-stage cascade
LC tuned differential amplifiers to provide enough gain.
The stack technique is utilized to lower the power con-
sumption. Figure 5 shows the schematic of the output
buffer. M1, M2, L1, and L2 form the first stage of the
output buffer, and M3, M4, L3, and L4 form the second
stage. The first stage is stacked on top of the second stage
to reuse the current. Here, the signal travels through the
path shown in black, while the supply current flows
through the path shown in gray. The bypass capacitor Cb
provides AC ground at the sources of M1, M2. The RF
output signals of the first stage are AC-coupled to the
second stage through C3, C4. The output of the buffer is
matched to the antenna by the on-chip impedance matching
network and the balanced-unbalanced impedance trans-
former.
The LO signals are provided by the integrated oscillator,
it is a negative-resistance LC oscillator. The outputs are
buffered by the LO buffers to drive the commutating
switches in the down-converter and the up-converter.
3.2 IF part
The receiver IF part consists of a band-pass-filtered AGC
loop and an ASK demodulator. The operating frequency is
about 10 MHz, but consider the frequency drift of the
integrated oscillator, the IF analog circuits are designed to
still work within the frequency range 5–20 MHz. Figure 6
shows the detailed block diagram of the receiver IF part.
The IF signals from the receiver RF front-end are AC-
coupled to an AGC loop which consists of one variable
gain amplifier (VGA), one constant gain amplifier (CA),
one peak detector (PEAKDET), one differential difference
amplifier (DDA) and one feedback Gm-C low-pass filter.
Fig. 5 The schematic of the
output buffer
63
The AGC loop automatically adjusts the signal strength to
ease the demodulation of the following ASK demodulator
(ASK DET). The Gm-C filter inside the AGC loop forms a
negative feedback from the output of the VGA to the input
of the VGA. The negative feedback makes the VGA
function like a high-pass filter to filter the low frequency
noises and the DC-offset from the RF front-end [8], which
makes the DC-couple feasible.
After the AGC loop, the signals are demodulated by an
ASK demodulator and the restored digital data are buffered
and sent to the digital controller. The output signal
amplitude of the AGC loop is set to a low value to lower
the power consumption. A differential peak detector is used
to detect both the peak value and the vale value, and the
differential detector could avoid the effects of the common
mode error induced by the constant gain amplifier on the
AGCs control accuracy and the bit-error-rate (BER) of the
ASK demodulation. The error between the peak detector’s
output and the reference is amplified by a DDA, and the
resulted signals are feedback to the VGA as the gain
control signals.
To achieve a wide gain tuning range and the stable loop
dynamic under the various input signal amplitude, the two-
stage VGA is designed to have the exponential gain control
characteristics. Figure 7 shows the schematic of the two-
stage VGA. It is a modified version of P. Huang’s topology
[10]. Each stage is a fully differential amplifier with an on-
chip common-mode feedback loop to stability the output
common mode voltage level. Vin+, Vin– is the IF signals
from the receiver RF front-end. The differential pair M3,
M4 converts the IF signals into the current signals. Another
differential pair M5, M6 also converts the feedback signals
Vfb+, Vfb– from the Gm-C low-pass filter into the current
signals. The above two current signals are subtracted at the
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Fig. 6 The detailed block
diagram of the receiver IF part
nodes Vout+, Vout– and the resulted outputs are converts
into the voltage signals again by the active load M9, M10.
Since Vfb+, Vfb– are the low-pass filtered copy of the
signals Vin+, Vin–, the forward signal path function like a
two-order high-pass filter. Indeed, the forward signal path
functions like a band-pass filter due to the native low-pass
characteristics of the VGA itself. The gain control signals
Fig. 7 (a) The schematic of one VGA Stage; (b) the connection
between two VGA stages
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Analog Integr Circ Sig Process (2007) 51:59–71
Vc+, Vc– are converted into the current signals and control
the tail bias currents of M3–M6 to adjust the gain of the
amplifier.
The Gm-cell in the Gm-C filter is a linearized OTA with
the source degenerated resistance. A open-loop amplifier
with a replica biasing [11] is used to provide a 20 dB
constant gain, which could relax the requirement on VGA
gain tuning range.
Any error of the peak detector results in an almost
identical error in AGC output. To lower the power con-
sumption, the output signal amplitude of the AGC loop is
set to a low value, so the ASK demodulator is designed to
be rather sensitive. If the gain of the AGC loop is too high,
the noise will become large, but if the gain of the AGC
loop is too low, the wanted signal is weaken. Both cases
will increase BER of the ASK demodulator. Based on the
above, it is crucial to design a low error peak detector. A
modified version of kruiskamp and Leenaerts’s peak
detector [12] is used. Figure 8 shows the partial schematic
of the peak detector. It only detects the highest peak
(Vout+) of the input signals. The circuit to detect the
lowest vale (Vout–) is the symmetrical version of Fig. 8.
The principle of the presented peak detector could be ex-
plained as following: The input voltage signals (Vin+, Vin–
) are compared with Vout+ by the operational amplifier
(OPA). If the highest peak of the input signal is higher than
Vout+, OPA would output low voltage in a short period to
drive M1(M4), so there is current flowing out the drain of
M1(M4). Since M1 and M2(M3 and M4) form a CMOS
current mirror, there is current to charge the capacitance Cp
and improve the voltage level of Vout+. The charge pro-
cess will continue until Vout+ is as high as the highest peak
of the input signals. After that, the output of OPA is turned
back to high voltage level, and M1 and M4 are always off
and the voltage level of Vout+ would keep unchanged, thus
Vout+ is the highest peak voltage of the input signals and
the peak detecting function has been implemented. Ip is a
weak bias current to periodically refresh the voltage level
of Vout+, which could avoid the case that Vout+ keeps the
Analog Integr Circ Sig Process (2007) 51:59–71
Fig. 8 The partial schematic of the peak detector
past highest peak and could not follow the amplitude var-
iation of the present input signals. The refresh period limits
the highest data rate of the receiver.
The ASK demodulator presented is a fully differential
well-controlled threshold detector. Its detecting threshold is
automatically well defined to avoid the wrong detection.
Figure 9 shows the schematic of the ASK demodulator.
The ASK demodulator consists of a rectifier [13] and a
hysteresis comparator. The rectifier outputs a current pro-
portional to the absolute value of the differential input
voltage, and then the hysteresis comparator restores the
original digital data from the current signal envelope. In
details, the input voltage signals are converted into the
currents (I1, I2, I1a, I2a) by the differential pair M1, M4/
M2, M3. The currents (I1, I2, I1a, I2a) are sent to the
current mirrors to do the subtraction operation, and the
resulted current I1–I2a, I2–I1a are got in the drains of M7
and M12. According to the basic principle of the current
mirror, only one between I1–I2a, I2–I1a is not equal to zero
at the same time. The currents are transferred by the
NMOS current mirrors M7/M8/M9, M12/M13/M14 and
summed at the nodes A, B. After further current mirroring
(by the PMOS current mirror) the currents I3, I4 are got.
The value of I3, I4 is equal to I1+I2–I1a–I2a. I3, I4 are sent
to a hysteresis comparator (M15-M18, the bias current
sources Ib2, Ib3), I3 sources current for one branch of the
comparator and I4 sinks currents from another branch of
the comparator, the action would result in a voltage dif-
Fig. 9 The schematic of the
ASK demodulator
65
Fig. 10 The schematic of the ASK modulator
ference. The voltage difference is further amplified by the
OPA and buffered by two inverters to restore the original
digital data.
The transmitter IF part consists of an integrated 20 MHz
IF PLL and an ASK modulator. The IF PLL provides the IF
sine carriers with the well-defined amplitude for the mod-
ulator, it could reject the harmonics and accurately control
the power at the output of the transmitter. It is a simple
integer-N PLL and consists of a divide-by-4 asynchronous
divider, a constant amplitude ring VCO, a rail-to-rail
charge pump, a zero dead zone PFD and a second-order
loop filter. The outputs of the PLL are differentially sent to
the ASK modulator.
The ASK modulator is only an on-off switch. When the
transmitted data is ‘1’, the switch is on, the 20 MHz IF
carriers are passed by without the loss; when the trans-
mitted data are ‘0’, the switch is off, the outputs of the ASK
modulator have no IF carriers. The schematic of the ASK
modulator is shown in Fig. 10. C+, C– are the sine carriers
from the IF PLL, the digital data Din from the digital
controller controls the switches M1–M4. If Din is ‘1’, M1,
M2 is close and M3, M4 is off, the differential carriers are
transferred to IF+, IF– without the loss; while Din is ‘0’,
M1, M2 is off and M3, M4 is close, IF+, IF– are connected
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to a common mode level Vcom, no carriers exists at the
outputs of the modulator. Thus, the ASK modulation is
implemented.
3.3 Bias circuit
The transceiver analog front-end is all biased by an on-chip
bandgap voltage reference or a constant-temperature cur-
rent source. Figure 11 gives out the schematic of the
bandgap reference and the constant-temperature current
source [14]. The bandgap reference can work at the low
power supply and consists of Q1, Q2, R1–R4, M1–M3 and
an operational amplifier (OPA 1). The voltage at the node
C is independent on the temperature. The capacitor C1 is
added to filter the bias noise. OPA 2 forms a unit-gain
amplifier to enhance the driving capability of the bias
voltage VB.
The bandgap reference also provides a reference volt-
age at the node D, but the voltage is dependent on the
temperature. The feedback loop (OPA 3, M5, R7) forces
Fig. 11 The schematic of the
bandgap reference and the
constant-temperature current
source
Fig. 12 The layout of the
transceiver analog front-end
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Analog Integr Circ Sig Process (2007) 51:59–71
the voltage at the node E equal to the voltage at the node
D. If the voltage at the node D has the same temperature
coefficient with the resistor R7, the current flowing into
R7 would be independent on the temperature. The tem-
perature-independent current is mirrored by the current
mirrors M5, M6 to provide the bias currents for other
circuits.
4 Experiment results
The transceiver analog front-end has been implemented in
0.25 lm CMOS. Figure 12 shows its layout. The die area
is 3.1 mm · 2.5 mm, most of which is occupied by the
passive components (inductors, capacitors, PADs) and
ESD protection circuits.
Figure 13 shows S11 of the receiver analog front-end.
When RF frequency is between 2.4 GHz and 2.5 GHz–S11
is smaller than –16 dB, so the receiver has implemented
on-chip input impedance matching.
Analog Integr Circ Sig Process (2007) 51:59–71 67

Fig. 13 S11 of the receiver analog front-end

Fig. 16 (a) The frequency characteristics of the forward signal path

(VGA, the constant gain amplifier and the Gm-C low-pass filter); (b)
The gain control curve of the forward signal path. P1 is the gain
Fig. 14 The conversion gain and NF of the receiver RF front-end control signal and proportional to the input signal amplitude (P1 is the
(LNA & Mixer) output of the peak detector)

Figure 14 shows the conversion gain and NF of the re- RF front-end is smaller than 7.4 dB and the conversion
ceiver RF front-end (LNA & Mixer). During this experi- power gain is higher than 11 dB when RF frequency is
ment, the IF frequency is 10 MHz, the load impedance is between 2.4 GHz and 2.5 GHz. However, the indeed load
set to be 500 W. Figure 14 shows that NF of the receiver of the RF front-end (LNA & Mixer) in the integrated

Fig. 15 IIP3 of the receiver RF

front-end (LNA & Mixer)

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Fig. 17 The various waveforms of the receiver analog front-end
receiver is 10 kW, so the voltage gain of the RF front-end
would be high, and the following IF circuits should have
little effects on the noise performance of the receiver.
Figure 15 shows IIP3 of the receiver RF front-end (LNA
& Mixer). Still, IF is 10 MHz and the load is set to be
500 W. The figure shows that IIP3 of the receiver RF front-
end is about –33.3 dBm when the RF frequency is between
2.4 GHz and 2.5 GHz.
The frequency characteristics of the forward signal path
(VGA, the constant gain amplifier and the Gm-C low-pass
filter) are shown in Fig. 16(a), where P1 is the gain control
signal and proportional to the input signal amplitude (P1 is
the output of the peak detector). The constant gain ampli-
fier is included in the simulation. Figure 16(a) shows that a
–40 dB/dec attenuation has been achieved in low fre-
quency, so the DC offset and the other low frequency
noises could be rejected. Figure 16(a) also shows that the
forward signal path functions like a band-pass filter, the
bandwidth is variable along with the gain, 3 dB bandwidth
is about 20 MHz at the highest gain (about 40 dB) and
extends to about 100 MHz at the lowest gain (about 4 dB).
The gain control curve given in Fig. 16(b) shows that the
relationship between the gain in dB and the control voltage
is almost linear, so the gain control function is exponential.
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Analog Integr Circ Sig Process (2007) 51:59–71
Figure 17 gives out the various waveforms of the re-
ceiver analog front-end, the signal source is a ASK mod-
ulated sine signal with the amplitude 28 lV (for ‘1’) or
2 lV (for ‘0’) and RF carrier frequency is 2.443 GHz, the
source resistance is 50 W and the data rate is 200 kbps.
VRFin is the RF input signal, VIF is the differential output
voltage of the receiver RF front-end (LNA, the down-
converter, the LC oscillator and the LO buffer), the IF
frequency is about 12 MHz, the voltage gain of the re-
ceiver RF front-end is about 17 dB. VLO is the LO signals
generated by the integrated oscillator. VAGC_out is the
output signal of the AGC loop, and Dout is the demodu-
lated digital data.
Figure 18 gives out the various waveforms of the
transmitter analog front-end, the data rate is 2 Mbps and
the load is 50 W impedance. Din is a pulse with a period
of 1 ls. Vout_PLL is the 20 MHz IF carrier with the
amplitude 190 mV from IF PLL. Vout-Mod is the ASK
modulated signal, Vout_PA is the output voltage of the
buffer, the buffer could output about 0 dBm power into
50 W load.
The transceiver analog front-end works at a power
supply of 2.5 V, while only consuming 15 mW in receiver
(RX) mode and 14 mW in transmitter (TX) mode. The
Analog Integr Circ Sig Process (2007) 51:59–71 69

Fig. 18 The various waveforms

of the transmitter analog front-
end

performance of the transceiver analog front-end is sum- 5 Conclusions

marized in Table 1.
This work presents the design and implementation of a
Table 1 Summarized performance of the presented transceiver ana- 2.4 GHz low power wireless transceiver analog front-end
log front-end for the endoscopy capsule system in 0.25 lm CMOS.
Receiver analog front-end Transmitter analog front-end Trade-off has been made over the design boundaries of the
different building blocks to optimize the overall system
Sensitivity –84 dBm Output power ~0 dBm
performance. All building blocks feature circuit topologies
IF frequency 5 MHz– Bandwidth <5 MHz
that enable comfortable operation at low power consump-
20 MHz
tion. As a result, the IC works at a power supply of 2.5 V,
Maximum input –40 dBm
power while only consuming 15 mW in receiver (RX) mode and
Modulation mode ASK Modulation mode ASK 14 mW in transmitter (TX) mode. To build a complete
Data rate <256 kbps Data rate <2 Mbps transceiver for the endoscopy capsule system, only an
Power consumption 15 mW Power 14 mW antenna, a duplexer, and a digital controller are needed
consumption besides the presented analog front-end chip. This work
shows the possibility of achieving the performance

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required by the endoscopy capsule system in 0.25 lm Baoyong Chi received the B.S.
CMOS. degree in microelectronics from
Peking University, Beijing,
China, in 1998 and the Ph.D
Acknowledgments This work was supported in part by National degree in 2003 from Tsinghua
Natural Science Foundation of China under Grant 90407006, University, Beijing, China. He
60475018 and The Fok Ying Tung Education Foundation under Grant now serves as an Associate
104028. Professor in Institute of Micro-
electronics, Tsinghua Univer-
sity. His research interests
References include RF integrated circuit
design, analog integrated circuit
1. Gavriel, I., Gavriel, M., Arkady, G., et al. (2000). Wireless design and monolithic wireless
capsule endoscopy. Nature, 405, 417–418 transceiver analog front-end.
2. Park, H. J., Nam, H. W., Song, B. S., et al. (2002) Design of bi-
directional and multi-channel miniaturized telemetry module for Jinke Yao is a Ph.D. candidate
wireless endoscopy. Microtechnologies in medicine & biology in Department of Electronic
2nd annual international IEEE-EMB special topic conference, Engineering, Tsinghua Univer-
Madison, Wisconsin, USA, 273–276 sity, Beijing, China. His re-
3. Wang, Z., Xie, X., & Zhang, C. (2003). Bi-directional digital search interests include analog
wireless endoscopy system. Chinese patent number: 03109810x, integrated circuits for wireless
04, 01 transceiver systems.
4. Uyttenhove, K., Vandenbussche, J., Lauwers, E., Gielen, G. G.
E., & Steyaert, M. S. J. (2003). Design techniques and imple-
mentation of an 8-bit 200-MS/s interpolating/averaging CMOS
A/D converter. IEEE Journal of Solid-State Circuits, 38(3), 483–
494
5. Chi, B., Zhu, X., Huang, S., & Wang, Z. (2005). 1 GHz mono-
lithic fractional-N frequency synthesizer with a 3-b third-order
delta-sigma modulator. Acta Electronica Sinica, 33(8), 1492– Shuguang Han is a Ph.D can-
1496 didate in Department of Elec-
6. Chi, B., Shi, B., & Wang, Z. (2004). CMOS implementation of tronic Engineering, Tsinghua
RF PLL frequency synthesizer. Acta Electronica Sinica, 32(11), University, Beijing, China. His
1761–1765 research interests include ana-
7. Chi, B., Zhu, X., Huang, S., & Wang, Z. (2004). 1 GHz mono- log integrated circuits and RF
lithic high spectrum purity fractional-N frequency synthesizer integrated circuits for wireless
with a 3-b third-order delta-sigma modulator. 7th International transceiver systems.
Conference on Solid-State and Integrated Circuits Technology,
Beijing, China, 2, 1504–1507
8. Kim, J. (2001). CMOS transceiver design for short range wireless
telemetry, Ph.D thesis. The University of Minnesota
9. Gilbert, B. (1968). A precision four-quadrant multiplier with sub-
nanosecond response. IEEE Journal Solid-State Circuits, SC-3,
365–373
10. Huang, P., Chiou, L., & Wang, C. (1998). A 3.3V CMOS
wideband exponential control variable gain amplifier. IEEE
International Symposium on Circuits and Systems, Monterey,
Xiang Xie received the Ph.D
CA, USA, 285–288
degree in 2006 from Tsinghua
11. Palmisano, G., & Salerno, R. (1998). A replica biasing for con-
University, Beijing, China. His
stant-gain CMOS open-loop amplifiers. IEEE International
research interests include bio-
Symposium on Circuits and Systems, Monterey, CA, USA, 363–
medical electronic product
366
development and digital inte-
12. Kruiskamp, M. W., & Leenaerts, D. M. W. (1994). A CMOS
grated circuit design.
peak detect sample and hold circuit. IEEE Transactions on Nu-
clear Science, 41(1), 295–298
13. Harjani, R., Birkenes, O., & Kim, J. (2000). An IF stage
design for an ASK-based wireless telemetry system. IEEE
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design of analog integrated circuits. John Wiley & Sons, Inc

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Analog Integr Circ Sig Process (2007) 51:59–71 71

Guolin Li serves as an Assis-

tant Professor in Department of
Electronic Engineering, Tsing-
hua University, Beijing, China.
His research interests include
RF/Microwave circuits and
wireless systems.

Zhihua Wang received his

B.S., M.S., and Ph.D. degrees
in Communication and Elec-
tronic Systems from the
Department of Electronic
Engineering, Tsinghua Uni-
versity, Beijing, China, in
1983, 1985, and 1990, respec-
tively. He has become a Pro-
fessor in the Department of
Electronic Engineering,
Tsinghua University since
1997. He has served as the
official member of the com-
mission C of China National
Commission of URSI starting
in 1998 and the Chairman of IEEE Solid-State Circuit Society Beijing
Chapter since 2000. His major research interests are the design
methodology of integrated circuits and systems, design of integrated
circuits for communication, analog and RF integrated circuit, as well
as high-speed real-time signal processing.

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