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Abstract
The Arithmetic Logic Unit is one of the essential component of a computer. It performs
arithmetic operations such as addition, subtraction, multiplication, division and various logical
functions. The Aim of this paper is to simulate an ALU and to analyze the various parameters
such as speed, power and number of logical blocks used by that ALU. The Floating point
numbers in this paper are represented according to the IEEE standard 754. The Arithmetic
operations such a s addition, subtraction, multiplication, division and the logical operations are
realized using Verilog HDL. Xilinx 7.1i software is used for writing the verilog codes and the
simulation is carried out with ModelSim 5.5f simulator.
1. INTRODUCTION
For the efficient way of representing real arithmetic operations like addition,
numbers the floating point numbers are subtraction, multiplication and division etc.
used. It is used when there is a need of
representing a number which is very large or 1.1 Single Precision IEEE 754 Format
very small but representation of such All the floating point numbers are composed
numbers are cannot be done without paying
by three components:
a price for it like as power, speed, accuracy,
ease of implementation and the memory of Sign: it indicates the sign of the number (0
the system. positive and 1 negative)
Mantissa: it sets the value of the number
In the various fields of science such as
Exponent: it contains the value of the base
physics and biology etc. the need of
measuring the dimensions of objects are power (biased)
essential for analyzing its characteristics. In If a Simple Precision format is used the bits
physics measuring the distance between
will be divided in that way:
stars or the size of an electron cannot be
done with the range of fixed numbers hence The first bit (31st bit) is set the sign (S) of the
we are in need of floating point numbers. number (0 positive and 1 negative)
Next w bits (from 30th to 23rd bit) represent
The Arithmetic Logic Unit is the basic
building block of a CPU which does various the exponent (E)
The rest of the string, t, (from 22nd to 0) is
Conversion of Decimal to Floating point 32
reserved to save the mantissa.
bit format is explained with an example.
Suppose the decimal number considered is
129.85. Before converting into floating
format this number is converted into binary
value which is 10000001.110111. After
conversion the radix point is moved to the
left such that there will be only one bit
towards the left of the radix point and this
Figure 1.1 Floating point number format
bit must be 1. This bit is known as “hidden
bit”.
Standard IEEE 754 specifies formats and
The binary value now can be represented
methods in order to operate with floating
as 1.00000011101110000000000. The
point arithmetic. These methods for
number which is after the radix point is
computational with floating point numbers
called the mantissa which is of 23 bits and
will yield the same result regardless the
the whole number is called significand
processing is done in hardware, software or
which is of 24 bits(including the hidden bit).
a combination for the two or the
Now the number of times the radix point is
implementation.
shifted (say x) is counted. In above case
there is 7 times shifting of radix point to the
The standard specifies:
left. This value must be added to 127 to get
Formats for binary and decimal floating the exponent value i.e. original exponent
point data for computation and data value is 127 + “x”. Thus the exponent
interchange becomes 127 + 7 = 134 which is 10000110.
Different operations as addition, Sign bit i.e. MSB is “0” because number is +
ve. Now the result is assembled into 32 bit
subtraction, multiplication and other
format which is sign, exponent, mantissa:
operations 01000011000000011101110000000000.
Conversion between integer-floating
2. LITERATURE SURVEY
point formats and the other way around
Different properties to be satisfied when In recent years, Floating-point numbers are
rounding numbers during arithmetic and widely adopted in many applications due to
conversions its high dynamic range and good robustness
Floating point exceptions and their
against quantization errors, capabilities.
handling (NaN, ±∞ or zero).
Floating-point representation is able to
retain its resolution and accuracy.
1.2 Conversion of Decimal to Floating Point
IEEE specified standard for floating-point provides a high performance. With
representation is known as IEEE 754 pipelining concept ALU execute multiple
standard. This standard specifies interchange instructions simultaneously (Suchita Pare et.
and arithmetic formats and methods for al, 2012) .
binary and decimal floating-point arithmetic
3. METHODOLOGY
in computer programming environments.
(IEEE 754-2008) The entire design is implemented by the
following steps in progression.
The main objective of implementation of
Conversion of the Floating Point
floating point operation on reconfigurable
Number into a novel integral
hardware is to utilize less chip area with less representation.
combinational delay (Karan Gumber et.al,
Conversion of the binary integer to its
May 2012) which means less latency i.e.
IEEE754 format.
faster speed. A parameterizable floating
point adder and multiplier implemented Pre-normalization of the operands
using the software-like language Handel-C,
using the Xilinx XCV1000 FPGA, a five Performing the selected operation.
serial.
intermediate answer.
0001001001000001001