A B C D E

MODEL NAME : AAM00

PCB NO : LA-C361P

1
BOM P/N :
Dell/Compal Confidential 1

Schematic Document
SKYLAKE-H
2014-05-22
Rev: 0.0 (M00)
@ : Nopop Component
2 2

CONN@ : Connector Component

R1@ / R3@ : R1/R3 CPN for CPU, GPU, PCB
TPM@ : TPM function
EMC@ : Pop of EMI parts
PCB CPU PCH GPU VRAMS@ : Samsung GDDR5 for GPU
UV1 BC@
VRAMH@ : Hynix GDDR5 for GPU
N16P-Q1-A2 VRAMM@ : Micron GDDR5 for GPU
ZZZ R1@ UH1 R1@
UH2 R1@ UV1 GX@
BreakDown@ : for measure power consumption
PCB 1BG LA-C361P REV0 MBSKL-H_BGA1440
SKY-H-PCH_BGA837 N16P-GX-A2
CSMB@ : CSMB sku
BC@ : BC sku (GPU N16P-Q1)
3 3

Samsung 2G
RV312
GX@ : GPU N16P-GX
UV5 UV6

20K_0402_1%
VRAMS@
UMA@ / DIS@ : UMA/DIS
K4G41325FC-HC03_FBGA170P~D K4G41325FC-HC03_FBGA170P~D
VRAMS@ VRAMS@

UV9 UV10

K4G41325FC-HC03_FBGA170P~D K4G41325FC-HC03_FBGA170P~D
VRAMS@ VRAMS@

Hynix 2G Micron 2G
RV312 RV312

UV5 UV6 UV5 UV6

34.8K_0402_1% 24.9K_0402_1%
VRAMH@ VRAMM@

4 4
H5GC4H24AJR-R0C_FBGA170P~D H5GC4H24AJR-R0C_FBGA170P~D EDW 4032BABG-60-F_FBGA170P~D EDW 4032BABG-60-F_FBGA170P~D
VRAMH@ VRAMH@ VRAMM@ VRAMM@

UV9 UV10 UV9 UV10

H5GC4H24AJR-R0C_FBGA170P~D H5GC4H24AJR-R0C_FBGA170P~D EDW 4032BABG-60-F_FBGA170P~D EDW 4032BABG-60-F_FBGA170P~D

VRAMH@ VRAMH@ VRAMM@ VRAMM@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/08/25 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS Size
ION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C. LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 1 of 71

A B C D E
 A B C D E

128M*32 x4 =2G
VRAM * 4
GDDR5 P.28~31

GB4-128 Memory Bus (DDR4) DDRIV-DIMM X2

GPU PEG 3.0 x16 Dual Channel
1.2V DDR4 2133 MHz CPU XDP
P.14~15
Conn.
1
N16P-GX Intel 32GB Max
P.6 1

P.23~27
Skylake-H HDMI
Processor Conn. P.36

35W/45W QC DDI x 2 Intel Alpine Ridge

BGA 1440 USB Type C
UHD 3840*2160 PCI-E x2 Conn.
eDP *4 lane Port 5,6
P.37~38 P.41
(4K*2K, eDP 1.3) P.35
P.7~13

DMI x4 PD P.39~41
100MHz controller
5GB/s

PCI-E x1 DC-in Conn.

SATA3.0 Port 0 HDD P.54
Port 3 Port 4
Conn. P.45
M.2 Slot A Key-E Card Reader Port 1
M.2 Slot C Key-M
2

(WLAN+BT4.0) RTS5242 2

P.43
P.51 PCI-E x4 (SATA/PCIe SSD)
P.44
USB2.0 3 in 1
Port 4 Socket Intel
USB 3.0 Port 2 USB 3.0
SLK-H-PCH Re-driver P.47 USB Powershare USB 3.0 Conn.
Port 4 USB 3.0 USB2.0 Port 1 TPS2546 ( USB Charger ) P.47

USB 3.0 Conn.

USB2.0
BGA 837 Balls P.46
( USB Charger ) USB Powershare Port 2
P.47
TPS2546 P.46
Touch Panel
Port 9
Conn. P.35

Digital Camera Port 12 USB2.0

Conn. P.35
Audio board

3
SPI Flash SPI Audio Codec 3

(BIOS 16MB)P.17 HD Audio Headphone / Mic. Jack

ALC3266 ( Combo )

FFS SMBus P16~22

LNG3DMTR AMP TAS5768

P.45

LPC Bus
TPM SPI 33MHz
NPCT650JAAYX Int. Speaker x2
Power On/Off CKT. P.42
P.42

MEC 5085
DC/DC Interface CKT.
P.32~34 SIO P.48
KB Board
SMBus PWM PS/2 Digital MIC Conn.
I2C
4
MCP 23017 Fan Control Touch Pad BCBUS KBC KSIO Int.KBD
4

GPIO Expander
P.42
ECE1117
P.49 P.42

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
Block diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C. LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 2 of 71

A B C D E
 A B C D E

Compal Confidential
Project Code : AAM00
File Name :

1 1

LA-C361P M/B

LS-C361P
Audio Board

2 2

JAUDIO
BtB Conn.

JKB JTP
15 pin 8 pin
FFC FFC

Touch Pad
LS-C362P
KB controller
Board JLED

3 3

4 pin FFC
Front Side LED/B

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
DB block diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 3 of 71
A B C D E
 A

Board ID Resistor USB3 DESTINATION USB 2.0 DESTINATION DDI DESTINATION

X00 N/A 1 USB Conn 1 (Right Side) 1 USB Conn 1 (Right Side) 1 Alpine Ridge

X01 2 USB Conn 2 (Left Side) 2 USB Conn 2 (Left Side) 2 Alpine Ridge

X02 3 None 3 None 3 None

X03 4 None 4 NGFF-1 WLAN + BT

A00 5 None 5 None

6 None 6 None

7 None LPC DESTINATION

PCI EXPRESS DESTINATION USB3 DESTINATION 8 None LPC0 MEC5085

Lane 1 NGFF-1 WLAN + BT 7 None 9 Touch screen LPC1 DEBUG PORT

Lane 2 CARD READER 8 None 10 None

Lane 3 None 9 None 11 None

Lane 4 None 10 None 12 CAMERA

Lane 5 None

Lane 6 None CLKOUT_PCIE DESTINATION CLKOUT_PCIE DESTINATION

Lane 7 None 0 None 10 None

Lane 8 None SATA DESTINATION 1 None 11 None

1 Lane 9 SSD 0A SSD 2 None 12 None 1

Lane 10 SSD 1A N/A 3 NGFF-1 WLAN 13 None

Lane 11 SSD N/A N/A 4 CARD READER 14 None

Lane 12 SSD N/A N/A 5 Thunderbolt 15 None

Lane 13 None 0B None 6 NGFF-2 SSD

Lane 14 None 1B HDD 7 GPU

Lane 15 2 None 8 None

Alpine Ridge
Lane 16 3 None 9 None

Symbol Note :

: means Digital Ground : means Analog Ground

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C. LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 4 of 71

A
 5 4 3 2 1

1K 1K
SMBUS Address [0x9a]
+3V_PCH +3VS
1K 1K
+3VS
AW44 SMBCLK
DMN66D0
BB43 SMBDATA DIMMA
DMN66D0
D D
5.1K
DIMMB
+3VS
5.1K
AR38 I2C0_SCK 0 ohm
PCH
AT42 I2C0_SDA 0 ohm Codec FFS

10K 10K
XDP

10K
+3VS +3VS_TP
10K
+3VS
AR41 I2C1_SCK_TP
I2C1_SDA_TP DMN66D0 TP
AR44
DMN66D0
AW45 AW42

SML1CLK 1K

SML1DATA 1K
+3V_PCH
C C

2.2K

A5 B6
+3VALW_EC
2.2K
A56 PBAT_SMBCLK 100 ohm
B59 PBAT_SMBDAT 100 ohm BATT 0x16
10K

+3VALW_EC
10K
MEC5085 B50 CHARGER_SMBCLK 0 ohm
A47 CHARGER_SMBDAT 0 ohm CHARGER 0x12

+3VS
B DMN66D0 B
Codec
DMN66D0

10K

+3V_PD
10K
+3VALW
DMN66D0
PD Controller
DMN66D0

10K 5.1K

+3VALW_EC 5.1K
+3.3V_GFX_AON
10K DGPU_PEX_RST#
B49 UPD_GPU_SMBCLK DMN66D0
GPU
B48 UPD_GPU_SMBDAT
DMN66D0 0x9E
2.2K

+3VALW_EC
A 2.2K A

B4 MCP23017_SMBCLK 0 ohm
A3 MCP23017_SMBDAT 0 ohm MCP23017 0x42

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
SMBus Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS Custom 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
O UT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 5 of 71
5 4 3 2 1
 5 4 3 2 1

+1V_PCH

1
XDP@

JTAG
CH3
+1V_PCH 0.1U_0402_25V6
2

RH492 1 2 XDP_PLTRST#
CPU
2.2K_0402_5%
1 XDP@ 2 CFG3
+3V_PCH RH474 1K_0402_5% XDP_TDO RH540 1 @ 2 0_0402_5% CPU_XDP_TDO [9]
+1V_PCH 1 @ 2 +1V_PCH
RH493 1 2 PCH_SYS_PWROK_XDP RH475 0_0402_5%
2.2K_0402_5% JXDP
D D
1 2 XDP_TDI RH541 1 @ 2 0_0402_5%
GND0 GND1 CPU_XDP_TDI [9]
3 4
[9,22] XDP_PREQ# OBSFN_A0 OBSFN_C0 CFG17 [9]
[9,22] XDP_PRDY# 5 6 CFG16 [9]
+VCCST 7 OBSFN_A1 OBSFN_C1 8
CFG0 9 GND2 GND3 10
[9] CFG0 OBSDATA_A0 OBSDATA_C0 CFG8 [9]
11 12
[9] CFG1 OBSDATA_A1 OBSDATA_C1 CFG9 [9] CPU_XDP_TMS [9]
13 14 XDP_TMS RH542 1 @ 2 0_0402_5%
RH97 1 @ 2 PCH_JTAG_TDO 15 GND4 GND5 16
[9] CFG2 OBSDATA_A2 OBSDATA_C2 CFG10 [9]
51_0402_5% CFG3 17 18
[9] CFG3 OBSDATA_A3 OBSDATA_C3 CFG11 [9]
RH98 1 @ 2 PCH_JTAG_TMS 19 20
51_0402_5% 21 GND6 GND7 22 XDP_TRST# RH543 1 @ 2 0_0402_5%
[9] XDP_BPM#0 OBSFN_B0 OBSFN_D0 CFG19 [9] CPU_XDP_TRST# [9,22]
RH100 1 @ 2 PCH_JTAG_TDI 23 24
[9] XDP_BPM#1 OBSFN_B1 OBSFN_D1 CFG18 [9]
51_0402_5% 25 26
[9] CFG4
27 GND8 GND9 28
CFG12 [9]
X06.13
29 OBSDATA_B0 OBSDATA_D0 30
+VCCSTG [9] CFG5 OBSDATA_B1 OBSDATA_D1 CFG13 [9]
31 32
33 GND10 GND11 34
[9] CFG6 OBSDATA_B2 OBSDATA_D2 CFG14 [9]
[9] CFG7 35 36 CFG15 [9]
37 OBSDATA_B3 OBSDATA_D3 38
RH494 1 2 CPU_XDP_TMS XDP_PWRGOOD 39 GND12 GND13 40
PW RGOOD/HOOK0 ITPCLK/HOOK4 PCH_XDP_CLK_P [17]
51_0402_5% PWRBTN#_XDP 41 42
HOOK1 ITPCLK#/HOOK5 PCH_XDP_CLK_N [17]
RH495 1 2 CPU_XDP_TDI 43 44
51_0402_5% PWR_DEBUG#_XDP 45 VCC_OBS_AB VCC_OBS_CD 46 XDP_PLTRST#
RH496 1 2 CPU_XDP_TDO PCH_SYS_PWROK_XDP 47 HOOK2 RESET#/HOOK6 48 XDP_DBRESET#
51_0402_5% 49 HOOK3 DBR#/HOOK7 50
51 GND14 GND15 52 XDP_TDO
[14,15,18,45] PCH_SMBDATA SDA TD0
53 54 XDP_TRST#
[14,15,18,45] PCH_SMBCLK SCL TRST#
PCH_JTAG_TCK 55 56 XDP_TDI
RH95 1 2 PCH_JTAG_TCK [18] PCH_JTAG_TCK CPU_XDP_TCK 57 TCK1 TDI 58 XDP_TMS

RH498 1
51_0402_5%
2 CPU_XDP_TCK X06.13
[9]
[18]
CPU_XDP_TCK
PCH_JTAGX
1
RH491
@ 2
0_0402_5%
59 TCK0
GND16
TMS
GND17
60 1 XDP@ 2
RH573 1K_0402_5%
PCH_SPI_WP#_R [17] PCH
51_0402_5% SAMTE_BSH-030-01-L-D-A
RH497 1 2 CPU_XDP_TRST# CONN@
51_0402_5%

C XDP_TMS RH12 1 @ 2 0_0402_5% PCH_JTAG_TMS C

PCH_JTAG_TMS [18]

XDP_TDI RH477 1 @ 2 0_0402_5% PCH_JTAG_TDI

PCH_JTAG_TDI [18]

XDP_TDO RH478 1 @ 2 0_0402_5% PCH_JTAG_TDO

RH479 1 XDP@ 2 0_0402_5% PCH_JTAG_TDO [18]
[18] PCH_ITP_PMODE

[9,16] PLTRST_CPU#
1 @ 2 XDP_PLTRST# X06.13
RH480 1K_0402_5%

[17] PCH_SPI_SI_R RH489 1 XDP@ 2 1K_0402_5%

RH490 1 @ 2 0_0402_5% PCH_SYS_PWROK_XDP +3VS

[18,48] RESET_OUT#
+3V_PCH_DSW
[18,48] PCH_RSMRST# RH481 1 XDP@ 2 1K_0402_5%

1
RH482 1 @ 2 1K_0402_5% XDP_PWRGOOD
[9,34] H_VCCST_PWRGD 1

RH5
XDP@ 1K_0402_5%
RH2

2
1K_0402_5%
X06.13
2

+VCCIO PWRBTN#_XDP RH6 1 XDP@ 2 0_0402_5% XDP_DBRESET# RH8 1 2 0_0402_5%

SIO_PWRBTN# [18,48] SYS_RESET# [18,52]
@
0.1U_0402_25V6

0.1U_0402_25V6
1

1
RH483
CH174
XDP@

CH175
XDP@
150_0402_5%
2

2
2

PWR_DEBUG#_XDP 1 2 CFG0
RH488 1K_0402_5%
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
XDP CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 6 of 71
5 4 3 2 1
 5 4 3 2 1

?
SKYLAKE_HALO
UH1C
BGA1440

PEG_GTX_C_HRX_P15 E25 B25 PEG_HTX_GRX_P15 DIS@ CH5 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P15

PEG_GTX_C_HRX_N15 D25 PEG_RXP[0] PEG_TXP[0] A25 PEG_HTX_GRX_N15 DIS@ CH6 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N15
PEG_HTX_C_GRX_P[0..15] PEG_RXN[0] PEG_TXN[0]
[23] PEG_HTX_C_GRX_P[0..15]
PEG_GTX_C_HRX_P14 E24 B24 PEG_HTX_GRX_P14 DIS@ CH7 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_N[0..15] PEG_GTX_C_HRX_N14 F24 PEG_RXP[1] PEG_TXP[1] C24 PEG_HTX_GRX_N14 DIS@ CH8 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N14
[23] PEG_HTX_C_GRX_N[0..15] PEG_RXN[1] PEG_TXN[1]
PEG_GTX_C_HRX_P[0..15] PEG_GTX_C_HRX_P13 E23 B23 PEG_HTX_GRX_P13 DIS@ CH9 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P13
[23] PEG_GTX_C_HRX_P[0..15] PEG_RXP[2] PEG_TXP[2]
PEG_GTX_C_HRX_N13 D23 A23 PEG_HTX_GRX_N13 DIS@ CH10 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N13
PEG_GTX_C_HRX_N[0..15] PEG_RXN[2] PEG_TXN[2]
[23] PEG_GTX_C_HRX_N[0..15]
PEG_GTX_C_HRX_P12 E22 B22 PEG_HTX_GRX_P12 DIS@ CH11 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P12
PEG_GTX_C_HRX_N12 F22 PEG_RXP[3] PEG_TXP[3] C22 PEG_HTX_GRX_N12 DIS@ CH12 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N12
PEG_RXN[3] PEG_TXN[3]
PEG_GTX_C_HRX_P11 E21 B21 PEG_HTX_GRX_P11 DIS@ CH13 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P11
D
PEG_GTX_C_HRX_N11 D21 PEG_RXP[4] PEG_TXP[4] A21 PEG_HTX_GRX_N11 DIS@ CH14 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N11 D
PEG_RXN[4] PEG_TXN[4]
PEG_GTX_C_HRX_P10 E20 B20 PEG_HTX_GRX_P10 DIS@ CH15 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P10
PEG_GTX_C_HRX_N10 F20 PEG_RXP[5] PEG_TXP[5] C20 PEG_HTX_GRX_N10 DIS@ CH16 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N10
PEG_RXN[5] PEG_TXN[5]
PEG_GTX_C_HRX_P9 E19 B19 PEG_HTX_GRX_P9 DIS@ CH17 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P9
PEG_GTX_C_HRX_N9 D19 PEG_RXP[6] PEG_TXP[6] A19 PEG_HTX_GRX_N9 DIS@ CH18 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N9
PEG_RXN[6] PEG_TXN[6]
PEG_GTX_C_HRX_P8 E18 B18 PEG_HTX_GRX_P8 DIS@ CH19 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P8
PEG_GTX_C_HRX_N8 F18 PEG_RXP[7] PEG_TXP[7] C18 PEG_HTX_GRX_N8 DIS@ CH20 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N8
PEG_RXN[7] PEG_TXN[7]
PEG_GTX_C_HRX_P7 D17 A17 PEG_HTX_GRX_P7 DIS@ CH21 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P7
PEG_GTX_C_HRX_N7 E17 PEG_RXP[8] PEG_TXP[8] B17 PEG_HTX_GRX_N7 DIS@ CH22 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N7
PEG_RXN[8] PEG_TXN[8]
PEG_GTX_C_HRX_P6 F16 C16 PEG_HTX_GRX_P6 DIS@ CH23 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P6
PEG_GTX_C_HRX_N6 E16 PEG_RXP[9] PEG_TXP[9] B16 PEG_HTX_GRX_N6 DIS@ CH24 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N6
PEG_RXN[9] PEG_TXN[9]
PEG_GTX_C_HRX_P5 D15 A15 PEG_HTX_GRX_P5 DIS@ CH25 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P5
PEG_GTX_C_HRX_N5 E15 PEG_RXP[10] PEG_TXP[10] B15 PEG_HTX_GRX_N5 DIS@ CH26 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N5
PEG_RXN[10] PEG_TXN[10]
PEG_GTX_C_HRX_P4 F14 C14 PEG_HTX_GRX_P4 DIS@ CH27 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P4
PEG_GTX_C_HRX_N4 E14 PEG_RXP[11] PEG_TXP[11] B14 PEG_HTX_GRX_N4 DIS@ CH28 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N4
PEG_RXN[11] PEG_TXN[11]
PEG_GTX_C_HRX_P3 D13 A13 PEG_HTX_GRX_P3 DIS@ CH29 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P3
PEG_GTX_C_HRX_N3 E13 PEG_RXP[12] PEG_TXP[12] B13 PEG_HTX_GRX_N3 DIS@ CH30 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N3
PEG_RXN[12] PEG_TXN[12]
PEG_GTX_C_HRX_P2 F12 C12 PEG_HTX_GRX_P2 DIS@ CH31 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P2
PEG_GTX_C_HRX_N2 E12 PEG_RXP[13] PEG_TXP[13] B12 PEG_HTX_GRX_N2 DIS@ CH32 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N2
PEG_RXN[13] PEG_TXN[13]
PEG_GTX_C_HRX_P1 D11 A11 PEG_HTX_GRX_P1 DIS@ CH33 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P1
PEG_GTX_C_HRX_N1 E11 PEG_RXP[14] PEG_TXP[14] B11 PEG_HTX_GRX_N1 DIS@ CH34 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N1
PEG_RXN[14] PEG_TXN[14]
+VCCIO PEG_GTX_C_HRX_P0 F10 C10 PEG_HTX_GRX_P0 DIS@ CH35 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P0
PEG_GTX_C_HRX_N0 E10 PEG_RXP[15] PEG_TXP[15] B10 PEG_HTX_GRX_N0 DIS@ CH36 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N0
PEG_RXN[15] PEG_TXN[15]

RH24 1 2 24.9_0402_1% G2
PEG_RCOMP
C C

D8 B8
[19] DMI_CRX_PTX_P0 DMI_RXP[0] DMI_TXP[0] DMI_CTX_PRX_P0 [19]
[19] DMI_CRX_PTX_N0 E8 A8 DMI_CTX_PRX_N0 [19]
DMI_RXN[0] DMI_TXN[0]

[19] DMI_CRX_PTX_P1 E6 C6 DMI_CTX_PRX_P1 [19]

F6 DMI_RXP[1] DMI_TXP[1] B6
[19] DMI_CRX_PTX_N1 DMI_RXN[1] DMI_TXN[1] DMI_CTX_PRX_N1 [19]

[19] DMI_CRX_PTX_P2 D5 B5 DMI_CTX_PRX_P2 [19]

E5 DMI_RXP[2] DMI_TXP[2] A5
[19] DMI_CRX_PTX_N2 DMI_RXN[2] DMI_TXN[2] DMI_CTX_PRX_N2 [19]
J8 D4
[19] DMI_CRX_PTX_P3 DMI_RXP[3] DMI_TXP[3] DMI_CTX_PRX_P3 [19]
J9 B4
[19] DMI_CRX_PTX_N3 DMI_RXN[3] DMI_TXN[3] DMI_CTX_PRX_N3 [19]

3 OF 14
SKL-H_BGA1440
REV = 1 ?
@

?
SKYLAKE_HALO
UH1D
BGA1440
K36 D29
[37] DDI1_HTX_TBRX_P0 DDI1_TXP[0] EDP_TXP[0] EDP_TXP0 [35]
[37] DDI1_HTX_TBRX_N0 K37 E29 EDP_TXN0 [35]
B
J35 DDI1_TXN[0] EDP_TXN[0] F28 B
[37] DDI1_HTX_TBRX_P1 DDI1_TXP[1] EDP_TXP[1] EDP_TXP1 [35]
J34 E28
[37] DDI1_HTX_TBRX_N1 DDI1_TXN[1] EDP_TXN[1] EDP_TXN1 [35]
[37] DDI1_HTX_TBRX_P2 H37 B29 EDP_TXN2 [35]
H36 DDI1_TXP[2] EDP_TXN[2] A29
[37] DDI1_HTX_TBRX_N2 DDI1_TXN[2] EDP_TXP[2] EDP_TXP2 [35]
[37] DDI1_HTX_TBRX_P3 J37 B28 EDP_TXN3 [35]
J38 DDI1_TXP[3] EDP_TXN[3] C28
[37] DDI1_HTX_TBRX_N3 DDI1_TXN[3] EDP_TXP[3] EDP_TXP3 [35]

[37] DDI1_CPU_AUXP D27 C26 EDP_AUXP [35]

E27 DDI1_AUXP EDP_AUXP B26
[37] DDI1_CPU_AUXN DDI1_AUXN EDP_AUXN EDP_AUXN [35]
H34
[37] DDI2_HTX_TBRX_P0 DDI2_TXP[0] +VCCIO
H33
[37] DDI2_HTX_TBRX_N0 DDI2_TXN[0]
[37] DDI2_HTX_TBRX_P1 F37 A33 EDP_DISP_UTIL RH456 1 @ 2 0_0402_5% BIA_PWM_PCH [16,35]
G38 DDI2_TXP[1] EDP_DISP_UTIL
[37] DDI2_HTX_TBRX_N1 DDI2_TXN[1]
[37] DDI2_HTX_TBRX_P2 F34
F35 DDI2_TXP[2] D37 EDP_COMP RH30 1 2 24.9_0402_1%
[37] DDI2_HTX_TBRX_N2 DDI2_TXN[2] EDP_RCOMP
E37
[37] DDI2_HTX_TBRX_P3 DDI2_TXP[3]
[37] DDI2_HTX_TBRX_N3 E36 EDP_COMP
DDI2_TXN[3] CAD Note:Trace width=20 mils ,Spacing=25mil,
F26 Max length=100 mils.
[37] DDI2_CPU_AUXP DDI2_AUXP
E26
[37] DDI2_CPU_AUXN DDI2_AUXN
C34
D34 DDI3_TXP[0]
B36 DDI3_TXN[0]
B34 DDI3_TXP[1]
F33 DDI3_TXN[1]
E33 DDI3_TXP[2]
C33 DDI3_TXN[2] Close to CPU
B33 DDI3_TXP[3]
DDI3_TXN[3] G27
PROC_AUDIO_CLK AUD_AZA_CPU_SCLK [18]
A27 G25
DDI3_AUXP PROC_AUDIO_SDI AUD_AZA_CPU_SDO [18]
B27 G29 RH145 1 2 20_0402_5% AUD_AZA_CPU_SDI_R [18]
DDI3_AUXN PROC_AUDIO_SDO

4 OF 14
SKL-H_BGA1440
?
A REV = 1 A
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
PROCESSOR(1/7) DMI,FDI,PEG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS C 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 7 of 71
5 4 3 2 1
 5 4 3 2 1

Interleave

?
SKYLAKE_HALO ?
SKYLAKE_HALO
UH1A UH1B
BGA1440 BGA1440
DDR_A_D0 BR6 AG1 DDR_B_D0 BT11 AM9
DDR0_DQ[0] DDR0_CKP[0] M_CLK_DDR0 [14] DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKP[0] M_CLK_DDR2 [15]
DDR_A_D1 BT6 AG2 DDR_B_D1 BR11 AN9
DDR0_DQ[1] DDR0_CKN[0] M_CLK_DDR#0 [14] DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[0] M_CLK_DDR#2 [15]
[14] DDR_A_D[0..63] DDR_A_D2 BP3 AK1 M_CLK_DDR#1 [14] DDR_B_D6 BT8 AM8 M_CLK_DDR#3 [15]
DDR_A_D7 BR3 DDR0_DQ[2] DDR0_CKN[1] AK2 DDR_B_D2 BR8 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKN[1] AM7
[14] DDR_A_MA[0..13] DDR0_DQ[3] DDR0_CKP[1] M_CLK_DDR1 [14] DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] M_CLK_DDR3 [15]
[14] DDR_A_DQS#[0..7] DDR_A_D4 BN5 AL3 DDR_B_D4 BP11 AM11
DDR_A_D5 BP6 DDR0_DQ[4] DDR0_CLKP[2] AK3 DDR_B_D5 BN11 DDR1_DQ[4]/DDR0_DQ[20] DDR1_CLKP[2] AM10
[14] DDR_A_DQS[0..7] DDR0_DQ[5] DDR0_CLKN[2] DDR1_DQ[5]/DDR0_DQ[21] DDR1_CLKN[2]
DDR_A_D6 BP2 AL2 DDR_B_D3 BP8 AJ10
DDR_A_D3 BN3 DDR0_DQ[6] DDR0_CLKP[3] AL1 DDR_B_D7 BN8 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CLKP[3] AJ11
DDR_A_D9 BL4 DDR0_DQ[7] DDR0_CLKN[3] DDR_B_D12 BL12 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CLKN[3]
DDR_A_D13 BL5 DDR0_DQ[8] AT1 DDR_B_D8 BL11 DDR1_DQ[8]/DDR0_DQ[24] AT8
D DDR0_DQ[9] DDR0_CKE[0] DDR_CKE0_DIMMA [14] DDR1_DQ[9]/DDR0_DQ[25] DDR1_CKE[0] DDR_CKE2_DIMMB [15] D
DDR_A_D10 BL2 AT2 DDR_B_D9 BL8 AT10
DDR0_DQ[10] DDR0_CKE[1] DDR_CKE1_DIMMA [14] DDR1_DQ[10]/DDR0_DQ[26] DDR1_CKE[1] DDR_CKE3_DIMMB [15]
DDR_A_D11 BM1 AT3 DDR_B_D10 BJ8 AT7
[15] DDR_B_D[0..63] DDR0_DQ[11] DDR0_CKE[2] DDR1_DQ[11]/DDR0_DQ[27] DDR1_CKE[2]
[15] DDR_B_MA[0..13] DDR_A_D12 BK4 AT5 DDR_B_D14 BJ11 AT11
DDR_A_D8 BK5 DDR0_DQ[12] DDR0_CKE[3] DDR_B_D11 BJ10 DDR1_DQ[12]/DDR0_DQ[28] DDR1_CKE[3]
[15] DDR_B_DQS#[0..7] DDR0_DQ[13] DDR1_DQ[13]/DDR0_DQ[29]
[15] DDR_B_DQS[0..7] DDR_A_D14 BK1 AD5 DDR_CS0_DIMMA# [14] DDR_B_D13 BL7 AF11 DDR_CS2_DIMMB# [15]
DDR_A_D15 BK2 DDR0_DQ[14] DDR0_CS#[0] AE2 DDR_B_D15 BJ7 DDR1_DQ[14]/DDR0_DQ[30] DDR1_CS#[0] AE7
DDR0_DQ[15] DDR0_CS#[1] DDR_CS1_DIMMA# [14] DDR1_DQ[15]/DDR0_DQ[31] DDR1_CS#[1] DDR_CS3_DIMMB# [15]
DDR_A_D20 BG4 AD2 DDR_B_D16 BG11 AF10
DDR_A_D16 BG5 DDR0_DQ[16]/DDR0_DQ[32] DDR0_CS#[2] AE5 DDR_B_D17 BG10 DDR1_DQ[16]/DDR0_DQ[48] DDR1_CS#[2] AE10
DDR_A_D23 BF4 DDR0_DQ[17]/DDR0_DQ[33] DDR0_CS#[3] DDR_B_D21 BG8 DDR1_DQ[17]/DDR0_DQ[49] DDR1_CS#[3]
DDR_A_D19 BF5 DDR0_DQ[18]/DDR0_DQ[34] AD3 DDR_B_D19 BF8 DDR1_DQ[18]/DDR0_DQ[50] AF7
DDR0_DQ[19]/DDR0_DQ[35] DDR0_ODT[0] M_ODT0 [14] DDR1_DQ[19]/DDR0_DQ[51] DDR1_ODT[0] M_ODT2 [15]
DDR_A_D21 BG2 AE4 DDR_B_D18 BF11 AE8
DDR0_DQ[20]/DDR0_DQ[36] DDR0_ODT[1] M_ODT1 [14] DDR1_DQ[20]/DDR0_DQ[52] DDR1_ODT[1] M_ODT3 [15]
DDR_A_D17 BG1 AE1 DDR_B_D22 BF10 AE9
DDR_A_D22 BF1 DDR0_DQ[21]/DDR0_DQ[37] DDR0_ODT[2] AD4 DDR_B_D20 BG7 DDR1_DQ[21]/DDR0_DQ[53] DDR1_ODT[2] AE11
DDR_A_D18 BF2 DDR0_DQ[22]/DDR0_DQ[38] DDR0_ODT[3] DDR_B_D23 BF7 DDR1_DQ[22]/DDR0_DQ[54] DDR1_ODT[3]
DDR_A_D24 BD2 DDR0_DQ[23]/DDR0_DQ[39] AH5 DDR_B_D26 BB11 DDR1_DQ[23]/DDR0_DQ[55] AH10
DDR0_DQ[24]/DDR0_DQ[40] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AH1 DDR_A_BS0 [14] DDR1_DQ[24]/DDR0_DQ[56] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] AH11 DDR_B_RAS# [15]
DDR_A_D25 BD1 DDR_B_D24 BC11
DDR0_DQ[25]/DDR0_DQ[41] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AU1 DDR_A_BS1 [14] DDR1_DQ[25]/DDR0_DQ[57] DDR1_W E#/DDR1_CAB[2]/DDR1_MA[14] AF8 DDR_B_WE# [15]
DDR_A_D26 BC4 DDR_B_D31 BB8
DDR0_DQ[26]/DDR0_DQ[42] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_A_BG0 [14] DDR1_DQ[26]/DDR0_DQ[58] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR_B_CAS# [15]
DDR_A_D27 BC5 DDR_B_D25 BC8
DDR_A_D28 BD5 DDR0_DQ[27]/DDR0_DQ[43] AH4 DDR_B_D28 BC10 DDR1_DQ[27]/DDR0_DQ[59] AH8
DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AG4 DDR_A_RAS# [14] DDR1_DQ[28]/DDR0_DQ[60] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AH9 DDR_B_BS0 [15]
DDR_A_D29 BD4 DDR_A_WE# [14] DDR_B_D30 BB10 DDR_B_BS1 [15]
DDR_A_D30 BC1 DDR0_DQ[29]/DDR0_DQ[45] DDR0_W E#/DDR0_CAB[2]/DDR0_MA[14] AD1 DDR_B_D29 BC7 DDR1_DQ[29]/DDR0_DQ[61] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AR9
DDR0_DQ[30]/DDR0_DQ[46] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR_A_CAS# [14] DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR_B_BG0 [15]
DDR_A_D31 BC2 DDR_B_D27 BB7
DDR_A_D32 AB1 DDR0_DQ[31]/DDR0_DQ[47] AH3 DDR_A_MA0 DDR_B_D34 AA11 DDR1_DQ[31]/DDR0_DQ[63] AJ9 DDR_B_MA0
DDR_A_D33 AB2 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] AP4 DDR_A_MA1 DDR_B_D38 AA10 DDR1_DQ[32]/DDR1_DQ[16] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] AK6 DDR_B_MA1
DDR_A_D34 AA4 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AN4 DDR_A_MA2 DDR_B_D32 AC11 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] AK5 DDR_B_MA2
DDR_A_D35 AA5 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AP5 DDR_A_MA3 DDR_B_D36 AC10 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] AL5 DDR_B_MA3
DDR_A_D36 AB5 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] AP2 DDR_A_MA4 DDR_B_D35 AA7 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[3] AL6 DDR_B_MA4
DDR_A_D37 AB4 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] AP1 DDR_A_MA5 DDR_B_D39 AA8 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[4] AM6 DDR_B_MA5
DDR_A_D38 AA2 DDR0_DQ[37]/DDR1_DQ[5] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] AP3 DDR_A_MA6 DDR_B_D37 AC8 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AN7 DDR_B_MA6
DDR_A_D39 AA1 DDR0_DQ[38]/DDR1_DQ[6] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AN1 DDR_A_MA7 DDR_B_D33 AC7 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] AN10 DDR_B_MA7
DDR_A_D44 V5 DDR0_DQ[39]/DDR1_DQ[7] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AN3 DDR_A_MA8 DDR_B_D40 W8 DDR1_DQ[39]/DDR1_DQ[23] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AN8 DDR_B_MA8
DDR_A_D45 V2 DDR0_DQ[40]/DDR1_DQ[8] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AT4 DDR_A_MA9 DDR_B_D41 W7 DDR1_DQ[40]/DDR1_DQ[24] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AR11 DDR_B_MA9
DDR_A_D43 U1 DDR0_DQ[41]/DDR1_DQ[9] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] AH2 DDR_A_MA10 DDR_B_D42 V10 DDR1_DQ[41]/DDR1_DQ[25] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] AH7 DDR_B_MA10
DDR_A_D47 U2 DDR0_DQ[42]/DDR1_DQ[10] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] AN2 DDR_A_MA11 DDR_B_D43 V11 DDR1_DQ[42]/DDR1_DQ[26] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AN11 DDR_B_MA11
DDR_A_D41 V1 DDR0_DQ[43]/DDR1_DQ[11] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] AU4 DDR_A_MA12 DDR_B_D44 W 11 DDR1_DQ[43]/DDR1_DQ[27] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AR10 DDR_B_MA12
DDR_A_D40 V4 DDR0_DQ[44]/DDR1_DQ[12] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] AE3 DDR_A_MA13 DDR_B_D45 W 10 DDR1_DQ[44]/DDR1_DQ[28] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AF9 DDR_B_MA13
DDR_A_D42 U5 DDR0_DQ[45]/DDR1_DQ[13] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU2 DDR_B_D47 V7 DDR1_DQ[45]/DDR1_DQ[29] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AR7
DDR0_DQ[46]/DDR1_DQ[14] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_BG1 [14] DDR1_DQ[46]/DDR1_DQ[30] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR_B_BG1 [15]
C DDR_A_D46 U4 AU3 DDR_A_ACT# [14] DDR_B_D46 V8 AT9 DDR_B_ACT# [15] C
DDR_A_D53 R2 DDR0_DQ[47]/DDR1_DQ[15] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR_B_D48 R11 DDR1_DQ[47]/DDR1_DQ[31] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR_A_D51 P5 DDR0_DQ[48]/DDR1_DQ[32] AG3 DDR_B_D51 P11 DDR1_DQ[48] AJ7
DDR0_DQ[49]/DDR1_DQ[33] DDR0_PAR DDR_A_PAR [14] DDR1_DQ[49] DDR1_PAR DDR_B_PAR [15]
DDR_A_D49 R4 AU5 DDR_B_D50 P7 AR8
DDR0_DQ[50]/DDR1_DQ[34] DDR0_ALERT# DDR_A_ALERT# [14] DDR1_DQ[50] DDR1_ALERT# DDR_B_ALERT# [15]
DDR_A_D55 P4 DDR_B_D52 R8
DDR_A_D52 R5 DDR0_DQ[51]/DDR1_DQ[35] DDR_B_D53 R10 DDR1_DQ[51]
DDR_A_D54 P2 DDR0_DQ[52]/DDR1_DQ[36] BR5 DDR_A_DQS#0 DDR_B_D55 P10 DDR1_DQ[52] BP9 DDR_B_DQS#0
DDR_A_D48 R1 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSN[0] BL3 DDR_A_DQS#1 DDR_B_D49 R7 DDR1_DQ[53] DDR1_DQSN[0]/DDR0_DQSN[2] BL9 DDR_B_DQS#1
DDR_A_D50 P1 DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQSN[1] BG3 DDR_A_DQS#2 DDR_B_D54 P8 DDR1_DQ[54] DDR1_DQSN[1]/DDR0_DQSN[3] BG9 DDR_B_DQS#2
DDR_A_D56 M4 DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQSN[2]/DDR0_DQSN[4] BD3 DDR_A_DQS#3 DDR_B_D58 L11 DDR1_DQ[55] DDR1_DQSN[2]/DDR0_DQSN[6] BC9 DDR_B_DQS#3
DDR_A_D57 M1 DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQSN[3]/DDR0_DQSN[5] AB3 DDR_A_DQS4 DDR_B_D57 M11 DDR1_DQ[56] DDR1_DQSN[3]/DDR0_DQSN[7] AC9 DDR_B_DQS#4
DDR_A_D58 L4 DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQSP[4]/DDR1_DQSP[0] V3 DDR_A_DQS5 DDR_B_D59 L7 DDR1_DQ[57] DDR1_DQSN[4]/DDR1_DQSN[2] W9 DDR_B_DQS#5
DDR_A_D63 L2 DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQSP[5]/DDR1_DQSP[1] R3 DDR_A_DQS6 DDR_B_D61 M8 DDR1_DQ[58] DDR1_DQSN[5]/DDR1_DQSN[3] R9 DDR_B_DQS#6
DDR_A_D60 M5 DDR0_DQ[59]/DDR1_DQ[43] DDR0_DQSP[6]/DDR1_DQSP[4] M3 DDR_A_DQS7 DDR_B_D62 L10 DDR1_DQ[59] DDR1_DQSN[6] M9 DDR_B_DQS#7
DDR_A_D61 M2 DDR0_DQ[60]/DDR1_DQ[44] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_B_D60 M10 DDR1_DQ[60] DDR1_DQSN[7]
DDR_A_D62 L5 DDR0_DQ[61]/DDR1_DQ[45] BP5 DDR_A_DQS0 DDR_B_D56 M7 DDR1_DQ[61] BR9 DDR_B_DQS0
DDR_A_D59 L1 DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQSP[0] BK3 DDR_A_DQS1 DDR_B_D63 L8 DDR1_DQ[62] DDR1_DQSP[0]/DDR0_DQSP[2] BJ9 DDR_B_DQS1
DDR0_DQ[63]/DDR1_DQ[47] DDR0_DQSP[1] BF3 DDR_A_DQS2 DDR1_DQ[63] DDR1_DQSP[1]/DDR0_DQSP[3] BF9 DDR_B_DQS2
BA2 DDR0_DQSP[2]/DDR0_DQSP[4] BC3 DDR_A_DQS3 AW 11 DDR1_DQSP[2]/DDR0_DQSP[6] BB9 DDR_B_DQS3
BA1 DDR0_ECC[0] DDR0_DQSP[3]/DDR0_DQSP[5] AA3 DDR_A_DQS#4 AY11 DDR1_ECC[0] DDR1_DQSP[3]/DDR0_DQSP[7] AA9 DDR_B_DQS4
AY4 DDR0_ECC[1] DDR0_DQSN[4]/DDR1_DQSN[0] U3 DDR_A_DQS#5 AY8 DDR1_ECC[1] DDR1_DQSP[4]/DDR1_DQSP[2] V9 DDR_B_DQS5
AY5 DDR0_ECC[2] DDR0_DQSN[5]/DDR1_DQSN[1] P3 DDR_A_DQS#6 AW 8 DDR1_ECC[2] DDR1_DQSP[5]/DDR1_DQSP[3] P9 DDR_B_DQS6
BA5 DDR0_ECC[3] DDR0_DQSN[6]/DDR1_DQSN[4] L3 DDR_A_DQS#7 AY10 DDR1_ECC[3] DDR1_DQSP[6] L9 DDR_B_DQS7
BA4 DDR0_ECC[4] DDR0_DQSN[7]/DDR1_DQSN[5] AW 10 DDR1_ECC[4] DDR1_DQSP[7]
AY1 DDR0_ECC[5] AY3 AY7 DDR1_ECC[5] AW 9
AY2 DDR0_ECC[6] DDR0_DQSP[8] BA3 AW 7 DDR1_ECC[6] DDR1_DQSP[8] AY9
DDR0_ECC[7] DDR0_DQSN[8] DDR1_ECC[7] DDR1_DQSN[8]

DDR CHANNEL B

DDR CHANNEL A RH148 1 2 121_0402_1% G1 BN13

DDR_RCOMP[0] DDR_VREF_CA +V_DDR_REFA_R
RH149 1 2 75_0402_1% H1 BP13
RH150 1 2 100_0402_1% J2 DDR_RCOMP[1] DDR0_VREF_DQ BR13
DDR_RCOMP[2] DDR1_VREF_DQ +V_DDR_REFB_R
1 OF 14 2 OF 14
SKL-H_BGA1440 SKL-H_BGA1440
REV = 1 ? REV = 1 ?
B @ @ B

A A

Security Classification Compal Secret Data

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
PROCESSOR(3/7) DDRIII
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS C 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 8 of 71
5 4 3 2 1
 5 4 3 2 1

CFG Straps for Processor +VCCST

Stall reset sequence after PCU PLL lock until de-as

serted 1 2 H_THERMTRIP#_R
?
SKYLAKE_HALO
RH163 1K_0402_5% UH1E
BGA1440

*
1 = (Default) Normal Operation; No stall. 1 @ 2 XDP_PREQ# B31 BN25 CFG0
[17] PCH_CPU_BCLK_P BCLKP CFG[0] CFG0 [6]
CFG0 RH156 51_0402_5% [17] PCH_CPU_BCLK_N A32 BN27 CFG1 CFG1 [6]
BCLKN CFG[1] BN26 CFG2
CFG[2] CFG2 [6]
1 2 H_VCCST_PWRGD [17] PCH_CPU_PCIBCLK_P D35 BN28 CFG3 CFG3 [6]
D
C36 PCI_BCLKP CFG[3] BR20 CFG4 D
0 = Stall. RH164 1K_0402_5% [17] PCH_CPU_PCIBCLK_N PCI_BCLKN CFG[4] CFG4 [6]
BM20 CFG5
CFG[5] CFG5 [6]
1 2 VR_SVID_DATA [17] CPU_24MHZ_P E31 BT20 CFG6 CFG6 [6]
RH151 100_0402_5% D31 CLK24P CFG[6] BP20 CFG7
[17] CPU_24MHZ_N CLK24N CFG[7] CFG7 [6]
CFG0 1 @ 2 BR23 CFG8 CFG8 [6]
RH183 1K_0402_5% 1 2 VR_SVID_ALERT# CFG[8] BR22 CFG9
CFG[9] CFG9 [6]
RH152 56.2_0402_1% BT23 CFG10
CFG[10] CFG10 [6]
BT22 CFG11 CFG11 [6]
1 @ 2 H_CATERR# CFG[11] BM19 CFG12
CFG[12] CFG12 [6]
RH570 49.9_0402_1% BR19 CFG13 CFG13 [6]
CFG[13] BP19 CFG14
CFG[14] CFG14 [6]
VR_SVID_ALERT# RH153 1 2 220_0402_5% VR_SVID_ALERT#_R BH31 BT19 CFG15
[64] VR_SVID_ALERT# VIDALERT# CFG[15] CFG15 [6]
[64] VR_SVID_CLK BH32
VR_SVID_DATA BH29 VIDSCK BN23 CFG17
[64] VR_SVID_DATA VIDSOUT CFG[17] CFG17 [6]
[48,56,64] H_PROCHOT# H_PROCHOT# RH158 1 2 499_0402_1% H_PROCHOT#_R BR30 BP23 CFG16 CFG16 [6]
+VCCSTG PROCHOT# CFG[16]
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS CFG[19]
BP22 CFG19 CFG19 [6]
DDR_VTT_PG_CTRL BT13 BN22 CFG18
DDR_VTT_CNTL CFG[18] CFG18 [6]

1: Normal Operation; Lane # definition matches BR27

BPM#[0] XDP_BPM#0 [6]
CFG2 BT27
socket pin map definition 1 2 H_PROCHOT# BPM#[1] BM31
XDP_BPM#1 [6]
RH165 1K_0402_5% H_VCCST_PWRGD 1 2 VCCST_PWRGD_CPU H13 BPM#[2] BT30
[6,34] H_VCCST_PWRGD VCCST_PW RGD BPM#[3]

*
0:Lane Reversed RH154 60.4_0402_1%
BT31
[18] H_CPUPWRGD PROCPW RGD
[6,16] PLTRST_CPU# PLTRST_CPU# BP35 BT28 CPU_XDP_TDO CPU_XDP_TDO [6]
H_PM_SYNC_R BM34 RESET# PROC_TDO BL32 CPU_XDP_TDI
[16] H_PM_SYNC_R PM_SYNC PROC_TDI CPU_XDP_TDI [6]
CFG2 1 2 H_PM_DOWN RH155 1 2 20_0402_5% H_PM_DOWN_R BP31 BP28 CPU_XDP_TMS
[16] H_PM_DOWN PM_DOW N PROC_TMS CPU_XDP_TMS [6]
RH184 1K_0402_5% RH190 1 @ 2 0_0402_5% H_PECI_R BT34 BR28 CPU_XDP_TCK
X06.26 [16,48]
[16,48]
H_PECI
H_THERMTRIP#_R H_THERMTRIP#_R J31 PECI PROC_TCK CPU_XDP_TCK [6]
THERMTRIP# BP30 CPU_XDP_TRST#
PROC_TRST# CPU_XDP_TRST# [6,22]
RH519 1 @ 2 0_0402_5% BR33 BL30 XDP_PREQ#
[16] PROC_DETECT# SKTOCC# PROC_PREQ# XDP_PREQ# [6,22]
BN1 BP27 XDP_PRDY#
PROC_SELECT# PROC_PRDY# XDP_PRDY# [6,22]
H_CATERR# BM30
CATERR# BT25 CFG_RCOMP
CFG_RCOMP
Display Port Presence Strap +1.2V_DDR

1
C UC1 C
5 1 RH59
VCC NC 5 OF 14
1 : Disabled; No Physical Display Port SKL-H_BGA1440 49.9_0402_1%
CFG4 1 2 DDR_VTT_PG_CTRL ?
attached to Embedded Display Port @ 4 A REV = 1
Y

2
CH197 3 @
GND

*
0 : Enabled; An external Display Port device is 2
0.1U_0402_10V7K
74AUP1G07GW_TSSOP5
connected to the Embedded Display Port

CFG4 1 2 +3VS
RH185 1K_0402_5%

1
RH525
220K_0402_5%
2

[59] SM_PG_CTRL
PCIE Port Bifurcation Straps
?
SKYLAKE_HALO

*10:
11: (Default) x16 - Device 1 functions 1 and 2 disa
bled UH1K
BGA1440
CFG[6:5] x8, x8 - Device 1 function 1 enabled ; function2
@ PAD~D T39 D1 BM33 T66 PAD~D @
disabled @ PAD~D T40 E1 RSVD_TP RSVD_TP BL33 T67 PAD~D @
E3 RSVD_TP RSVD_TP
01: Reserved - (Device 1 function 1 disabled ; func
tion @ PAD~D T41
RSVD_TP
@ PAD~D T42 E2 BJ14 T68 PAD~D @
2 enabled) RSVD_TP RSVD_TP BJ13 T69 PAD~D @
BR1 RSVD_TP
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled @ PAD~D T43
RSVD_TP
@ PAD~D T44 BT2 BK28 T70 PAD~D @
RSVD_TP RSVD BJ28 T71 PAD~D @
@ PAD~D T45 BN35 RSVD
CFG5 1 @ 2 RSVD BJ18
B
RH186 1K_0402_5% @ PAD~D T46 J24 VSS B

@ PAD~D T47 H24 RSVD BJ16 T73 PAD~D @

CFG6 1 @ 2 @ PAD~D T48 BN33 RSVD RSVD_TP BK16 T74 PAD~D @
RH187 1K_0402_5% @ PAD~D T49 BL34 RSVD RSVD_TP
RSVD
@ PAD~D T50 N29 BK24 T75 PAD~D @
@ PAD~D T51 R14 RSVD RSVD_TP BJ24 T76 PAD~D @
@ PAD~D T52 AE29 RSVD RSVD_TP
@ PAD~D T53 AA14 RSVD BK21 T77 PAD~D @
RSVD RSVD BJ21 T78 PAD~D @
RSVD
PEG DEFER TRAINING A36
RSVD
A37 BT17 T79 PAD~D @
RSVD RSVD BR17 T80 PAD~D @
RSVD

*
1: (Default) PEG Train immediately following xxRESE
TB [22] PCH_TRIGGER PCH_TRIGGER RH167 1 2 30_0402_5% PCH_TRIGGER_R H23
RH192 1 2 30_0402_5% J23 PROC_TRIGIN BK18
CFG7 de assertion [22] CPU_TRIGGER CPU_TRIGGER CPU_TRIGGER_R
PROC_TRIGOUT VSS
@ PAD~D T57 F30 BJ34 T81 PAD~D @
E30 RSVD RSVD_TP BJ33
0: PEG Wait for BIOS for training @ PAD~D T58
RSVD RSVD_TP
T82 PAD~D @

@ PAD~D T59 B30

@ PAD~D T60 C30 RSVD
CFG7 1 @ 2 RSVD G13 T83 PAD~D @
RH188 1K_0402_5% @ PAD~D T61 G3 RSVD AJ8 T84 PAD~D @
@ PAD~D T62 J3 RSVD RSVD BL31
RSVD RSVD
B2 T85 PAD~D @
NCTF B38 T86 PAD~D @
NCTF BP1 T87 PAD~D @
@ PAD~D T63 BR35 NCTF BR2 T88 PAD~D @
@ PAD~D T64 BR31 RSVD NCTF C1 T89 PAD~D @
@ PAD~D T65 BH30 RSVD NCTF C38 T90 PAD~D @
RSVD NCTF

11 OF 14
SKL-H_BGA1440
REV = 1 ?
@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
PROCESSOR(4/7) RSVD,CFG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS C 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 9 of 71
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE +VCC_CORE

?
SKYLAKE_HALO
UH1J
D D
? BGA1440
BJ17
UH1G SKYLAKE_HALO BJ19 VCCOPC
BJ20 VCCOPC
BGA1440 BK17 VCCOPC
AA13 V32 BK19 VCCOPC
AA31 VCC VCC V33 BK20 VCCOPC
AA32 VCC VCC V34 BL16 VCCOPC
AA33 VCC VCC V35 BL17 VCCOPC
AA34 VCC VCC V36 BL18 VCCOPC
AA35 VCC VCC V37 BL19 VCCOPC
AA36 VCC VCC V38 BL20 VCCOPC
AA37 VCC VCC W13 BL21 VCCOPC
AA38 VCC VCC W14 BM17 VCCOPC
AB29 VCC VCC W29 BN17 VCCOPC
AB30 VCC VCC W30 VCCOPC
AB31 VCC VCC W31 BJ23
AB32 VCC VCC W32 BJ26 RSVD
AB35 VCC VCC W35 BJ27 RSVD
AB36 VCC VCC W36 BK23 RSVD
AB37 VCC VCC W37 BK26 RSVD
AB38 VCC VCC W38 BK27 RSVD
AC13 VCC VCC Y29 BL23 RSVD
AC14 VCC VCC Y30 BL24 RSVD
AC29 VCC VCC Y31 BL25 RSVD
AC30 VCC VCC Y32 BL26 RSVD
AC31 VCC VCC Y33 BL27 RSVD
AC32 VCC VCC Y34 BL28 RSVD
AC33 VCC VCC Y35 BM24 RSVD
AC34 VCC VCC Y36 RSVD
AC35 VCC VCC L14
AC36 VCC VCC P29 BL15
AD13 VCC VCC P30 BM16 VCCOPC_SENSE
AD14 VCC VCC P31 VSSOPC_SENSE
C
AD31 VCC VCC P32 BL22 C
AD32 VCC VCC P33 BM22 RSVD
AD33 VCC VCC P34 RSVD
AD34 VCC VCC P35
AD35 VCC VCC P36 BP15
AD36 VCC VCC R13 BR15 VCCEOPIO
AD37 VCC VCC R31 BT15 VCCEOPIO
AD38 VCC VCC R32 VCCEOPIO
AE13 VCC VCC R33 BP16
AE14 VCC VCC R34 BR16 RSVD
AE30 VCC VCC R35 BT16 RSVD
AE31 VCC VCC R36 RSVD
AE32 VCC VCC R37
AE35 VCC VCC R38 BN15
AE36 VCC VCC T29 BM15 VCCEOPIO_SENSE
AE37 VCC VCC T30 VSSEOPIO_SENSE
AE38 VCC VCC T31 BP17
AF35 VCC VCC T32 BN16 RSVD
AF36 VCC VCC T35 RSVD
AF37 VCC VCC T36
AF38 VCC VCC T37 BM14
K13 VCC VCC T38 BL14 VCC_OPC_1P8
K14 VCC VCC U29 VCC_OPC_1P8
L13 VCC VCC U30 BJ35
N13 VCC VCC U31 BJ36 RSVD
N14 VCC VCC U32 RSVD
N30 VCC VCC U33
N31 VCC VCC U34 +VCC_CORE AT13
N32 VCC VCC U35 AW13 ZVM#
N35 VCC VCC U36 MSM#
N36 VCC VCC V13 AU13
VCC VCC ZVM2#
1

N37 V14 AY13

N38 VCC VCC V31 RH197 MSM2#
P13 VCC VCC P14 RH166 1 @ 2 49.9_0402_1% BT29
VCC VCC 100_0402_1% OPC_RCOMP
B RH57 1 @ 2 49.9_0402_1% BR25 B
RH58 1 @ 2 49.9_0402_1% BP25 OPCE_RCOMP
OPCE_RCOMP2
2

AG37 RH198 1 @ 2 0_0402_5% VCC_SENSE [64]

VCC_SENSE AG38 RH465 1 @ 2 0_0402_5%
VSS_SENSE VSS_SENSE [64] 10 OF 14
SKL-H_BGA1440
X06.26 REV = 1 ?
1

RH466 @
7 OF 14
SKL-H_BGA1440 100_0402_1%
REV = 1 ?
2

A A

Security Classification Compal Secret Data

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
PROCESSOR(5/7) PWR,BYPASS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS Size Document Number
ION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS Custom 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
O UT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 10 of 71
5 4 3 2 1
 5 4 3 2 1

+VCCSA
+VCCIO +VCCSTG +VCCST

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
D D

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CH102

CH103

CH104

CH105

CH106

CH107

CH108

CH109

CH110

CH111

CH112

CH113

CH114

CH115

CH116

CH117
+VCCSA +1.2V_DDR
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

?
SKYLAKE_HALO
UH1I
BGA1440
J30 AA6
K29 VCCSA VDDQ AE12
K30 VCCSA VDDQ AF5
K31 VCCSA VDDQ AF6 +1.2V_DDR +VCCSA +VCCSA
K32 VCCSA VDDQ AG5
K33 VCCSA VDDQ AG9
K34 VCCSA VDDQ AJ12
K35 VCCSA VDDQ AL11
L31 VCCSA VDDQ AP6

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

330U_B2_2.5VM_R9M
L32 VCCSA VDDQ AP7

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

47U_0603_6.3V6M
VCCSA VDDQ 1 1 1 1 1 1 1 1
L35 AR12

CH133

CH134

CH135
VCCSA VDDQ 1
L36 AR6 +

CH129

CH130

CH131

CH132

CH136

CH138
L37 VCCSA VDDQ AT12 +1.2V_DDR
L38 VCCSA VDDQ AW6 2 2 2 2 2 2 2
M29 VCCSA VDDQ AY6 2 2
VCCSA VDDQ X06.26

1
M30 J5
M31 VCCSA VDDQ J6 RH473
M32 VCCSA VDDQ K12 @
VCCSA VDDQ 0_0402_5%
M33 K6
M34 VCCSA VDDQ L12 X06.08
VCCSA VDDQ

2
M35 L6
C +VCCIO M36 VCCSA VDDQ R6 C
VCCSA VDDQ T6 +1.2V_VCCPLL_OC +1.2V_DDR
VDDQ W6
AG12 VDDQ RH530 1 @ 2 0_0402_5%
G15 VCCIO Y12
G17 VCCIO VDDQC
G19 VCCIO BH13 +1.2V_DDR
G21 VCCIO VCCPLL_OC G11
H15 VCCIO VCCPLL_OC +VCCST
H16 VCCIO
H17 VCCIO H30
H19 VCCIO VCCST +VCCSTG

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
H20 VCCIO H29

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
H21 VCCIO VCCSTG
VCCIO 1 1 1 1 1 1 1 1 1 1 1
H26 G30

CH118

CH121

CH124

CH120

CH119

CH122

CH123

CH125

CH126

CH127

CH128
H27 VCCIO VCCSTG +VCCST
J15 VCCIO H28
J16 VCCIO VCCPLL J28 2 2 2 2 2 2 2 2 2 2 2
J17 VCCIO VCCPLL
J19 VCCIO RH201 1 2 100_0402_1%
VCCIO +VCCSA
J20 M38 RH202 1 @ 2 0_0402_5% VCCSA_SENSE [64]
J21 VCCIO VCCSA_SENSE M37 RH470 1 @ 2 0_0402_5%
VCCIO VSSSA_SENSE VSSSA_SENSE [64]
J26 RH469 1 2 100_0402_1%
J27 VCCIO H14
VCCIO VCCIO_SENSE J14 X06.26
VSSIO_SENSE

VCCIO_SENSE [61]
VSSIO_SENSE [61]

B B
9 OF 14
SKL-H_BGA1440
REV = 1 ?
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
PROCESSOR(6/7) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS Custom 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
O UT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 11 of 71
5 4 3 2 1
 5 4 3 2 1

+VCCGT
+VCCGT +VCCGT
?
? SKYLAKE_HALO
UH1HSKYLAKE_HALO UH1N
BGA1440
D BG34 BGA1440 D
VCCGT AV29 AJ29
BG35 VCCGT VCCGT
VCCGT AV30 AJ30
BG36 VCCGT VCCGT AF29
VCCGT AV31 AJ31 VCCGTX
BH33 VCCGT VCCGT AF30
VCCGT AV32 AJ32 VCCGTX
BH34 VCCGT VCCGT AF31
VCCGT AV33 AJ33 VCCGTX
BH35 VCCGT VCCGT AF32
VCCGT AV34 AJ34 VCCGTX
BH36 VCCGT VCCGT AF33
VCCGT AV35 AJ35 VCCGTX
BH37 VCCGT VCCGT AF34
VCCGT AV36 AJ36 VCCGTX
BH38 VCCGT VCCGT AG13
VCCGT AW14 AK31 VCCGTX
BJ37 VCCGT VCCGT AG14
VCCGT AW31 AK32 VCCGTX
BJ38 VCCGT VCCGT AG31
VCCGT AW32 AK33 VCCGTX
BL36 VCCGT VCCGT AG32
VCCGT AW33 AK34 VCCGTX
BL37 VCCGT VCCGT AG33
VCCGT AW34 AK35 VCCGTX
BM36 VCCGT VCCGT AG34
VCCGT AW35 AK36 VCCGTX
BM37 VCCGT VCCGT AG35
VCCGT AW36 AK37 VCCGTX
BN36 VCCGT VCCGT AG36
VCCGT AW37 AK38 VCCGTX
BN37 VCCGT VCCGT AH13
VCCGT AW38 AL13 VCCGTX
BN38 VCCGT VCCGT AH14
VCCGT AY29 AL29 VCCGTX
BP37 VCCGT VCCGT AH29
VCCGT AY30 AL30 VCCGTX
BP38 VCCGT VCCGT AH30
VCCGT AY31 AL31 VCCGTX
BR37 VCCGT VCCGT AH31
VCCGT AY32 AL32 VCCGTX
BT37 VCCGT VCCGT AH32
VCCGT AY35 AL35 VCCGTX
BE38 VCCGT VCCGT AJ13
VCCGT AY36 AL36 VCCGTX
BF13 VCCGT VCCGT AJ14
VCCGT AY37 AL37 VCCGTX
BF14 VCCGT VCCGT
VCCGT AY38 AL38
BF29 VCCGT VCCGT
VCCGT BA13 AM13
BF30 VCCGT VCCGT
VCCGT BA14 AM14
BF31 VCCGT VCCGT
VCCGT BA29 AM29
BF32 VCCGT VCCGT
VCCGT BA30 AM30
BF35 VCCGT VCCGT
VCCGT BA31 AM31
BF36 VCCGT VCCGT
VCCGT BA32 AM32
BF37 VCCGT VCCGT
VCCGT BA33 AM33
C BF38 VCCGT VCCGT C
VCCGT BA34 AM34
BG29 VCCGT VCCGT
VCCGT BA35 AM35
BG30 VCCGT VCCGT
VCCGT BA36 AM36
BG31 VCCGT VCCGT
VCCGT BB13 AN13
BG32 VCCGT VCCGT
VCCGT BB14 AN14
BG33 VCCGT VCCGT
VCCGT BB31 AN31
BC36 VCCGT VCCGT
VCCGT BB32 AN32
BC37 VCCGT VCCGT
VCCGT BB33 AN33
BC38 VCCGT VCCGT
VCCGT BB34 AN34
BD13 VCCGT VCCGT
VCCGT BB35 AN35
BD14 VCCGT VCCGT
VCCGT BB36 AN36
BD29 VCCGT VCCGT
VCCGT BB37 AN37
BD30 VCCGT VCCGT
VCCGT BB38 AN38
BD31 VCCGT VCCGT
VCCGT BC29 AP13
BD32 VCCGT VCCGT
VCCGT BC30 AP14
BD33 VCCGT VCCGT +VCCGT
VCCGT BC31 AP29
BD34 VCCGT VCCGT
VCCGT BC32 AP30
BD35 VCCGT VCCGT
VCCGT BC35 AP31
BD36 VCCGT VCCGT
VCCGT BE33 AP32
BE31 VCCGT VCCGT
VCCGT BE34 AP35
BE32 VCCGT VCCGT
VCCGT BE35 AP36
BE37 VCCGT VCCGT
VCCGT BE36 AP37

1
VCCGT AP38 VCCGT
VCCGT RH203
AR29
8 OF 14 AR30 VCCGT 100_0402_1%
SKL-H_BGA1440 AR31 VCCGT
? AR32 VCCGT

2
REV = 1 AR33 VCCGT AH38 RH204 1 @ 2 0_0402_5%
VCCGT VCCGT_SENSE VCCGT_SENSE [64]
@ AR34 AH35
AR35 VCCGT VSSGTX_SENSE AH37 RH471 1 @ 2 0_0402_5%
VCCGT VSSGT_SENSE VSSGT_SENSE [64]
AR36 AH36
VCCGT VCCGTX_SENSE
B
AT14
AT31 VCCGT X06.26 B

AT32 VCCGT
AT33 VCCGT

1
AT34 VCCGT
VCCGT RH472
AT35
AT36 VCCGT 100_0402_1%
AT37 VCCGT
AT38 VCCGT

2
AU14 VCCGT
AU29 VCCGT
AU30 VCCGT
AU31 VCCGT
AU32 VCCGT
AU35 VCCGT
AU36 VCCGT
AU37 VCCGT
VCCGT 14 OF 14
AU38
VCCGT

SKL-H_BGA1440
?
REV = 1
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
PROCESSOR(2/7) PM,XDP,CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS Custom 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
O UT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 12 of 71
5 4 3 2 1
 5 4 3 2 1

? ?
SKYLAKE_HALO
UH1FSKYLAKE_HALO UH1L
BGA1440 UH1MSKYLAKE_HALO
BGA1440
Y38 K1 BGA1440
VSS VSS C17 C25
Y37 J36 VSS VSS BB4 AK30
VSS VSS C13 C23 VSS VSS
Y14 J33 VSS VSS BB3 AK29
VSS VSS C9 C21 VSS VSS
Y13 J32 VSS VSS BB2 AK4
D VSS VSS BT32 C19 VSS VSS D
Y11 J25 VSS VSS BB1 AJ38
VSS VSS BT26 C15 VSS VSS
Y10 J22 VSS VSS BA38 AJ37
VSS VSS BT24 C11 VSS VSS
Y9 J18 VSS VSS BA37 AJ6
VSS VSS BT21 C8 VSS VSS
Y8 J10 VSS VSS BA12 AJ5
VSS VSS BT18 C5 VSS VSS
Y7 J7 VSS VSS BA11 AJ4
VSS VSS BT14 BM29 VSS VSS
W34 J4 VSS VSS BA10 AJ3
VSS VSS BT12 BM25 VSS VSS
W33 H35 VSS VSS BA9 AJ2
VSS VSS BT9 BM18 VSS VSS
W12 H32 VSS VSS BA8 AJ1
VSS VSS BT5 BM11 VSS VSS
W5 H25 VSS VSS BA7 AH34
VSS VSS BR36 BM8 VSS VSS
W4 H22 VSS VSS BA6 AH33
VSS VSS BR34 BM7 VSS ? VSS
W3 H18 VSS VSS B9 AH12
VSS VSS BR29 BM5 VSS VSS
W2 H12 VSS VSS AY34 AH6
VSS VSS BR26 BM3 VSS VSS
W1 H11 VSS VSS AY33 AG30
VSS VSS BR24 BL38 VSS VSS
V30 G28 VSS VSS AY14 AG29
VSS VSS BR21 BL35 VSS VSS
V29 G26 VSS VSS AY12 AG11
VSS VSS BR18 BL13 VSS VSS
V12 G24 VSS VSS AW30 AG10
VSS VSS BR14 BL6 VSS VSS
V6 G23 VSS VSS AW29 AG8
VSS VSS BR12 BK25 VSS VSS
U38 G22 VSS VSS AW12 AG7
VSS VSS BR7 BK22 VSS VSS
U37 G20 VSS VSS AW5 AG6
VSS VSS BP34 BK13 VSS VSS
U6 G18 VSS VSS AW4 AF14
VSS VSS BP33 BK6 VSS VSS
T34 G16 VSS VSS AW3 AF13
VSS VSS BP29 BJ30 VSS VSS
T33 G14 VSS VSS AW2 AF12
VSS VSS BP26 BJ29 VSS VSS
T14 G12 VSS VSS AW1 AF4
VSS VSS BP24 BJ15 VSS VSS
T13 G10 VSS VSS AV38 AF3
VSS VSS BP21 BJ12 VSS VSS
T12 G9 VSS VSS AV37 AF2
VSS VSS BP18 BH11 VSS VSS
T11 G8 VSS VSS AU34 AF1
VSS VSS BP14 BH10 VSS VSS
T10 G6 VSS VSS AU33 AE34
VSS VSS BP12 BH7 VSS VSS
T9 G5 VSS VSS AU12 AE33
VSS VSS BP7 BH6 VSS VSS
T8 G4 VSS VSS AU11 AE6
VSS VSS BN34 BH3 VSS VSS
T7 F36 VSS VSS AU10 AD30
VSS VSS BN31 BH2 VSS VSS
T5 F31 VSS VSS AU9 AD29
VSS VSS BN30 BG37 VSS VSS
T4 F29 VSS VSS AU8 AD12
C VSS VSS BN29 BG14 VSS VSS C
T3 F27 VSS VSS AU7 AD11
VSS VSS BN24 BG6 VSS VSS
T2 F25 VSS VSS AU6 AD10
VSS VSS BN21 BF34 VSS VSS
T1 F23 VSS VSS AT30 AD9
VSS VSS BN20 BF6 VSS VSS
R30 F21 VSS VSS AT29 AD8
VSS VSS BN19 BE30 VSS VSS
R29 F19 VSS VSS AT6 AD7
VSS VSS BN18 BE5 VSS VSS
R12 F17 VSS VSS AR38 AD6
VSS VSS BN14 BE4 VSS VSS
P38 F15 VSS VSS AR37 AC38
VSS VSS BN12 BE3 VSS VSS
P37 F13 VSS VSS AR14 AC37
VSS VSS BN9 BE2 VSS VSS
P12 F11 VSS VSS AR13 AC12
VSS VSS BN7 BE1 VSS VSS
P6 F9 VSS VSS AR5 AC6
VSS VSS BN4 BD38 VSS VSS
N34 F8 VSS VSS AR4 AC5
VSS VSS BN2 BD37 VSS VSS
N33 F5 VSS VSS AR3 AC4
VSS VSS BM38 BD12 VSS VSS
N12 F4 VSS VSS AR2 AC3
VSS VSS BM35 BD11 VSS VSS
N11 F3 VSS VSS AR1 AC2
VSS VSS BM28 BD10 VSS VSS
N10 F2 VSS VSS AP34 AC1
VSS VSS BM27 BD8 VSS VSS
N9 E38 VSS VSS AP33 AB34
VSS VSS BM26 BD7 VSS VSS
N8 E35 VSS VSS AP12 AB33
VSS VSS BM23 BD6 VSS VSS
N7 E34 VSS VSS AP11 AB6
VSS VSS BM21 BC33 VSS VSS
N6 E9 VSS VSS AP10 AA30
VSS VSS BM13 BC14 VSS VSS
N5 E4 VSS VSS AP9 AA29
VSS VSS BM12 BC13 VSS VSS
N4 D33 VSS VSS AP8 AA12
VSS VSS BM9 BC6 VSS VSS
N3 D30 VSS VSS AN30 A30
VSS VSS BM6 BB30 VSS VSS
N2 D28 VSS VSS AN29 A28
VSS VSS BM2 BB29 VSS VSS
N1 D26 VSS VSS AN12 A26
VSS VSS BL29 BB6 VSS VSS
M14 D24 VSS VSS AN6 A24
VSS VSS BK29 BB5 VSS VSS
M13 D22 VSS VSS AN5 A22
VSS VSS BK15 VSS VSS
M12 D20 VSS AM38 A20
VSS VSS BK14 VSS VSS
M6 D18 VSS AM37 A18
VSS VSS BJ32 VSS VSS
L34 D16 VSS AM12 A16
VSS VSS BJ31 VSS VSS
L33 D14 VSS AM5 A14
VSS VSS BJ25 VSS VSS
L30 D12 VSS AM4 A12
VSS VSS BJ22 VSS VSS
L29 D10 VSS AM3 A10
B VSS VSS BH14 VSS VSS B
K38 D9 VSS C2 AM2 A9
VSS VSS BH12 NCTFVSS VSS VSS
K11 D6 VSS BT36 AM1 A6
VSS VSS BH9 NCTFVSS VSS VSS
K10 D3 VSS BT35 AL34
VSS VSS BH8 NCTFVSS VSS
K9 C37 VSS BT4 AL33
VSS VSS BH5 NCTFVSS VSS
K8 C31 VSS BT3 AL14 B37
VSS VSS BH4 NCTFVSS VSS NCTFVSS
K7 C29 VSS BR38 AL12 B3
VSS VSS BH1 NCTFVSS VSS NCTFVSS
K5 C27 VSS AL10 A34
VSS VSS BG38 VSS NCTFVSS
K4 VSS AL9 A4
VSS BG13 VSS NCTFVSS
K3 D38 VSS AL8 A3
VSS NCTFVSS BG12 VSS NCTFVSS
K2 VSS AL7
VSS BF33 VSS
VSS AL4
BF12 VSS
6 OF 14 BE29 VSS
SKL-H_BGA1440 BE6 VSS
? BD9 VSS 13 OF 14
REV = 1 BC34 VSS SKL-H_BGA1440
@ BC12 VSS ?
BB12 VSS REV = 1
VSS @
12 OF 14
SKL-H_BGA1440
?
REV = 1
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
PROCESSOR(7/7) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS Size Document Number
ION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS Custom 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 13 of 71
5 4 3 2 1
 5 4 3 2 1

[8] DDR_A_D[0..63]
[8] DDR_A_MA[0..13] JDIMM1
+1.2V_DDR JP?
[8] DDR_A_DQS#[0..7] +1.2V_DDR
[8] DDR_A_DQS[0..7]
1 2
VSS1 VSS2
Layout Note: Layout Note: DDR_A_D5 3
DQ5 DQ4
4 DDR_A_D4
5 6
Place near JDIMM1.257,259 Place near JDIMM1.258 DDR_A_D1 7 VSS3 VSS4 8 DDR_A_D0
9 DQ1 DQ0 10
DDR_A_DQS#0 11 VSS5 VSS6 12
DDR_A_DQS0 13 DQS0_c DM0_n/DBI0_n 14
15 DQS0_t VSS7 16 DDR_A_D6
DDR_A_D7 17 VSS8 DQ6 18
+2.5V_MEM +0.6VS 19 DQ7 VSS9 20 DDR_A_D2
VSS10 DQ2
Layout Note: DDR_A_D3 21
DQ3 VSS11
22
23 24 DDR_A_D12
Place near JDIMM1.255 DDR_A_D13 25 VSS12 DQ12 26
D 27 DQ13 VSS13 28 DDR_A_D8 D

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
DDR_A_D9 29 VSS14 DQ8 30
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K
1U_0402_6.3V6K 31 DQ9 VSS15 32 DDR_A_DQS#1

1U_0402_6.3V6K
1 1 1 1 VSS16 DQS1_c
33 34 DDR_A_DQS1

CD12

CD13

CD14

CD15
1 1 1 1 DM1_n/DBI_n DQS1_t
35 36
CD3

CD4
DDR_A_D15 37 VSS17 VSS18 38 DDR_A_D14
CD9

CD10

2 2 2 2 +3VS 39 DQ15 DQ14 40

2 2 2 2 DDR_A_D10 41 VSS19 VSS20 42 DDR_A_D11
43 DQ10 DQ11 44
DDR_A_D21 45 VSS21 VSS22 46 DDR_A_D20
47 DQ21 DQ20 48
DDR_A_D17 49 VSS23 VSS24 50 DDR_A_D16

.1U_0402_16V7K
51 DQ17 DQ16 52
1 1 VSS25 VSS26
DDR_A_DQS#2 53 54

CD16
CD17 DDR_A_DQS2 55 DQS2_c DM2_n/DBI2_n 56
2.2U_0402_6.3V6M 57 DQS2_t VSS27 58 DDR_A_D22
2 2 DDR_A_D23 59 VSS28 DQ22 60
61 DQ23 VSS29 62 DDR_A_D18
DDR_A_D19 63 VSS30 DQ18 64
65 DQ19 VSS31 66 DDR_A_D28
VSS32 DQ28
Layout Note: DDR_A_D29 67
DQ29 VSS33
68
69 70 DDR_A_D24
Place near JDIMM1 DDR_A_D25 71 VSS34 DQ24 72
DQ25 VSS35

73 74 DDR_A_DQS#3
75 VSS36 DQS3_c 76 DDR_A_DQS3
+1.2V_DDR 77 DM3_n/DBI3_n DQS3_t 78
DDR_A_D30 79 VSS37 VSS38 80 DDR_A_D31
81 DQ30 DQ31 82
DDR_A_D26 83 VSS39 VSS40 84 DDR_A_D27
85 DQ26 DQ27 86
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

87 VSS41 VSS42 88
1 1 1 1 1 1 1 1 CB5/NC CB4/NC
89 90
CD1

CD2

CD75

CD74

CD77

CD76

CD79

CD78

91 VSS43 VSS44 92
93 CB1/NC CB0/NC 94
2 2 2 2 2 2 2 2 95 VSS45 VSS46 96
97 DQS8_c DM8_n/DBI_n/NC 98
99 DQS8_t VSS47 100
101 VSS48 CB6/NC 102
C 103 CB2/NC VSS49 104 C
105 VSS50 CB7/NC 106
107 CB3/NC VSS51 108 DDR4_DRAMRST#
DDR_CKE0_DIMMA 109 VSS52 RESET_n 110 DDR_CKE1_DIMMA
[8] DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA [8]
111 112
+1.2V_DDR DDR_A_BG1 113 VDD1 VDD2 114
[8] DDR_A_BG1 BG1 ACT_n DDR_A_ACT# [8]
DDR_A_BG0 115 116 DDR_A_ALERT#
[8] DDR_A_BG0 BG0 ALERT_n DDR_A_ALERT# [8]
117 118
DDR_A_MA12 119 VDD3 VDD4 120 DDR_A_MA11
DDR_A_MA9 121 A12 A11 122 DDR_A_MA7
123 A9 A7 124
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

DDR_A_MA8 125 VDD5 VDD6 126 DDR_A_MA5

1 A8 A5
1 1 1 1 1 1 1 1 DDR_A_MA6 127 128 DDR_A_MA4
+ CD11 129 A6 A4 130
220U_D7_2VM_R6M DDR_A_MA3 131 VDD7 VDD8 132 DDR_A_MA2
CD5

CD6

CD7

CD8

CD70

CD71

CD72

CD73

DDR_A_MA1 133 A3 A2 134 All VREF traces should

2 2 2 2 2 2 2 2 2 135 A1 EVENT_n/NF 136
VDD9 VDD10
have 10 mil trace width
[8] M_CLK_DDR0 M_CLK_DDR0 137 138 M_CLK_DDR1 M_CLK_DDR1 [8]
M_CLK_DDR#0 139 CK0_t CK1_t/NF 140 M_CLK_DDR#1
[8] M_CLK_DDR#0 CK0_c CK1_c/NF M_CLK_DDR#1 [8]
141 142
DDR_A_PAR 143 VDD11 VDD12 144 DDR_A_MA0
[8] DDR_A_PAR PARITY A0
DDR_A_BS1 145 146 DDR_A_MA10
[8] DDR_A_BS1 BA1 A10/AP
147 148
DDR_CS0_DIMMA# 149 VDD13 VDD14 150 DDR_A_BS0
[8] DDR_CS0_DIMMA# CS0_n BA0 DDR_A_BS0 [8]
DDR_A_W E# 151 152 DDR_A_RAS#
[8] DDR_A_W E# W E_n/A14 RAS_n/A16 DDR_A_RAS# [8]
153 154
M_ODT0 155 VDD15 VDD16 156 DDR_A_CAS#
[8] M_ODT0 ODT0 CAS_n/A15 DDR_A_CAS# [8]
[8] DDR_CS1_DIMMA# DDR_CS1_DIMMA# 157 158 DDR_A_MA13
159 CS1_n A13 160
M_ODT1 161 VDD17 VDD18 162
[8] M_ODT1 ODT1 C0/CS2_n/NC
163 164 +V_DDR_REFA
165 VDD19 VREFCA 166 DIMM_CHA_SA2
167 C1, CS3_n,NC SA2 168
DDR_A_D37 169 VSS53 VSS54 170 DDR_A_D36

.1U_0402_16V7K
171 DQ37 DQ36 172
VSS55 VSS56 1
DDR_A_D33 173 174 DDR_A_D32

CD18
175 DQ33 DQ32 176
+1.2V_DDR DDR_A_DQS#4 177 VSS57 VSS58 178
DDR_A_DQS4 179 DQS4_c DM4_n/DBI4_n 180 +1.2V_DDR 2
181 DQS4_t VSS59 182 DDR_A_D39
B +3VS +3VS +3VS DDR_A_D38 183 VSS60 DQ39 184 B
185 DQ38 VSS61 186 DDR_A_D35
DDR_A_D34 187 VSS62 DQ35 188
189 DQ34 VSS63 190 DDR_A_D45
VSS64 DQ45
1

DDR_A_D44 191 192

DQ44 VSS65
1

RD35 193 194 DDR_A_D41

RD1 RD2 RD3 470_0402_1% DDR_A_D40 195 VSS66 DQ41 196
@ @ @ 197 DQ40 VSS67 198 DDR_A_DQS#5
0_0402_5% 0_0402_5% 0_0402_5% VSS68 DQS5_c
199 200 DDR_A_DQS5
+1.2V_DDR DM5_n/DBI5_n DQS5_t
2

201 202
VSS69 VSS70
2

0_0402_5% DDR_A_D46 203 204 DDR_A_D47

DIMM_CHA_SA0 DIMM_CHA_SA1 DIMM_CHA_SA2 DDR4_DRAMRST# 1 2 205 DQ46 DQ47 206
[15] DDR4_DRAMRST# H_DRAMRST# [18] VSS71 VSS72
RD31 @ DDR_A_D42 207 208 DDR_A_D43
209 DQ42 DQ43 210
.1U_0402_16V7K

VSS73 VSS74
1

1 DDR_A_D52 211 212 DDR_A_D53

X06.12 213 DQ52 DQ53 214
CD69

RD28 RD29 RD30 @

@ @ @ DDR_A_D49 215 VSS75 VSS76 216 DDR_A_D48
0_0402_5% 0_0402_5% 0_0402_5% DQ49 DQ48
217 218
2 DDR_A_DQS#6 219 VSS77 VSS78 220
X06.16 DQS6_c DM6_n/DBI6_n +1.2V_DDR
2

DDR_A_DQS6 221 222

223 DQS6_t VSS79 224 DDR_A_D54
DDR_A_D55 225 VSS80 DQ54 226
227 DQ55 VSS81 228 DDR_A_D50
DDR_A_D51 229 VSS82 DQ50 230
231 DQ51 VSS83 232 DDR_A_D60
DDR_A_D61 233 VSS84 DQ60 234
235 DQ61 VSS85 236 DDR_A_D57
DDR_A_D56 237 VSS86 DQ57 238
+V_DDR_REFA_R +1.2V_DDR 239 DQ56 VSS87 240 DDR_A_DQS#7
241 VSS88 DQS7_c 242 DDR_A_DQS7
+1.2V_DDR 243 DM7_n/DBI7_n DQS7_t 244
VSS89 VSS90
1

DDR_A_D62 245 246 DDR_A_D63

RH206 247 DQ62 DQ63 248
249 VSS91 VSS92 250
20mil 1K_0402_1% DDR_A_D58
251 DQ58 DQ59 252
DDR_A_D59

PCH_SMBCLK 253 VSS93 VSS94 254 PCH_SMBDATA

[6,15,18,45] PCH_SMBCLK SCL SDA PCH_SMBDATA [6,15,18,45]
2

255 256 DIMM_CHA_SA0

+3VS VDDSPD SA0
RH484 1 2 2_0402_1% +V_DDR_REFA +2.5V_MEM
257 258 +0.6VS
259 VPP1 VTT 260 DIMM_CHA_SA1
261 VPP2 SA1 262
1 GND1 GND2
1

A A
CH101 RH209
0.022U_0402_25V7K 1K_0402_1%
2
1

BELLW _SD-80886-1021 CONN@

2

RH211
24.9_0402_1%
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
DDRIII DIMMA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS Size
ION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C. LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 14 of 71

5 4 3 2 1
 5 4 3 2 1

JDIMM2
+1.2V_DDR JP?
[8] DDR_B_D[0..63] +1.2V_DDR
[8] DDR_B_MA[0..13]
[8] DDR_B_DQS#[0..7]
1 2
DDR_B_D5 3 VSS1 VSS2 4 DDR_B_D4
[8] DDR_B_DQS[0..7] DQ5 DQ4
Layout Note: Layout Note: 5
VSS3 VSS4
6
DDR_B_D1 7 8 DDR_B_D0
Place near JDIMM1.258 Place near JDIMM2.257,259 9 DQ1 DQ0 10
DDR_B_DQS#0 11 VSS5 VSS6 12
DDR_B_DQS0 13 DQS0_c DM0_n/DBI0_n 14
15 DQS0_t VSS7 16 DDR_B_D6
DDR_B_D7 17 VSS8 DQ6 18
19 DQ7 VSS9 20 DDR_B_D2
DDR_B_D3 21 VSS10 DQ2 22
+0.6VS +2.5V_MEM 23 DQ3 VSS11 24 DDR_B_D12
DDR_B_D13 25 VSS12 DQ12 26
D 27 DQ13 VSS13 28 DDR_B_D8 D
DDR_B_D9 29 VSS14 DQ8 30
31 DQ9 VSS15 32 DDR_B_DQS#1
VSS16 DQS1_c
Layout Note: 33 34 DDR_B_DQS1
1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M
35 DM1_n/DBI_n DQS1_t 36
1 1 1 1 1 1 1 1 Place near JDIMM2.255 DDR_B_D15 37 VSS17 VSS18 38 DDR_B_D14
CD32

CD30

CD31
39 DQ15 DQ14 40
CD90

CD89

CD88

CD27

CD28
DDR_B_D10 41 VSS19 VSS20 42 DDR_B_D11
2 2 2 2 2 2 2 2 43 DQ10 DQ11 44
DDR_B_D21 45 VSS21 VSS22 46 DDR_B_D20
47 DQ21 DQ20 48
DDR_B_D17 49 VSS23 VSS24 50 DDR_B_D16
+2.5V_MEM 51 DQ17 DQ16 52
DDR_B_DQS#2 53 VSS25 VSS26 54
DDR_B_DQS2 55 DQS2_c DM2_n/DBI2_n 56
57 DQS2_t VSS27 58 DDR_B_D22
DDR_B_D23 59 VSS28 DQ22 60
61 DQ23 VSS29 62 DDR_B_D18

.1U_0402_16V7K
DDR_B_D19 63 VSS30 DQ18 64
1 1 DQ19 VSS31
65 66 DDR_B_D28

CD34
CD35 DDR_B_D29 67 VSS32 DQ28 68
2.2U_0402_6.3V6M 69 DQ29 VSS33 70 DDR_B_D24
2 2 DDR_B_D25 71 VSS34 DQ24 72
DQ25 VSS35
Layout Note:
73 74 DDR_B_DQS#3
Place near JDIMMB 75 VSS36 DQS3_c 76 DDR_B_DQS3
77 DM3_n/DBI3_n DQS3_t 78
DDR_B_D30 79 VSS37 VSS38 80 DDR_B_D31
81 DQ30 DQ31 82
DDR_B_D26 83 VSS39 VSS40 84 DDR_B_D27
85 DQ26 DQ27 86
87 VSS41 VSS42 88
89 CB5/NC CB4/NC 90
91 VSS43 VSS44 92
+1.2V_DDR 93 CB1/NC CB0/NC 94
95 VSS45 VSS46 96
97 DQS8_c DM8_n/DBI_n/NC 98
99 DQS8_t VSS47 100
101 VSS48 CB6/NC 102
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

C 103 CB2/NC VSS49 104 C

1 1 1 1 1 1 1 1 VSS50 CB7/NC
105 106
CD19

CD20

CD21

CD22

CD83

CD81

CD80

CD82

107 CB3/NC VSS51 108 DDR4_DRAMRST#

VSS52 RESET_n DDR4_DRAMRST# [14]
DDR_CKE2_DIMMB 109 110 DDR_CKE3_DIMMB
2 2 2 2 2 2 2 2 [8] DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB [8]
111 112
DDR_B_BG1 113 VDD1 VDD2 114
[8] DDR_B_BG1 BG1 ACT_n DDR_B_ACT# [8]
DDR_B_BG0 115 116 DDR_B_ALERT#
[8] DDR_B_BG0 BG0 ALERT_n DDR_B_ALERT# [8]
117 118
DDR_B_MA12 119 VDD3 VDD4 120 DDR_B_MA11
DDR_B_MA9 121 A12 A11 122 DDR_B_MA7
123 A9 A7 124
DDR_B_MA8 125 VDD5 VDD6 126 DDR_B_MA5
+1.2V_DDR DDR_B_MA6 127 A8 A5 128 DDR_B_MA4
129 A6 A4 130
DDR_B_MA3 131 VDD7 VDD8 132 DDR_B_MA2
DDR_B_MA1 133 A3 A2 134 All VREF traces should
135 A1 EVENT_n/NF 136
VDD9 VDD10
have 10 mil trace width
M_CLK_DDR2 137 138 M_CLK_DDR3
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

[8] M_CLK_DDR2 CK0_t CK1_t/NF M_CLK_DDR3 [8]

1 M_CLK_DDR#2 139 140 M_CLK_DDR#3
[8] M_CLK_DDR#2 CK0_c CK1_c/NF M_CLK_DDR#3 [8]
1 1 1 1 1 1 1 1 141 142
+ CD33 DDR_B_PAR 143 VDD11 VDD12 144 DDR_B_MA0
[8] DDR_B_PAR PARITY A0
220U_D7_2VM_R6M DDR_B_BS1 145 146 DDR_B_MA10
CD23

CD24

CD25

CD26

CD87

CD85

CD84

CD86

[8] DDR_B_BS1 BA1 A10/AP

147 148
2 2 2 2 2 2 2 2 2 DDR_CS2_DIMMB# 149 VDD13 VDD14 150 DDR_B_BS0
[8] DDR_CS2_DIMMB# CS0_n BA0 DDR_B_BS0 [8]
DDR_B_W E# 151 152 DDR_B_RAS#
[8] DDR_B_W E# W E_n/A14 RAS_n/A16 DDR_B_RAS# [8]
153 154
M_ODT2 155 VDD15 VDD16 156 DDR_B_CAS#
[8] M_ODT2 ODT0 CAS_n/A15 DDR_B_CAS# [8]
[8] DDR_CS3_DIMMB# DDR_CS3_DIMMB# 157 158 DDR_B_MA13
159 CS1_n A13 160
M_ODT3 161 VDD17 VDD18 162
[8] M_ODT3 ODT1 C0/CS2_n/NC
163 164 +V_DDR_REFB
165 VDD19 VREFCA 166 DIMM_CHB_SA2
167 C1, CS3_n,NC SA2 168
DDR_B_D37 169 VSS53 VSS54 170 DDR_B_D36

.1U_0402_16V7K
171 DQ37 DQ36 172
VSS55 VSS56 1
DDR_B_D33 173 174 DDR_B_D32

CD29
175 DQ33 DQ32 176
DDR_B_DQS#4 177 VSS57 VSS58 178
DDR_B_DQS4 179 DQS4_c DM4_n/DBI4_n 180 +1.2V_DDR 2
181 DQS4_t VSS59 182 DDR_B_D39
B DDR_B_D38 183 VSS60 DQ39 184 B
185 DQ38 VSS61 186 DDR_B_D35
DDR_B_D34 187 VSS62 DQ35 188
189 DQ34 VSS63 190 DDR_B_D45
DDR_B_D44 191 VSS64 DQ45 192
193 DQ44 VSS65 194 DDR_B_D41
DDR_B_D40 195 VSS66 DQ41 196
+3VS +3VS +3VS 197 DQ40 VSS67 198 DDR_B_DQS#5
199 VSS68 DQS5_c 200 DDR_B_DQS5
+1.2V_DDR 201 DM5_n/DBI5_n DQS5_t 202
DDR_B_D46 203 VSS69 VSS70 204 DDR_B_D47
205 DQ46 DQ47 206
X06.12 VSS71 VSS72
1

DDR_B_D42 207 208 DDR_B_D43

RD4 RD5 RD6 209 DQ42 DQ43 210
@ @ 0_0402_5% @ DDR_B_D52 211 VSS73 VSS74 212 DDR_B_D53
0_0402_5% 0_0402_5% DQ52 DQ53
213 214
DDR_B_D49 215 VSS75 VSS76 216 DDR_B_D48
DQ49 DQ48
2

217 218
DIMM_CHB_SA0 DIMM_CHB_SA1 DIMM_CHB_SA2 DDR_B_DQS#6 219 VSS77 VSS78 220
DDR_B_DQS6 221 DQS6_c DM6_n/DBI6_n 222 +1.2V_DDR
223 DQS6_t VSS79 224 DDR_B_D54
X06.12 X06.12 VSS80 DQ54
1

DDR_B_D55 225 226

RD38 RD39 RD40 227 DQ55 VSS81 228 DDR_B_D50
@ 0_0402_5% @ @ 0_0402_5% DDR_B_D51 229 VSS82 DQ50 230
0_0402_5% DQ51 VSS83
231 232 DDR_B_D60
DDR_B_D61 233 VSS84 DQ60 234
DQ61 VSS85
2

235 236 DDR_B_D57

DDR_B_D56 237 VSS86 DQ57 238
239 DQ56 VSS87 240 DDR_B_DQS#7
241 VSS88 DQS7_c 242 DDR_B_DQS7
+1.2V_DDR 243 DM7_n/DBI7_n DQS7_t 244
+V_DDR_REFB_R DDR_B_D62 245 VSS89 VSS90 246 DDR_B_D63
+1.2V_DDR 247 DQ62 DQ63 248
DDR_B_D58 249 VSS91 VSS92 250 DDR_B_D59
251 DQ58 DQ59 252
VSS93 VSS94
1

PCH_SMBCLK 253 254 PCH_SMBDATA

[6,14,18,45] PCH_SMBCLK SCL SDA PCH_SMBDATA [6,14,18,45]
RH207 255 256 DIMM_CHB_SA0
+3VS VDDSPD SA0
1K_0402_1% +2.5V_MEM
257 258 +0.6VS
259 VPP1 VTT 260
20mil 261 VPP2 SA1 262
DIMM_CHB_SA1
GND1 GND2
2

A A
RH485 1 2 2_0402_1% +V_DDR_REFB
1

1 BELLW _SD-80886-1021
RH210 CONN@
CH100 1K_0402_1%
0.022U_0402_25V7K
2
2
1

RH212
24.9_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
DDRIII DIMMB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS Size
ION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C. LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 15 of 71

5 4 3 2 1
 5 4 3 2 1

SKY-S-PCH_BGA837
UH2C

AV2
[43] CLINK_CLK CL_CLK G31
AV3 PCIE9_RXN/SATA0A_RXN SATA_PRX_SSDTX_N0A [44]
[43] CLINK_DATA CL_DATA CLINK H31
AW 2 PCIE9_RXP/SATA0A_RXP SATA_PRX_SSDTX_P0A [44]
[43] CLINK_RST# CL_RST# C31
PCIE9_TXN/SATA0A_TXN SATA_PTX_SSDRX_N0A [44]
B31
@ PAD~D T91 R44 PCIE9_TXP/SATA0A_TXP SATA_PTX_SSDRX_P0A [44]
GPP_G8/FAN_PW M_0
@ PAD~D T92 R43
U39 GPP_G9/FAN_PW M_1 G29
SSD
GPP_G10/FAN_PW M_2 PCIE10_RXN/SATA1A_RXN PCIE_PRX_SSDTX_N10 [44]
N42 E29 PCIE_PRX_SSDTX_P10 [44]
GPP_G11/FAN_PW M_3 PCIE10_RXP/SATA1A_RXP C32
FAN PCIE10_TXN/SATA1A_TXN PCIE_PTX_SSDRX_N10 [44]
B32 PCIE_PTX_SSDRX_P10 [44]
D [35] CAM_CBL_DET# CAM_CBL_DET# U43 PCIE10_TXP/SATA1A_TXP D
@ PAD~D T94 U42 GPP_G0/FAN_TACH_0
GPP_G1/FAN_TACH_1 F41
U41 PCIE15_RXN/SATA2_RXN PCIE_PRX_TBTX_N15 [37]
[37] TBT_CIO_PLUG_EVENT# GPP_G2/FAN_TACH_2 E41
M44 PCIE15_RXP/SATA2_RXP PCIE_PRX_TBTX_P15 [37]
[33] SSD_PWR_EN GPP_G3/FAN_TACH_3 B39
U36 PCIE15_TXN/SATA2_TXN PCIE_PTX_TBRX_N15 [37]
GPP_G4/FAN_TACH_4 A39 PCIE_PTX_TBRX_P15 [37]
P44 PCIE15_TXP/SATA2_TXP
T45 GPP_G5/FAN_TACH_5 Thunderbolt
GPP_G6/FAN_TACH_6 D43
T44 PCIE16_RXN/SATA3_RXN PCIE_PRX_TBTX_N16 [37]

PCIe/SATA
GPP_G7/FAN_TACH_7 E42 PCIE_PRX_TBTX_P16 [37]
PCIE16_RXP/SATA3_RXP A41
B33 PCIE16_TXN/SATA3_TXN PCIE_PTX_TBRX_N16 [37]
[44] PCIE_PTX_SSDRX_P11 PCIE11_TXP A40
C33 PCIE16_TXP/SATA3_TXP PCIE_PTX_TBRX_P16 [37]
SSD [44]
[44]
PCIE_PTX_SSDRX_N11
PCIE_PRX_SSDTX_P11
K31 PCIE11_TXN
PCIE11_RXP H42
[44] PCIE_PRX_SSDTX_N11 L31 PCIE17_RXN/SATA4_RXN
PCIE11_RXN H40
PCIE17_RXP/SATA4_RXP E45
AB33 PCIE17_TXN/SATA4_TXN
GPP_F10/SCLOCK F45 +3VS
AB35 PCIE17_TXP/SATA4_TXP
AA44 GPP_F11/SLOAD
GPP_F13/SDATAOUT0 K37
AA45 PCIE18_RXN/SATA5_RXN
GPP_F12/SDATAOUT1 G37 mCARD_PCIE#_SATA 1 2
B38 PCIE18_RXP/SATA5_RXP G45 RH508 10K_0402_5%
[45] SATA_PTX_DRX_N1B PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN
HDD [45] SATA_PTX_DRX_P1B C38
PCIE14_TXP/SATA1B_TXP PCIE18_TXP/SATA5_TXP
G44
D39 CAM_CBL_DET# 1 2
[45] SATA_PRX_DTX_N1B PCIE14_RXN/SATA1B_RXN
E37 AD44 PCH_SATA_LED# RH511 10K_0402_5%
[45] SATA_PRX_DTX_P1B PCIE14_RXP/SATA1B_RXP GPP_E8/SATALED#
AG36
C36 GPP_E0/SATAXPCIE0/SATAGP0 mCARD_PCIE#_SATA [44] PCH_SATA_LED# 1 2
PCIE13_TXN/SATA0B_TXN AG35 T182 PAD~D @
B36 GPP_E1/SATAXPCIE1/SATAGP1 RH512 10K_0402_5%
PCIE13_TXP/SATA0B_TXP AG39 HDD_DET# HDD_DET# [45]
G35 GPP_E2/SATAXPCIE2/SATAGP2
PCIE13_RXN/SATA0B_RXN AD35 T104 PAD~D @
E35 GPP_F0/SATAXPCIE3/SATAGP3 HDD_DET# 1 2
PCIE13_RXP/SATA0B_RXP AD31 T105 PAD~D @
GPP_F1/SATAXPCIE4/SATAGP4 RH513 10K_0402_5%
AD38 T106 PAD~D @
A35 GPP_F2/SATAXPCIE5/SATAGP5
[44] PCIE_PTX_SSDRX_P12 PCIE12_TXP AC43 T107 PAD~D @
SSD [44] PCIE_PTX_SSDRX_N12 B35
PCIE12_TXN
GPP_F3/SATAXPCIE6/SATAGP6 AB44 T108 PAD~D @
H33 GPP_F4/SATAXPCIE7/SATAGP7
[44] PCIE_PRX_SSDTX_P12 PCIE12_RXP
G33
[44] PCIE_PRX_SSDTX_N12 PCIE12_RXN W 36
GPP_F21/EDP_BKLTCTL BIA_PWM_PCH [7,35]
J45 W 35
PCIE20_TXP GPP_F20/EDP_BKLTEN PANEL_BKEN_PCH [35]
K44 W 42
PCIE20_TXN GPP_F19/EDP_VDDEN ENVDD_PCH [33,48]
N38
N39 PCIE20_RXP HOST AJ3 H_THERMTRIP# RH191 1 2 620_0402_5%
PCIE20_RXN THERMTRIP# H_THERMTRIP#_R [9,48]
H44 AL3 PCH_PECI RH539 1 2 13_0402_5% H_PECI [9,48]
C
H43 PCIE19_TXP PECI AJ4 RH189 1 2 30_0402_5% C
PCIE19_TXN PM_SYNC H_PM_SYNC_R [9]
L39 AK2
PCIE19_RXP PLTRST_CPU# PLTRST_CPU# [6,9]
L37 AH2 H_PM_DOWN [9]
PCIE19_RXN PM_DOW N

SKY-H-PCH_BGA837
REV = 1.3 3 OF 12
@

UH2E
SKY-S-PCH_BGA837
+3VS
BB3 DDI2_DDPC_CTRLCLK DDI2_DDPC_CTRLCLK [37]
[37] DDI1_PCH_HPD DDI1_PCH_HPD AW 4 GPP_I7/DDPC_CTRLCLK
GPP_I0/DDPB_HPD0 BD6 DDI2_DDPC_CTRLDAT
DDI2_PCH_HPD AY2 GPP_I8/DDPC_CTRLDATA DDI2_DDPC_CTRLDAT [37]
[37] DDI2_PCH_HPD GPP_I1/DDPC_HPD1 BA5 DDI1_DDPB_CTRLCLK
AV4 GPP_I5/DDPB_CTRLCLK DDI1_DDPB_CTRLCLK [37]
GPP_I2/DDPD_HPD2 BC4 DDI1_DDPB_CTRLDAT DDI1_DDPB_CTRLDAT [37]
BA4 GPP_I6/DDPB_CTRLDATA
GPP_I3/DDPE_HPD3 BE5
GPP_I9/DDPD_CTRLCLK LCD_DBC RH527 1 2 10K_0402_5%
BE6
GPP_I10/DDPD_CTRLDATA
Y44
GPP_F14 PROC_DETECT# [9]
V44 T2 PAD~D @ RH528 1 @ 2 10K_0402_5%
GPP_F23 W 39
BD7 GPP_F22
[35] EDP_HPD GPP_I4/EDP_HPD L43 T4 PAD~D @
GPP_G23 L44
GPP_G22 U35 LCD_DBC
GPP_G21 R35
GPP_G20 BD36 T8 PAD~D @
GPP_H23

B B
SKY-H-PCH_BGA837
REV = 1.3 5 OF 12
@
+3VS

DDI2_DDPC_CTRLCLK
DDI2_DDPC_CTRLDAT
DDI1_DDPB_CTRLCLK
DDI1_DDPB_CTRLDAT
RP1
1 8
2 7
3 6
4 5

2.2K_8P4R_5%

PCH Strap PIN

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
PCH (1/8) SATA,HDA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
SSD
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C. LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 16 of 71

5 4 3 2 1
 5 4 3 2 1

UH2G SKY-S-PCH_BGA837
RTC CRYSTAL
PCH_RTCX1
AR17
GPP_A16/CLKOUT_48
L1 RH70 1 2 10M_0402_5% PCH_RTCX2
+3VS G1 CLKOUT_ITPXDP PCH_XDP_CLK_N [6]
[9] CPU_24MHZ_P CLKOUT_CPUNSSC_P L2 YH1
F1 CLKOUT_ITPXDP_P PCH_XDP_CLK_P [6]
RP2 [9] CPU_24MHZ_N CLKOUT_CPUNSSC 32.768KHZ_X1A000141000300
J1
4 5 WLAN_CLK_REQ# CLKOUT_CPUPCIBCLK PCH_CPU_PCIBCLK_N [9]
[9] PCH_CPU_BCLK_P G2 J2 PCH_CPU_PCIBCLK_P [9]
3 6 CR_CLK_REQ# CLKOUT_CPUBCLK_P CLKOUT_CPUPCIBCLK_P 1 2
H2
2 7 TBT_CLK_REQ# [9] PCH_CPU_BCLK_N CLKOUT_CPUBCLK
1 8 SSD_CLK_REQ# N7
XTAL24_OUT A5 CLKOUT_PCIE_N0
XTAL24_OUT N8
10K_0804_8P4R_5%
+1V_PCH XTAL24_IN A6 CLKOUT_PCIE_P0 Max Crystal ESR
XTAL24_IN
D
L7 1
= 50k Ohm. 1
D
RH71 1 2 2.7K_0402_1% E1 CLKOUT_PCIE_N1
XCLK_BIASREF L5
CLKOUT_PCIE_P1 CH45 CH46
+3VS PCH_RTCX1 BC9
RTCX1 D3 8.2P_0402_50V8D 8.2P_0402_50V8D
PCH_RTCX2 BD10 CLKOUT_PCIE_N2 2 2
RTCX2 F2
CLKOUT_PCIE_P2
CLKREQ_PCIE#0 BC24
RH548 1 @ 2 10K_0402_5% CLKREQ_PCIE#0 GPP_B5/SRCCLKREQ0# E5
CLK_PCIE_WLAN# [43]
SRCCLKREQ1# AW 24 CLKOUT_PCIE_N3
RH549 1 @ 2 10K_0402_5% SRCCLKREQ1#
SRCCLKREQ2# AT24 GPP_B6/SRCCLKREQ1#
CLKOUT_PCIE_P3
G4 CLK_PCIE_WLAN [43] NGFF - WLAN
RH550 1 @ 2 10K_0402_5% SRCCLKREQ2#
BD25 GPP_B7/SRCCLKREQ2#
[43] WLAN_CLK_REQ# WLAN_CLK_REQ#
RH551 1 2 10K_0402_5% VGA_CLK_REQ# GPP_B8/SRCCLKREQ3# D5 CLK_PCIE_CR# [51]
CR_CLK_REQ# BB24 CLKOUT_PCIE_N4
[51]
[37]
CR_CLK_REQ#
TBT_CLK_REQ# TBT_CLK_REQ# BE25 GPP_B9/SRCCLKREQ4#
CLKOUT_PCIE_P4
E6
CLK_PCIE_CR [51] Card Reader
SSD_CLK_REQ# AT33 GPP_B10/SRCCLKREQ5#
[44] SSD_CLK_REQ# GPP_H0/SRCCLKREQ6# D8
VGA_CLK_REQ# AR31 CLKOUT_PCIE_N5 CLK_PCIE_TBT# [37]
[23] VGA_CLK_REQ#
SRCCLKREQ8# BD32 GPP_H1/SRCCLKREQ7#
CLKOUT_PCIE_P5
D7
CLK_PCIE_TBT [37] Thunderbolt
SRCCLKREQ9# BC32 GPP_H2/SRCCLKREQ8#
+3VS GPP_H3/SRCCLKREQ9# R8
SRCCLKREQ10# BB31 CLKOUT_PCIE_N6 CLK_PCIE_SSD# [44]
SRCCLKREQ11# BC33 GPP_H4/SRCCLKREQ10#
CLKOUT_PCIE_P6
R7
CLK_PCIE_SSD [44] NGFF - SSD
RP22@ GPP_H5/SRCCLKREQ11#
SRCCLKREQ12# BA33
4 5 SRCCLKREQ15# GPP_H6/SRCCLKREQ12# U5
SRCCLKREQ13# AW 33 CLKOUT_PCIE_N7 CLK_PEG_VGA# [23]
3 6 SRCCLKREQ9#
SRCCLKREQ14# BB33 GPP_H7/SRCCLKREQ13#
CLKOUT_PCIE_P7
U7 CLK_PEG_VGA [23] GPU - N16P-GX
2 7 SRCCLKREQ8# GPP_H8/SRCCLKREQ14#
SRCCLKREQ15# BD33
1 8 SRCCLKREQ10# GPP_H9/SRCCLKREQ15# W 10
CLKOUT_PCIE_N8 W 11
R13 CLKOUT_PCIE_P8
10K_0804_8P4R_5% CLKOUT_PCIE_N15 XTAL24_IN
+3VS R11
CLKOUT_PCIE_P15 N3
CLKOUT_PCIE_N9 N2
P1 CLKOUT_PCIE_P9
RP23@ CLKOUT_PCIE_N14 RH72 1 2 1M_0402_5% XTAL24_OUT
R2
4 5 SRCCLKREQ12# CLKOUT_PCIE_P14 P3
3 6 SRCCLKREQ13# CLKOUT_PCIE_N10 P2
W7 CLKOUT_PCIE_P10 YH2
2 7 SRCCLKREQ14# CLKOUT_PCIE_N13
Y5
1 8 SRCCLKREQ11# CLKOUT_PCIE_P13 R3 1 3
CLKOUT_PCIE_N11 R4 2 4
U2 CLKOUT_PCIE_P11
10K_0804_8P4R_5% CLKOUT_PCIE_N12
U3
CLKOUT_PCIE_P12
1 24MHZ_12PF_X3G024000DC1H 1
SKY-H-PCH_BGA837
REV = 1.3 7 OF 12 CH47 CH48
C @ 15P_0402_50V8J 18P_0402_50V8J C
2 2

SKY-S-PCH_BGA837
+3VS
UH2A

@ PAD~D T17 BD17 BB27 PCH_PLTRST#

GPP_A11/PME# GPP_B13/PLTRST# TOUCH_SCREEN_PD# RH510 1 2 10K_0402_5%
AG15
RSVD_AG15 P43
AG14 GPP_G16/GSXCLK TBT_FORCE_PWR [37] TOUCHPAD_INTR# RH547 1 2 10K_0402_5%
+3V_ROM RSVD_AG14 R39 RTD3_CIO_PWR_EN [37]
AF17 GPP_G12/GSXDOUT
RSVD_AF17 R36
AE17 GPP_G13/GSXSLOAD EC_SLP_S0IX# RH535 1 @ 2 10K_0402_5%
RSVD_AE17 R42
GPP_G14/GSXDIN R41
RH74 1 @ 2 3.3K_0402_5% PCH_SPI_CS# AR19 GPP_G15/GSXSRESET#
AN17 TP5 +3V_PCH
RH75 1 2 1K_0402_5% PCH_SPI_WP#_R TP4
AF41 SIO_EXT_SMI#
PCH_SPI_SI_R BB29 GPP_E3/CPU_GP0 SIO_EXT_SMI# [48]
SPI0_MOSI AE44 TOUCH_SCREEN_PD# TOUCH_SCREEN_PD# [35]
RH78 1 2 1K_0402_5% PCH_SPI_HOLD#_R PCH_SPI_SO_R BE30 GPP_E7/CPU_GP1 SIO_EXT_SMI# RH110 1 2 10K_0402_5%
SPI0_MISO BC23 TOUCHPAD_INTR#
PCH_SPI_CS# BD31 GPP_B3/CPU_GP2
SPI0_CS0# BD24 EC_SLP_S0IX#
PCH_SPI_CLK_R BC31 GPP_B4/CPU_GP3 EC_SLP_S0IX# [48] MEDIACARD_IRQ# RH546 1 2 10K_0402_5%
RH455 1 @ 2 1K_0402_5% PCH_SPI_HOLD#_R PAD~D T18 @ PCH_SPI_CS1# AW 31 SPI0_CLK
SPI0_CS1# BC36
PCH_SPI_WP#_R BC29 GPP_H18/SML4ALERT# BE34
PCH_SPI_HOLD#_RBD30 SPI0_IO2 GPP_H17/SML4DATA BD39
AT31 SPI0_IO3 GPP_H16/SML4CLK BB36
[42] PCH_SPI_CS2# SPI0_CS2# GPP_H15/SML3ALERT# BA35 +RTCVCC
AN36 GPP_H14/SML3DATA
GPP_D1/SPI1_CLK BC35
MEDIACARD_IRQ# AL39 GPP_H13/SML3CLK
[51] MEDIACARD_IRQ# GPP_D0/SPI1_CS# BD35
9/5 MOW AN41 GPP_H12/SML2ALERT#
[45] FFS_INT2 GPP_D3/SPI1_MOSI AW 35
AN38 GPP_H11/SML2DATA INTRUDER# RH531 1 2 330K_0402_5%
Option 1: Implement a 1 kOhm pull-down resistor on the signal and de-populate the [42] TPM_PIRQ# GPP_D2/SPI1_MISO BD34
AH43 GPP_H10/SML2CLK
B
required 1 kOhm pull-up resistor. In this case, customers must ensure that the SPI AG44 GPP_D22/SPI1_IO3 BE11 INTRUDER# B
GPP_D21/SPI1_IO2 INTRUDER#
flash device on the platform has HOLD functionality disabled by default.

Note that the pull down resistor on SPI0_IO3 is only needed for SKL U/Y platforms SKY-H-PCH_BGA837 1 OF 12 REV = 1.3
with ES and SKL S/H platforms with pre-ES1/ES1 samples. @

RP4
+3V_PCH
DH1
PCH_SPI_CLK 1 8 PCH_SPI_CLK_R
PCH_SPI_SI 2 7 PCH_SPI_SI_R TOUCHPAD_INTR# 2 1
PCH_SPI_SI_R [6] PTP_INT# [42,48]
PCH_SPI_SO 3 6 PCH_SPI_SO_R RH586 1 @ 2 0_0402_5%
PCH_SPI_WP# 4 5 PCH_SPI_WP#_R PCH_SPI_WP#_R [6] RB751S40T1G_SOD523-2
+3VS
33_0804_8P4R_5% X06.27
RH587 1 @ 2 0_0402_5%

PCH_SPI_HOLD# RH576 1 @ 2 0_0402_5% PCH_SPI_HOLD#_R

PCH_TPM_SO RH577 1 @ 2 0_0402_5% PCH_SPI_SO_R +3V_ROM +3V_PCH
[42] PCH_TPM_SO
PCH_TPM_SI RH578 1 @ 2 0_0402_5% PCH_SPI_SI_R
[42] PCH_TPM_SI

5
PCH_TPM_CLK RH579 1 @ 2 0_0402_5% PCH_SPI_CLK_R UH7
[42] PCH_TPM_CLK X06.27

VCC
1 PCH_PLTRST#
X06.27 1 @ 2
[23,37,42,43,44,48,51] PCH_PLTRST#_EC
4 IN1
RH585 0_0603_5% OUT 2

GND
IN2

1
MC74VHC1G08DFT2G_SC70-5

3
RH77

SPI ROM FOR ME ( 16MByte )

100K_0402_5%

2
A A
UH8
PCH_SPI_CS# 1 8
PCH_SPI_SO 2 /CS VCC 7 PCH_SPI_HOLD#
PCH_SPI_WP# 3 DO(IO1) /HOLD(IO3) 6 PCH_SPI_CLK
4 /W P(IO2) CLK 5 PCH_SPI_SI
GND DI(IO0)
W25Q128FVSIQ_SO8

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
PCH (2/8) SMBUS, CLK, SPI, LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C. LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 17 of 71

5 4 3 2 1
 5 4 3 2 1

+3V_PCH_DSW

RP15
1 8 HDA_BITCLK UH2D SKY-S-PCH_BGA837 PCH_PCIE_WAKE# RH453 1 2 1K_0402_5%
[52] HDA_BITCLK_AUDIO
2 7 HDA_SYNC
[52] HDA_SYNC_AUDIO
3 6 HDA_RST# PCH_BATLOW# RH515 1 2 8.2K_0402_5%
[52] HDA_RST#_AUDIO
[52] HDA_SDOUT_AUDIO 4 5 HDA_SDOUT HDA_BITCLK BA9 BB17
HDA_RST# BD8 HDA_BCLK GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF# AW 22 CLKRUN# AC_PRESENT RH533 1 2 8.2K_0402_5%
HDA_RST# GPP_A8/CLKRUN# CLKRUN# [48]
33_8P4R_5% [52] HDA_SDIN0_AUDIO RH96 1 @ 2 0_0402_5% HDA_SDIN0 BE7
D
BC8 HDA_SDI0 AR15 LAN_WAKE# RH545 1 2 10K_0402_5% D
X06.20 HDA_SDI1 GPD11/LANPHYPC
HDA_SDOUT BB7 AV13
HDA_SYNC BD9 HDA_SDO GPD9/SLP_W LAN# SIO_SLP_WLAN# [48] +3V_PCH
HDA_SYNC BC14
DRAM_RESET# H_DRAMRST# [14]
BD1 BD23
Close to PCH BE2 RSVD_BD1 GPP_B2/VRALERT# AL27
+RTCVCC RSVD_BE2 GPP_B1 AR27 ME_SUS_PWR_ACK RH506 1 @ 2 1M_0402_5%
1 2 AUD_AZA_CPU_SDO_R AM1 AUDIO GPP_B0 N44
[7] AUD_AZA_CPU_SDO DISPA_SDO GPP_G17/ADR_COMPLETE
RH83 1 2 20K_0402_5% PCH_SRTCRST# RH146 30_0402_5% AUD_AZA_CPU_SDI_R AN2 AN24 SYS_RESET# RH571 1 @ 2 8.2K_0402_5%
[7] AUD_AZA_CPU_SDI_R DISPA_SDI GPP_B11
1 2 AUD_AZA_CPU_SCLK_R AM2 AY1 RESET_OUT#
[7] AUD_AZA_CPU_SCLK DISPA_BCLK SYS_PW ROK RESET_OUT# [6,48]
RH147 30_0402_5%
1

BC13 PCH_PCIE_WAKE# +3VS

@ PAD~D AL42
T120 W AKE# PCH_PCIE_WAKE# [48]
CH52 GPP_D8/SSP0_SCLK BC15
@ PAD~D AN42
T121 GPD6/SLP_A# SIO_SLP_A# [48,52]
1U_0402_6.3V6K GPP_D7/SSP0_RXD AV15 T20 PAD~D @
@ PAD~D AM43
T122 SLP_LAN#
2

GPP_D6/SSP0_TXD BC26 CLKRUN# RH85 1 2 8.2K_0402_5%

@ PAD~D AJ33
T123 GPP_B12/SLP_S0# SIO_SLP_S0# [34,42,52]
GPP_D5/SSP0_SFRM AW 15
@ PAD~D AH44
T124 GPD4/SLP_S3# SIO_SLP_S3# [34,37,48,52]
GPP_D20/DMIC_DATA0 BD15 SIO_SLP_S4# [34,48,52]
AJ35 GPD5/SLP_S4#
GPP_D19/DMIC_CLK0 BA13
+RTCVCC DGPU_PWROK AJ38 GPD10/SLP_S5# SIO_SLP_S5# [34,48,52]
[63] DGPU_PW ROK GPP_D18/DMIC_DATA1
@ PAD~D T127 AJ42
GPP_D17/DMIC_CLK1 AN15
GPD8/SUSCLK BD13 SUSCLK [43,44]
RH84 1 2 20K_0402_5% PCH_RTCRST# PCH_BATLOW#
GPD0/BATLOW # BB19
GPP_A15/SUSACK# BD19 SUSACK# [48] +3V_PCH
PCH_RTCRST# BC10 ME_SUS_PWR_ACK
[52] PCH_RTCRST# RTCRST# GPP_A13/SUSW ARN#/SUSPW RDNACK ME_SUS_PWR_ACK [48]
1

PCH_SRTCRST# BB10
CH53 CLRP1 SRTCRST#
1U_0402_6.3V6K SHORT PADS X06.20 PCH_PWROK AW 11 BD11 LAN_WAKE# LAN_WAKE# [48] RH82 1 @ 2 4.7K_0402_5% SPKR
PCH_PW ROK GPD2/LAN_W AKE#
2

[6,48] PCH_RSMRST# RH133 1 @ 2 0_0402_5% PCH_RSMRST#_R BA11 BB15 AC_PRESENT AC_PRESENT [48]
RSMRST# GPD1/ACPRESENT BB13
SLP_SUS# SIO_SLP_SUS# [48]
AT13 SIO_PWRBTN# [6,48]
[48] PCH_DPWROK RH309 1 @ 2 0_0402_5% PCH_DPWROK_R AV11 GPD3/PW RBTN#
DSW _PW ROK AW 1 SYS_RESET#
SMBALERT# BB41 SYS_RESET# BD26 SPKR
SYS_RESET# [6,52] Top Swap Override (internal PD)
GPP_C2/SMBALERT# SPKR [52]

SMBUS
SMBCLK AW 44 GPP_B14/SPKR
GPP_C0/SMBCLK AM3 H_CPUPWRGD [9] HIGH ENABLE
SMBDATA BB43 PROCPW RGD
SML0ALERT# BA40 GPP_C1/SMBDATA
+3V_PCH GPP_C5/SML0ALERT# AT2 PCH_ITP_PMODE LOW(DEFAULT) DISABLE
SML0_SMBCLK AY44 ITP_PMODE PCH_ITP_PMODE [6]
GPP_C3/SML0CLK AR3 PCH_JTAGX
SML0_SMBDATA BB39 JTAGX PCH_JTAGX [6]
GPP_C4/SML0DATA JTAG AR2 PCH_JTAG_TMS
SML1ALERT# AT27 JTAG_TMS PCH_JTAG_TMS [6]
C GPP_B23/SML1ALERT#/PCHHOT# AP1 PCH_JTAG_TDO PCH_JTAG_TDO [6] C
SML1_SMBCLK AW 42 JTAG_TDO
RH458 1 2 1K_0402_5% SMBCLK [48] SML1_SMBCLK GPP_C6/SML1CLK AP2 PCH_JTAG_TDI
SML1_SMBDAT AW 45 JTAG_TDI PCH_JTAG_TDI [6]
RH459 1 2 1K_0402_5% SMBDATA [48] SML1_SMBDAT GPP_C7/SML1DATA AN3 PCH_JTAG_TCK
JTAG_TCK PCH_JTAG_TCK [6]
RH460 1 2 1K_0402_5% SML1_SMBCLK
RH461 1 2 1K_0402_5% SML1_SMBDAT +3V_PCH
RH501 1 2 499_0402_1% SML0_SMBCLK SKY-H-PCH_BGA837 REV = 1.3 4 OF 12
RH502 1 2 499_0402_1% SML0_SMBDATA @
RH505 1 TPM@ 2 4.7K_0402_5% SMBALERT#
+3VS

RH463 1 2 1K_0402_5% PCH_SMBCLK

TLS CONFIDENTIALITY
RH462 1 2 1K_0402_5% PCH_SMBDATA
RH516 1 2 10K_0402_5% DGPU_PWROK
HIGH vPRO
LOW(DEFAULT) non-vPRO
+3VS

RH91 1 2 100K_0402_5% RESET_OUT#

+3VS
PCH to DDR, XDP, FFS
+3V_PCH

5
UH14
RH88 1 2 47K_0402_5% PCH_RSMRST#_R QH4A

VCC
2

DMN65D8LDW-7_SOT363-6 1
[64] IMVP_VR_PG IN1 4 PCH_PWROK RH503 1 @ 2 4.7K_0402_5% SML0ALERT#
RH401 1 2 100K_0402_5% PCH_DPWROK_R SMBCLK 6 1 PCH_SMBCLK 2 OUT
PCH_SMBCLK [6,14,15,45]

GND
[48] RUNPW ROK IN2
5

EC interface

1
3
SMBDATA 3 4 PCH_SMBDATA PCH_SMBDATA [6,14,15,45] MC74VHC1G08DFT2G_SC70-5 RH529 HIGH ESPI
100K_0402_5%
LOW(DEFAULT) LPC
QH4B

2
DMN65D8LDW-7_SOT363-6
B B

+3V_PCH

RH504 1 2 150K_0402_5% SML1ALERT#

Service Mode Switch:

Add a switch to ME_FWP signal to unlock the ME region and PCHHOT#
allow the entire region of the SPI flash to be updated using FPT. HIGH Enable
+3V_PCH LOW(DEFAULT) Disable
1

RH536
1K_0402_5%

SW4
Reserve for EMI
2

1
HDA_SDOUT 1K_0402_5% 2 1 RH454 ME_EN 2 CH50 1 2 10P_0402_25V8J HDA_BITCLK
3 EMC@
0_0402_5% 2 @ 1 RH487
4 @ CH51 1 2 10P_0402_25V8J HDA_SDOUT
G
5
[48] ME_FWP_EC G
SSAL120100_3P Reserve for RF please close to UH1
X06.34 @
ME_FWP PCH has internal 20K PD.
FLASH DESCRIPTOR SECURITY OVERRIDE
Disable ME Protect (ME can be updated) ----> Pin1 & Pin2 short
A A
Enable ME Protect (ME cannot be updated)-->Pin3 & Pin2 short(Default position)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
PCH (3/8) DMI,FDI,PM,GFX,DP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C. LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 18 of 71

5 4 3 2 1
 5 4 3 2 1

SKY-S-PCH_BGA837
UH2B

[7] DMI_CTX_PRX_N0 L27

DMI_RXN0 AF5 USB20_N1 [46]
N27 USB2N_1
[7] DMI_CTX_PRX_P0 AG7
[7] DMI_CRX_PTX_N0
C27 DMI_RXP0
USB2P_1 AD5
USB20_P1 [46] USB Conn 1 (Right side)
B27 DMI_TXN0 USB20_N2 [46]
D [7] DMI_CRX_PTX_P0 USB2N_2 AD7 D
[7] DMI_CTX_PRX_N1
E24 DMI_TXP0
USB2P_2 AG8
USB20_P2 [46] USB Conn 2 (Left side)
G24 DMI_RXN1
[7] DMI_CTX_PRX_P1 USB2N_3 AG10
B28 DMI_RXP1
[7] DMI_CRX_PTX_N1 USB2P_3 AE1
A28 DMI_TXN1 USB20_N4 [43]
[7] DMI_CRX_PTX_P1 USB2N_4
[7] DMI_CTX_PRX_N2 G27 DMI_TXP1 DMI
USB2P_4
AE2
AC2
USB20_P4 [43] Mini Card(WLAN)
E26 DMI_RXN2
[7] DMI_CTX_PRX_P2 USB2N_5 AC3
B29 DMI_RXP2
[7] DMI_CRX_PTX_N2 USB2P_5 AF2
C29 DMI_TXN2
[7] DMI_CRX_PTX_P2 USB2N_6 AF3
L29 DMI_TXP2
[7] DMI_CTX_PRX_N3 USB2P_6 AB3
K29 DMI_RXN3
[7] DMI_CTX_PRX_P3 USB2N_7 AB2
B30 DMI_RXP3 USB 2.0
[7] DMI_CRX_PTX_N3 USB2P_7 AL8
A30 DMI_TXN3
[7] DMI_CRX_PTX_P3 USB2N_8 AL7
DMI_TXP3
USB2P_8 AA1
B18 USB2N_9 USB20_N9 [35]
1 2 C17 PCIE_RCOMPN
USB2P_9
AA2
AJ8
USB20_P9 [35] Touch Screen
RH108 100_0402_1% PCIE_RCOMPP
USB2N_10 AJ7
H15 USB2P_10 W2
[43] PCIE_PRX_WLANTX_N1 PCIE1_RXN/USB3_7_RXN USB2N_11
G15 W3
NGFF [43] PCIE_PRX_WLANTX_P1
A16 PCIE1_RXP/USB3_7_RXP USB2P_11 AD3
[43] PCIE_PTX_WLANRX_N1 PCIE1_TXN/USB3_7_TXN USB2N_12 USB20_N12 [35]
B16 AD2 Camera
[43] PCIE_PTX_WLANRX_P1 USB20_P12 [35]

PCIe/USB 3
B19 PCIE1_TXP/USB3_7_TXP USB2P_12 V2 +3V_PCH
[51] PCIE_PTX_CARDRX_N2 PCIE2_TXN/USB3_8_TXN USB2N_13
C19 V1
CARD_READER [51] PCIE_PTX_CARDRX_P2
E17 PCIE2_TXP/USB3_8_TXP USB2P_13 AJ11 USB_OC3# RH555 1 2 10K_0402_5%
[51] PCIE_PRX_CARDTX_N2 PCIE2_RXN/USB3_8_RXN USB2N_14
[51] PCIE_PRX_CARDTX_P2 G17 AJ13 USB_OC2# RH554 1 2 10K_0402_5%
L17 PCIE2_RXP/USB3_8_RXP USB2P_14 USB_OC1# RH553 1 2 10K_0402_5%
K17 PCIE3_RXN/USB3_9_RXN USB_OC0# RH552 1 2 10K_0402_5%
B20 PCIE3_RXP/USB3_9_RXP
C20 PCIE3_TXN/USB3_9_TXN
PCIE3_TXP/USB3_9_TXP AD43 USB_OC0#
E20 GPP_E9/USB2_OC0# USB_OC0# [46]
PCIE4_RXN/USB3_10_RXN AD42 USB_OC1# USB_OC1# [46]
G19 GPP_E10/USB2_OC1#
PCIE4_RXP/USB3_10_RXP AD39 USB_OC2#
B21 GPP_E11/USB2_OC2#
PCIE4_TXN/USB3_10_TXN AC44 USB_OC3# +3V_PCH
A21 GPP_E12/USB2_OC3#
PCIE4_TXP/USB3_10_TXP Y43 USB_OC4#
K19 GPP_F15/USB2_OCB_4 RP8
PCIE5_RXN Y41 USB_OC5#
L19 GPP_F16/USB2_OCB_5 USB_OC5# 4 5
PCIE5_RXP W 44 USB_OC6#
D22 GPP_F17/USB2_OCB_6 USB_OC4# 3 6
PCIE5_TXN W 43 USB_OC7#
C22 GPP_F18/USB2_OCB_7 USB_OC6# 2 7
G22 PCIE5_TXP USB_OC7# 1 8
C C
E22 PCIE6_RXN
PCIE6_RXP AG3 RH109 1 2 113_0402_1%
B22 USB2_COMP 10K_0804_8P4R_5%
PCIE6_TXN AD10 RH580 1 @ 2 0_0402_5%
A23 USB2_VBUSSENSE
PCIE6_TXP AB13
L22 RSVD_AB13
PCIE7_RXN AG2 RH581 1 @ 2 0_0402_5%
K22 USB2_ID
C23 PCIE7_RXP
B23 PCIE7_TXN X06.27
K24 PCIE7_TXP BD14
PCIE8_RXN GPD7/RSVD 3.3V_CAM_EN# [35]
L24
C24 PCIE8_RXP
B24 PCIE8_TXN
PCIE8_TXP

SKY-H-PCH_BGA837
REV = 1.3 2 OF 12
@

UH2F SKY-S-PCH_BGA837

[47] USB3TN1 C11 AT22 LPC_AD0 [48]

LPC/eSPI

B11 USB3_1_TXN GPP_A1/LAD0/ESPI_IO0 AV22

[47] USB3TP1 USB3_1_TXP GPP_A2/LAD1/ESPI_IO1 LPC_AD1 [48]
B USB Conn 1 (Right Side) [47] USB3RN1 B7
A7 USB3_1_RXN GPP_A3/LAD2/ESPI_IO2
AT19
BD16
LPC_AD2 [48] +3VS B
[47] USB3RP1 USB3_1_RXP GPP_A4/LAD3/ESPI_IO3 LPC_AD3 [48]
[47] USB3TN2 B12
USB3_2_TXN/SSIC_1_TXN IRQ_SERIRQ 1 2
A12 BE16
[47] USB3TP2 LPC_FRAME# [48]
USB Conn 2 (Left Side) [47] USB3RN2
C8 USB3_2_TXP/SSIC_1_TXP GPP_A5/LFRAME#/ESPI_CS# BA17 IRQ_SERIRQ
IRQ_SERIRQ [48] SIO_RCIN#
RH111
1
10K_0402_5%
2
B8 USB3_2_RXN/SSIC_1_RXN GPP_A6/SERIRQ AW 17
[47] USB3RP2 USB3_2_RXP/SSIC_1_RXP GPP_A7/PIRQA#/ESPI_ALERT0# AT17 FFS_INT1 [45] RH518 10K_0402_5%
SIO_RCIN# SIO_RCIN# [48]
B15 GPP_A0/RCIN#/ESPI_ALERT1# BC18
C15 USB3_6_TXN
GPP_A14/SUS_STAT#/ESPI_RESET#
K15 USB3_6_TXP
USB3_6_RXN
USB

K13 BC17 RH168 1 2 22_0402_5% CLK_PCI_MEC [48]

USB3_6_RXP GPP_A9/CLKOUT_LPC0/ESPI_CLK AV19 RH428 1 2 22_0402_5%
B14 GPP_A10/CLKOUT_LPC1 PCI_CLK_LPC1 [48]
C14 USB3_5_TXN
USB3_5_TXP M45
G13 GPP_G19/SMI#
USB3_5_RXN N43
H13 GPP_G18/NMI#
USB3_5_RXP
D13
USB3_3_TXP/SSIC_2_TXP AE45
C13 GPP_E6/DEVSLP2
USB3_3_TXN/SSIC_2_TXN AG43
A9 GPP_E5/DEVSLP1
USB3_3_RXP/SSIC_2_RXP AG42
B10 GPP_E4/DEVSLP0 mSATA_DEVSLP [44]
USB3_3_RXN/SSIC_2_RXN AB39
GPP_F9/DEVSLP7 AB36
B13 GPP_F8/DEVSLP6
SATA

USB3_4_TXP AB43
A14 GPP_F7/DEVSLP5
USB3_4_TXN AB42
G11 GPP_F6/DEVSLP4
USB3_4_RXP AB41
E11 GPP_F5/DEVSLP3
USB3_4_RXN

SKY-H-PCH_BGA837
REV = 1.3 6 OF 12 PCI_CLK_LPC1
@ CLK_PCI_MEC

1 1
@ CH198 CH199 @
15P_0402_50V8J 15P_0402_50V8J
2 2

A RF Reserved. A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
PCH (4/8) PCI, USB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C. LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 19 of 71

5 4 3 2 1
 5 4 3 2 1

UH2K SKY-S-PCH_BGA837

BBS_BIT0 AT29
GPP_B22/GSPI1_MOSI AL44
AR29 GPP_D9
[33] 3.3V_TS_EN GPP_B21/GSPI1_MISO AL36
+3VS SIO_EXT_SCI# AV29 GPP_D10 DGPU_HOLD_RST# [23]
[48] SIO_EXT_SCI# GPP_B20/GSPI1_CLK AL35
NGFF_PWREN BC27 GPP_D11
[33] NGFF_PWREN GPP_B19/GSPI1_CS# AJ39 DGPU_PWR_EN
GPP_D12 DGPU_PWR_EN [32]
NRB_BIT BD28
3.3V_mSATA_EN BD27 GPP_B18/GSPI0_MOSI AJ43
AW 27 GPP_B17/GSPI0_MISO GPP_D16/ISH_UART0_CTS# AL43 +3VS
[23] GC6_FB_EN GPP_B16/GSPI0_CLK GPP_D15/ISH_UART0_RTS#
[23] GPU_EVENT# AR24 AK44
GPP_B15/GSPI0_CS# GPP_D14/ISH_UART0_TXD AK45
RH424 1 @ 2 5.1K_0402_1% I2C0_SCK AV44 GPP_D13/ISH_UART0_RXD
D [48] UARTT0_TX GPP_C9/UART0_TXD D
RH425 1 @ 2 5.1K_0402_1% I2C0_SDA BID_DIS BA41 SPK_DET# RH572 1 2 100K_0402_5%
1 2 [48] BID_DIS AU44 GPP_C8/UART0_RXD
RH383 10K_0402_5% SIO_EXT_SCI# HOST_SD_WP#
[51] HOST_SD_WP# GPP_C11/UART0_CTS#
RH561 1 2 49.9K_0402_1% UART2_TXD AV43 AUD_PWR_EN RH569 1 2 100K_0402_5%
RH562 1 2 49.9K_0402_1% UART2_RXD GPP_C10/UART0_RTS#
BID_BC AU41 BC38 DGPU_PWR_EN RH537 1 @ 2 10K_0402_5%
RH563 1 2 10K_0402_5% HOST_SD_WP# AT44 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H20/ISH_I2C0_SCL BB38
AT43 GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_H19/ISH_I2C0_SDA RH538 1 2 10K_0402_5%
TBT_PWR_EN AU43 GPP_C13/UART1_TXD/ISH_UART1_TXD BD38
RH520 1 2 100K_0402_5% NGFF_PWREN GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H22/ISH_I2C1_SCL BE39 AUD_PWR_EN RH568 1 @ 2 100K_0402_5%
AN43 GPP_H21/ISH_I2C1_SDA
SIO_EXT_WAKE# AN44 GPP_C23/UART2_CTS# USB_PWR_EN RH544 1 2 10K_0402_5%
+3V_PCH [48] SIO_EXT_WAKE# AR39 GPP_C22/UART2_RTS#
[52] UART2_TXD UART2_TXD
UART2_RXD AR45 GPP_C21/UART2_TXD BC22
[52] UART2_RXD GPP_C20/UART2_RXD GPP_A23/ISH_GP5 BD18
RH119 1 2 4.7K_0402_5% I2C1_SCK_TP I2C1_SCK_TP AR41 GPP_A22/ISH_GP4 BE21 AUD_PWR_EN
[42] I2C1_SCK_TP GPP_C19/I2C1_SCL GPP_A21/ISH_GP3 AUD_PWR_EN [52,54]
RH120 1 2 4.7K_0402_5% I2C1_SDA_TP I2C1_SDA_TP AR44 BD22 KB_DET#
[42] I2C1_SDA_TP GPP_C18/I2C1_SDA GPP_A20/ISH_GP2 KB_DET# [52]
[48,52] I2C0_SCK_DSP RH521 1 @ 2 0_0402_5% I2C0_SCK AR38 BD21 SPK_DET#
GPP_C17/I2C0_SCL GPP_A19/ISH_GP1 SPK_DET# [48,52]
[48,52] I2C0_SDA_DSP RH522 1 @ 2 0_0402_5% I2C0_SDA AT42 BB22 CLKDET#
RH523 1 2 10K_0402_5% SIO_EXT_WAKE# GPP_C16/I2C0_SDA GPP_A18/ISH_GP0 BC19 USB_PWR_EN +3V_PCH
AM44 GPP_A17/ISH_GP7 USB_PWR_EN [46]
[35] EDP_PANEL_DAT_PCH GPP_D4/ISH_I2C2_SDA
[35] EDP_PANEL_CLK_PCH AJ44
GPP_D23/ISH_I2C2_SCL
RH556 1 2 10K_0402_5% TBT_PWR_EN
KB_DET# RH557 1 2 10K_0402_5%
SKY-H-PCH_BGA837
REV = 1.3 11 OF 12 CLKDET# RH558 1 @ 2 10K_0402_5%
@

+3V_PCH

3.3V_mSATA_EN RH423 1 @ 2 100K_0402_5% RH130 1 @ 2 4.7K_0402_5% BBS_BIT0

C Boot BIOS Strap Bit (internal PD) C

+3V_PCH +3V_PCH
HIGH LPC
LOW(DEFAULT) SPI
1

RH564 UMA@ RH566 BC@

100K_0402_5% 100K_0402_5%
2

+3V_PCH
BID_DIS BID_BC
RH524 1 @ 2 4.7K_0402_5% NRB_BIT
1

RH565 DIS@ RH567 CSMB@

100K_0402_5% 100K_0402_5% NO REBOOT mode (internal PD)
HIGH ENABLE
2

LOW(DEFAULT) DISABLE

SYSTEM ID 1 (UMA/DIS) SYSTEM ID 2 (BC/CSMB)

HIGH = UMA HIGH = BC
LOW = DIS LOW = CSMB

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
PCH (5/8) GPIO, CPU, MISC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C. LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 20 of 71

5 4 3 2 1
 5 4 3 2 1

+1VALW +1V_PCH
@
PJP1302
1 2

PAD-OPEN 43x39
+1V_MPHY
X06.27
RZ70 1 2 0_0805_5% +1VALW
@ @ UH2H SKY-S-PCH_BGA837
PJP1303
+1V_PCH
+3VALW +3V_PCH_DSW 1 2 +1V_PCH_PRIM AA23
AA26 VCCPRIM_1P0_AA23 +3V_PCH_DSW
PAD-OPEN 43x39 AA28 VCCPRIM_1P0_AA26 AL22
1 @ 2 AC23 VCCPRIM_1P0_AA28 VCCPRIM_1P0_AL22

CORE
RH137 0_0603_5% AC26 VCCPRIM_1P0_AC23 BA24
AC28 VCCPRIM_1P0_AC26 VCCDSW _3P3_BA24
D VCCPRIM_1P0_AC28 BA31 D

VCCGPIO
AE23 VCCPGPPA
+1V_PCH +1V_VCCDSW AE26 VCCPRIM_1P0_AE23 BC42
+1V_VCCDSW Y23 VCCPRIM_1P0_AE26 VCCPGPPBH_BC42 BD40
Y25 VCCPRIM_1P0_Y23 VCCPGPPBH_BD40 AJ41 +3V_PCH
1 @ 2 +1V_PCH BA29 VCCPRIM_1P0_Y25 VCCPGPPEF_AJ41 AL41
RH196 0_0402_5% DCPDSW _1P0 VCCPGPPEF_AL41 AD41
N17 VCCPGPPG AN5
R19 VCCCLK1 VCCPRIM_3P3_AN5
U20 VCCCLK3 +1V_PCH
+1V_MPHY +1V_MPHY_MPHYPLL V17 VCCCLK4 AD15
X06.27 +1V_PCH_CLK5 R17 VCCCLK2 VCCPRIM_1P0_AD15 AD13
+3VS
VCCCLK6 VCCATS BA20
K2 VCCRTCPRIM_3P3
1 @ 2 VCCCLK5_K2 BA22
K3 VCCRTC +RTCVCC
RH582 0_0603_5% VCCCLK5_K3 BA26
+1V_MPHY DCPRTC +DCPRTC
U21
+1V_PCH_USBPLL VCCMPHY_1P0_U21 AJ20 +1V_PCH_PRIM
+1VALW U23 VCCPRIM_1P0_AJ20

MPHY
+1V_MPHY_MPHYPLL VCCMPHY_1P0_U23 AJ21
U25 VCCPRIM_1P0_AJ21
VCCMPHY_1P0_U25 AJ23
U26 VCCPRIM_1P0_AJ23 +3V_PCH
V26 VCCMPHY_1P0_U26
VCCPRIM_1P0_AJ25
AJ25 X06.27
1 @ 2 +1V_MPHY A43 VCCMPHY_1P0_V26
RH583 0_0603_5% B43 VCCMPHYPLL_1P0_A43 BE41 +3V_PCH_SPI 2 @ 1
C44 VCCMPHYPLL_1P0_B43 VCCSPI_BE41 BE43 0_0603_5% RH136 +3V_PCH
X06.06 +1V_PCH C45 VCCPCIE3PLL_1P0_C44 VCCSPI_BE43 BE42
X06.05 V28
VCCPCIE3PLL_1P0_C45 VCCSPI_BE42
BC44
+1VALW +1V_PCH_AZPLL +1V_PCH_USBPLL VCCAPLLEBB_1P0 VCCPGPPCD_BC44
X06.06 +1V_PCH_AZPLL AC17 BA45

USB
AJ5 VCCPRIM_1P0_AC17 VCCPGPPCD_BA45 BC45
+3V_PCH_AZIO VCCUSB2PLL_1P0_AJ5 VCCPGPPCD_BC45
AL5 BB45
AN19 VCCUSB2PLL_1P0_AL5 VCCPGPPCD_BB45 +3V_PCH
1 2 +3V_PCH_DSW VCCHDAPLL_1P0 BD3
LH2 BLM15PX221SN1D_2P BA15 VCCPRIM_3P3_BD3
X06.05 W 15
VCCHDA
VCCPRIM_3P3_BE3
BE3
BE4
VCCDSW _3P3_W 15 VCCPRIM_3P3_BE4

SKY-H-PCH_BGA837
REV = 1.3 8 OF 12
+3V_PCH +3V_PCH_AZIO
@
C C

1 2
LH1 BLM15PX221SN1D_2P
X06.06 X06.06
+1V_PCH_AZPLL +1V_VCCDSW +3V_PCH_AZIO +DCPRTC +3VS

+1V_PCH
X06.27 +1V_PCH_CLK5 Close to AN19 Close to BA29 Close to BA15 Close to BA26 Close to AD13

0.1U_0402_10V7K

0.1U_0402_10V7K
0.1U_0402_10V7K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 @ 2

CH200
1 1 1 1 1
RH584 0_0603_5%

CH203

CH176

CH70

CH188
X06.06 2 2 2 2 2

+1V_PCH_CLK5 +1V_MPHY_MPHYPLL +1V_MPHY +1V_PCH_USBPLL

Close to K2,K3 Close to A43,B43 Close to U21,U23 Close to AJ5,AL5 X06.05

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1 1 1 1 1 1 1 1 1 1
+3V_PCH +3V_PCH_DSW +3V_PCH +3V_PCH +3V_PCH
CH179

CH180

CH183
CH177

CH178

CH181

CH182

CH184

CH201

CH202

2 2
@
2
@
2
@
2 2 2 2
@
2
@
2 Close to AD41 Close to W15 Close to AN5 Close to BC42,BD40 Close to AJ41,AL41

0.1U_0402_10V7K

1U_0402_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
1 1 1 1 1

CH82
@ @ @ @ @

CH190

CH189

CH192

CH191
2 2 2 2 2

B B

+RTCVCC +3V_PCH

Close to BA22 Close to BA20

1U_0402_6.3V6K

1U_0402_6.3V6K
0.1U_0402_10V7K

0.1U_0402_10V7K

1 1 1 1
CH80

CH187
CH173

CH186

2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
PCH (6/8) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C. LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 21 of 71

5 4 3 2 1
 5 4 3 2 1

UH2LSKY-S-PCH_BGA837
UH2I
SKY-S-PCH_BGA837
C42 AB11
AC18 AR5 VSS VSS
VSS VSS D10 AB7
AN4 AR7 VSS VSS
VSS VSS D12 AB14
AN10 U15 VSS VSS
VSS VSS D15 AB31
BE14 AL4 VSS VSS
VSS VSS D16 AB32
BE18 AE29 VSS VSS
VSS VSS D17 AB38
BE23 AE4 VSS VSS
D VSS VSS D19 AB4 D
BE28 AE42 VSS VSS
VSS VSS D21 AB5
BE32 AF18 VSS VSS
VSS VSS D24 AC1
BE37 AF20 VSS VSS
VSS VSS D25 AC20
BE40 AF21 VSS VSS
VSS VSS D27 AC21
BE9 AF23 VSS VSS
VSS VSS D29 AC25
C10 AF25 VSS VSS
VSS VSS D30 AC29
C2 AF26 VSS VSS
VSS VSS D31 AC45
C28 AF28 VSS VSS
VSS VSS D33 AB8
C37 AF29 VSS VSS
VSS VSS D35 AD11
J7 AG11 VSS VSS
VSS VSS D36 AD14
K10 AG13 VSS VSS
VSS VSS E13 AB15
K27 AG31 VSS VSS
VSS VSS E15 AD32
K33 AG32 VSS VSS
VSS VSS E31 AD33 SKY-S-PCH_BGA837
K36 AG33 VSS VSS UH2J
VSS VSS E33 AD36
K4 AG38 VSS VSS
VSS VSS F44 AD4
K42 AG4 VSS VSS
VSS VSS F8 AD8
K43 AH1 VSS VSS
VSS VSS G42 AE18
L12 AH17 VSS VSS BD2 AR22
VSS VSS G9 AE20 VSS_BD2 RSVD_AR22
L13 AH18 VSS VSS BD45 W13
VSS VSS H17 AE21 VSS_BD45 RSVD_W13
L15 AH20 VSS VSS BD44 U13
VSS VSS H19 AE25 VSS_BD44 RSVD_U13
L4 AH21 VSS VSS BE44
VSS VSS H22 AE28 VSS_BE44 P31
L41 AH23 VSS VSS D45 RSVD_P31
VSS VSS H24 AL10 VSS_D45 N31
L8 AH25 VSS VSS A42 RSVD_N31
VSS VSS H27 AL11 VSS_A42
M35 AH26 VSS VSS B45 P27
VSS VSS H29 AL13 VSS_B45 RSVD_P27
M42 AH28 VSS VSS B44 R27
VSS VSS H3 AL17 VSS_B44 RSVD_R27
N10 AH29 VSS VSS A4 N29
VSS VSS H35 AL19 VSS_A4 RSVD_N29
N15 AH45 VSS VSS A3 P29
VSS VSS J10 AL24 VSS_A3 RSVD_P29
N19 AJ10 VSS VSS B2 AN29
VSS VSS J11 AL29 VSS_B2 RSVD_AN29
N22 AJ14 VSS VSS A2 R24
VSS VSS J3 AL32 VSS_A2 RSVD_R24
N24 AJ15 VSS VSS B1 P24
VSS VSS J39 AL33 VSS_B1 RSVD_P24
N35 AJ17 VSS VSS BB1
VSS VSS J5 AL38 VSS_BB1 AT3
N36 AJ18 VSS VSS BC1 PREQ# XDP_PREQ# [6,9]
C VSS VSS T42 AM15 VSS_BC1 AT4 C
N4 AJ26 VSS VSS A44 PRDY# XDP_PRDY# [6,9]
VSS VSS U10 AM17 VSS_A44 AY5
N41 AJ28 VSS VSS CPU_TRST# CPU_XDP_TRST# [6,9]
VSS VSS U11 AM19 C1 AL2
N5 AJ29 VSS VSS RSVD_C1 PCH_TRIGOUT PCH_TRIGGER [9]
VSS VSS U14 AM22 D1 AK1
P17 AJ31 VSS VSS RSVD_D1 PCH_TRIGIN CPU_TRIGGER [9]
VSS VSS U17 AM24
P19 AJ32 VSS VSS
VSS VSS U18 AM27
P22 AJ36 VSS VSS
VSS VSS U28 AM29
P45 AK4 VSS VSS
VSS VSS U29 AM45
R10 AK42 VSS VSS
VSS VSS U31 AN11 SKY-H-PCH_BGA837
R14 AU7 VSS VSS REV = 1.3 10 OF 12
VSS VSS U32 AN22
R22 AV17 VSS VSS @
VSS VSS U33 AN27
R29 AV24 VSS VSS
VSS VSS U38 AN31
R33 AV27 VSS VSS
VSS VSS U4 AN39
R38 AV31 VSS VSS
VSS VSS U8 AN7
R5 AV33 VSS VSS
VSS VSS V18 AN8
T1 AV6 VSS VSS
VSS VSS V20 AP11
T2 AW13 VSS VSS
VSS VSS V21 AP4
T4 AW19 VSS VSS
VSS VSS V23 AR33
Y18 AW29 VSS VSS
VSS VSS V25 AR34
Y20 AW37 VSS VSS
VSS VSS V29 AR42
Y21 AW9 VSS VSS
VSS VSS V3 AR9
Y26 AY38 VSS VSS
VSS VSS V45 AT10
Y28 AY45 VSS VSS
VSS VSS W14 AT15
Y29 B25 VSS VSS
VSS VSS W31 AT36
A18 B3 VSS VSS
VSS VSS W32 AT9
A25 B37 VSS VSS
VSS VSS W33 AU1
A32 B40 VSS VSS
VSS VSS W38 AU35
A37 B6 VSS VSS
VSS VSS W4 AU36
AA17 BA1 VSS VSS
VSS VSS W8 AU39
AA18 BB11 VSS VSS
VSS VSS Y17 AU45
AA20 BB16 VSS VSS
VSS VSS C4
AA21 BB21 VSS
AA25 VSS VSS BB25
B AA29 VSS VSS BB30 B
AA4 VSS VSS BB34
AA42 VSS VSS BC2
AB10 VSS VSS BD43
VSS VSS SKY-H-PCH_BGA837
12 OF 12 REV = 1.3
SKY-H-PCH_BGA837 @
REV = 1.3 9 OF 12
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
PCH (8/8) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS Size
ION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C. LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 22 of 71

5 4 3 2 1
 5 4 3 2 1

UV1A

PEG_HTX_C_GRX_P0 AN12 Part 1 of 7 P6 GC6_FB_EN GC6_FB_EN [20]

PEG_HTX_C_GRX_N0 AM12 PEX_RX0 GPIO0 M3
PEG_HTX_C_GRX_P[0..15] PEG_HTX_C_GRX_P1 AN14 PEX_RX0_N GPIO1 L6
[7] PEG_HTX_C_GRX_P[0..15] AM14 PEX_RX1 GPIO2 P5
PEG_HTX_C_GRX_N1 +3.3V_GFX_AON
PEG_HTX_C_GRX_N[0..15] PEG_HTX_C_GRX_P2 AP14 PEX_RX1_N GPIO3 P7
[7] PEG_HTX_C_GRX_N[0..15] PEX_RX2 GPIO4
PEG_HTX_C_GRX_N2 AP15 L7 3V3_MAIN_EN 3V3_MAIN_EN [32,62,63]
PEG_GTX_C_HRX_P[0..15] PEG_HTX_C_GRX_P3 AN15 PEX_RX2_N GPIO5 M7 GC6_EVENT#_D GPU_HOT#_R RV543 1 DIS@ 2 100K_0402_5%
[7] PEG_GTX_C_HRX_P[0..15] PEX_RX3 GPIO6
PEG_HTX_C_GRX_N3 AM15 N8 GC6_EVENT#_D RV542 1 DIS@ 2 10K_0402_5%
PEG_GTX_C_HRX_N[0..15] PEG_HTX_C_GRX_P4 AN17 PEX_RX3_N GPIO7 M1 THERMATRIP_GPU#
[7] PEG_GTX_C_HRX_N[0..15] PEX_RX4 GPIO8
PEG_HTX_C_GRX_N4 AM17 M2 THERMAL_ALERT# FBVREF_ALTV RV544 1 DIS@ 2 100K_0402_5%
PEG_HTX_C_GRX_P5 AP17 PEX_RX4_N GPIO9 L1 FBVREF_ALTV
AP18 PEX_RX5 GPIO10 M5 FBVREF_ALTV [28,29,30,31]
PEG_HTX_C_GRX_N5 GPU_VID_0
PEX_RX5_N GPIO11 GPU_VID_0 [63]
PEG_HTX_C_GRX_P6 AN18 N3 GPU_HOT#_R
PEG_HTX_C_GRX_N6 AM18 PEX_RX6 GPIO12 M4 GPU_GPIO13 RV10 1 @ 2 0_0402_5% +3.3V_GFX_AON

GPIO
PEX_RX6_N GPIO13 GPU_PSI [63]
PEG_GTX_C_HRX_P0 CV531 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P0 PEG_HTX_C_GRX_P7 AN20 N4
D
PEG_GTX_C_HRX_N0 CV532 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N0 PEG_HTX_C_GRX_N7 AM20 PEX_RX7 GPIO14 P2 RPH32
D
PEG_HTX_C_GRX_P8 AP20 PEX_RX7_N GPIO15 R8 X06.30 CLK_REQ# 4 5
PEG_GTX_C_HRX_P1 CV533 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P1 PEG_HTX_C_GRX_N8 AP21 PEX_RX8 GPIO16 M6 GC6_FB_EN 3 6
PEG_GTX_C_HRX_N1 CV534 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N1 PEG_HTX_C_GRX_P9 AN21 PEX_RX8_N GPIO17 R1 XTALSSIN 2 7
PEG_HTX_C_GRX_N9 AM21 PEX_RX9 GPIO18 P3 XTALOUTBUFF 1 8
PEG_GTX_C_HRX_P2 CV535 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P2 PEG_HTX_C_GRX_P10 AN23 PEX_RX9_N GPIO19 P4
PEG_GTX_C_HRX_N2 CV536 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N2 PEG_HTX_C_GRX_N10 AM23 PEX_RX10 GPIO20 P1 GPU_PEX_RST_HOLD# 10K_0804_8P4R_5%
PEG_HTX_C_GRX_P11 AP23 PEX_RX10_N GPIO21
PEX_RX11 DIS@
PEG_GTX_C_HRX_P3 CV537 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P3 PEG_HTX_C_GRX_N11 AP24 AJ11 DGPU_PEX_RST#
PEG_GTX_C_HRX_N3 CV538 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N3 PEG_HTX_C_GRX_P12 AN24 PEX_RX11_N PEX_W AKE_N
PEG_HTX_C_GRX_N12 AM24 PEX_RX12
PEG_GTX_C_HRX_P4 CV539 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P4 PEG_HTX_C_GRX_P13 AN26 PEX_RX12_N @ +3.3V_GFX_AON
PEG_GTX_C_HRX_N4 CV540 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N4 PEG_HTX_C_GRX_N13 AM26 PEX_RX13 RPH15
PEG_HTX_C_GRX_P14 AP26 PEX_RX13_N AK9 1 8
PEG_GTX_C_HRX_P5 CV541 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P5 PEG_HTX_C_GRX_N14 AP27 PEX_RX14 DACA_RED AL10 2 7
PEX_RX14_N DACA_GREEN

2
PEG_GTX_C_HRX_N5 CV542 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N5 PEG_HTX_C_GRX_P15 AN27 AL9 3 6

G
PEG_HTX_C_GRX_N15 AM27 PEX_RX15 DACA_BLUE 4 5
PEG_GTX_C_HRX_P6 CV543 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P6 PEX_RX15_N THERMATRIP_GPU# 3 1
2 1 0.22U_0201_6.3V6M DIS@ THERMATRIP3# [48]
PEG_GTX_C_HRX_N6 CV544 PEG_GTX_HRX_N6 2.2K_8P4R_5%

D
PEG_GTX_HRX_P0 AK14 AM9

DACs
PEG_GTX_C_HRX_P7 CV545 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P7 PEG_GTX_HRX_N0 AJ14 PEX_TX0 DACA_HSYNC AN9 L2N7002WT1G_SC-70-3 RPH13
PEG_GTX_C_HRX_N7 CV546 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N7 PEG_GTX_HRX_P1 AH14 PEX_TX0_N DACA_VSYNC I2CA_SCL 1 8
PEX_TX1 QV88
PEG_GTX_HRX_N1 AG14 I2CA_SDA 2 7
PEX_TX1_N DIS@

PCI EXPRESS
PEG_GTX_C_HRX_P8 CV547 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P8 PEG_GTX_HRX_P2 AK15 I2CB_SCL 3 6
PEG_GTX_C_HRX_N8 CV548 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N8 PEG_GTX_HRX_N2 AJ15 PEX_TX2 AG10 RV479 1 @ 2 10K_0402_5% I2CB_SDA 4 5
PEG_GTX_HRX_P3 AL16 PEX_TX2_N DACA_VDD AP9
PEG_GTX_C_HRX_P9 CV550 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P9 PEG_GTX_HRX_N3 AK16 PEX_TX3 DACA_VREF AP8 2.2K_8P4R_5%
PEG_GTX_C_HRX_N9 CV551 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N9 PEG_GTX_HRX_P4 AK17 PEX_TX3_N DACA_RSET
PEX_TX4 DIS@
PEG_GTX_HRX_N4 AJ17
PEG_GTX_C_HRX_P10 CV552 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P10 PEG_GTX_HRX_P5 AH17 PEX_TX4_N +3.3V_GFX_AON
PEG_GTX_C_HRX_N10 CV557 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N10 PEG_GTX_HRX_N5 AG17 PEX_TX5
PEG_GTX_HRX_P6 AK18 PEX_TX5_N RPH34
PEG_GTX_C_HRX_P11 CV558 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P11 PEG_GTX_HRX_N6 AJ18 PEX_TX6 GPU_PEX_RST_HOLD# 4 5
PEG_GTX_C_HRX_N11 CV559 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N11 PEG_GTX_HRX_P7 AL19 PEX_TX6_N R4 I2CA_SCL THERMAL_ALERT# 3 6
PEG_GTX_HRX_N7 AK19 PEX_TX7 I2CA_SCL R5 I2CA_SDA 3V3_MAIN_EN 2 7
PEG_GTX_C_HRX_P12 CV560 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P12 PEG_GTX_HRX_P8 AK20 PEX_TX7_N I2CA_SDA THERMATRIP_GPU# 1 8
PEG_GTX_C_HRX_N12 CV561 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N12 PEG_GTX_HRX_N8 AJ20 PEX_TX8 R7 I2CB_SCL
PEG_GTX_HRX_P9 AH20 PEX_TX8_N I2CB_SCL R6 I2CB_SDA 10K_0804_8P4R_5%
C C

I2C
PEG_GTX_C_HRX_P13 CV562 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P13 PEG_GTX_HRX_N9 AG20 PEX_TX9 I2CB_SDA
PEX_TX9_N DIS@
PEG_GTX_C_HRX_N13 CV563 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N13 PEG_GTX_HRX_P10 AK21 R2 I2CC_SCL RV299 1 DIS@ 2 2.2K_0402_5%
PEG_GTX_HRX_N10 AJ21 PEX_TX10 I2CC_SCL R3 I2CC_SDA RV300 1 DIS@ 2 2.2K_0402_5% I2CC_SCL RV319 1 DIS@ 2 2.2K_0402_5%
PEG_GTX_C_HRX_P14 CV564 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P14 PEG_GTX_HRX_P11 AL22 PEX_TX10_N I2CC_SDA I2CC_SDA RV331 1 DIS@ 2 2.2K_0402_5%
PEG_GTX_C_HRX_N14 CV565 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N14 PEG_GTX_HRX_N11 AK22 PEX_TX11 T4 EC_SMB_CK2_PX
PEG_GTX_HRX_P12 AK23 PEX_TX11_N I2CS_SCL T3 EC_SMB_DA2_PX LV14
2 1 0.22U_0201_6.3V6M DIS@ AJ23 PEX_TX12 I2CS_SDA
PEG_GTX_C_HRX_P15 CV566 PEG_GTX_HRX_P15 PEG_GTX_HRX_N12
PEX_TX12_N Under GPU BLM15PD300SN1D_2P
PEG_GTX_C_HRX_N15 CV567 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N15 PEG_GTX_HRX_P13 AH23 1 2
PEX_TX13 +1.05VSDGPU
PEG_GTX_HRX_N13 AG23
PEX_TX13_N DV10
PEG_GTX_HRX_P14 AK24 1 1 DIS@
PEG_GTX_HRX_N14 AJ24 PEX_TX14 CV773 GC6_EVENT#_D 2 1
PEX_TX14_N GPU_EVENT# [20]
PEG_GTX_HRX_P15 AL25 0.1U_0402_10V7K CV574
PEG_GTX_HRX_N15 AK25 PEX_TX15 22U_0603_6.3V6M RB751S40T1G_SOD523-2
PEX_TX15_N AD8 +PLLVDD 2 2
PLLVDD DIS@ DIS@ Near GPU DIS@
AE8 DV11
SP_PLLVDD 300 ohm, 0.2 ESR
AL13 GPU_HOT#_R 2 1
[17] CLK_PEG_VGA PEX_REFCLK GPU_PW R_LEVEL [48]
AK13 AD7 +CLK_PLLVDD LV2 1 2
[17] CLK_PEG_VGA# PEX_REFCLK_N VID_PLLVDD +1.05VSDGPU
CLK_REQ# AK12 PBY160808T-301Y-N_2P RB751S40T1G_SOD523-2
PEX_CLKREQ_N H3 CLK_27M_IN

0.1U_0402_10V7K

0.1U_0402_10V7K

10U_0603_6.3V6M
CLK
XTAL_IN DIS@ DIS@
@ RV286 1 2 200_0402_1% PEX_TSTCLK_OUT AJ26 H2 CLK_27M_OUT

47U_0805_6.3V6M
[60] ALL_GPW RGD PEX_TSTCLK_OUT XTAL_OUT 1 1 1 1
PEX_TSTCLK_OUT# AK26

CV570

CV571

CV572
PEX_TSTCLK_OUT_N H1 XTALSSIN

CV573
XTAL_SSIN J4 XTALOUTBUFF
AJ12 XTAL_OUTBUFF 2 2 2 2
DGPU_PEX_RST#
PEX_RST_N Under GPU
AP29
PEX_TERMP
Near GPU
2

@ N16P-GX-A2 DIS@ DIS@ DIS@ DIS@

G

RV290
1 3 CLK_REQ# 2.49K_0402_1%
[17] VGA_CLK_REQ#
DIS@ DV9
D

2
[62] 1.05V_DGPU_PG
2

L2N7002WT1G_SC-70-3
QV39 YV1 DIS@ 1
4 3 FBVDD_EN [32,60]
CLK_27M_OUT
DIS@ VDD OUT GC6_FB_EN 3
B B

1
DIS@

100K_0402_5%
1
BAT54CW-7-F_SOT323-3~D

RV209
CLK_27M_IN 1 2 CV576 DIS@
VCOUNT GND 10P_0402_25V8J
27MHZ_10PF_5YEA27000102IF50Q3 2
DIS@

2
1
+3.3V_GFX_AON CV575
10P_0402_25V8J
+3.3V_GFX_AON 2 DIS@
1
0.1U_0402_10V7K
CV129

2@ RV50
@ 10K_0402_5%
5

+3.3V_GFX_AON +3.3V_GFX_RUN
VCC

1
[20] DGPU_HOLD_RST# IN1 4 SYS_PEX_RST_MON# X06.10
2 OUT SYS_PEX_RST_MON# [24]
[17,37,42,43,44,48,51] PCH_PLTRST#_EC
GND

IN2
1

UV14 RV187

1
MC74VHC1G08DFT2G_SC70-5 10K_0402_5%
3
1

DIS@ RV325 RV326

DIS@
RV45 1.8K_0402_5% 1.8K_0402_5%
2

100K_0402_5% DIS@ DIS@

DIS@

2
2

EC_SMB_CK2_PX 1 6
0_0402_5%

UPD_GPU_SMBCLK [39,48]
RV208

5
@ QV21A
DMN65D8LDW-7_SOT363-6
+3.3V_GFX_AON EC_SMB_DA2_PX 4 3
UPD_GPU_SMBDAT [39,48]
2

DIS@
A A
QV21B
DMN65D8LDW-7_SOT363-6
1
10K_0402_5%
RV29

DIS@
DIS@
DV8
SYS_PEX_RST_MON# 2
2

1 DGPU_PEX_RST#

GPU_PEX_RST_HOLD# 3
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/08/08 Deciphered Date 2014/07/01 Title
BAT54AW-7-F_SOT323-3
DIS@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR
Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
N15P (1/5)-PCIE / GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 23 of 71
5 4 3 2 1
 5 4 3 2 1

Straps
+3.3V_GFX_RUN +3.3V_GFX_AON

15K_0402_1%
34.8K_0402_1%

10K_0402_1%

10K_0402_1%
4.99K_0402_1%

4.99K_0402_1%

30.1K_0402_1%

49.9K_0402_1%
UV1D

2
RV304

RV305

RV306
RV303

RV301

RV302

RV307

RV308
Part 4 of 7
AM6 P8 @ @ @ @ @ @ @
AN6 IFPA_TXC NC_0 AC6
AP3 IFPA_TXC_N NC_1 AJ28
IFPA_TXD0 NC_2

1
D AN3 AJ4 D
AN5 IFPA_TXD0_N NC_3 AJ5 DIS@
AM5 IFPA_TXD1 NC_4 AL11 STRAP0
AL6 IFPA_TXD1_N NC_5 C15 STRAP1

NC
AK6 IFPA_TXD2 NC_6 D19 STRAP2
AJ6 IFPA_TXD2_N NC_7 D20 STRAP3
AH6 IFPA_TXD3 NC_8 D23 STRAP4
IFPA_TXD3_N NC_9 D26 ROM_SCLK_GPU
NC_10 H31 ROM_SI_GPU
AJ9 NC_11 T8 ROM_SO_GPU
IFPB_TXC NC_12

10K_0402_1%
4.99K_0402_1%

4.99K_0402_1%

4.99K_0402_1%

45.3K_0402_1%

4.99K_0402_1%

34.8K_0402_1%

4.99K_0402_1%
AH9 V32
IFPB_TXC_N NC_13

2
AP6
AP5 IFPB_TXD4

RV311

RV312

RV313

RV309

RV310

RV314

RV315

RV316
AM7 IFPB_TXD4_N @ @ @ @ @ @
AL7 IFPB_TXD5
AN8 IFPB_TXD5_N L2
IFPB_TXD6 BUFRST_N

1
AM8
AK8 IFPB_TXD6_N
AL8 IFPB_TXD7 L3 DIS@ DIS@
IFPB_TXD7_N CEC SYS_PEX_RST_MON# [23]

AK1 J2 STRAP0
AJ1 IFPC_L0 STRAP0 J7 STRAP1
AJ3 IFPC_L0_N STRAP1 J6 STRAP2
AJ2 IFPC_L1 STRAP2 J5 STRAP3
AH3 IFPC_L1_N STRAP3 J3 STRAP4
GENERAL
LVDS/TMDS

AH4 IFPC_L2 STRAP4

AG5 IFPC_L2_N
AG4 IFPC_L3
IFPC_L3_N

AM1
C AM2 IFPD_L0 J1 MULTI_STRAP_REF0_GND C
AM3 IFPD_L0_N MULTI_STRAP_REF0_GND
IFPD_L1

1
AM4
AL3 IFPD_L1_N RV318
AL4 IFPD_L2
IFPD_L2_N 40.2K_0402_1%
AK4 DIS@
AK5 IFPD_L3
IFPD_L3_N

2
AD2 K3
AD3 IFPE_L0 THERMDP
AD1 IFPE_L0_N K4
AC1 IFPE_L1 THERMDN
AC2 IFPE_L1_N
AC3 IFPE_L2
AC4 IFPE_L2_N
AC5 IFPE_L3
IFPE_L3_N

AE3 L4
AE4 IFPF_L0 VDD_SENSE GPU_VDD_SENSE [63]
AF4 IFPF_L0_N
AF5 IFPF_L1
AD4 IFPF_L1_N
AD5 IFPF_L2 +3.3V_GFX_AON
AG1 IFPF_L2_N
AF1 IFPF_L3 L5
IFPF_L3_N GND_SENSE GPU_VSS_SENSE [63]
@

10K_0402_5%
1

RV320
AG3
AG2 IFPC_AUX_I2CW_SCL
B IFPC_AUX_I2CW_SDA_N TEST B
2

AK3 AK11 GPU_TESTMODE

AK2 IFPD_AUX_I2CX_SCL TESTMODE AM10 GPU_JTAG_TCK @ T174
IFPD_AUX_I2CX_SDA_N JTAG_TCK AM11 GPU_JTAG_TDI @ T11
10K_0402_5%

JTAG_TDI
1

AP12 GPU_JTAG_TDO @ T12

AB3 JTAG_TDO AP11 GPU_JTAG_TMS @ T13
RV323

AB4 IFPE_AUX_I2CY_SCL JTAG_TMS AN11 GPU_JTAG_TRST# DIS@

IFPE_AUX_I2CY_SDA_N JTAG_TRST_N
1

AF3 RV324
AF2 IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N SERIAL DIS@ 10K_0402_5%

H6 ROM_CS_GPU @ T176
ROM_CS_N
2

H5 ROM_SI_GPU
ROM_SI H7 ROM_SO_GPU
ROM_SO H4 ROM_SCLK_GPU
ROM_SCLK

@ N16P-GX-A2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/08/08 Deciphered Date 2014/07/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
N15P (2/5)-DP / Straps
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS Size
ION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 24 of 71
5 4 3 2 1
 5 4 3 2 1

+1.05VSDGPU

+1.35VSDGPU PLACE UNDER BGA PLACE NEAR GPU

UV1E
@

1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
Part 5 of 7 1 1 @ 1 1 1 @ 1 1
AA27 AG13
PEX_IOVDD/Q 3.3A

CV580

CV581

CV583

CV584

CV585

CV586
AA30 FBVDDQ_0 PEX_IOVDDQ_0 AG15

CV582
D AB27 FBVDDQ_1 PEX_IOVDDQ_1 AG16 D
AB33 FBVDDQ_2 PEX_IOVDDQ_2 AG18 2 2 2 2 2 2 2
AC27 FBVDDQ_3 PEX_IOVDDQ_3 AG25 DIS@ DIS@
close to the GPU Close to Pin AD27 FBVDDQ_4 PEX_IOVDDQ_4 AH15
AE27 FBVDDQ_5 PEX_IOVDDQ_5 AH18
AF27 FBVDDQ_6 PEX_IOVDDQ_6 AH26 DIS@ DIS@
AG27 FBVDDQ_7 PEX_IOVDDQ_7 AH27 +1.05VSDGPU
B13 FBVDDQ_8 PEX_IOVDDQ_8 AJ27
22U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_25V6

0.1U_0402_25V6
@ B16 FBVDDQ_9 PEX_IOVDDQ_9 AK27
1 1 1 1 1 1 1 1 1 FBVDDQ_10 PEX_IOVDDQ_10
@ B19 AL27
CV587

CV588

CV815

CV589

CV590

1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
E13 FBVDDQ_11 PEX_IOVDDQ_11 AM28

CV591

CV592

CV593

CV594
FBVDDQ_12 PEX_IOVDDQ_12 1 1 1 1 1 1 1
E16 AN28

CV597

CV598

CV599

CV600

CV601
2 2 2 2 2 2 2 2 2 E19 FBVDDQ_13 PEX_IOVDDQ_13

CV595

CV596
DIS@ H10 FBVDDQ_14
H11 FBVDDQ_15 AG19 2 2 2 2 2 2 2
H12 FBVDDQ_16 PEX_IOVDD_0 AG21 DIS@ DIS@
DIS@ DIS@ DIS@ DIS@ DIS@ H13 FBVDDQ_17 PEX_IOVDD_1 AG22
DIS@
H14 FBVDDQ_18 PEX_IOVDD_2 AG24
H15 FBVDDQ_19 PEX_IOVDD_3 AH21 DIS@ DIS@ DIS@ DIS@ DIS@
H16 FBVDDQ_20 PEX_IOVDD_4 AH25

POWER
H18 FBVDDQ_21 PEX_IOVDD_5
H19 FBVDDQ_22
H20 FBVDDQ_23 AG26 +PEX_PLLVDD LV3 1 2 BLM15PX121SN1D_2P
FBVDDQ_24 PEX_PLLVDD +1.05VSDGPU
H21
22U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_10V7K

1U_0402_6.3V6K

4.7U_0603_6.3V6K

1U_0402_6.3V6K
H22 FBVDDQ_25
0.15A
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1 1 1 1 1 1 1 1 1 DIS@ 1
@ @ @ H23 FBVDDQ_26 +3.3V_GFX_AON @
CV602

CV603

CV610

CV612
1 1 1 FBVDDQ_27
H24
CV816

CV604

CV605

CV606

CV607

CV608

CV609

CV611

CV613
H8 FBVDDQ_28 J8 +3.3V_GFX_RUN
2 2 2 2 2 2 H9 FBVDDQ_29 VDD33_0 K8 2 2 2 2
DIS@ 2 2 2 L27 FBVDDQ_30 VDD33_1 L8
M27 FBVDDQ_31 VDD33_2 M8
N27 FBVDDQ_32 VDD33_3
C P27 FBVDDQ_33 DIS@ C
DIS@ DIS@
DIS@ DIS@ DIS@ DIS@ DIS@ R27 FBVDDQ_34 +3.3V_GFX_RUN
FBVDDQ_35
T27
FBVDDQ_36 FB_CAL_PD_VDDQ
J27 RV327 1 DIS@ 2 40.2_0402_1%
+1.35VSDGPU Under GPU Near GPU
T30
T33 FBVDDQ_37
X06.38 V27 FBVDDQ_38 H27 RV328 1 DIS@ 2 40.2_0402_1%
W27 FBVDDQ_39 FB_CAL_PU_GND

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
W30 FBVDDQ_40
FBVDDQ_41 1 1 1 1 1
W33 H25 RV329 1 DIS@ 2 60.4_0402_1%
Y27 FBVDDQ_42 FB_CAL_TERM_GND

CV623

CV622

CV621

CV619

CV617
FBVDDQ_43
AH8 F2 RV330 1 DIS@ 2 100_0402_1% 2 2 2 2 2
AJ8 IFPAB_PLLVDD FB_GND_SENSE
AG8 IFPAB_RSET
AG9 IFPA_IOVDD F1 RV332 1 DIS@ 2 100_0402_1%
IFPB_IOVDD FB_VDDQ_SENSE +1.35VSDGPU
DIS@ DIS@ DIS@ DIS@ DIS@

AF7
AF8 IFPC_PLLVDD +3.3V_GFX_AON
AF6 IFPC_RSET AH12
IFPC_IOVDD PEX_PLL_HVDD
AG12
0.21A

0.1U_0402_10V7K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AG7 PEX_SVDD_3V3 @
IFPD_PLLVDD 1 1 1
AN2

CV614

CV615

CV616
AG6 IFPD_RSET
IFPD_IOVDD
2 2 2
AB8
AD6 IFPEF_PLLVDD
AC7 IFPEF_RSET
AC8 IFPE_IOVDD DIS@
IFPF_IOVDD DIS@
B B

@ N16P-GX-A2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/08/08 Deciphered Date 2014/07/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
N15P (3/5)-Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS Size
ION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 25 of 71
5 4 3 2 1
 5 4 3 2 1

UV1F

AG11 Part 6 of 7 D2
A2 GND_0 GND_101 D31
A33 GND_1 GND_102 D33
AA13 GND_2 GND_103 E10
AA15 GND_3 GND_104 E22
AA17 GND_4 GND_105 E25
D AA18 GND_5 GND_106 E5 D
AA20 GND_6 GND_107 E7
AA22 GND_7 GND_108 F28
AB12 GND_8 GND_109 F7
AB14 GND_9 GND_110 G10
AB16 GND_10 GND_111 G13 +GPU_CORE
AB19 GND_11 GND_112 G16 UV1G +GPU_CORE
AB2 GND_12 GND_113 G19
AB21 GND_13 GND_114 G2 AA12 V17
AB23 GND_14 GND_115 G22 AA14 VDD_0 Part 7 of 7 VDD_56 V18
AB28 GND_15 GND_116 G25 AA16 VDD_1 VDD_57 V20
AB30 GND_16 GND_117 G28 AA19 VDD_2 VDD_58 V22
AB32 GND_17 GND_118 G3 AA21 VDD_3 VDD_59 W12
AB5 GND_18 GND_119 G30 AA23 VDD_4 VDD_60 W14
AB7 GND_19 GND_120 G32 AB13 VDD_5 VDD_61 W16
AC13 GND_20 GND_121 G33 AB15 VDD_6 VDD_62 W19
AC15 GND_21 GND_122 G5 AB17 VDD_7 VDD_63 W21
AC17 GND_22 GND_123 G7 AB18 VDD_8 VDD_64 W23
AC18 GND_23 GND_124 K2 AB20 VDD_9 VDD_65 Y13
AC20 GND_24 GND_125 K28 AB22 VDD_10 VDD_66 Y15
AC22 GND_25 GND_126 K30 AC12 VDD_11 VDD_67 Y17
AE2 GND_26 GND_127 K32 AC14 VDD_12 VDD_68 Y18
AE28 GND_27 GND_128 K33 AC16 VDD_13 VDD_69 Y20
AE30 GND_28 GND_129 K5 AC19 VDD_14 VDD_70 Y22
AE32 GND_29 GND_130 K7 AC21 VDD_15 VDD_71
AE33 GND_30 GND_131 M13 AC23 VDD_16
AE5 GND_31 GND_132 M15 M12 VDD_17 U1
AE7 GND_32 GND_133 M17 M14 VDD_18 XVDD_1 U2
AH10 GND_33 GND_134 M18 M16 VDD_19 XVDD_2 U3
AH13 GND_34 GND_135 M20 M19 VDD_20 XVDD_3 U4
AH16 GND_35 GND_136 M22 M21 VDD_21 XVDD_4 U5

POWER
AH19 GND_36 GND_137 N12 M23 VDD_22 XVDD_5 U6
C AH2 GND_37 GND_138 N14 N13 VDD_23 XVDD_6 U7 C
AH22 GND_38 GND_139 N16 N15 VDD_24 XVDD_7 U8
AH24 GND_39 GND_140 N19 N17 VDD_25 XVDD_8 V1
AH28 GND_40 GND_141 N2 N18 VDD_26 XVDD_9 V2
AH29 GND_41 GND_142 N21 N20 VDD_27 XVDD_10 V3
AH30 GND_42 GND_143 N23 N22 VDD_28 XVDD_11 V4
AH32 GND_43 GND_144 N28 P12 VDD_29 XVDD_12 V5
AH33 GND_44 GND_145 N30 P14 VDD_30 XVDD_13 V6
GND
AH5 GND_45 GND_146 N32 P16 VDD_31 XVDD_14 V7
AH7 GND_46 GND_147 N33 P19 VDD_32 XVDD_15 V8
AJ7 GND_47 GND_148 N5 P21 VDD_33 XVDD_16 W2
AK10 GND_48 GND_149 N7 P23 VDD_34 XVDD_17 W3
AK7 GND_49 GND_150 P13 R13 VDD_35 XVDD_18 W4
AL12 GND_50 GND_151 P15 R15 VDD_36 XVDD_19 W5
AL14 GND_51 GND_152 P17 R17 VDD_37 XVDD_20 W7
AL15 GND_52 GND_153 P18 R18 VDD_38 XVDD_21 W8
AL17 GND_53 GND_154 P20 R20 VDD_39 XVDD_22 Y1
AL18 GND_54 GND_155 P22 R22 VDD_40 XVDD_23 Y2
AL2 GND_55 GND_156 R12 T12 VDD_41 XVDD_24 Y3
AL20 GND_56 GND_157 R14 T14 VDD_42 XVDD_25 Y4
AL21 GND_57 GND_158 R16 T16 VDD_43 XVDD_26 Y5
AL23 GND_58 GND_159 R19 T19 VDD_44 XVDD_27 Y6
AL24 GND_59 GND_160 R21 T21 VDD_45 XVDD_28 Y7
AL26 GND_60 GND_161 R23 T23 VDD_46 XVDD_29 Y8
AL28 GND_61 GND_162 T13 U13 VDD_47 XVDD_30 AA1
AL30 GND_62 GND_163 T15 U15 VDD_48 XVDD_31 AA2
AL32 GND_63 GND_164 T17 U17 VDD_49 XVDD_32 AA3
AL33 GND_64 GND_165 T18 U18 VDD_50 XVDD_33 AA4
AL5 GND_65 GND_166 T2 U20 VDD_51 XVDD_34 AA5
AM13 GND_66 GND_167 T20 U22 VDD_52 XVDD_35 AA6
AM16 GND_67 GND_168 T22 V13 VDD_53 XVDD_36 AA7
AM19 GND_68 GND_169 T28 V15 VDD_54 XVDD_37 AA8
B AM22 GND_69 GND_170 T32 VDD_55 XVDD_38 B
AM25 GND_70 GND_171 T5
AN1 GND_71 GND_172 T7
AN10 GND_72 GND_173 U12
AN13 GND_73 GND_174 U14 @ N16P-GX-A2
AN16 GND_74 GND_175 U16
AN19 GND_75 GND_176 U19
AN22 GND_76 GND_177 U21
AN25 GND_77 GND_178 U23
AN30 GND_78 GND_179 V12
AN34 GND_79 GND_180 V14
AN4 GND_80 GND_181 V16
AN7 GND_81 GND_182 V19
AP2 GND_82 GND_183 V21
AP33 GND_83 GND_184 V23
B1 GND_84 GND_185 W13
B10 GND_85 GND_186 W15
B22 GND_86 GND_187 W17
B25 GND_87 GND_188 W18
B28 GND_88 GND_189 W20
B31 GND_89 GND_190 W22
B34 GND_90 GND_191 W28
B4 GND_91 GND_192 Y12
B7 GND_92 GND_193 Y14
C10 GND_93 GND_194 Y16
C13 GND_94 GND_195 Y19
C19 GND_95 GND_196 Y21
C22 GND_96 GND_197 Y23
C25 GND_97 GND_198 AH11
C28 GND_98 GND_199
C7 GND_99 C16
GND_100 GND_OPT W32
A GND_OPT A

@ N16P-GX-A2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/08/08 Deciphered Date 2014/07/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
N15P (4/5)-Power / GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS Size
ION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 26 of 71
5 4 3 2 1
 5 4 3 2 1

FBA_D[0..31] FBB_D[0..31]
[28] FBA_D[0..31] [30] FBB_D[0..31]
FBA_D[32..63] FBB_D[32..63]
[29] FBA_D[32..63] [31] FBB_D[32..63]
FBA_CMD[0..31] FBB_CMD[0..31]
[28,29] FBA_CMD[0..31] [30,31] FBB_CMD[0..31]
FBA_DBI[4..7] FBB_DBI[4..7]
[29] FBA_DBI[4..7] [31] FBB_DBI[4..7]
FBA_DBI[0..3] FBB_DBI[0..3]
[28] FBA_DBI[0..3] [30] FBB_DBI[0..3]
FBA_EDC[4..7] FBB_EDC[4..7]
[29] FBA_EDC[4..7] [31] FBB_EDC[4..7]
D FBA_EDC[0..3] FBB_EDC[0..3] D
[28] FBA_EDC[0..3] [30] FBB_EDC[0..3]
UV1B UV1C

Part 3 of 7
FBA_D0 L28 Part 2 of 7 U30 FBA_CMD0 FBB_D0 G9 D13 FBB_CMD0
FBA_D1 M29 FBA_D00 FBA_CMD0 T31 FBA_CMD1 FBB_D1 E9 FBB_D00 FBB_CMD0 E14 FBB_CMD1
FBA_D2 L29 FBA_D01 FBA_CMD1 U29 FBA_CMD2 FBB_D2 G8 FBB_D01 FBB_CMD1 F14 FBB_CMD2
FBA_D3 M28 FBA_D02 FBA_CMD2 R34 FBA_CMD3 FBB_D3 F9 FBB_D02 FBB_CMD2 A12 FBB_CMD3
FBA_D4 N31 FBA_D03 FBA_CMD3 R33 FBA_CMD4 FBB_D4 F11 FBB_D03 FBB_CMD3 B12 FBB_CMD4
FBA_D5 P29 FBA_D04 FBA_CMD4 U32 FBA_CMD5 FBB_D5 G11 FBB_D04 FBB_CMD4 C14 FBB_CMD5
FBA_D6 R29 FBA_D05 FBA_CMD5 U33 FBA_CMD6 FBB_D6 F12 FBB_D05 FBB_CMD5 B14 FBB_CMD6
FBA_D7 P28 FBA_D06 FBA_CMD6 U28 FBA_CMD7 FBB_D7 G12 FBB_D06 FBB_CMD6 G15 FBB_CMD7
FBA_D8 J28 FBA_D07 FBA_CMD7 V28 FBA_CMD8 +1.35VSDGPU FBB_D8 G6 FBB_D07 FBB_CMD7 F15 FBB_CMD8 +1.35VSDGPU
FBA_D9 H29 FBA_D08 FBA_CMD8 V29 FBA_CMD9 RV338 FBB_D9 F5 FBB_D08 FBB_CMD8 E15 FBB_CMD9 RV409
FBA_D10 J29 FBA_D09 FBA_CMD9 V30 FBA_CMD10 10K_0402_5% FBB_D10 E6 FBB_D09 FBB_CMD9 D15 FBB_CMD10 10K_0402_5%
FBA_D10 FBA_CMD10 FBB_D10 FBB_CMD10
FBA_D11 H28
FBA_D11 FBA_CMD11
U34 FBA_CMD11 CKE_H FBA_CMD30 1 DIS@ 2 FBB_D11 F6
FBB_D11 FBB_CMD11
A14 FBB_CMD11 CKE_H FBB_CMD30 1 DIS@ 2
FBA_D12 G29 U31 FBA_CMD12 FBB_D12 F4 D14 FBB_CMD12
FBA_D13 E31 FBA_D12 FBA_CMD12 V34 FBA_CMD13 RV339 FBB_D13 G4 FBB_D12 FBB_CMD12 A15 FBB_CMD13 RV410
FBA_D14 E32 FBA_D13 FBA_CMD13 V33 FBA_CMD14 10K_0402_5% FBB_D14 E2 FBB_D13 FBB_CMD13 B15 FBB_CMD14 10K_0402_5%
FBA_D14 FBA_CMD14 FBB_D14 FBB_CMD14
FBA_D15 F30
FBA_D15 FBA_CMD15
Y32 FBA_CMD15 CKE_L FBA_CMD14 1 DIS@ 2 FBB_D15 F3
FBB_D15 FBB_CMD15
C17 FBB_CMD15 CKE_L FBB_CMD14 1 DIS@ 2
FBA_D16 C34 AA31 FBA_CMD16 FBB_D16 C2 D18 FBB_CMD16
FBA_D17 D32 FBA_D16 FBA_CMD16 AA29 FBA_CMD17 FBB_D17 D4 FBB_D16 FBB_CMD16 E18 FBB_CMD17
FBA_D18 B33 FBA_D17 FBA_CMD17 AA28 FBA_CMD18 RV340 FBB_D18 D3 FBB_D17 FBB_CMD17 F18 FBB_CMD18 RV414
FBA_D19 C33 FBA_D18 FBA_CMD18 AC34 FBA_CMD19 10K_0402_5% FBB_D19 C1 FBB_D18 FBB_CMD18 A20 FBB_CMD19 10K_0402_5%
FBA_D19 FBA_CMD19 FBB_D19 FBB_CMD19
FBA_D20 F33
FBA_D20 FBA_CMD20
AC33 FBA_CMD20 RST_H* FBA_CMD29 1 DIS@ 2 FBB_D20 B3
FBB_D20 FBB_CMD20
B20 FBB_CMD20 RST_H* FBB_CMD29 1 DIS@ 2
FBA_D21 F32 AA32 FBA_CMD21 FBB_D21 C4 C18 FBB_CMD21
FBA_D22 H33 FBA_D21 FBA_CMD21 AA33 FBA_CMD22 RV341 FBB_D22 B5 FBB_D21 FBB_CMD21 B18 FBB_CMD22 RV418
FBA_D23 H32 FBA_D22 FBA_CMD22 Y28 FBA_CMD23 10K_0402_5% FBB_D23 C5 FBB_D22 FBB_CMD22 G18 FBB_CMD23 10K_0402_5%
FBA_D23 FBA_CMD23 FBB_D23 FBB_CMD23
+1.05VSDGPU
NEED FIND 30R BEAD
+FBA_DLL_AVDD
FBA_D24 P34
FBA_D24 FBA_CMD24
Y29 FBA_CMD24 RST_L* FBA_CMD13 1 DIS@ 2 FBB_D24 A11
FBB_D24 FBB_CMD24
G17 FBB_CMD24 RST_L* FBB_CMD13 1 DIS@ 2
FBA_D25 P32 W31 FBA_CMD25 FBB_D25 C11 F17 FBB_CMD25
LV21 FBA_D26 P31 FBA_D25 FBA_CMD25 Y30 FBA_CMD26 FBB_D26 D11 FBB_D25 FBB_CMD25 D16 FBB_CMD26
C HCB1608KF-300T20 FBA_D27 P33 FBA_D26 FBA_CMD26 AA34 FBA_CMD27 FBB_D27 B11 FBB_D26 FBB_CMD26 A18 FBB_CMD27 C
1 2 +FBA_DLL_AVDD FBA_D28 L31 FBA_D27 FBA_CMD27 Y31 FBA_CMD28 FBB_D28 D8 FBB_D27 FBB_CMD27 D17 FBB_CMD28
FBA_D28 FBA_CMD28 FBB_D28 FBB_CMD28
DIS@ FBA_D29 L34 Y34 FBA_CMD29
for Test/Debug FBB_D29 A8 A17 FBB_CMD29
for Test/Debug
22U_0603_6.3V6M

FBA_D30 L32 FBA_D29 FBA_CMD29 Y33 FBA_CMD30 FBB_D30 C8 FBB_D29 FBB_CMD29 B17 FBB_CMD30
1U_0402_6.3V6K

0.1U_0402_10V7K

1 1 1 FBA_D30 FBA_CMD30 FBB_D30 FBB_CMD30

FBA_D31 L33 V31 FBA_CMD31 FBB_D31 B8 E17 FBB_CMD31
CV791

FBA_D32 AG28 FBA_D31 FBA_CMD31 FBB_D32 F24 FBB_D31 FBB_CMD31

CV790

CV637

MEMORY INTERFACE

MEMORY INTERFACE
FBA_D33 AF29 FBA_D32 P30 FBA_DBI0 FBB_D33 G23 FBB_D32 E11 FBB_DBI0
2 2 2 FBA_D34 AG29 FBA_D33 FBA_DQM0 F31 FBA_DBI1 FBB_D34 E24 FBB_D33 FBB_DQM0 E3 FBB_DBI1
DIS@ AF28 FBA_D34 FBA_DQM1 F34 G24 FBB_D34 FBB_DQM1 A3
FBA_D35 FBA_DBI2 FBB_D35 FBB_DBI2
FBA_D36 AD30 FBA_D35 FBA_DQM2 M32 FBA_DBI3 FBB_D36 D21 FBB_D35 FBB_DQM2 C9 FBB_DBI3
FBA_D37 AD29 FBA_D36 FBA_DQM3 AD31 FBA_DBI4 FBB_D37 E21 FBB_D36 FBB_DQM3 F23 FBB_DBI4
FBA_D38 AC29 FBA_D37 FBA_DQM4 AL29 FBA_DBI5 FBB_D38 G21 FBB_D37 FBB_DQM4 F27 FBB_DBI5
DIS@ AD28 FBA_D38 FBA_DQM5 AM32 F21 FBB_D38 FBB_DQM5 C30
DIS@ FBA_D39 FBA_DBI6 FBB_D39 FBB_DBI6
FBA_D40 AJ29 FBA_D39 FBA_DQM6 AF34 FBA_DBI7 FBB_D40 G27 FBB_D39 FBB_DQM6 A24 FBB_DBI7
FBA_D41 AK29 FBA_D40 FBA_DQM7 FBB_D41 D27 FBB_D40 FBB_DQM7
FBA_D42 AJ30 FBA_D41 M30 FBB_D42 G26 FBB_D41 D9
FBA_D43 AK28 FBA_D42 FBA_DQS_RN0 H30 FBB_D43 E27 FBB_D42 FBB_DQS_RN0 E4
FBA_D44 AM29 FBA_D43 FBA_DQS_RN1 E34 FBB_D44 E29 FBB_D43 FBB_DQS_RN1 B2
+1.35VSDGPU FBA_D45 AM31 FBA_D44 FBA_DQS_RN2 M34 FBB_D45 F29 FBB_D44 FBB_DQS_RN2 A9
FBA_D46 AN29 FBA_D45 FBA_DQS_RN3 AF30 FBB_D46 E30 FBB_D45 FBB_DQS_RN3 D22
FBA_D47 AM30 FBA_D46 FBA_DQS_RN4 AK31 FBB_D47 D30 FBB_D46 FBB_DQS_RN4 D28
FBA_D47 FBA_DQS_RN5 FBB_D47 FBB_DQS_RN5
1

FBA_D48 AN31 AM34 FBB_D48 A32 A30

@ RV342 FBA_D49 AN32 FBA_D48 FBA_DQS_RN6 AF32 FBB_D49 C31 FBB_D48 FBB_DQS_RN6 B23
A

B
1.1K_0402_1% FBA_D50 AP30 FBA_D49 FBA_DQS_RN7 FBB_D50 C32 FBB_D49 FBB_DQS_RN7
FBA_D51 AP32 FBA_D50 M31 FBA_EDC0 FBB_D51 B32 FBB_D50 D10 FBB_EDC0
16mil FBA_D52 AM33 FBA_D51 FBA_DQS_WP0 G31 FBA_EDC1 FBB_D52 D29 FBB_D51 FBB_DQS_WP0 D5 FBB_EDC1
FBA_D52 FBA_DQS_WP1 FBB_D52 FBB_DQS_WP1
2

+FB_VREF FBA_D53 AL31 E33 FBA_EDC2 FBB_D53 A29 C3 FBB_EDC2

FBA_D54 AK33 FBA_D53 FBA_DQS_WP2 M33 FBA_EDC3 FBB_D54 C29 FBB_D53 FBB_DQS_WP2 B9 FBB_EDC3
FBA_D54 FBA_DQS_WP3 FBB_D54 FBB_DQS_WP3
1

1 FBA_D55 AK32 AE31 FBA_EDC4 FBB_D55 B29 E23 FBB_EDC4

FBA_D56 AD34 FBA_D55 FBA_DQS_WP4 AK30 FBA_EDC5 FBB_D56 B21 FBB_D55 FBB_DQS_WP4 E28 FBB_EDC5
@ RV343 @ CV638 FBA_D57 AD32 FBA_D56 FBA_DQS_WP5 AN33 FBA_EDC6 FBB_D57 C23 FBB_D56 FBB_DQS_WP5 B30 FBB_EDC6
1.1K_0402_1% 0.01U_0402_16V7K FBA_D58 AC30 FBA_D57 FBA_DQS_WP6 AF33 FBA_EDC7 FBB_D58 A21 FBB_D57 FBB_DQS_WP6 A23 FBB_EDC7
B 2 FBA_D59 AD33 FBA_D58 FBA_DQS_WP7 FBB_D59 C21 FBB_D58 FBB_DQS_WP7 B
FBA_D59 FBB_D59
2

FBA_D60 AF31 R32 FBB_D60 B24 C12

FBA_D61 AG34 FBA_D60 FBA_CMD_RFU0 AC32 FBB_D61 C24 FBB_D60 FBB_CMD_RFU0 C20
FBA_D62 AG32 FBA_D61 FBA_CMD_RFU1 FBB_D62 B26 FBB_D61 FBB_CMD_RFU1
FBA_D63 AG33 FBA_D62 FBB_D63 C26 FBB_D62
FBA_D63 R30 +FBA_PLL_AVDD FBB_D63 D12
FBA_CLK0 R31 CLKA0 [28] FBB_CLK0 E12 CLKB0 [30]
+FBA_PLL_AVDD U27 FBA_CLK0_N CLKA0# [28] +FBA_PLL_AVDD H17 FBB_CLK0_N CLKB0# [30]
FBA_PLL_AVDD AB31 FBB_PLL_AVDD E20
+FB_VREF H26 FBA_CLK1 AC31 CLKA1 [29] FBB_CLK1 F20 CLKB1 [31]
FB_VREF FBA_CLK1_N CLKA1# [29] 1 FBB_CLK1_N CLKB1# [31]
DIS@ CV636
CV639 1 2 0.1U_0402_10V7K K31 FBA_WCK01 0.1U_0402_10V7K F8 FBB_WCK01
FBA_WCK01 FBA_WCK01 [28] FBB_WCK01 FBB_WCK01 [30]
+FBA_PLL_AVDD RV510 1 2 0_0402_5% +FBA_DLL_AVDD K27 L30 FBA_WCK01# E8 FBB_WCK01#
FB_DLL_AVDD FBA_WCK01_N H34 FBA_WCK23 FBA_WCK01# [28] 2 FBB_WCK01_N A5 FBB_WCK23 FBB_WCK01# [30]
@
E1 FBA_WCK23 J34 FBA_WCK23# FBA_WCK23 [28] DIS@ FBB_WCK23 A6 FBB_WCK23# FBB_WCK23 [30]
X06.30 FB_CLAMP FBA_WCK23_N AG30 FBA_WCK45
FBA_WCK23# [28] FBB_WCK23_N D24 FBB_WCK45
FBB_WCK23# [30]
1 DIS@ 2 10K_0402_5% FBA_WCK45 AG31 FBA_WCK45 [29] FBB_WCK45 D25 FBB_WCK45 [31]
RV501 FBA_WCK45# FBB_WCK45#
R28 FBA_WCK45_N AJ34 FBA_WCK67 FBA_WCK45# [29] G14 FBB_WCK45_N B27 FBB_WCK67 FBB_WCK45# [31]
AC28 FBA_DEBUG0 FBA_WCK67 AK34 FBA_WCK67# FBA_WCK67 [29] G20 FBB_DEBUG0 FBB_WCK67 C27 FBB_WCK67# FBB_WCK67 [31]
FBA_DEBUG1 FBA_WCK67_N FBA_WCK67# [29] FBB_DEBUG1 FBB_WCK67_N FBB_WCK67# [31]
2

2
THE FBA_ECKBxx ARE J30 THE FBA_ECKBxx ARE D6
@ RV344 @ RV345 USED ON GK107. NC FBA_WCKB01 J31 USED ON GK107. FBB_WCKB01 D7
60.4_0402_1% 60.4_0402_1% ON GF108 AND GF117 FBA_WCKB01_N J32 @ RV346 @ RV347 NC ON GF108 AND FBB_WCKB01_N C6
FBA_WCKB23 J33 60.4_0402_1% 60.4_0402_1% GF117 FBB_WCKB23 B6
FBA_WCKB23_N AH31 FBB_WCKB23_N F26
FBA_WCKB45 FBB_WCKB45
1

1
AJ31 E26
+1.35VSDGPU FBA_WCKB45_N +1.35VSDGPU FBB_WCKB45_N
AJ32 A26
FBA_WCKB67 AJ33 FBB_WCKB67 A27
FBA_WCKB67_N FBB_WCKB67_N

@ N16P-GX-A2 @ N16P-GX-A2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/08/08 Deciphered Date 2014/07/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
N15P (5/5)-Memory A/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS Size
ION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 27 of 71
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Lower 32 UV5

NORMAL

bits 64X32 GDDR5 MF=0 MF=1 MF=1

DQ24
MF=0

DQ0
A4 FBA_D0
FBA_EDC0 C2 A2 FBA_D1 FBA_CMD[0..31]
EDC0 EDC3 DQ25 DQ1 FBA_CMD[0..31] [27,29]
FBA_EDC1 C13 B4 FBA_D2
FBA_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D3 FBA_D[0..31]
EDC2 EDC1 DQ27 DQ3 FBA_D[0..31] [27]
FBA_EDC3 R2 E4 FBA_D4
EDC3 EDC0 DQ28 DQ4 E2 FBA_D5 FBA_DBI[0..3]
DQ29 DQ5 FBA_DBI[0..3] [27]
F4 FBA_D6
FBA_DBI0 D2 DQ30 DQ6 F2 FBA_D7 FBA_EDC[0..3]
D13 DBI0# DBI3# DQ31 DQ7 A11 FBA_EDC[0..3] [27]
D FBA_DBI1 FBA_D8 D
FBA_DBI2 P13 DBI1# DBI2# DQ16 DQ8 A13 FBA_D9
FBA_DBI3 P2 DBI2# DBI1# DQ17 DQ9 B11 FBA_D10
DBI3# DBI0# DQ18 DQ10 B13 FBA_D11
CLKA0 J12 DQ19 DQ11 E11 FBA_D12
[27] CLKA0 CK DQ20 DQ12
CLKA0# 1 DIS@ 2 CLKA0 CLKA0# J11 E13 FBA_D13
[27] CLKA0# CK# DQ21 DQ13
RV348 80.6_0402_1% FBA_CMD14 J3 F11 FBA_D14
CKE# DQ22 DQ14 F13 FBA_D15
FBA_CMD9 J5 DQ23 DQ15 U11 FBA_D16
A12/A13 DQ8 DQ16 U13 FBA_D17
FBA_CMD6 K4 DQ9 DQ17 T11 FBA_D18
FBA_CMD7 K5 A8/A7 A10/A0 DQ10 DQ18 T13 FBA_D19
FBA_CMD4 K10 A11/A6 A9/A1 DQ11 DQ19 N11 FBA_D20
FBA_CMD3 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 FBA_D21
BA2/A4 BA0/A2 DQ13 DQ21 M11 FBA_D22
FBA_CMD1 H10 DQ14 DQ22 M13 FBA_D23
FBA_CMD2 H11 BA3/A3 BA1/A5 DQ15 DQ23 U4 FBA_D24
FBA_CMD11 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2 FBA_D25
FBA_CMD10 H4 A9/A1 A11/A6 DQ1 DQ25 T4 FBA_D26
A10/A0 A8/A7 DQ2 DQ26 T2 FBA_D27
DQ3 DQ27 N4 FBA_D28
A5 DQ4 DQ28 N2 FBA_D29
U5 NC DQ5 DQ29 M4 FBA_D30
NC DQ6 DQ30 M2 FBA_D31
DQ7 DQ31
RV352 1 DIS@ 2 1K_0402_1% J1 +1.35VSDGPU
RV353 1 DIS@ 2 1K_0402_1% FBA_SEN0 J10 MF
RV354 1 DIS@ 2 121_0402_1% J13 SEN B1
ZQ VDDQ D1
VDDQ F1
FBA_CMD8 J4 VDDQ M1
FBA_CMD12 G3 ABI# VDDQ P1
FBA_CMD0 G12 RAS# CAS# VDDQ T1
C
FBA_CMD15 L3 CS# WE# VDDQ G2 C

FBA_CMD5 L12 CAS# RAS# VDDQ L2

WE# CS# VDDQ B3
VDDQ D3
VDDQ F3
FBA_WCK01# D5 VDDQ H3
[27] FBA_W CK01# WCK01# WCK23# VDDQ
FBA_WCK01 D4 K3
[27] FBA_W CK01 WCK01 WCK23 VDDQ M3
FBA_WCK23# P5 VDDQ P3
[27] FBA_W CK23# WCK23# WCK01# VDDQ
FBA_WCK23 P4 T3
[27] FBA_W CK23 WCK23 WCK01 VDDQ E5
+FBA_VREFD_L VDDQ N5
+1.35VSDGPU +FBA_VREFD_L A10 VDDQ E10
RV357 RV358 U10 VREFD VDDQ N10
1 1 VREFD VDDQ

1
931_0402_1% 549_0402_1% J14 B12
820PF_0402_50V7K
CV776

820PF_0402_50V7K

1.33K_0402_1%
2 DIS@ 1 2 DIS@ 1 CV650 VREFC VDDQ D12

RV355
VDDQ F12
RV359 RV360 DIS@ 2 DIS@ 2 VDDQ H12
931_0402_1% 549_0402_1% DIS@ FBA_CMD13 J2 VDDQ K12
RESET# VDDQ
2

2 DIS@ 1 2 DIS@ 1 M12

VDDQ P12
VDDQ T12 @ @

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
+FBA_VREFC_L +FBA_VREFC_L VDDQ G13
VDDQ 1 1 1 1 1 1 1 1 1 1 1
L13

CV652

CV655

CV656

CV657

CV658

CV800

CV799

CV802

CV801
VDDQ
1

B14

CV653

CV654
D 1 VDDQ
1

CV651 RV356 +1.35VSDGPU D14

2 QV22 820PF_0402_50V7K 1.33K_0402_1% VDDQ F14 2 2 2 2 2 2 2 2 2 2 2
[23,29,30,31] FBVREF_ALTV VDDQ M14
G L2N7002WT1G_SC-70-3 DIS@
2 G1 VDDQ P14
S DIS@ VDD VDDQ
3

L1 T14
DIS@ VDD VDDQ DIS@ DIS@
G4 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
L4 VDD
B C5 VDD A1 B
R5 VDD VSSQ C1
C10 VDD VSSQ E1
R10 VDD VSSQ N1
D11 VDD VSSQ R1
G11 VDD VSSQ U1
L11 VDD VSSQ H2
P11 VDD VSSQ K2
G14 VDD VSSQ A3
L14 VDD VSSQ C3
VDD VSSQ E3
@ VSSQ N3
10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K

VSSQ R3
1 1 1 1 1 VSSQ
H1 U3
CV659

CV662

CV663

K1 VSS VSSQ C4
CV660

CV661

B5 VSS VSSQ R4
2 2 2 2 2 G5 VSS VSSQ F5
L5 VSS VSSQ M5
T5 VSS VSSQ F10
B10 VSS VSSQ M10
DIS@ DIS@ D10 VSS VSSQ C11
DIS@ DIS@
G10 VSS VSSQ R11
L10 VSS VSSQ A12
P10 VSS VSSQ C12
T10 VSS VSSQ E12
H14 VSS VSSQ N12
K14 VSS VSSQ R12
VSS170-BALL VSSQ U12
VSSQ H13
SGRAM GDDR5 VSSQ K13
VSSQ A14
VSSQ C14
VSSQ E14
A VSSQ N14 A
VSSQ R14
VSSQ
H5GC4H24AJR-R0C VSSQ
U14
K4G41325FC-HC03 K4G41325FC-HC04_FBGA170~D
EDW4032BABG-60-F
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/08/08 Deciphered Date 2014/07/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
VRAM_GDDR5_A Lower
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
O UT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 28 of 71
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Upper 32 bits UV6

NORMAL
MF=0 MF=1 MF=1 MF=0

A4 FBA_D32 FBA_CMD[0..31]
DQ24 DQ0 FBA_CMD[0..31] [27,28]
FBA_EDC4 C2 A2 FBA_D33
FBA_EDC5 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D34 FBA_D[32..63]
EDC1 EDC2 DQ26 DQ2 FBA_D[32..63] [27]
FBA_EDC6 R13 B2 FBA_D35
FBA_EDC7 R2 EDC2 EDC1 DQ27 DQ3 E4 FBA_D36 FBA_DBI[4..7]
EDC3 EDC0 DQ28 DQ4 FBA_DBI[4..7] [27]
E2 FBA_D37
DQ29 DQ5 F4 FBA_D38 FBA_EDC[4..7]
DQ30 DQ6 FBA_EDC[4..7] [27]
FBA_DBI4 D2 F2 FBA_D39
FBA_DBI5 D13 DBI0# DBI3# DQ31 DQ7 A11 FBA_D40
D FBA_DBI6 P13 DBI1# DBI2# DQ16 DQ8 A13 FBA_D41 D
FBA_DBI7 P2 DBI2# DBI1# DQ17 DQ9 B11 FBA_D42
DBI3# DBI0# DQ18 DQ10 B13 FBA_D43
CLKA1 J12 DQ19 DQ11 E11 FBA_D44
[27] CLKA1 CK DQ20 DQ12
CLKA1# 1 DIS@ 2 CLKA1 CLKA1# J11 E13 FBA_D45
[27] CLKA1# J3 CK# DQ21 DQ13 F11
RV361 80.6_0402_1% FBA_CMD30 FBA_D46
CKE# DQ22 DQ14 F13 FBA_D47
FBA_CMD25 J5 DQ23 DQ15 U11 FBA_D48
A12/A13 DQ8 DQ16 U13 FBA_D49
FBA_CMD22 K4 DQ9 DQ17 T11 FBA_D50
FBA_CMD23 K5 A8/A7 A10/A0 DQ10 DQ18 T13 FBA_D51
FBA_CMD20 K10 A11/A6 A9/A1 DQ11 DQ19 N11 FBA_D52
FBA_CMD19 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 FBA_D53
BA2/A4 BA0/A2 DQ13 DQ21 M11 FBA_D54
FBA_CMD17 H10 DQ14 DQ22 M13 FBA_D55
FBA_CMD18 H11 BA3/A3 BA1/A5 DQ15 DQ23 U4 FBA_D56
FBA_CMD27 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2 FBA_D57
FBA_CMD26 H4 A9/A1 A11/A6 DQ1 DQ25 T4 FBA_D58
A10/A0 A8/A7 DQ2 DQ26 T2 FBA_D59
DQ3 DQ27 N4 FBA_D60
A5 DQ4 DQ28 N2 FBA_D61
U5 NC DQ5 DQ29 M4 FBA_D62
NC DQ6 DQ30 M2 FBA_D63
DQ7 DQ31
RV363 1 DIS@ 2 1K_0402_1% J1 +1.35VSDGPU
RV366 1 DIS@ 2 1K_0402_1% FBA_SEN2 J10 MF
RV365 1 DIS@ 2 121_0402_1% J13 SEN B1
ZQ VDDQ D1
VDDQ F1
FBA_CMD24 J4 VDDQ M1
FBA_CMD28 G3 ABI# VDDQ P1
FBA_CMD16 G12 RAS# CAS# VDDQ T1
FBA_CMD31 L3 CS# WE# VDDQ G2
C
FBA_CMD21 L12 CAS# RAS# VDDQ L2 C
WE# CS# VDDQ B3
VDDQ D3
VDDQ F3
FBA_WCK45# D5 VDDQ H3
[27] FBA_W CK45# WCK01# WCK23# VDDQ
FBA_WCK45 D4 K3
[27] FBA_W CK45 WCK01 WCK23 VDDQ M3
FBA_WCK67# P5 VDDQ P3
[27] FBA_W CK67# WCK23# WCK01# VDDQ
FBA_WCK67 P4 T3
[27] FBA_W CK67 WCK23 WCK01 VDDQ
+1.35VSDGPU E5
VDDQ N5
+FBA_VREFD_H +FBA_VREFD_H A10 VDDQ E10

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
U10 VREFD VDDQ N10 @ @
1 1 VREFD VDDQ 1 1 1 1 1 1 1 1 1 1 1
RV370 RV371 1 J14 B12
820PF_0402_50V7K

820PF_0402_50V7K

1.33K_0402_1%

CV677

CV680

CV681

CV682

CV683

CV804

CV803

CV806

CV805
931_0402_1% 549_0402_1% VREFC VDDQ D12
CV777

CV675

RV368

CV678

CV679
2 DIS@ 1 2 DIS@ 1 VDDQ F12
2 2 VDDQ H12 2 2 2 2 2 2 2 2 2 2 2
RV372 RV373 DIS@ DIS@ FBA_CMD29 J2 VDDQ K12
RESET# VDDQ
2

931_0402_1% 549_0402_1% M12

2 DIS@ 1 2 DIS@ 1 VDDQ P12
VDDQ DIS@ DIS@
T12 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
DIS@ VDDQ G13 DIS@
+FBA_VREFC_H +FBA_VREFC_H VDDQ L13
VDDQ B14
D VDDQ
1

1 +1.35VSDGPU D14
2 QV23 RV369 VDDQ F14
[23,28,30,31] FBVREF_ALTV VDDQ
G L2N7002WT1G_SC-70-3 CV676 1.33K_0402_1% M14
820PF_0402_50V7K G1 VDDQ P14
S
2 VDD VDDQ
3

L1 T14
DIS@ DIS@ VDD VDDQ
2

G4
DIS@ VDD
L4
C5 VDD A1
B R5 VDD VSSQ C1 B
C10 VDD VSSQ E1
R10 VDD VSSQ N1
D11 VDD VSSQ R1
G11 VDD VSSQ U1
L11 VDD VSSQ H2
P11 VDD VSSQ K2
G14 VDD VSSQ A3
L14 VDD VSSQ C3
VDD VSSQ E3
VSSQ N3
10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K

@ VSSQ R3
1 1 1 1 1 VSSQ
H1 U3
CV684

CV687

CV688

K1 VSS VSSQ C4
CV685

CV686

B5 VSS VSSQ R4
2 2 2 2 2 G5 VSS VSSQ F5
L5 VSS VSSQ M5
T5 VSS VSSQ F10
B10 VSS VSSQ M10
DIS@ DIS@ VSS VSSQ
DIS@ DIS@ D10 C11
G10 VSS VSSQ R11
L10 VSS VSSQ A12
P10 VSS VSSQ C12
T10 VSS VSSQ E12
H14 VSS VSSQ N12
K14 VSS VSSQ R12
VSS170-BALL VSSQ U12
VSSQ H13
SGRAM GDDR5 VSSQ K13
VSSQ A14
VSSQ C14
VSSQ E14
VSSQ N14
A VSSQ R14 A
VSSQ U14
VSSQ
K4G41325FC-HC04_FBGA170~D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/08/08 Deciphered Date 2014/07/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
VRAM_GDDR5_A Upper
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
O UT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 29 of 71
5 4 3 2 1
 5 4 3 2 1

Memory Partition B - Lower 32 UV9

NORMAL

bits 64X32 GDDR5 MF=0 MF=1 MF=1

DQ24
MF=0

DQ0
A4 FBB_D0 FBB_CMD[0..31]
FBB_CMD[0..31] [27,31]
FBB_EDC0 C2 A2 FBB_D1
FBB_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBB_D2 FBB_D[0..31]
R13 EDC1 EDC2 DQ26 DQ2 B2 FBB_D[0..31] [27]
FBB_EDC2 FBB_D3
FBB_EDC3 R2 EDC2 EDC1 DQ27 DQ3 E4 FBB_D4
EDC3 EDC0 DQ28 DQ4 E2 FBB_D5 FBB_DBI[0..3]
DQ29 DQ5 F4 FBB_D6 FBB_DBI[0..3] [27]
FBB_DBI0 D2 DQ30 DQ6 F2 FBB_D7
FBB_DBI1 D13 DBI0# DBI3# DQ31 DQ7 A11 FBB_D8
D FBB_DBI2 P13 DBI1# DBI2# DQ16 DQ8 A13 FBB_D9 FBB_EDC[0..3] D
FBB_DBI3 P2 DBI2# DBI1# DQ17 DQ9 B11 FBB_D10 FBB_EDC[0..3] [27]
DBI3# DBI0# DQ18 DQ10 B13 FBB_D11
CLKB0 J12 DQ19 DQ11 E11 FBB_D12
CLKB0# 1 DIS@ 2 CLKB0 [27] CLKB0 CLKB0# J11 CK DQ20 DQ12 E13 FBB_D13
[27] CLKB0# J3 CK# DQ21 DQ13 F11
RV374 80.6_0402_1% FBB_CMD14 FBB_D14
CKE# DQ22 DQ14 F13 FBB_D15
FBB_CMD9 J5 DQ23 DQ15 U11 FBB_D16
A12/A13 DQ8 DQ16 U13 FBB_D17
FBB_CMD6 K4 DQ9 DQ17 T11 FBB_D18
FBB_CMD7 K5 A8/A7 A10/A0 DQ10 DQ18 T13 FBB_D19
FBB_CMD4 K10 A11/A6 A9/A1 DQ11 DQ19 N11 FBB_D20
FBB_CMD3 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 FBB_D21
BA2/A4 BA0/A2 DQ13 DQ21 M11 FBB_D22
FBB_CMD1 H10 DQ14 DQ22 M13 FBB_D23
FBB_CMD2 H11 BA3/A3 BA1/A5 DQ15 DQ23 U4 FBB_D24
FBB_CMD11 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2 FBB_D25
FBB_CMD10 H4 A9/A1 A11/A6 DQ1 DQ25 T4 FBB_D26
A10/A0 A8/A7 DQ2 DQ26 T2 FBB_D27
DQ3 DQ27 N4 FBB_D28
A5 DQ4 DQ28 N2 FBB_D29
U5 NC DQ5 DQ29 M4 FBB_D30
NC DQ6 DQ30 M2 FBB_D31
DQ7 DQ31
RV378 1 DIS@ 2 1K_0402_1% J1 +1.35VSDGPU
RV379 1 DIS@ 2 1K_0402_1% FBB_SEN0 J10 MF
RV380 1 DIS@ 2 121_0402_1% J13 SEN B1
ZQ VDDQ D1
VDDQ F1
FBB_CMD8 J4 VDDQ M1
FBB_CMD12 G3 ABI# VDDQ P1
FBB_CMD0 G12 RAS# CAS# VDDQ T1
C FBB_CMD15 L3 CS# WE# VDDQ G2 C
FBB_CMD5 L12 CAS# RAS# VDDQ L2
WE# CS# VDDQ B3
VDDQ D3
VDDQ F3
FBB_WCK01# D5 VDDQ H3
[27] FBB_WCK01# FBB_WCK01 D4 WCK01# WCK23# VDDQ K3
[27] FBB_WCK01 WCK01 WCK23 VDDQ M3
FBB_WCK23# P5 VDDQ P3
[27] FBB_WCK23# FBB_WCK23 P4 WCK23# WCK01# VDDQ T3
[27] FBB_WCK23 WCK23 WCK01 VDDQ E5
VDDQ N5
+FBB_VREFD_L +1.35VSDGPU +FBB_VREFD_L A10 VDDQ E10
RV383 RV384 U10 VREFD VDDQ N10
1 1 VREFD VDDQ

1
931_0402_1% 549_0402_1% J14 B12
820PF_0402_50V7K
CV778

820PF_0402_50V7K
CV700

1.33K_0402_1%
2 DIS@ 1 2 DIS@ 1 VREFC VDDQ D12

RV381
VDDQ F12
RV385 RV386 DIS@ 2 DIS@ 2 DIS@ VDDQ H12
931_0402_1% 549_0402_1% FBB_CMD13 J2 VDDQ K12
RESET# VDDQ
2

2 DIS@ 1 2 DIS@ 1 M12

VDDQ P12
VDDQ T12 @ @

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
+FBB_VREFC_L +FBB_VREFC_L VDDQ G13
VDDQ 1 1 1 1 1 1 1 1 1 1 1
L13

CV702

CV705

CV706

CV707

CV708

CV808

CV807

CV810

CV809
D 1 VDDQ
1

B14

CV703

CV704
2 QV24 CV701 RV382 +1.35VSDGPU VDDQ D14
[23,28,29,31] FBVREF_ALTV VDDQ F14 2 2 2 2 2 2 2 2 2 2 2
G L2N7002WT1G_SC-70-3 820PF_0402_50V7K 1.33K_0402_1%
2 DIS@ VDDQ M14
S DIS@ VDDQ
3

G1 P14
DIS@ VDD VDDQ
2

L1 T14
G4 VDD VDDQ DIS@ DIS@
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
L4 VDD
B C5 VDD A1 B
R5 VDD VSSQ C1
C10 VDD VSSQ E1
R10 VDD VSSQ N1
D11 VDD VSSQ R1
G11 VDD VSSQ U1
L11 VDD VSSQ H2
P11 VDD VSSQ K2
G14 VDD VSSQ A3
L14 VDD VSSQ C3
VDD VSSQ E3
VSSQ N3
10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K

@ VSSQ R3
1 1 1 1 1 VSSQ
H1 U3
CV709

CV712

CV713

K1 VSS VSSQ C4
CV710

CV711

B5 VSS VSSQ R4
2 2 2 2 2 G5 VSS VSSQ F5
L5 VSS VSSQ M5
T5 VSS VSSQ F10
B10 VSS VSSQ M10
DIS@ DIS@ D10 VSS VSSQ C11
DIS@ DIS@
G10 VSS VSSQ R11
L10 VSS VSSQ A12
P10 VSS VSSQ C12
T10 VSS VSSQ E12
H14 VSS VSSQ N12
K14 VSS VSSQ R12
VSS170-BALL VSSQ U12
VSSQ H13
SGRAM GDDR5 VSSQ K13
VSSQ A14
VSSQ C14
A VSSQ E14 A
VSSQ N14
VSSQ R14
VSSQ U14
VSSQ
K4G41325FC-HC04_FBGA170~D

@Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/08/08 Deciphered Date 2014/07/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
VRAM_GDDR5_B Lower
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS Size
ION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 30 of 71
5 4 3 2 1
 5 4 3 2 1

Memory Partition B - Upper 32 bits UV10

MF=0
NORMAL
MF=1 MF=1 MF=0

A4 FBB_D32
FBB_EDC4 C2 DQ24 DQ0 A2 FBB_D33 FBB_CMD[0..31]
C13 EDC0 EDC3 DQ25 DQ1 B4 FBB_CMD[0..31] [27,30]
FBB_EDC5 FBB_D34
FBB_EDC6 R13 EDC1 EDC2 DQ26 DQ2 B2 FBB_D35 FBB_D[32..63]
EDC2 EDC1 DQ27 DQ3 FBB_D[32..63] [27]
FBB_EDC7 R2 E4 FBB_D36
EDC3 EDC0 DQ28 DQ4 E2 FBB_D37 FBB_DBI[4..7]
DQ29 DQ5 FBB_DBI[4..7] [27]
F4 FBB_D38
FBB_DBI4 D2 DQ30 DQ6 F2 FBB_D39 FBB_EDC[4..7]
DBI0# DBI3# DQ31 DQ7 FBB_EDC[4..7] [27]
FBB_DBI5 D13 A11 FBB_D40
FBB_DBI6 P13 DBI1# DBI2# DQ16 DQ8 A13 FBB_D41
D FBB_DBI7 P2 DBI2# DBI1# DQ17 DQ9 B11 FBB_D42 D
DBI3# DBI0# DQ18 DQ10 B13 FBB_D43
CLKB1 J12 DQ19 DQ11 E11 FBB_D44
[27] CLKB1 CK DQ20 DQ12
CLKB1# 1 DIS@ 2 CLKB1 CLKB1# J11 E13 FBB_D45
[27] CLKB1# CK# DQ21 DQ13
RV387 80.6_0402_1% FBB_CMD30 J3 F11 FBB_D46
CKE# DQ22 DQ14 F13 FBB_D47
FBB_CMD25 J5 DQ23 DQ15 U11 FBB_D48
A12/A13 DQ8 DQ16 U13 FBB_D49
FBB_CMD22 K4 DQ9 DQ17 T11 FBB_D50
FBB_CMD23 K5 A8/A7 A10/A0 DQ10 DQ18 T13 FBB_D51
FBB_CMD20 K10 A11/A6 A9/A1 DQ11 DQ19 N11 FBB_D52
FBB_CMD19 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 FBB_D53
BA2/A4 BA0/A2 DQ13 DQ21 M11 FBB_D54
FBB_CMD17 H10 DQ14 DQ22 M13 FBB_D55
FBB_CMD18 H11 BA3/A3 BA1/A5 DQ15 DQ23 U4 FBB_D56
FBB_CMD27 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2 FBB_D57
FBB_CMD26 H4 A9/A1 A11/A6 DQ1 DQ25 T4 FBB_D58
A10/A0 A8/A7 DQ2 DQ26 T2 FBB_D59
DQ3 DQ27 N4 FBB_D60
A5 DQ4 DQ28 N2 FBB_D61
U5 NC DQ5 DQ29 M4 FBB_D62
NC DQ6 DQ30 M2 FBB_D63
DQ7 DQ31
RV389 1 DIS@ 2 1K_0402_1% J1 +1.35VSDGPU
RV392 1 DIS@ 2 1K_0402_1% FBB_SEN2 J10 MF
RV391 1 DIS@ 2 121_0402_1% J13 SEN B1
ZQ VDDQ D1
VDDQ F1
FBB_CMD24 J4 VDDQ M1
FBB_CMD28 G3 ABI# VDDQ P1
FBB_CMD16 G12 RAS# CAS# VDDQ T1
FBB_CMD31 L3 CS# WE# VDDQ G2
C FBB_CMD21 L12 CAS# RAS# VDDQ L2 C
WE# CS# VDDQ B3
VDDQ D3
VDDQ F3
FBB_WCK45# D5 VDDQ H3
[27] FBB_WCK45# FBB_WCK45 D4 WCK01# WCK23# VDDQ K3
[27] FBB_WCK45 WCK01 WCK23 VDDQ M3
FBB_WCK67# P5 VDDQ P3
[27] FBB_WCK67# P4 WCK23# WCK01# VDDQ T3
FBB_WCK67
[27] FBB_WCK67 WCK23 WCK01 VDDQ E5
VDDQ N5
+FBB_VREFD_H +1.35VSDGPU +FBB_VREFD_H A10 VDDQ E10

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
U10 VREFD VDDQ N10 @ @
VREFD VDDQ 1 1 1 1 1 1 1 1 1 1 1

1
RV396 RV397 J14 B12
820PF_0402_50V7K

820PF_0402_50V7K

1.33K_0402_1%

CV727

CV730

CV731

CV732

CV733

CV812

CV811

CV814

CV813
1 1 VREFC VDDQ
931_0402_1% 549_0402_1% D12

CV728

CV729
2 DIS@ 1 2 DIS@ 1 VDDQ F12
CV789

CV725

RV394
VDDQ H12 2 2 2 2 2 2 2 2 2 2 2
RV398 RV399 2 2 FBB_CMD29 J2 VDDQ K12
RESET# VDDQ
2

931_0402_1% 549_0402_1% M12

2 DIS@ 1 2 DIS@ 1 VDDQ P12
VDDQ T12 DIS@ DIS@
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
DIS@ VDDQ G13
+FBB_VREFC_H VDDQ L13
DIS@ DIS@
+FBB_VREFC_H VDDQ B14
+1.35VSDGPU VDDQ D14
VDDQ
1

1 F14
VDDQ M14
D VDDQ
1

CV726 RV395 G1 P14

2 QV25 820PF_0402_50V7K 1.33K_0402_1% L1 VDD VDDQ T14
[23,28,29,30] FBVREF_ALTV 2 VDD VDDQ
G L2N7002WT1G_SC-70-3 DIS@ G4
DIS@ VDD
2

S L4
VDD
3

C5 A1
B DIS@ R5 VDD VSSQ C1 B
C10 VDD VSSQ E1
R10 VDD VSSQ N1
D11 VDD VSSQ R1
G11 VDD VSSQ U1
L11 VDD VSSQ H2
P11 VDD VSSQ K2
G14 VDD VSSQ A3
L14 VDD VSSQ C3
VDD VSSQ E3
@ VSSQ N3
10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K

VSSQ R3
1 1 1 1 1 VSSQ
H1 U3
CV734

CV737

CV738

K1 VSS VSSQ C4
CV735

CV736

B5 VSS VSSQ R4
2 2 2 2 2 G5 VSS VSSQ F5
L5 VSS VSSQ M5
T5 VSS VSSQ F10
B10 VSS VSSQ M10
DIS@ DIS@ VSS VSSQ
DIS@ DIS@ D10 C11
G10 VSS VSSQ R11
L10 VSS VSSQ A12
P10 VSS VSSQ C12
T10 VSS VSSQ E12
H14 VSS VSSQ N12
K14 VSS VSSQ R12
VSS170-BALL VSSQ U12
VSSQ H13
SGRAM GDDR5 VSSQ K13
VSSQ A14
VSSQ C14
VSSQ E14
A VSSQ N14 A
VSSQ R14
VSSQ U14
VSSQ
K4G41325FC-HC04_FBGA170~D

@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/08/08 Deciphered Date 2014/07/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
VRAM_GDDR5_B Upper
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
O UT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 31 of 71
5 4 3 2 1
 5 4 3 2 1

+3.3V_GFX_RUN +3VALW to +3.3V_GFX_AON

+3VS +5VALW +3VS QV86 DIS@ +3.3V_GFX_AON

X06.31 +3.3V_GFX_RUN DMG2301U-7_SOT23-3 X06.31
RV511
UZ17 RZ69 0_0805_5%

1
D 0_0805_5% 3 1 1 2 D

100K_0402_5%

D
1 8 1 2 @

RV181
2 VIN VOUT 7 @ DIS@

0.1U_0402_25V6
VIN VOUT

G
2

1
3 6 CZ95 1 2

CV363
[23,62,63] 3V3_MAIN_EN EN CT

2
@ DIS@
4 5 2200P_0402_25V7K DGPU_PWR_EN#
+5VALW VBIAS GND

2
9
GND

L2N7002WT1G_SC-70-3
APE8937GN2_DFN8_2X2 D

1
DIS@ 2

QV87
[20] DGPU_PWR_EN
G
S

3
DIS@

C +3.3V_GFX_RUN GPU Power Up Power Rail Sequence GPU Power Up Sub-system Sequence C

T1
T8
Driver call
0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

4.7U_0603_6.3V6K

1 1 1 1
CV792

CV793

CV795

CV797

to enable GPU
+3V_GPU
2 2 2 2
Power EN
+GPU_CORE
NV3V3Pgood
DIS@ DIS@
DIS@
DIS@
+1.05V_GPU 27Mhz

+3.3V_GFX_AON GPU all PG T1 Custom

+1.35V_GPU T2 >0
T3 >0
The ramp time for any rail must be more than 40us. CLK REQ# T4 >0
0.1U_0402_10V7K

1U_0402_6.3V6K

4.7U_0603_6.3V6K

1 1 1 T5 >100us
CV794

CV796

CV798

100MHz T6 >0
T7 <48ms
2 2 2 T8 500ms
GPU Power Down Sequence GPU Reset# T9 >0

DIS@
DIS@ First rail to power down PCIe Training
DIS@
B B

Toff < 10ms T9 T2 T3 T4 T5 T6 T7

Last rail to power down
GPU Power Down Sub-system Sequence
Under GPU Near GPU T1
T7
GPU Disable call

Link tear

Discharge down
GPU Reset#

Power EN
+3VALW +1.35VSDGPU T1 Custom
27Mhz T2 >0
+1.05VSDGPU +GPU_CORE +3.3V_GFX_AON T3 >0
1

T4 <=0
RZ12 RZ8 100MHz T5 >=0
1

100K_0402_5% 10_0402_1%
DIS@ DIS@ RZ9 RZ10 RZ11 T6 Custom
1_0402_5% 1_0402_5% 100_0603_5% NV3V3Pgood T7 Custom
2

DIS@ DIS@ DIS@

2

A A
Call Return
QZ6B DIS@ QZ6A DIS@ QZ7A DIS@
3

DMN65D8LDW-7_SOT363-6 DMN65D8LDW-7_SOT363-6 QZ8 DIS@ DMN65D8LDW-7_SOT363-6

D
1

L2N7002WT1G_SC-70-3 DMN65D8LDW-7_SOT363-6
DGPU_PWR_EN# 2 QZ7B DIS@ T2 T3 T4 T5 T6
5 2 G 2 5
[23,60] FBVDD_EN
S Security Classification Compal Secret Data Compal Electronics, Inc.
3
4

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
GPU DC/DC interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS Size
ION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 32 of 71
5 4 3 2 1
 A B C D E

+5VALW to +5VS X06.18 WLAN Load Switch

+3VALW to +3VS RZ13 1495mA +3VALW
X06.18 +3VS_WLAN
UZ1 0_0603_5%
1 14 1 2 UN3 RN34
+5VALW VIN1 VOUT1 +5VS +5VALW
2 13 @ 0_0603_5%
VIN1 VOUT1 1 8 1 2
RUN_ON_EC 3 12 CZ4 1 2 470P_0603_50V7K 2 VIN VOUT 7 @
[34,48] RUN_ON_EC ON1 CT1 VIN VOUT

+5VALW 4 11 NGFF_ON 3 6 1 2
VBIAS GND EN CT @
RUN_ON_EC 5 10 CZ6 1 2 470P_0603_50V7K 4 5 CN22
ON2 CT2 VBIAS GND 9 2200P_0402_25V7K
6 9 1 @ 2 GND
+3VALW VIN2 VOUT2 +3VS
7 8 DN3 APE8937GN2_DFN8_2X2
VIN2 VOUT2 0_0603_5% 2041mA [20] NGFF_PWREN
2
15 RZ15
1 GPAD 1 NGFF_ON 1

RZ43 1 2 100K_0402_5% RUN_ON_EC EM5209VF_DFN14_3X2 X06.18

[48] AUX_EN_WOWL 3
RN33 1 2 100K_0402_5% NGFF_ON
BAT54CW-7-F_SOT323-3~D

Close UZ4 Close UZ4

+5VALW +3VALW +5VS +3VS

1 1 1 1
@ CZ11 @ CZ12 CZ8 CZ9 +3VALW to +3V_PCH
1U_0603_10V6K 1U_0603_10V6K 10U_0603_6.3V6M 10U_0603_6.3V6M
2 2 2 2

+3VALW X06.18 +3V_PCH +3V_PCH

CZ18 UZ4 RZ18
1U_0402_6.3V6K 0_0603_5%
2 1 1 8 1 2 1
VIN VOUT
Touch Screen Load Switch & Card Reader
2 7 @
VIN VOUT CZ19
PCH_ALW_ON 3 6 1 2 0.1U_0402_10V7K
[34,48,58] PCH_ALW_ON EN CT 2
+5VALW 4 5 2200P_0402_25V7K
VBIAS GND 9 CZ20
GND
+3VALW X06.18 +3VS_TS +3VS_TS
APE8937GN2_DFN8_2X2
CZ26 UZ5 RZ26
1U_0402_6.3V6K 0_0603_5%
2 1 1 8 1 2 1
2 VIN VOUT 7 @
VIN VOUT CZ29
3.3V_TS_EN 3 6 1 2 0.1U_0402_10V7K
[20] 3.3V_TS_EN EN CT 2
2 2
4 5 2200P_0402_25V7K
+5VALW VBIAS GND 9 CZ31
GND
RZ46 1 2 100K_0402_5% PCH_ALW_ON
APE8937GN2_DFN8_2X2
RZ39 2 1 100K_0402_5% 3.3V_TS_EN

HDD, SSD Load Switch

X06.18
+3VS RZ28 +3VS_CR X06.18
0_0603_5%
1 2 RZ34 +5VS_HDD +5VS_HDD
@ UZ7 0_0805_5%
+5VALW 1 14 1 2
2 VIN1 VOUT1 13 @
VIN1 VOUT1 1
RUN_ON_EC 3 12 CZ37 1 2 470P_0603_50V7K CZ45
ON1 CT1
0.1U_0402_10V7K
2
eDP & Camera Load Switch +5VALW 4 11
VBIAS GND +3.3VDX_SSD
RUN_ON_EC RZ76 1 @ 2 0_0402_5% 5 10 CZ39 1 2 470P_0603_50V7K
X06.18 ON2 CT2
+3VALW X06.18 [16] SSD_PWR_EN SSD_PWR_EN RZ75 1 @ 2 0_0402_5% 6 9 1 @ 2 +3.3VDX_SSD
+EDPVDD 7 VIN2 VOUT2 8
+EDPVDD +3VALW VIN2 VOUT2
RZ35 0_0805_5%
UZ8 0_0603_5% 15 RZ36 1
5 1 1 2 GPAD
IN OUT @ 1 EM5209VF_DFN14_3X2 X06.18 CZ46
2 SSD_PWR_EN RZ74 1 @ 2 100K_0402_5% 0.1U_0402_10V7K
3 GND CZ41 2 3
ENVDD 4 3 0.1U_0402_10V7K
EN OC 2

SY6288C20AAC_SOT23-5

DV7
BAT54CW-7-F_SOT323-3~D
2
[48] LCD_VCC_TEST_EN
1 ENVDD ENVDD RZ40 1 2 100K_0402_5% +VCCST Load Switch
3
[16,48] ENVDD_PCH

+VCCST
+1VALW

UZ15
1
2 VIN1 RZ66
VIN2 0_0603_5%
+5VALW
Alpine Ridge(TBT) Load Switch
7 6 1 2
VIN thermal VOUT @
1
3
1
VBIAS CZ28 X06.18

1U_0402_6.3V6K

0.1U_0402_25V6
1
4 5 0.1U_0402_10V7K

CZ96

@ CZ97
ON GND 2
+3VALW
2

2
TPS22961DNYR_WSON8

+3V_TBT_PWR
4.4mohm/6A
+3VA_TBT TR=12.5us@Vin=1.05V
UT3
[34] SUS_ON_EC_ST
4 +3V_TBT_PWR 4
1 8
2 VIN VOUT 7 RT114 1 @ 2 0.01_0603_1%
10U_0603_6.3V6M

VIN VOUT
10U_0603_6.3V6M

[34,48] SUS_ON_EC RT240 1 @ 2 0_0402_5% 3 6 1

EN CT
470P_0402_50V7K

CT105

1 1
4 5
CT162

X06.18 +5VALW VBIAS GND 9

GND 2
CT106

2 2
APE8937GN2_DFN8_2X2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
SYS DC/DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C. LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 33 of 71

A B C D E
 5 4 3 2 1

+3V_PCH
DDR4 VPP Load Switch +5VALW

5
UZ20
X06.18
X06.18

VCC
[33,48] RUN_ON_EC 1
IN1 4 RZ58 1 @ 2 0_0402_5% RZ53
OUT

1
[18,37,48,52] SIO_SLP_S3# SIO_SLP_S3# 2 0_0603_5% UZ10

GND
IN2 1 2 +2.5VS_G9141 5 1 CZ54
+2.5V_MEM OUT IN
@ 1U_0603_10V6K

2
+3V_PCH

1
2
GND

3
MC74VHC1G08DFT2G_SC70-5 RZ54
30.1K_0402_1% 4 3

@
D SET SHDN D

5
UZ11

1
G9090-250T11U_SOT23-5

VCC

1 2
1 CZ53 VSET
IN1 4 RUN_ON_P 1U_0603_10V6K
OUT RUN_ON_P [59,61]

2
[18,42,52] SIO_SLP_S0# SIO_SLP_S0# RZ59 1 @ 2 0_0402_5% 2 RZ52

GND
IN2

1
19.6K_0402_1%

@
RZ50

1
100K_0402_5%

2
RZ85 MC74VHC1G08DFT2G_SC70-5 SUS_ON_EC_P
100K_0402_5% @ @

2
2
+3V_PCH
5

UZ21
X06.18
VCC

1
[48] IMVP_VR_ON IN1 4 RZ60 1 @ 2 0_0402_5%
SIO_SLP_S3# 2 OUT +VCCSTG
GND

IN2

+3V_PCH
+VCCSTG Load Switch
3

MC74VHC1G08DFT2G_SC70-5
+1VALW X06.18

1
UZ12
UZ9 RZ48

VCC
1 1 @ 0_0603_5%
IN1 4 2 VIN1
OUT VR_ON [64] VIN2
SIO_SLP_S0# RZ61 1 @ 2 0_0402_5% 2

GND
IN2

2
+5VALW

1
7 6 1 2
VIN thermal VOUT
1

RZ71 @ CZ82 0.1U_0402_10V7K

RZ86 100K_0402_5% 3
VBIAS
3
100K_0402_5% @ MC74VHC1G08DFT2G_SC70-5 1

1
4 5

1U_0402_6.3V6K

0.1U_0402_10V7K
@ CZ86
C @ C
ON GND

CZ88
2

2
TPS22961DNYR_WSON8
+VCCSTG
4.4mohm/6A
TR=12.5us@Vin=1.05V
1
CZ47
0.1U_0402_10V7K
2

RUN_ON_P

RZ91 1 @ 2 0_0402_5%
X06.18
X06.03
+3VALW
SUS_ON_EC_P
SUS_ON_EC_P [59]
5

UZ23
+3VALW
VCC

1
IN1 4
OUT SUS_ON_EC_ST [33]
5

UZ22 2
[33,48,58] PCH_ALW_ON
GND

IN2
+VCCPLL_OC Load Switch
VCC

1
[33,48] SUS_ON_EC IN1
1

4
OUT
3

[18,48,52] SIO_SLP_S4# 2 MC74VHC1G08DFT2G_SC70-5 RZ88

GND

IN2 @ @ 100K_0402_5%
B B
3

MC74VHC1G08DFT2G_SC70-5
+3VALW
+1.2V_DDR
X06.18
X06.18 +1.2V_VCCPLL_OC
+5VALW UZ16 RZ67
0_0603_5%
5

UZ18 RUN_ON_P RZ90 1 @ 2 0_0402_5% 1 8 1 2

DZ1 2 VIN VOUT 7 @
VCC

SIO_SLP_S0# 2 1 VIN VOUT

IN1 4 SUS_ON_P SUS_ON_P RZ72 1 @ 2 0_0402_5% 3 6 CZ57 1 2 +1.2V_VCCPLL_OC
1 2 OUT EN CT @
GND

IN2
1

4 5 2200P_0402_25V7K
VBIAS GND
1

3 RZ80 9 1
[18,48,52] SIO_SLP_S5# GND
RZ87 @ 100K_0402_5%
3

100K_0402_5% MC74VHC1G08DFT2G_SC70-5 APE8937GN2_DFN8_2X2 CZ49

BAT54AW-7-F_SOT323-3 @ 0.1U_0402_10V7K
2
2

@
2

X06.02
RZ89 1 2 0_0402_5%
@
X06.04

+3V_PCH

RZ82 1 @ 2 0_0402_5%
1

RZ84 +3V_PCH
100K_0402_5%
A A
2

UZ19
1
[48] H_VCCST_PWRGD_EC
G VCC

B 4
Y H_VCCST_PW RGD [6,9]
SIO_SLP_S3# RZ81 1 @ 2 0_0402_5% 2
A
X06.18 MC74VHC1G09DFT2G_SC70-5
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
EC ENE-KB9012/ KC3810
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C. LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 34 of 71

5 4 3 2 1
 5 4 3 2 1

LCD backlight PWR CTRL eDP & TS Conn.

+EDPVDD
B+ +INV_PWR_SRC

60mil

10U_0603_6.3V6M
DV1
QV11 2
[49] PANEL_BKEN_EC 1 1
SI3457BDV-T1-E3_TSOP6~D

CV157
1 DISPOFF# CV156
60mil

D
6 8.2P_0402_50V8D @

S
2 2

1
4 5 [16] PANEL_BKEN_PCH 3
2 RV107
1 BAT54CW-7-F_SOT323-3~D 10K_0402_5%

G
1
RV119 1
D D

2
CV168 1M_0402_5%
1U_0603_25V6 CV169 DV2

2
0.1U_0402_25V6 [7,16] BIA_PWM_PCH 2
2

2
1 INV_PWM

1
[48] BIA_PWM_EC 3

RV120 BAT54CW-7-F_SOT323-3~D RV109

100K_0402_5% 100K_0402_5%
RV135 2 1 220K_0402_5% EN_INVPWR

2
JEDP1
D

1
40 41
+INV_PWR_SRC CONNTST MGND1
[48] EN_INVPWR EN_INVPWR 2 QV12 W=60mils 39 42
G L2N7002WT1G_SC-70-3 38 LCD_VDD MGND2 43
37 LCD_VDD MGND3 44
S V_EDID MGND4

3
[48] LCD_TST RV110 1 @ 2 0_0402_5% 36 45
35 BIST MGND5 46
34 EDID_CLK MGND6
X06.21 33 EDID_DATA
+3VS_CAM USB20_P12_R 32 LVDS_A0-
USB20_N12_R 31 LVDS_A0+
30 LVDS_A1-
RV520 1 2 0_0402_5% EDP_TXP0_R 29 LVDS_A1+
[16] CAM_CBL_DET# LVDS_A2-
@ 28
27 LVDS_A2+
CV158 1 2 0.1U_0402_10V7K EDP_TXP0_C EDP_PANEL_DAT 26 GND
[7] EDP_TXP0 LVDS_A_CLK-
INV_PWM 25

CCD Conn.
DISPOFF# 24 LVDS_A_CLK+
CV159 1 2 0.1U_0402_10V7K EDP_TXN0_C EDP_HPD_S 23 GND
+3VS_CAM [7] EDP_TXN0 LVDS_B0-
22
21 LVDS_B0+
+EDPVDD LVDS_B1-
RV521 1 2 0_0402_5% EDP_TXN0_R W=60mils 20
DV12 @ 19 LVDS_B1+
USB20_P12_R 1 6 EDP_PANEL_CLK 18 LVDS_B2-
1 1 1 V I/O V I/O LVDS_B2+
@ RV522 1 2 0_0402_5% EDP_TXP1_R 17
CV183 CV184 CV185 2 5 @ EDP_AUXP_R 16 GND
Ground V BUS +3VS LCD_B_CLK-
.1U_0402_16V7K 8.2P_0402_50V8D 10U_0603_6.3V6M EDP_AUXN_R 15
2 2 2 USB20_N12_R 3 4 CV160 1 2 0.1U_0402_10V7K EDP_TXP1_C 14 LCD_B_CLK+
V I/O V I/O [7] EDP_TXP1 VR_GND
EDP_TXP0_R 13
IP4223CZ6_SO6-6 EDP_TXN0_R 12 VR_GND
CV161 1 2 0.1U_0402_10V7K EDP_TXN1_C 11 VR_GND
EMC@ [7] EDP_TXN1 CONNTST_GND
EDP_TXP1_R 10
EDP_TXN1_R 9 PWM
RV523 1 2 0_0402_5% EDP_TXN1_R 8 DISP_ON/OFF#
@ EDP_TXP2_R 7 NC
EDP_TXN2_R 6 VR_SRC
RV524 1 2 0_0402_5% EDP_TXP2_R 5 VR_SRC
C QZ9 @ EDP_TXP3_R 4 VR_SRC C
+3VS DMG2301U-7_SOT23-3 +3VS_CAM +3VS_CAM EDP_TXN3_R 3 BREATH_WHITE_LED
EMC@ BATT_YELLOW_LED
RZ37 [7] EDP_TXP2 CV162 1 2 0.1U_0402_10V7K EDP_TXP2_C 2
MCM1012B900F06BP_4P 0_0603_5% 1 BATT_WHITE_LED
USB20_P12 4 3 USB20_P12_R 3 1 1 2 GND
S

[19] USB20_P12 1
@ [7] EDP_TXN2 CV163 1 2 0.1U_0402_10V7K EDP_TXN2_C
1 CZ44 ACES_59003-04006-001
USB20_N12 1 2 USB20_N12_R 1U_0402_6.3V6K CONN@
G

[19] USB20_N12 X06.21 2

2

CZ43 RV525 1 2 0_0402_5% EDP_TXN2_R

LV22 0.1U_0402_10V7K @
2

X06.21 3.3V_CAM_EN# RV526 1 2 0_0402_5% EDP_TXP3_R

3.3V_CAM_EN# [19]
@
+3VS CV164 1 2 0.1U_0402_10V7K EDP_TXP3_C +5VS
[7] EDP_TXP3

3.3V_CAM_EN# RZ38 1 @ 2 100K_0402_5% [7] EDP_TXN3 CV165 1 2 0.1U_0402_10V7K EDP_TXN3_C

2
G
RV527 1 2 0_0402_5% EDP_TXN3_R
@ 3 1

D
@
QV9
RV528 1 2 0_0402_5% EDP_AUXN_R L2N7002WT1G_SC-70-3
@

[7] EDP_AUXN CV166 1 2 0.1U_0402_10V7K EDP_AUXN_C

[16] EDP_HPD RV113 1 @ 2 0_0402_5% EDP_HPD_S

1
CV167 1 2 0.1U_0402_10V7K EDP_AUXP_C
[7] EDP_AUXP X06.21
RV114
RV529 1 2 0_0402_5% EDP_AUXP_R 100K_0402_5%
@

2
X06.21

B B

+EDPVDD

X06.21

1
0_0402_5%

1
RV547
@ RV546 RV545
2.2K_0402_5% @ @ 2.2K_0402_5%

2
UV17

2
1 8 RV549
NC VCC 0_0402_5%
[39,48] DOCK_TNY_SMB_CLK 2 7 EDP_PANEL_CLK 1 @ 2 EDP_PANEL_CLK_PCH [20]
SCL0 SCL1

Touch Screen Conn.

3 6 EDP_PANEL_DAT 1 2
[39,48] DOCK_TNY_SMB_DAT SDA0 SDA1 EDP_PANEL_DAT_PCH [20]
@
4 5 EDP_CTRL_EN_C [48] RV548
GND EN 0_0402_5%
CONN@
PCA9515BDGKR_VSSOP8
ACES_50208-00601-P01
8
7 GND X06.01
6 GND
USB20_P9_R 5 6
+3VS_TS USB20_N9_R 4 5
3 4
1 2 2 3
[17] TOUCH_SCREEN_PD# 2
DI1 RB751S40T1G_SOD523-2 1
1
JTS

USB20_P9_R

USB20_N9_R

EMC@
MCM1012B900F06BP_4P
2

[19] USB20_P9 4 3 USB20_P9_R

DI3 @
AZ5125-02S.R7G_SOT23-3

A 1 2 USB20_N9_R A
[19] USB20_N9
LI1

X06.21
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
eDP /TS conn.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
O UT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C. LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 35 of 71

5 4 3 2 1
 5 4 3 2 1

HDMI Active Level Shift(ALS type) Place between ESD and CM-Choke Place close to JHDMI1

TMDS_L_TXCN
1014: Steg change to 0201 package.

1
TMDS_TXCN RV530 1 EMC@ 2 8.2_0402_1% TMDS_L_TXCN
CV170 2 1 0.1U_0201_6.3V6K TMDS_TXCN RV538
[37] TBT_ML3_N
CV171 2 1 0.1U_0201_6.3V6K TMDS_TXCP 150_0402_5%
[37] TBT_ML3_P
EMC@ TMDS_TXCP RV531 1 EMC@ 2 8.2_0402_1% TMDS_L_TXCP
CV172 2 1 0.1U_0201_6.3V6K TMDS_TX0N
[37] TBT_ML0_N

2
CV173 2 1 0.1U_0201_6.3V6K TMDS_TX0P TMDS_L_TXCP
D [37] TBT_ML0_P D
CV174 2 1 0.1U_0201_6.3V6K TMDS_TX1N
[37] TBT_ML1_N
CV175 2 1 0.1U_0201_6.3V6K TMDS_TX1P
[37] TBT_ML1_P
CV176 2 1 0.1U_0201_6.3V6K TMDS_TX2N
[37] TBT_ML2_N
CV177 2 1 0.1U_0201_6.3V6K TMDS_TX2P TMDS_L_TX0N
[37] TBT_ML2_P

1
TMDS_TX0N RV532 1 EMC@ 2 8.2_0402_1% TMDS_L_TX0N
RV539
RV512 1 2 475_0402_1% 150_0402_5%
RV513 1 2 475_0402_1% EMC@ TMDS_TX0P RV533 1 EMC@ 2 8.2_0402_1% TMDS_L_TX0P
RV514 1 2 475_0402_1%

2
RV515 1 2 475_0402_1% TMDS_L_TX0P
RV516 1 2 475_0402_1%
RV517 1 2 475_0402_1%
RV518 1 2 475_0402_1%
RV519 1 2 475_0402_1%

TMDS_L_TX1N

1
TMDS_TX1N RV534 1 EMC@ 2 8.2_0402_1% TMDS_L_TX1N
+3VS RV540
150_0402_5%
EMC@ TMDS_TX1P RV535 1 EMC@ 2 8.2_0402_1% TMDS_L_TX1P

2
1
TMDS_L_TX1P
RV121
10K_0402_5%

1
2 QV13 TMDS_L_TX2N
C G C
L2N7002WT1G_SC-70-3

1
S TMDS_TX2N RV536 1 EMC@ 2 8.2_0402_1% TMDS_L_TX2N

3
RV541
150_0402_5%
+3VS EMC@ TMDS_TX2P RV537 1 EMC@ 2 8.2_0402_1% TMDS_L_TX2P

2
TMDS_L_TX2P
2

RV122
1M_0402_5% X06.32
2
G
1

3 1 HDMI_HPLUG 1 2
[37] TB_HDMI_HPLUG DV4 DV5
RV123 20K_0402_5% @ @
S

TMDS_L_TXCN 1 1 10 9 TMDS_L_TXCN TMDS_L_TX1P 1 1 10 9 TMDS_L_TX1P

QV14
L2N7002WT1G_SC-70-3 TMDS_L_TXCP 2 2 9 8 TMDS_L_TXCP TMDS_L_TX1N 2 2 9 8 TMDS_L_TX1N

TMDS_L_TX2N 4 4 7 7 TMDS_L_TX2N TMDS_L_TX0P 4 4 7 7 TMDS_L_TX0P

TMDS_L_TX2P 5 5 6 6 TMDS_L_TX2P TMDS_L_TX0N 5 5 6 6 TMDS_L_TX0N

3 3 3 3

8 8

AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9

B B

HDMI DDC HDMI conn

+VDISPLAY_VCC
UV16
JHDMI1
+5VS 19
+3VS 3
W=40mils HDMI_HPLUG
+VDISPLAY_VCC 18 HPD
OUT 17 +5V
1 DDC_DAT_HDMI 16 DDC/CEC GND

0.1U_0402_10V7K

10U_0603_6.3V6M
IN 1 1 SDA
2

DDC_CLK_HDMI 15

CV178

CV179
RV124 RV125 2 HDMI_Reserved 14 SCL
GND HDMI_CEC 13 Reserved
2.2K_0402_5% 2.2K_0402_5% CEC
2 2 TMDS_L_TXCN 12
11 CK-
AP2330W-7_SC59-3 CK_Shield
1

1
2

TMDS_L_TXCP 10
TMDS_L_TX2N 9 CK+
1 6 DDC_CLK_HDMI 8 D0-
[37] TBT_DDC_CLK D0_Shield
TMDS_L_TX2P 7
6 D0+
QX1A For EMI Reserve TMDS_L_TX1N
D1-
5
DMN65D8LDW-7_SOT363-6 TMDS_L_TX1P 4 D1_Shield 20
@ CV180 1 2 0.1U_0402_25V6 HDMI_HPLUG TMDS_L_TX0N 3 D1+ GND1 21
D2- GND2
5

2 22
@ CV181 1 2 0.1U_0402_25V6 HDMI_Reserved TMDS_L_TX0P 1 D2_Shield GND3 23
A 4 3 DDC_DAT_HDMI D2+ GND4 A
[37] TBT_DDC_DATA
@ CV182 1 2 0.1U_0402_25V6 HDMI_CEC ACON_HMRB9-AK120C
QX1B CONN@
DMN65D8LDW-7_SOT363-6 close to JHDMI

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS Custom LA-C361P 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
O UT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 36 of 71
5 4 3 2 1
 5 4 3 2 1

+3VA_TBT_LC

UT1A
[16] PCIE_PTX_TBRX_P15 CT2 2 1 0.22U_0201_6.3V6M PCIE_PTX_TBRX_P15_C Y23 V23 PCIE_PRX_TBTX_P15_C CT1 2 1 0.22U_0201_6.3V6M PCIE_PRX_TBTX_P15 [16]
PCIE_RX0_P PCIE_TX0_P
1

1
CT4 2 1 0.22U_0201_6.3V6M PCIE_PTX_TBRX_N15_C Y22 V22 PCIE_PRX_TBTX_N15_C CT3 2 1 0.22U_0201_6.3V6M
10K_0201_5% [16] PCIE_PTX_TBRX_N15 PCIE_PRX_TBTX_N15 [16]

10K_0201_5%

10K_0201_5%

10K_0201_5%
PCIE_RX0_N PCIE_TX0_N
RT6

RT7

RT8

RT9
[16] PCIE_PTX_TBRX_P16 CT6 2 1 0.22U_0201_6.3V6M PCIE_PTX_TBRX_P16_C T23 P23 PCIE_PRX_TBTX_P16_C CT5 2 1 0.22U_0201_6.3V6M PCIE_PRX_TBTX_P16 [16]
PCIE_RX1_P PCIE_TX1_P

PCIe GEN3
CT8 2 1 0.22U_0201_6.3V6M PCIE_PTX_TBRX_N16_C T22 P22 PCIE_PRX_TBTX_N16_C CT7 2 1 0.22U_0201_6.3V6M
[16] PCIE_PTX_TBRX_N16 PCIE_RX1_N PCIE_TX1_N PCIE_PRX_TBTX_N16 [16]
2

2
M23 K23
TBT_JTAG_TDI T196 @ PAD~D M22 PCIE_RX2_P PCIE_TX2_P K22
TBT_JTAG_TMS T197 @ PAD~D PCIE_RX2_N PCIE_TX2_N
TBT_JTAG_TCK T198 @ PAD~D H23 F23
TBT_JTAG_TDO T199 @ PAD~D H22 PCIE_RX3_P PCIE_TX3_P F22
D PCIE_RX3_N PCIE_TX3_N X06.25 D
V19 L4
[17] CLK_PCIE_TBT PCIE_REFCLK_100_IN_P PERST_N PCH_PLTRST#_EC [17,23,42,43,44,48,51]
[17] CLK_PCIE_TBT# T19
AC5 PCIE_REFCLK_100_IN_N N16 1 2
[17] TBT_CLK_REQ# PCIE_CLKREQ_N PCIE_RBIAS RT1 3.01K_0402_1%
[7] DDI1_HTX_TBRX_P0 CT17 2 1 0.1U_0201_6.3V6K DDI1_HTX_TBRX_P0_C AB7 R2
TBT_ML0_P [36]
CT18 2 1 0.1U_0201_6.3V6K DDI1_HTX_TBRX_N0_C AC7 DPSNK0_ML0_P DPSRC_ML0_P R1
[7] DDI1_HTX_TBRX_N0 DPSNK0_ML0_N DPSRC_ML0_N TBT_ML0_N [36]
+3V_TBT CT19 2 1 0.1U_0201_6.3V6K DDI1_HTX_TBRX_P1_C AB9 N2
[7] DDI1_HTX_TBRX_P1 DPSNK0_ML1_P DPSRC_ML1_P TBT_ML1_P [36]
[7] DDI1_HTX_TBRX_N1 CT20 2 1 0.1U_0201_6.3V6K DDI1_HTX_TBRX_N1_C AC9 N1 TBT_ML1_N [36]

SOURCE PORT 0
DPSNK0_ML1_N DPSRC_ML1_N

SINK PORT 0
[7] DDI1_HTX_TBRX_P2 CT21 2 1 0.1U_0201_6.3V6K DDI1_HTX_TBRX_P2_C AB11 L2
TBT_ML2_P [36]
CT22 2 1 0.1U_0201_6.3V6K DDI1_HTX_TBRX_N2_C AC11 DPSNK0_ML2_P DPSRC_ML2_P L1
[7] DDI1_HTX_TBRX_N2 DPSNK0_ML2_N DPSRC_ML2_N TBT_ML2_N [36]
RT107 1 2 10K_0201_5% TBT_SRC_CFG1 [7] DDI1_HTX_TBRX_P3 CT23 2 1 0.1U_0201_6.3V6K DDI1_HTX_TBRX_P3_C AB13 J2 TBT_ML3_P [36]
CT24 2 1 0.1U_0201_6.3V6K DDI1_HTX_TBRX_N3_C AC13 DPSNK0_ML3_P DPSRC_ML3_P J1
[7] DDI1_HTX_TBRX_N3 DPSNK0_ML3_N DPSRC_ML3_N TBT_ML3_N [36]
PU for support HDMI mode, PD for support DP mode
[7] DDI1_CPU_AUXP CT25 2 1 0.1U_0201_6.3V6K DDI1_CPU_AUXP_C Y11 W 19
CT26 2 1 0.1U_0201_6.3V6K DDI1_CPU_AUXN_C W 11 DPSNK0_AUX_P DPSRC_AUX_P Y19
[7] DDI1_CPU_AUXN DPSNK0_AUX_N DPSRC_AUX_N
DDI1_PCH_HPD AA2 G1 TB_HDMI_HPLUG
[16] DDI1_PCH_HPD DPSNK0_HPD DPSRC_HPD TB_HDMI_HPLUG [36]
RT202 1 @ 2 10K_0201_5% TBT_POC_RST#
X06.25 [16] DDI1_DDPB_CTRLCLK DDI1_DDPB_CTRLCLK Y5 N6 1 2
RT21 1 @ 2 10K_0201_5% TBT_CLK_REQ# DDI1_DDPB_CTRLDAT R4 DPSNK0_DDC_CLK DPSRC_RBIAS RT2 14K_0402_1%
[16] DDI1_DDPB_CTRLDAT DPSNK0_DDC_DATA U1 TBT_I2C_DATA TBT_I2C_DATA [39]
RT33 1 2 2.2K_0201_5% TBT_DDC_CLK CT29 2 1 0.1U_0201_6.3V6K DDI2_HTX_TBRX_P0_C AB15 GPIO_0 U2 TBT_I2C_CLK
[7] DDI2_HTX_TBRX_P0 DPSNK1_ML0_P GPIO_1 TBT_I2C_CLK [39]
RT34 1 2 2.2K_0201_5% TBT_DDC_DATA [7] DDI2_HTX_TBRX_N0 CT30 2 1 0.1U_0201_6.3V6K DDI2_HTX_TBRX_N0_C AC15 V1 TBT_ROM_WP#

LC GPIO
DPSNK1_ML0_N GPIO_2 V2 TBT_TMU_CLK_OUT
CT31 2 1 0.1U_0201_6.3V6K DDI2_HTX_TBRX_P1_C AB17 GPIO_3 W1 TBT_PCIE_WAKE#
[7] DDI2_HTX_TBRX_P1 DPSNK1_ML1_P GPIO_4 TBT_PCIE_WAKE# [48]
[7] DDI2_HTX_TBRX_N1 CT32 2 1 0.1U_0201_6.3V6K DDI2_HTX_TBRX_N1_C AC17 W2 TBT_CIO_PLUG_EVENT# TBT_CIO_PLUG_EVENT# [16]
+3VA_TBT DPSNK1_ML1_N GPIO_5 Y1 TBT_DDC_DATA
GPIO_6 TBT_DDC_DATA [36]
[7] DDI2_HTX_TBRX_P2 CT33 2 1 0.1U_0201_6.3V6K DDI2_HTX_TBRX_P2_C AB19 Y2 TBT_DDC_CLK TBT_DDC_CLK [36]

SINK PORT 1
CT34 2 1 0.1U_0201_6.3V6K DDI2_HTX_TBRX_N2_C AC19 DPSNK1_ML2_P GPIO_7 AA1 TBT_SRC_CFG1
[7] DDI2_HTX_TBRX_N2 DPSNK1_ML2_N GPIO_8 J4 TBTA_I2C_INT#
POC_GPIO_0 TBTA_I2C_INT# [39]
[7] DDI2_HTX_TBRX_P3 CT35 2 1 0.1U_0201_6.3V6K DDI2_HTX_TBRX_P3_C AB21 E2 T195 @

POC GPIO
RT35 1 2 2.2K_0201_5% TBT_I2C_DATA CT36 2 1 0.1U_0201_6.3V6K DDI2_HTX_TBRX_N3_C AC21 DPSNK1_ML3_P POC_GPIO_1 D4 RTD3_USB_PWR_EN PAD~D
[7] DDI2_HTX_TBRX_N3 DPSNK1_ML3_N POC_GPIO_2
RT36 1 2 2.2K_0201_5% TBT_I2C_CLK H4 TBT_FORCE_PWR
POC_GPIO_3 TBT_FORCE_PWR [17]
C RT22 1 @ 2 10K_0201_5% TBT_PCIE_WAKE# [7] DDI2_CPU_AUXP CT108 2 1 0.1U_0201_6.3V6K DDI2_CPU_AUXP_C Y12 F2 TBT_BATLOW# C
RT23 1 2 10K_0201_5% TBT_CIO_PLUG_EVENT# CT107 2 1 0.1U_0201_6.3V6K DDI2_CPU_AUXN_C W 12 DPSNK1_AUX_P POC_GPIO_4 D2 SIO_SLP_S3#
RT25 1 2 10K_0201_5% TBT_BATLOW#
[7] DDI2_CPU_AUXN DPSNK1_AUX_N POC_GPIO_5 F1 RTD3_CIO_PWR_EN
SIO_SLP_S3# [18,34,48,52]
RTD3_CIO_PWR_EN [17]
X06.25
DDI2_PCH_HPD Y6 POC_GPIO_6
[16] DDI2_PCH_HPD DPSNK1_HPD E1 TBT_TEST_EN 100_0201_1% 2 1 RT3
DDI2_DDPC_CTRLCLK Y8 TEST_EN
[16] DDI2_DDPC_CTRLCLK

Misc
DDI2_DDPC_CTRLDAT N4 DPSNK1_DDC_CLK AB5 TBT_TEST_PWRG 100_0201_1% 2 1 RT4
[16] DDI2_DDPC_CTRLDAT DPSNK1_DDC_DATA TEST_PW R_GOOD RB751S40T1G_SOD523-2
2 1 Y18 F4 TBT_POC_RST# 2 @ 1 DT29
DPSNK_RBIAS RESET_N TBTA_RESET_N [39]
RT5 14K_0402_1% 2 1 YT1
UPD_MRESET [39,48]
TBT_JTAG_TDI Y4 D22 XTAL_25_IN 0_0402_5% @ RT244 1 2
RT37 1 2 100K_0201_5% TBT_TMU_CLK_OUT TBT_JTAG_TMS V4 TDI XTAL_25_IN D23 XTAL0 GND0
RT38 1 2 100K_0201_5% TBT_FORCE_PWR TBT_JTAG_TCK T4 TMS XTAL_25_OUT XTAL_25_OUT 3 4
RT39 1 2 RTD3_CIO_PWR_EN TBT_JTAG_TDO W4 TCK AB3 TBT_ROM_DI XTAL1 GND1
100K_0201_5%
TDO MISC EE_DI
RT40 1 2 100K_0201_5% RTD3_USB_PWR_EN AC4 TBT_ROM_DO 25MHZ_10PF_7V25000014
RT41 1 2 100K_0201_5% DDI1_PCH_HPD TBT_RBIAS H6 EE_DO AC3 TBT_ROM_CS# X06.25
RT42 1 2 100K_0201_5% DDI2_PCH_HPD 1 2 TBT_RSENSE J6 RBIAS EE_CS_N AB4 TBT_ROM_CLK
RSENSE EE_CLK 1 1
RT43 1 2 100K_0201_5% TBTA_HPD RT10 4.75K_0402_0.5%
RT44 1 2 1M_0201_1% TBT_LSTX [41] TBT_USB3_RX1_P
A15 B7 CT44 CT43
RT45 1 2 1M_0201_1% TBT_LSRX B15 PA_RX1_P PB_RX1_P A7 10P_0402_25V8J 10P_0402_25V8J
[41] TBT_USB3_RX1_N PA_RX1_N PB_RX1_N 2 2
RT207 1 2 100K_0201_5% NC_B4
RT208 1 2 100K_0201_5% NC_B5 [41] TBT_USB3_TX1_P CT37 2 1 0.22U_0201_6.3V6M TBT_USB3_TX1_P_C A17 A9
RT209 1 2 100K_0201_5% NC_G2 CT38 2 1 0.22U_0201_6.3V6M TBT_USB3_TX1_N_C B17 PA_TX1_P PB_TX1_P B9
[41] TBT_USB3_TX1_N PA_TX1_N PB_TX1_N
[41] TBT_USB3_TX0_P CT39 2 1 0.22U_0201_6.3V6M TBT_USB3_TX0_P_C A19 A11
CT40 2 1 0.22U_0201_6.3V6M TBT_USB3_TX0_N_C B19 PA_TX0_P PB_TX0_P B11
[41] TBT_USB3_TX0_N PA_TX0_N PB_TX0_N

TBT PORTS
[41] TBT_USB3_RX0_P B21 A13
A21 PA_RX0_P PB_RX0_P B13
[41] TBT_USB3_RX0_N

Port A

PORT B
PA_RX0_N PB_RX0_N
[39] TBTA_AUX_P CT41 2 1 0.1U_0201_6.3V6K TBTA_AUX_P_C Y15 Y16
CT42 2 1 0.1U_0201_6.3V6K TBTA_AUX_N_C W 15 PA_DPSRC_AUX_P PB_DPSRC_AUX_P W 16
+3V_TBT_SPI [39] TBTA_AUX_N PA_DPSRC_AUX_N PB_DPSRC_AUX_N
+3VA_TBT_LC E20 E19
[39] TBT_USB2_D+ PA_USB2_D_P PB_USB2_D_P
D20 D19
@ [39] TBT_USB2_D- PA_USB2_D_N PB_USB2_D_N
RT242 1 2 0_0402_5%
TBT_LSTX A5 B4 NC_B4
VCC3V3_FLASH [39] TBT_LSTX PA_LS_G1 PB_LS_G1
A4 B5

POC
TBT_LSRX NC_B5

POC
B [39] TBT_LSRX PA_LS_G2 PB_LS_G2 B
TBTA_HPD M4 G2 NC_G2
[39] TBTA_HPD PA_LS_G3 PB_LS_G3
RT243 1 @ 2 0_0402_5%
RT12 2 1 499_0201_1% H19 F19 RT164 2 1 499_0201_1%
PA_USB2_RBIAS PB_USB2_RBIAS
X06.25 AC23 D6
AB23 THERMDA MONDC_SVR
THERMDA A23
V18 ATEST_P B23
PCIE_ATEST ATEST_N
AC1 DEBUG E18
TEST_EDM USB2_ATEST
L15 W 13
N15 FUSE_VQPS_64 MONDC_DPSNK_0
FUSE_VQPS_128 W 18
C23 MONDC_DPSNK_1
C22 MONDC_CIO_0 AB2
MONDC_CIO_1 MONDC_DPSRC

ALPINE-RIDGE_BGA337

+3V_TBT_SPI +3V_TBT_SPI
0.1U_0201_6.3V6K
1

1
3.3K_0201_1%

3.3K_0201_1%

3.3K_0201_1%

3.3K_0201_1%
RT15

RT18

RT16

RT17
CT47

2
2

A A
UT2
8 1 TBT_ROM_CS#
TBT_ROM_HOLD# 7 VCC CS# 2 TBT_ROM_DO
TBT_ROM_CLK 6 HOLD#(IO3) DO(IO1) 3 TBT_ROM_WP#
TBT_ROM_DI 5 CLK W P#(IO2) 4
DI(IO0) GND
W25Q80DVSSIG_SO8
TBT_ROM_DI RT228 1 @ 2 0_0201_5% TBT_ROM_DI_R [39]
TBT_ROM_DO RT229 1 @ 2 0_0201_5% TBT_ROM_DO_R [39]
Compal Electronics, Inc.
TBT_ROM_CS# RT230 1 @ 2 0_0201_5%
TBT_ROM_CLK RT231 1 @ 2 0_0201_5%
TBT_ROM_CS#_R [39] Security Classification Compal Secret Data
TBT_ROM_CLK_R [39]
Issued Date 2014/01/20 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
AR_TBT (1/2) DP / PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
C LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 37 of 71

5 4 3 2 1
 5 4 3 2 1

+3VA_TBT

+3V_TBT +3VA_TBT +3V_TBT

+VCC0V9_DP +3VA_TBT_LC
+3V_TBT_S0
RT46 2 @ 1 0_0603_5%

1U_0201_6.3V6M

1U_0201_6.3V6M
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1 1

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1
+3VALW

CT50

CT143

CT53

CT54

CT55

CT56
CT62

CT63

CT64

CT65

CT66

CT67

CT68

CT52
2 2
2 2 2 2 2 2 2 RT113 2 @ 1 0_0603_5% 2 2 2 2 2
+VCC0V9_DP

R13
UT1B

R6

H9
F8
D D
L8 A2

VCC3P3_S0
VCC3P3_LC

VCC3P3_SX

VCC3P3A
L11 VCC0P9_DP VCC3P3_SVR A3
L12 VCC0P9_DP VCC3P3_SVR B3
M8 VCC0P9_DP VCC3P3_SVR
+VCC0V9_PCIE +VCC0V9_USB T11 VCC0P9_DP
+3VS +3V_TBT T12 VCC0P9_DP L9 VCC0V9_SVR
L6 VCC0P9_DP VCC0P9_SVR M9

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
M6 VCC0P9_ANA_DPSRC VCC0P9_SVR E12
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
VCC0P9_ANA_DPSRC VCC0P9_SVR_ANA 1 1 1 1 1 1 1
1 1 1 1 1 1 1 V11 E13
VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA

CT83

CT84

CT74

CT85

CT86
2 1 0_0603_5% V12 F11

CT142

CT141
RT241 @
+VCC0V9_PCIE VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA
CT80

CT71

CT72

CT81

CT82

CT93

CT94
V13 F12
VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F13 2 2 2 2 2 2 2
2 2 2 2 2 2 2 M13 VCC0P9_SVR_ANA F15
M15 VCC0P9_PCIE VCC0P9_SVR_ANA J9
X06.25 VCC0P9_PCIE VCC0P9_SVR_SENSE
M16
L19 VCC0P9_PCIE 0.6uH, 5A, 20m ohm by TB CRB
N19 VCC0P9_ANA_PCIE_1 C1 TBT_SVR_IND LT1 1 2 0.6UH_XFL4012-601MEC_20%
L18 VCC0P9_ANA_PCIE_1 SVR_IND C2
M18 VCC0P9_ANA_PCIE_2 SVR_IND D1 1 1 1

47U_0603_6.3V6M

47U_0603_6.3V6M

47U_0603_6.3V6M
N18 VCC0P9_ANA_PCIE_2 SVR_IND
VCC0P9_ANA_PCIE_2

VCC
+VCC0V9_USB

CT88

CT89

CT90
+VCC0V9_CIO R15 A1
R16 VCC0P9_USB SVR_VSS B1 2 2 2
VCC0P9_USB SVR_VSS B2
+VCC0V9_CIO R8 SVR_VSS
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

R9 VCC0P9_CIO
1 1 1 VCC0P9_CIO
R11
VCC0P9_CIO X06.08
CT101

CT102

CT103

R12 F18 VCC0V9_LVR_OUT

VCC0P9_CIO VCC0P9_LVR H18

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
2 2 2 VCC_3V3_PCIE L16 VCC0P9_LVR J11
VCC3P3_ANA_PCIE VCC0P9_LVR 1 1 1 1
+3V_TBT VCC_3V3_USB2 J16 H11

CT95

CT96

CT97

CT98
1U_0201_6.3V6M

1U_0201_6.3V6M
+3V_TBT_S0 VCC3P3_ANA_USB2 VCC0P9_LVR_SENSE
LT14 1 1
A6 V5
VSS_ANA VSS_ANA 2 2 2 2

CT99

CT100
1 2 A8 V6
A10 VSS_ANA VSS_ANA V8
LQM18PN1R0MFHD_2P 2 2 A12 VSS_ANA VSS_ANA V9
A14 VSS_ANA VSS_ANA V15
1U_0201_6.3V6M

C C
47U_0603_6.3V6M

47U_0603_6.3V6M

A16 VSS_ANA VSS_ANA V16

1 1 1 VSS_ANA VSS_ANA
A18 V20
CT164

CT165

VSS_ANA VSS_ANA
CT163

A20 W5
A22 VSS_ANA VSS_ANA W6
2 2 2 B6 VSS_ANA VSS_ANA W8
B8 VSS_ANA VSS_ANA W9
B10 VSS_ANA VSS_ANA W 20
B12 VSS_ANA VSS_ANA W 22
X06.08 B14 VSS_ANA VSS_ANA W 23
B16 VSS_ANA VSS_ANA Y9
B18 VSS_ANA VSS_ANA Y13
B20 VSS_ANA VSS_ANA Y20
B22 VSS_ANA VSS_ANA AA22
D8 VSS_ANA VSS_ANA AA23
D9 VSS_ANA VSS_ANA AB6
D11 VSS_ANA VSS_ANA AB8
D12 VSS_ANA VSS_ANA AB10
D13 VSS_ANA VSS_ANA AB12
D15 VSS_ANA VSS_ANA AB14
D16 VSS_ANA VSS_ANA AB16
VSS_ANA VSS_ANA

GND
D18 AB18
E8 VSS_ANA VSS_ANA AB20
E9 VSS_ANA VSS_ANA AB22
E11 VSS_ANA VSS_ANA AC6
E15 VSS_ANA VSS_ANA AC8
E16 VSS_ANA VSS_ANA AC10
E22 VSS_ANA VSS_ANA AC12
E23 VSS_ANA VSS_ANA AC14
F9 VSS_ANA VSS_ANA AC16
F16 VSS_ANA VSS_ANA AC18
F20 VSS_ANA VSS_ANA AC20
G22 VSS_ANA VSS_ANA AC22
G23 VSS_ANA VSS_ANA D5
H1 VSS_ANA VSS E4
H2 VSS_ANA VSS E5
H12 VSS_ANA VSS E6
H13 VSS_ANA VSS F5
B
H15 VSS_ANA VSS F6 B
H16 VSS_ANA VSS H5
H20 VSS_ANA VSS H8
J5 VSS_ANA VSS J8
J18 VSS_ANA VSS J12
J19 VSS_ANA VSS J13
J20 VSS_ANA VSS J15
J22 VSS_ANA VSS L13
J23 VSS_ANA VSS M11
K1 VSS_ANA VSS M12
K2 VSS_ANA VSS N8
L5 VSS_ANA VSS N9
L20 VSS_ANA VSS N11
L22 VSS_ANA VSS N12
L23 VSS_ANA VSS N13
M1 VSS_ANA VSS T6
M2 VSS_ANA VSS T8
M5 VSS_ANA VSS T9
M19 VSS_ANA VSS T13
M20 VSS_ANA VSS T15
N5 VSS_ANA VSS T16
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
N20 VSS_ANA VSS T18
N22 VSS_ANA VSS AB1
N23 VSS_ANA VSS AC2
VSS_ANA VSS
R18
R19
R20
R22
R23

T20
U22
U23
P1
P2
R5

T1
T2
T5
ALPINE-RIDGE_BGA337

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/01/20 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
AR_TBT (2/2) PWR / GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
C LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 38 of 71

5 4 3 2 1
 5 4 3 2 1

VCC5V0_SYS +3V_VC TBTA_LDO_BMC VCC3V3_TBT_SX VCC3V3_FLASH VCC1V8A_TBTA_LDO VCC1V8D_TBTA_LDO

+5VALW VCC5V0_SYS

1 1 1 1 1 1
RT165 1 @ 2 0_0805_5%
1 1 1 1 CT161 CT144 CT145 CT146 CT151 CT152
CT147 CT148 CT149 CT150 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M
X06.23 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 2 2 2 2 2 2

2 2 2 2

D D

PP_HV +VBUS_1

1
CT155 CT153
4.7U_0603_25V6K 1U_0603_25V6
2

2
+3VA_TBT

X06.35
RT167 1 2 10K_0201_5% TBTA_I2C_INT# UT4

A6 B10
PP_HV PP_HV SENSEP PD_SENSEP [55]
A7 A10
VCC3V3_FLASH A8 PP_HV SENSEN PD_SENSEN [55]
B7 PP_HV
PP_HV B9 T191 PAD~D @
RT168 1 2 3.3K_0201_1% PD_EE_CS# A11 HV_GATE1 A9 T192 PAD~D @ +VBUS_1
VCC5V0_SYS PP_5V0 HV_GATE2 TBTA_VBUS_L
RT169 1 2 3.3K_0201_1% PD_EE_DO C11
RT170 1 2 3.3K_0201_1% PD_EE_WP# B11 PP_5V0 LT11 EMC@
RT171 1 2 3.3K_0201_1% PD_HOLD# +3V_VC D11 PP_5V0 H11 1 2
PP_5V0 VBUS J10 HCB2012KF-121T50_2P
VBUS

3
H10 J11
PP_CABLE VBUS

1
K11
B1 VBUS CT157 DT10
VDDIO 1U_0603_25V6 AZ4024-02S_SOT23-3~D

2
H1 H2 VCC3V3_TBT_SX EMC@
VIN_3V3 VOUT_3V3 G1
LDO_3V3 VCC3V3_FLASH

1
K1 VCC1V8A_TBTA_LDO
D1 LDO_1V8A A2
[37] TBT_I2C_DATA I2C_SDA1 LDO_1V8D VCC1V8D_TBTA_LDO
D2 E1
[37] TBT_I2C_CLK I2C_SCL1 LDO_BMC TBTA_LDO_BMC
C [37] TBTA_I2C_INT# C1 C
I2C_IRQ1_N
UPD_SMBDAT A5
UPD_SMBCLK B5 I2C_SDA2 CT160 1 2 220P_0402_50V7K
B6 I2C_SCL2 L9
[48] PD_I2C_ALERT# I2C_IRQ2_N C_CC1 TBTA_CC1 [41]
L10 TBTA_CC2 [41]
C_CC2 CT159 1 2 220P_0402_50V7K
PD_EE_CLK A3 K9
PD_EE_DI B4 SPI_CLK RPD_G1 K10
PD_EE_DO A4 SPI_MOSI RPD_G2
PD_EE_CS# B3 SPI_MISO
SPI_SS_N K6
C_USB_TP TBTA_USB2_D_P_R [41]
L6 TBTA_USB2_D_N_R [41]
L5 C_USB_TN
[37] TBT_USB2_D+ USB_RP_P
K5
[37] TBT_USB2_D- USB_RP_N K7 TBTA_I2C_D_P [41]
C_USB_BP L7
C_USB_BN TBTA_I2C_D_N [41]
[37] TBTA_AUX_P J1
J2 AUX_P
[37] TBTA_AUX_N AUX_N K8 TBTA_PD_SBU1 RT176 1 @ 2 0_0402_5%
C_SBU1 TBTA_SBU1 [41]
L8 TBTA_PD_SBU2 RT177 1 @ 2 0_0402_5% TBTA_SBU2 [41]
@ PAD~D T193 G4 C_SBU2
@ PAD~D T194 F4 SW D_CLK
SW D_DATA B2 T185 PAD~D @
X06.23 GPIO0 C2 RT178 1 @ 2 0_0402_5%
EN_PD_HV [55]
E2 GPIO1 D10
UART_TX GPIO2 PWR_SRC_ON_PC [55]
F2 G11 T187 PAD~D @
X06.23 UART_RX GPIO3 C10 RT181 1 @ 2 0_0402_5% TBTA_HPD [37]
TBT_LSTX L4 GPIO4 E10 T200 PAD~D @
[37] TBT_LSTX LSTX/R2P GPIO5
TBT_LSRX K4 G10 RT198 1 @ 2 0_0402_5%
[37] TBT_LSRX LSRX/P2R GPIO6 PWR_SRC_ILIMIT [55]
D7 RT182 1 @ 2 0_0402_5%
RT226 1 2 10K_0201_5% E4 GPIO7 H6 RT183 1 2 0_0402_5%
VCC3V3_FLASH DEBUG_CTL1 GPIO8
RT227 1 2 10K_0201_5% D5 @ PWR_BTN_DOCK1#
DEBUG_CTL2 X06.23
RT184 1 @ 2 0_0402_5% TBTA_DEBUG1 L2 RT245 1 @ 2 0_0201_5%
X06.23 [35,48]
[35,48]
DOCK_TNY_SMB_CLK
DOCK_TNY_SMB_DAT RT185 1 @ 2 0_0402_5% TBTA_DEBUG2 K2 DEBUG1 E11 RT186 1 2 100K_0201_5%
UPD_MRESET [37,48]
DEBUG2 MRESET
TBT_LSTX RT233 1 @ 2 0_0201_5% TBTA_DEBUG3_LSTX L3 F11 TBTA_RESET_N [37]
B
TBT_LSRX RT232 1 @ 2 0_0201_5% TBTA_DEBUG4_LSRX K3 DEBUG3 RESET_N B
DEBUG4 F10 RT189 1 @ 2 0_0402_5%
BUSPOW ER_N VCC3V3_FLASH
F1
I2C_ADDR G2 RT246 1 @ 2 0_0402_5%
R_OSC VCC1V8A_TBTA_LDO
2

2
100K_0201_5%

100K_0201_5%

H7
RT187

RT188

X06.23
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

SS
1
0_0402_5%

15K_0402_1%
1

1
RT190

0_0402_5%
RT199
1
@ TPS65982_BGA96

RT191
L11
G5

G8
A1
D6
E5
E6
E7
F5

H4
H5

G6
G7
B8
D8
E8
F6
F7
F8

H8
L1
1

@
2
2

CT158

2
0.22U_0402_10V6K
X06.23

+3VA_TBT
VCC3V3_FLASH
+3VA_TBT

[37] TBT_ROM_CLK_R RT210 1 @ 2 0_0201_5% PD_EE_CLK

[37] TBT_ROM_DI_R RT211 1 @ 2 0_0201_5% PD_EE_DI
[37] TBT_ROM_DO_R RT212 1 @ 2 0_0201_5% PD_EE_DO
1

[37] TBT_ROM_CS#_R RT213 1 @ 2 0_0201_5% PD_EE_CS#

RT192 RT193

1
3.3K_0201_1% @ @ 3.3K_0201_1%
VCC3V3_FLASH RT194
100K_0402_5%
2

2
2

2
G
2
1 6 UPD_SMBDAT UT5
[23,48] UPD_GPU_SMBDAT
8 1 PD_EE_CS# PWR_BTN_DOCK1# 3 1 RT195 1 @ 2 0_0402_5% PWR_TB_DOCK# [48]
@ PD_HOLD# 7 VCC /CS 2 PD_EE_DO

D
QT1A PD_EE_CLK 6 /HOLD/IO3 DO/IO1 3 PD_EE_WP#
A DMN65D8LDW-7_SOT363-6 PD_EE_DI 5 CLK /W P/IO2 4 X06.23 A
RT200 1 @ 2 0_0402_5% DI/IO0 GND QV89
X06.23 W25Q32FVSSIQ_SO8 L2N7002WT1G_SC-70-3
5

[23,48] UPD_GPU_SMBCLK 4 3 UPD_SMBCLK

@
QT1B
DMN65D8LDW-7_SOT363-6 Security Classification Compal Secret Data Compal Electronics, Inc.
RT201 1 @ 2 0_0402_5% 2011/08/25 2012/07/25 Title
Issued Date Deciphered Date
X06.23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR
Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
PCH (7/8) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C. LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 39 of 71

5 4 3 2 1
 5 4 3 2 1

D D

Reserve

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
Power on Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 40 of 71
5 4 3 2 1
 5 4 3 2 1

D D
TBT_USB3_TX0_P 1 2 TBT_USB3_RX0_P 1 2
DT12 ESD108-B1-CSP0201_WLL-2-1-2 DT20 ESD108-B1-CSP0201_WLL-2-1-2
EMC@ EMC@

TBT_USB3_TX0_N 1 2 TBT_USB3_RX0_N 1 2
DT13 ESD108-B1-CSP0201_WLL-2-1-2 DT21 ESD108-B1-CSP0201_WLL-2-1-2
EMC@ EMC@

TBTA_CC1 1 2 TBTA_SBU2 1 2
DT14 ESD108-B1-CSP0201_WLL-2-1-2 DT22 ESD108-B1-CSP0201_WLL-2-1-2
CMMI21T-900Y-N_4P EMC@ EMC@
[39] TBTA_I2C_D_N 4 3 TBTA_I2C_C_N
4 3 TBTA_USB2_D_P_C 1 2 TBTA_I2C_C_N 1 2
DT15 ESD108-B1-CSP0201_WLL-2-1-2 DT23 ESD108-B1-CSP0201_WLL-2-1-2
1 2 TBTA_I2C_C_P EMC@ EMC@
[39] TBTA_I2C_D_P 1 2
LT13 TBTA_USB2_D_N_C 1 2 TBTA_I2C_C_P 1 2
DT16 ESD108-B1-CSP0201_WLL-2-1-2 DT24 ESD108-B1-CSP0201_WLL-2-1-2
EMC@ EMC@

TBTA_SBU1 1 2 TBTA_CC2 1 2
DT17 ESD108-B1-CSP0201_WLL-2-1-2 DT25 ESD108-B1-CSP0201_WLL-2-1-2
EMC@ EMC@
CMMI21T-900Y-N_4P
4 3 TBTA_USB2_D_P_C TBT_USB3_RX1_N 1 2 TBT_USB3_TX1_N 1 2
[39] TBTA_USB2_D_P_R 4 3 DT18 ESD108-B1-CSP0201_WLL-2-1-2 DT26 ESD108-B1-CSP0201_WLL-2-1-2
EMC@ EMC@
1 2 TBTA_USB2_D_N_C
[39] TBTA_USB2_D_N_R 1 2 TBT_USB3_RX1_P 1 2 TBT_USB3_TX1_P 1 2
LT12 DT19 ESD108-B1-CSP0201_WLL-2-1-2 DT27 ESD108-B1-CSP0201_WLL-2-1-2
EMC@ EMC@
X06.24

C C

+VBUS_1 +VBUS_1

JUSBC1
+VBUS_1 A1 B12
GND GND
[37] TBT_USB3_TX0_P TBT_USB3_TX0_P A2 B11 TBT_USB3_RX0_P TBT_USB3_RX0_P [37]
TBT_USB3_TX0_N A3 SSTXP1 SSRXP1 B10 TBT_USB3_RX0_N
[37] TBT_USB3_TX0_N SSTXN1 SSRXN1 TBT_USB3_RX0_N [37]
CT120 1 2 0.47U_0402_25V6K A4 B9 CT122 1 2 0.47U_0402_25V6K
VBUS VBUS
1

[39] TBTA_CC1 TBTA_CC1 A5 B8 TBTA_SBU2 TBTA_SBU2 [39]

DT28 CC1 RFU2
RB751S40T1G_SOD523-2 TBTA_USB2_D_P_C A6 B7 TBTA_I2C_C_N
TBTA_USB2_D_N_C A7 DP1 DN2 B6 TBTA_I2C_C_P
DN1 DP2

Bottom
2

[39] TBTA_SBU1 TBTA_SBU1 A8 B5 TBTA_CC2 TBTA_CC2 [39]

B RFU1 CC2 B

TOP
CT121 1 2 0.47U_0402_25V6K A9 B4 CT123 1 2 0.47U_0402_25V6K
VBUS VBUS
TBT_USB3_RX1_N A10 B3 TBT_USB3_TX1_N
[37] TBT_USB3_RX1_N SSRXN2 SSTXN2 TBT_USB3_TX1_N [37]
[37] TBT_USB3_RX1_P TBT_USB3_RX1_P A11 B2 TBT_USB3_TX1_P TBT_USB3_TX1_P [37]
SSRXP2 SSTXP2
A12 B1
GND GND

1 4
GND GND
2 3
GND GND

JAE_DX07S024XJ2
CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/01/20 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
PD USB TYPE-C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
C LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 41 of 71

5 4 3 2 1
 5 4 3 2 1

Power Button and LED

+3VS +5VS +5VS +3VS

PWM FAN

1
+5VALW RE100

1
10K_0402_5%
RE81 RE82
X06.29

2
100K_0402_5% 10K_0402_5% JFAN1

1
1
[48] FAN1_PWM 2 1

2
RE1041 @ 2 0_0603_5% 5VS_FAN1
RE3 2 1 3 2
[48] FAN1_TACH 4 3
300_0402_5% DE7 RB751S40T1G_SOD523-2
1 5 4
6 G1

2
D CE66 D
G2
0.01U_0402_16V7K
LED6 ACES_50224-00401-001
1 2 2 CONN@
[48] PWRBTN_LED#
HT-F196BP5_WHITE

+3VS +5VS +5VS +3VS

SW1 3

1
4
PBTN_SW# [48,52]
RE101

1
2

3
10K_0402_5%
DE2 RE83 RE84
X06.29

2
2 1 AZ5125-02S.R7G_SOT23-3 100K_0402_5% 10K_0402_5% JFAN2
EMC@ 1
SKRBAAE010_4P [48] FAN2_PWM 2 1

2
RE1051 @ 2 0_0603_5% 5VS_FAN2
2 1 3 2
[48] FAN2_TACH 4 3
DE8 RB751S40T1G_SOD523-2
1 5 4
CE67 6 G1
G2

1
0.01U_0402_16V7K
ACES_50224-00401-001
2 CONN@

C C
power rail option: TPM power rail must same as +3.3V_SPI (SPI ROM)

Touch pad Nuvoton TPM +3VS_TPM

+3VS_TPM
RE128 1 @ 2 0_0402_5% TPM_VDD +3V_PCH
+3VALW +3VS_TP
+3VS RE1211 @ 2 0_0603_5%
UE6 X06.29 +3VS_TPM
+5VALW RE129 1 @ 2 0_0402_5%
1 8 RE93 1 2 0_0603_5%
2 VIN VOUT 7 @
VIN VOUT CE65 1 TPM@ 2 TPM_PIRQ# X06.29 +3VALW +3VS_TPM_VSB
TP_PW_EN 3 6 1 2 RE86 10K_0402_5%
[49] TP_PW_EN EN CT @ RE1411 @ 2 0_0603_5%
4 5 2200P_0402_25V7K
VBIAS GND 9 1 @ 2 TPM_GPIO4
GND RE134 10K_0402_5% X06.09 X06.29
APE8937GN2_DFN8_2X2
+3VS_TPM_VSB
+3VS_TPM
RZ32 1 2 100K_0402_5% TP_PW_EN X06.29 UE1
1
RE125 1 @ 2 0_0402_5% 29 VSB

10U_0603_6.3V6M
[18,34,52] SIO_SLP_S0# GPIO0/SDA/XOR_OUT
30 8 TPM_VDD

0.1U_0402_25V6

0.1U_0402_25V6
+3VS_TP TPM_LPM# 3 GPIO1/SCL VDD 14
GPIO2/GPX VDD 1 1 1
+3V_PCH 6 22
+3VS_TP GPIO3/BADD VDD

CE12

CE13

CE14
RE113 1 TPM@ 2 33_0402_5% 24 2
[17] PCH_TPM_SO LAD0/MISO NC 2 2 2
RE114 1 TPM@ 2 33_0402_5% 21 7
[17] PCH_TPM_SI TPM_PIRQ# 18 LAD1/MOSI NC 10
[17] TPM_PIRQ# TPM@ TPM@ TPM@
RE7 15 LAD2/SPI_IRQ# NC 11
LAD3 NC
2

QE2A QE19A 1 2 2.4K_0402_5% 25

B X06.29 RE115 1 TPM@ 2 33_0402_5% PCH_TPM_CLK_C 19 NC 26 B
6 1 1 6 [17] PCH_TPM_CLK 1 2 0_0402_5% 20 LCKL/SCLK NC 31
I2C1_SDA_TP_C RE133 @ PCH_SPI_CS2#_R
[20] I2C1_SDA_TP [17] PCH_SPI_CS2# LFRAME#/SCS# NC
17
[17,23,37,43,44,48,51] PCH_PLTRST#_EC LRESET#/SPI_RST#/SRESET#
DMN65D8LDW-7_SOT363-6 DMN65D8LDW-7_SOT363-6 RE85 1 TPM@ 2 10K_0402_5% 27 9
PCH_SPI_CS2# RE1261 @ 2 0_0402_5% TPM_GPIO4 13 SERIRQ GND 16
RE9 RE77 1 @ 2 4.7K_0402_5% 28 CLKRUN#/GPIO4/SINT# GND 23
+3VS_TPM LPCPD# GND
5

1 2 2.4K_0402_5% 32
4 GND 33
3 4 4 3 I2C1_SCK_TP_C +3VS_TPM 5 PP PGND 12
[20] I2C1_SCK_TP TEST Reserved +3VS_TPM_VSB
QE2B QE19B 1 NPCT650JAAYX_QFN32_5X5
DMN65D8LDW-7_SOT363-6 DMN65D8LDW-7_SOT363-6 TPM@
RE14

0.1U_0402_25V6
@ 4.7K_0402_5% 1
TPM@
+3VS_TP +3VS_TP TPM_VDD

CE11
1 2

2
+3VS_TPM
1

RE13
RE87 @ 10K_0402_5%

10U_0603_6.3V6M
0.1U_0402_25V6
100K_0402_5%
1 1
2
2

3
DMG2301U-7_SOT23-3
G

G X06.09
2

+3VS_TP PCH_SPI_CS2# 1 TPM@ 2 2

CE75

CE76
1 3 PTP_INT#_R RE132 100_0402_5% QE17
[17,48] PTP_INT# D 2 2
PCH_TPM_CLK_C TPM@
D

1
TPM@ TPM@
JTP
1

TPM_LPM#
QE13 8 @ RE11
8 S
L2N7002WT1G_SC-70-3I2C1_SDA_TP_C 7 10 33_0402_5%
7 G2

1
I2C1_SCK_TP_C 6 9
5 6 G1 RE127 TPM@
5
2

A PTP_INT#_R 4 A
4 1 10K_0402_5%
3
[49] PTP_DIS# 2 3
[48] DAT_TP_SIO @ CE8
2

2
1 27P_0402_50V8J
[48] CLK_TP_SIO 1 2
PESD5V0U2BT_SOT23-3

PESD5V0U2BT_SOT23-3

1 1 ACES_51524-0080N-001
3

@ @
22P_0402_50V8J
CE80

22P_0402_50V8J
CE79

1 1
CE78
22P_0402_50V8J
CE77 EMC@
22P_0402_50V8J DE4
DE5
2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
2 2
EMC@ Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title
@ @
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR
Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
FAN/TP/KB/PWR SW
1

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS Size Document Number
ION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS Custom LA-C361P 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 42 of 71
5 4 3 2 1
 5 4 3 2 1

M.2 Slot-A Key-A (WLAN + BT)

+3VS_WLAN
CONCR_213AAAA32FA
JNGFF1
1 2 W LAN_W IGIG60GHZ_DIS#_R 2 1
3 1 2 4 W LAN_W IGIG60GHZ_DIS# [49]
USB20_P4_R
USB20_N4_R 5 3 4 6 DN1

.1U_0402_16V7K
7 5 6 RB751S40T1G_SOD523-2
7

22U_0603_6.3V6M
1 1
BT_RADIO_DIS#_R 2 1

CN2
BT_RADIO_DIS# [49]

CN1
8 DN2
9 8 10 2 2 RB751S40T1G_SOD523-2
11 9 10 12
D
13 11 12 14 D
15 13 14 16
17 15 16 18
19 17 18 20
21 19 20 22
23 21 22 24
Close to JNGFF
25 23 24 26
CN21 1 2 0.1U_0402_10V7K PCIE_PTX_WLANRX_RE_P1 27 25 26 28
[19] PCIE_PTX_WLANRX_P1 27 28
[19] PCIE_PTX_WLANRX_N1 CN20 1 2 0.1U_0402_10V7K PCIE_PTX_WLANRX_RE_N1 29 30 CLINK_RST# CLINK_RST# [16]
31 29 30 32 CLINK_DATA
31 32 CLINK_DATA [16]
33 34 CLINK_CLK
[19] PCIE_PRX_WLANTX_P1 33 34 CLINK_CLK [16]
35 36
[19] PCIE_PRX_WLANTX_N1 35 36
37 38
39 37 38 40
[17] CLK_PCIE_WLAN 39 40
[17] CLK_PCIE_WLAN# 41 42 SUSCLK_R RN1 1 @ 2 0_0402_5% SUSCLK [18,44]
43 41 42 44
43 44 PCH_PLTRST#_EC [17,23,37,42,44,48,51]
45 46 BT_RADIO_DIS#_R
[17] WLAN_CLK_REQ# 45 46
[44,48] PCIE_WAKE# PCIE_WAKE# 47 48 WLAN_WIGIG60GHZ_DIS#_R
49 47 48 50
51 49 50 52
53 51 52 54
55 53 54 56
57 55 56 58
59 57 58 60 +3VS_WLAN
61 59 60 62
63 61 62 64
65 63 64 66
67 65 66

22U_0603_6.3V6M

.1U_0402_16V7K
67
1 1
69 68

CN6

CN7
GND GND

2 2
CONN@

C C
Reserve for EMI
Close to JNGFF
+3VS_WLAN +3VS_WLAN

1 1
@ CN8 @ CN9
.1U_0402_16V7K 1000P_0402_50V7K
2 2

EMC@
MCM1012B900F06BP_4P
4 3 USB20_P4_R
[19] USB20_P4

1 2 USB20_N4_R
[19] USB20_N4
LN1

X06.33

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
NGFF
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
C LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 43 of 71

5 4 3 2 1
 5 4 3 2 1

+3.3VDX_SSD

M.2 Slot-C Key-M (SSD)

RF Reserved.
JNGFF2 EMC@ EMC@
1 2

4.7U_0603_6.3V6K
CD36

.1U_0402_16V7K
CD38

0.01U_0402_16V7K
CD39

47P_0402_50V8J
CD40

15P_0402_50V8J
CD41
1 2 1 1 1 1 1
3 4
5 3 4 6
[16] PCIE_PRX_SSDTX_N12 5 6
[16] PCIE_PRX_SSDTX_P12 7 8
9 7 8 10 2 2 2 2 2
CD37 1 2 0.22U_0402_10V6K PCIE_PTX_SSDRX_N12_C 11 9 10 12
[16] PCIE_PTX_SSDRX_N12 11 12
CD42 1 2 0.22U_0402_10V6K PCIE_PTX_SSDRX_P12_C 13 14
[16] PCIE_PTX_SSDRX_P12 13 14
15 16
17 15 16 18
[16] PCIE_PRX_SSDTX_N11 17 18
19 20
[16] PCIE_PRX_SSDTX_P11 19 20
21 22
D PCIe SSD CD43 1 2 0.22U_0402_10V6K PCIE_PTX_SSDRX_N11_C 23 21 22 24 D
[16] PCIE_PTX_SSDRX_N11 23 24
CD44 1 2 0.22U_0402_10V6K PCIE_PTX_SSDRX_P11_C 25 26
[16] PCIE_PTX_SSDRX_P11 25 26
27 28
29 27 28 30
[16] PCIE_PRX_SSDTX_N10 29 30
[16] PCIE_PRX_SSDTX_P10 31 32
33 31 32 34
CD45 1 2 0.22U_0402_10V6K PCIE_PTX_SSDRX_N10_C 35 33 34 36 RD7 2 1 10K_0402_5%
[16] PCIE_PTX_SSDRX_N10 35 36 +3.3VDX_SSD
[16] PCIE_PTX_SSDRX_P10 CD46 1 2 0.22U_0402_10V6K PCIE_PTX_SSDRX_P10_C 37 38
39 37 38 40 mSATA_DEVSLP [19]
41 39 40 42
[16] SATA_PRX_SSDTX_P0A 41 42
43 44
[16] SATA_PRX_SSDTX_N0A 43 44
45 46
SATA SSD CD53 1 2 0.22U_0402_10V6K SATA_PTX_SSDRX_N0A_C 47 45 46 48
[16] SATA_PTX_SSDRX_N0A 47 48
CD51 1 2 0.22U_0402_10V6K SATA_PTX_SSDRX_P0A_C 49 50
[16] SATA_PTX_SSDRX_P0A 49 50 PCH_PLTRST#_EC [17,23,37,42,43,48,51]
51 52 SSD_CLK_REQ# [17]
53 51 52 54 SSD_PCIE_WAKE# RD59 1 @ 2 0_0402_5%
[17] CLK_PCIE_SSD# 53 54 PCIE_WAKE# [43,48]
55 56
[17] CLK_PCIE_SSD 55 56
57 58 RD8 1 2 10K_0402_5% +3.3VDX_SSD
57 58

59 60 RD9 1 @ 2 0_0402_5%
59 60 SUSCLK [18,43]
+3VS RD10 1 @ 2 10K_0402_5% 61 62
+3.3VDX_SSD
+3VS 63 61 62 64
65 63 64 66
67 65 66
67
1
@
CD47
0.1U_0402_10V7K
2 68 69
GND GND

UD2
5

S IC TC7SZ14FU SSOP 5P CONCR_213MAAA32FA

1 CONN@
P

4 NC 2 mCARD_PCIE_SATA#
[16] mCARD_PCIE#_SATA Y A
G

@
C
SATA -> High C

PCIe -> Low SATA -> GND

3

PCIe -> OPEN

RD58 1 @ 2 0_0402_5%

X06.19

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
SSD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
C LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 44 of 71

5 4 3 2 1
 5 4 3 2 1

HDD CONN
CONN@
JHDD
1
2 1
3 2
4 3
SATA_PTX_DRX_P1B_RC 5 4
SATA_PTX_DRX_N1B_RC 6 5
7 6
SATA_PRX_DTX_N1B_RC 8 7
SATA_PRX_DTX_P1B_RC 9 8
10 9
FFS_INT2_Q 11 10
D
12 11 D
[16] HDD_DET# 13 12
14 13
15 14
+5VS_HDD 15
16
17 16
18 17
19 18
20 19
21 20
22 GND
23 GND
24 GND
GND
J-L_UCNR2234B020-0

Place near HDD CONN (JHDD1)

+5VS_HDD

1 1 1 1
CS12 CS13 CS14 CS15
1000P_0402_50V7K .1U_0402_16V7K 1U_0402_6.3V6K 10U_0603_6.3V6M
2 2 2 2

C C

[16] SATA_PTX_DRX_P1B SATA_PTX_DRX_P1B CS17 1 2 0.01U_0402_16V7K SATA_PTX_DRX_P1B_RC

SATA_PTX_DRX_N1B CS18 1 2 0.01U_0402_16V7K SATA_PTX_DRX_N1B_RC
[16] SATA_PTX_DRX_N1B

[16] SATA_PRX_DTX_P1B SATA_PRX_DTX_P1B CS19 1 2 0.01U_0402_16V7K SATA_PRX_DTX_P1B_RC

SATA_PRX_DTX_N1B CS20 1 2 0.01U_0402_16V7K SATA_PRX_DTX_N1B_RC
[16] SATA_PRX_DTX_N1B

BYPASS Circuit

Free Fall Sensor

+3VS +3VS_FFS

1 @ 2

RF1 0_0603_5%
X06.28 1 1
CF1 CF2
10U_0603_6.3V6M 0.1U_0402_25V6
B 2 2 B

UF1
LNG3DM 10
1 RES 13
14 VDD_IO RES 15
VDD RES 16
FFS_INT1 11 RES
[19] FFS_INT1 INT 1
FFS_INT2 9 5
[17] FFS_INT2 INT 2 GND 12
7 GND
PCH_SMBDATA 6 SDO/SA0 +5VS
[6,14,15,18] PCH_SMBDATA SDA / SDI / SDO
[6,14,15,18] PCH_SMBCLK PCH_SMBCLK 4
SCL/SPC

1
2
8 NC 3 RF2
CS NC 100K_0402_5%
LNG3DMTR_LGA16_3X3~D
+3VS

2
FFS_INT2_Q

1
RF3
100K_0402_5%

3
2
+3VS_FFS QF1B
5 DMN65D8LDW-7_SOT363-6

RF4 1 2 100K_0402_5% FFS_INT1

4
6
RF5 1 2 100K_0402_5% FFS_INT2
QF1A
FFS_INT2 2 DMN65D8LDW-7_SOT363-6

1
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
DC/DC INTERFACE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
C LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 45 of 71

5 4 3 2 1
 5 4 3 2 1

USB Powershare
Device Control Pins CTL1 = 0 : Enable Power Share DCP mode in Suspend ode
m
Flow Line
Condition Suspend mode
CTL1 CTL2 CTL3 ILIM_SEL
CTL1 = 1 : Disable Power Share in Suspend mode (ForSupport USB wake)
0 1 1 X DCP AUTO
D D
ILIM_SEL = 0 : SDP mode (0.9A by ILIM_LO setting)
1 1 1 0 SDP
S0 mode
1 1 1 1 CDP ILIM_SEL = 1 : CDP mode (STATUS# trigger by ILIM_HI=2.2A)

+3VALW
USB3.0 / USB2.0 Port1 (Right Side)
RI30 1 2 100K_0402_5% ILIM_SEL_R
+5VALW
RI9 1 2 100K_0402_5% USB_R_CTL

RI10 1 2 100K_0402_5% USB_PWR_SHR_EN_R# 1

RI13 1 2 10K_0402_5% USB_PWR_SHR_VBUS_EN_R +3VALW CI2
0.1U_0402_25V6
CI22 2 +5V_CHGUSB_1
1 2

0.1U_0402_10V7K 2.1A
UI2

5
UI5 1 12
C USB_PWR_EN 1 USB_STATUS#_R 9 IN OUT 10 USBP1_D+ C
USBP1_D+ [47]

P
INB 4 USB_PWR_EN_R 13 STATUS# DP_IN 11 USBP1_D-
O [19] USB_OC0# FAULT# DM_IN USBP1_D- [47]
USB_PWR_SHR_VBUS_EN_R 2 ILIM_SEL_R 4 2
[47,49] USB_PWR_SHR_VBUS_EN_R INA ILIM_SEL DM_OUT USB20_N1 [19]

1
USB_PWR_EN_R 5 3
EN DP_OUT USB20_P1 [19]
MC74VHC1G32DFT2G_SC70-5~D RI27 USB_PWR_SHR_EN_R# 6 15 ILIM_LO1 RI11 1 2 33K_0402_1%
[49] USB_PWR_SHR_EN_R# CTL1 ILIM_LO

3
1M_0402_5% 7 16 ILIM_HI1 1 2
USB_R_CTL 8 CTL2 ILIM_HI 14 RI12 22.1K_0402_1%
CTL3 GND 17
T-PAD

2
TPS2546RTER_QFN16_3X3

RI28 1 @ 2 0_0402_5%

USB3.0 / USB2.0 Port2 (Left Side)

+3VALW

RI31 1 2 100K_0402_5% ILIM_SEL_L

RI4 1 2 100K_0402_5% USB_L_CTL +5VALW

RI5 1 2 100K_0402_5% USB_PWR_SHR_EN_L#

1
RI8 1 2 10K_0402_5% USB_PWR_SHR_VBUS_EN_L
CI1 +5V_CHGUSB_2
0.1U_0402_25V6

2.1A
+3VALW 2

CI21 UI1
1 2 1 12
B USB_STATUS#_L 9 IN OUT 10 B
STATUS# DP_IN USBP2_D+ [47]
0.1U_0402_10V7K 13 11
[19] USB_OC1# FAULT# DM_IN USBP2_D- [47]
ILIM_SEL_L 4 2
ILIM_SEL DM_OUT USB20_N2 [19]
5

UI4 USB_PWR_EN_L 5 3
EN DP_OUT USB20_P2 [19]
USB_PWR_EN 1 USB_PWR_SHR_EN_L# 6 15 ILIM_LO3 RI6 1 2 33K_0402_1%
[20] USB_PWR_EN [48] USB_PWR_SHR_EN_L#
P

INB 4 USB_PWR_EN_L 7 CTL1 ILIM_LO 16 ILIM_HI3 1 2

USB_PWR_SHR_VBUS_EN_L 2 O USB_L_CTL 8 CTL2 ILIM_HI 14 RI7 22.1K_0402_1%
[49] USB_PWR_SHR_VBUS_EN_L INA CTL3 GND
G

17
T-PAD
1

MC74VHC1G32DFT2G_SC70-5~D
3

RI26
1M_0402_5% TPS2546RTER_QFN16_3X3
2

X06.17
DI12
2 ILIM_SEL_R RI32 1 @ 2 0_0402_5% USB_STATUS#_L

1
[49] USB_ILIM_SEL
3 ILIM_SEL_L RI33 1 @ 2 0_0402_5% USB_STATUS#_R

BAT54CW-7-F_SOT323-3~D

RI35 1 @ 2 0_0402_5% ILIM_SEL_R RI34 1 @ 2 0_0402_5% ILIM_SEL_L

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
USB Powershare
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS Size
ION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C. LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 46 of 71

5 4 3 2 1
 5 4 3 2 1

USB3.0 Re-driver
+3VS +3V_PS8723 +3V_PS8723
Equalizer control and program for channel A1&A2/B1&
B2
RI14 1 2 0_0805_5% A_EQ0 RI15 1 2 10K_0402_5% Ω
3.3V tolerant. Internally pulled down at ~150K
@ A_EQ1 @ RI16 1 2 0_0402_5% [EQ1, EQ0] ==
LL: equalization for channel loss up to 9.5dB (defa
ult)

0.01U_0402_16V7K
X06.15 LH: equalization for channel loss up to 13 dB

0.1U_0402_10V7K
+3V_PS8723 HL: equalization for channel loss up to 4.5dB
1 1 HH: equalization for channel loss up to 7.5dB
UI3 B_EQ0 RI17 1 2 10K_0402_5%
1 B_EQ1 @ RI18 1 2 0_0402_5%
D 2 2 +3V_PS8723 VDD D
13
CI3

CI4
VDD

A_EQ1 15 4 B_EQ1 +3V_PS8723

A_DE0 16 A_EQ1/SDA_CTL B_EQ1/I2C_ADDR1 3 B_DE0 Programmable output de-emphasis level setting for hcannel A1&A2/B1&B2
A_EQ0 17 A_DE0/SCL_CTL B_DE0/I2C_ADDR0 2 B_EQ0 A_DE0 @ RI19 1 2 4.7K_0402_5% Ω
3.3V tolerant. Internally pulled down at ~150K
A_DE1 18 A_EQ0/NC B_EQ0/NC 6 B_DE1 A_DE1 @ RI20 1 2 4.7K_0402_5% [DE1, DE0] ==
A_DE1/NC B_DE1/NC LL: 3.5dB de-emphasis (default)
+3V_PS8723 LH: No de-emphasis
[19] USB3TP1 CI5 1 2 0.1U_0402_10V7K USB3TP1_C 19 12 USB3TP1_RE
HL: 2.7dB de-emphasis
CI6 1 2 0.1U_0402_10V7K USB3TN1_C 20 A_INp A_OUTp 11 USB3TN1_RE
[19] USB3TN1 A_INn A_OUTn HH: 5.0dB de-emphasis
B_DE0 @ RI21 1 2 4.7K_0402_5%
B_DE1 @ RI22 1 2 4.7K_0402_5%
USB3RP1_RE 9 22 USB3RP1_C 0.1U_0402_10V7K 2 1CI7
B_INp B_OUTp USB3RP1 [19]
USB3RN1_RE 8 23 USB3RN1_C 0.1U_0402_10V7K 2 1CI8
B_INn B_OUTn USB3RN1 [19] +3V_PS8723
X06.15 0_0402_5% LFPS swing adjust.
[46,49] USB_PWR_SHR_VBUS_EN_R DI11 1 2RB751S40T1G_SOD523-2 2 @ 1 RI36 5 USB8723_test @ RI24 1 2 4.7K_0402_5% Ω.
3.3V tolerant. Internally pulled down at ~150K
2 1 7 PD# 10 TST ==
4.99K_0402_1% RI23 USB8723_test 14 REXT GND 21 L: Normal LFPS swing (default)
2 @ 1 I2C_EN8723 24 TEST GND 25 H: Tune down LFPS swing
0_0402_5% RI25 I2C_EN GPAD
PS8713BTQFN24GTR2_TQFN24_4X4
X06.15

USB3.0 / USB2.0 Port1 (Right Side)

LI2
USBP1_D- 1 2 USBP1_R_D-
C [46] USBP1_D- C

USBP1_D+ 4 3 USBP1_R_D+
[46] USBP1_D+
MCM1012B900F06BP_4P +5V_CHGUSB_1
DI9 EMC@ JUSB2
EMC@
USB3RN1_D- 1 1 10 9 USB3RN1_D- USB3TP1_D+ 9
1 SSTX+
2 2 VBUS
USB3RP1_D+ 9 8 USB3RP1_D+ USB3TN1_D- 8
SSTX-
USBP1_R_D+ 3
4 4 D+
USB3TN1_D- 7 7 USB3TN1_D- 7

10U_0603_6.3V6M

0.1U_0402_25V6
1 1 1 GND
USB3TN1_RE 1 2 USB3T_N1 RI37 1 @ 2 0_0402_5% USB3TN1_D- USBP1_R_D- 2 11

CI18
5 5 D- GND
CI16 0.1U_0402_10V7K USB3TP1_D+ 6 6 USB3TP1_D+ CI17 USB3RP1_D+ 6 12

CI19
4 SSRX+ GND 13
47U_0805_6.3V6M GND GND
2 2 2

3
USB3TP1_RE 1 2 USB3T_P1 RI38 1 @ 2 0_0402_5% USB3TP1_D+ 3 3 USB3RN1_D- 5 14
CI20 0.1U_0402_10V7K 10 SSRX- GND

DI10 EMC@
AZ5125-02S.R7G_SOT23-3
[48] USB_DET#_R Plug_DET
8
TAIWI_USB019-107CRL-TWD
CONN@
AZ1045-04F_DFN2510P10E-10-9

Place close to JUSB2

1
USB3RP1_RE RI39 1 @ 2 0_0402_5% USB3RP1_D+

USB3RN1_RE RI40 1 @ 2 0_0402_5% USB3RN1_D-

X06.15
B B

LI5
USB3.0 / USB2.0 Port2 (Left Side)
USBP2_D- 1 2 USBP2_R_D-
[46] USBP2_D-

USBP2_D+ 4 3 USBP2_R_D+
[46] USBP2_D+
MCM1012B900F06BP_4P +5V_CHGUSB_2
DI7 EMC@ JUSB1
EMC@
USB3RN2_D- 1 1 10 9 USB3RN2_D- USB3TP2_D+ 9
1 SSTX+
2 2 VBUS
USB3RP2_D+ 9 8 USB3RP2_D+ USB3TN2_D- 8

10U_0603_6.3V6M
USBP2_R_D+ 3 SSTX-
4 4 D+
USB3TN2_D- 7 7 USB3TN2_D- 7

0.1U_0402_25V6
1 1 1 GND
1 2 USB3T_N2 RI41 1 @ 2 0_0402_5% USB3TN2_D- USBP2_R_D- 2 11

CI12
[19] USB3TN2 D- GND
CI9 0.1U_0402_10V7K USB3TP2_D+ 5 5 6 6 USB3TP2_D+ CI11 USB3RP2_D+ 6 12

CI13
4 SSRX+ GND 13
47U_0805_6.3V6M GND GND
2 2 2

3
1 2 USB3T_P2 RI42 1 @ 2 0_0402_5% USB3TP2_D+ 3 3 USB3RN2_D- 5 14
[19] USB3TP2 SSRX- GND
CI10 0.1U_0402_10V7K 10

DI8 EMC@
AZ5125-02S.R7G_SOT23-3
[48] USB_DET#_L Plug_DET
8
TAIWI_USB019-107CRL-TWD
CONN@
AZ1045-04F_DFN2510P10E-10-9

Place close to JUSB1

1
A RI43 1 @ 2 0_0402_5% USB3RP2_D+ A
[19] USB3RP2

[19] USB3RN2 RI44 1 @ 2 0_0402_5% USB3RN2_D-

X06.15 Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
USB conn.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS Size
ION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C. LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 47 of 71

5 4 3 2 1
 A B C D E F G H

+RTCVCC X06.14 +3VALW_5085

+3VS
RE16 1 @ 2 0_0402_5% +RTC_CELL_VBAT
+RTCVCC

0.1U_0402_25V6
RP19

1
BC_DAT_ECE1117 1 8

1
PTP_INT#_EC 2 7

CE17
RE137 RE136 3 6

2
5.1K_0402_1% 5.1K_0402_1% BATBTN# 4 5
+3VALW_5085

2
100K_0804_8P4R_5%

2
UPD_GPU_SMBDAT 6 1 +3VALW_5085

0.1U_0402_25V6

1U_0402_6.3V6K
I2C0_SDA_DSP [20,52]

5
1

1
QE18A

CE18
+3VALW_5085 UPD_GPU_SMBCLK 3 4 PCIE_W AKE# RE19 1 2 10K_0402_5%

CE19
+3VALW_5085 DMN65D8LDW -7_SOT363-6 I2C0_SCK_DSP [20,52]
USBC_MCP23017_SMBDATRE20 1 2 2.2K_0402_5%

2
USBC_MCP23017_SMBCLKRE21 1 2 2.2K_0402_5%
RE17 1 2 2.2K_0402_5% PBAT_SMBDAT QE18B CHARGER_SMBDAT RE22 1 2 10K_0402_5%
RE18 1 2 2.2K_0402_5% PBAT_SMBCLK DMN65D8LDW -7_SOT363-6 CHARGER_SMBCLK RE23 1 2 10K_0402_5%
THERMATRIP3# RE25 1 2 10K_0402_5%
UPD_GPU_SMBDAT RE94 1 2 2.2K_0402_5%
UPD_GPU_SMBCLK RE95 1 2 2.2K_0402_5%

1U_0402_6.3V6K
0.1U_0402_25V6
SIO_EXT_SMI# RE1401 @ 2 10K_0402_5%
+3VS_TP

1
1 UE3 PD_I2C_ALERT# RE99 1 2 10K_0402_5% 1

CE20

CE21
X06.14

2
RE24 1 2 4.7K_0402_5% CLK_TP_SIO B64 A10 VGA_ID RE112 1 @ 2 0_0402_5%
BID_DIS [20]
RE26 1 2 4.7K_0402_5% DAT_TP_SIO VBAT GPIO021/RC_ID1 B10 BOARD_ID MSDATA RE27 1 @ 2 10K_0402_5%
GPIO020/RC_ID2 B8 PCIE_W AKE# SUS_ON_EC RE30 1 2 100K_0402_5%
+3VALW +3VALW_5085 GPIO014/GPTP-IN7/RC_ID3 PCIE_W AKE# [43,44]
A22 B27
H_VTR GPIO025/UART_CLK LAN_W AKE# [18]
B44 HOST_DEBUG_TX
PJP1205 GPIO120/UART_TX/V2P_COUT_HI1 B46
GPIO124/GPTP-OUT5/UART_RX/V2P_COUT_LO1 PCH_PCIE_W AKE# [18]
1 2 A58 B26 RUNPWROK
VTR_ADC VCC_PW RGD RUNPW ROK [18]
RE31 1 @ 2 10K_0402_5% PCH_PLTRST#_EC A25
RE32 1 2 100K_0402_5% LCD_TST PAD-OPEN1x1m GPIO060/KBRST/BCM_B_INT# B36 SIO_SLP_S4#
EN_INVPW R [35] X06.14

10U_0603_6.3V6M

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
GPIO101/ECGP_SCLK SIO_SLP_S4# [18,34,52]
RE33 1 @ 2 10K_0402_5% RESET_OUT# @ B3 B37 PTP_INT#_EC
VTR GPIO103/ECGP_MISO

1
A11 B38 0_0402_5% 2 @ 1 RE118
VTR GPIO105/ECGP_MOSI AUX_EN_W OW L [33] BAT1_LED# [52]

CE23
A26 A34
Amber

CE22

CE24

CE25

CE26

CE27

CE28
VTR GPIO102/BCM_C_INT# PCH_ALW _ON [33,34,58]
B35 A35 SIO_SLP_S3# MSDATA_R 0_0402_5% 2 @ 1 RE102 MSDATA
VTR GPIO104/SLP_S0# SIO_SLP_S3# [18,34,37,52]

2
A41 A36
VTR GPIO106 PCH_DPW ROK [18]
A52 A40 MSDATA_R MSCLK_R 0_0402_5% 2 @ 1 RE103 MSCLK
VTR GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP B43 MSCLK_R
GPIO117/MSCLK/V2P_COUT_HI A45 0_0402_5% 2 @ 1 RE119
GPIO127/A20M B65 FW P#
PCH_RSMRST# [6,18] BAT2_LED# [52] White
A5 nFW P
[18] SML1_SMBDAT GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA
B6
+RTCVCC
Connect PCH [18] SML1_SMBCLK
CLK_TP_SIO A37 GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_DATA0 B57
HDA_I2S_SEL = Low ; HDA Mode [42] CLK_TP_SIO GPIO110/PS2_CLK2/GPTP-IN6 GPIO156/LED1/GANG_DATA1 PW RBTN_LED# [42]
DAT_TP_SIO B40 B1
HDA_I2S_SEL = High ; I2S Mode Connect Touch Pad [42] DAT_TP_SIO
LCD_TST A38 GPIO111/PS2_DAT2/GPTP-OUT6 GPIO157/LED0 A55
ME_FW P_EC [18]
[35] LCD_TST GPIO112/PS2_CLK1A GPIO153/LED2/GANG_DATA4 USB_PW R_SHR_EN_L# [46]
1

B41 A1 PCIE_W AKE# 0_0402_5% 2 @ 1 RE120

[23] GPU_PW R_LEVEL GPIO113/PS2_DAT1A GPIO027/GPTP-OUT1 IMVP_VR_ON [34] TBT_PCIE_W AKE# [37]
RE34 A39 B28
[33] LCD_VCC_TEST_EN GPIO114/PS2_CLK0A GPIO026/GPTP-IN1 SIO_SLP_A# [18,52]
100K_0402_5% SPK_DET#_EC B42 B2
[54] PBAT_SMBDAT PBAT_SMBDAT B59 GPIO115/PS2_DAT0A GPIO001/ECSPI_CS1/32KHZ_OUT A8
VBUS_HV_DIS#
ME_SUS_PW R_ACK
[55]
[18]
X06.37
2 1 RE110 PBAT_SMBCLK A56 GPIO154/I2C1C_DATA/PS2_CLK1B/GANG_DATA5 GPIO015/GPTP-OUT7 B9 RUN_ON
[39] PWR_TB_DOCK# Connect Battery [54] PBAT_SMBCLK GPIO155/I2C1C_CLK/PS2_DAT1B/GANG_DATA6 GPIO016/GPTP-IN8
2

10K_0402_5% A9 SUS_ON
POW ER_SW _IN# JTAG_TDI A51 GPIO017/GPTP-OUT8 B39 RESET_OUT#
GPIO145/I2C1K_DATA/JTAG_TDI GPIO107/NRESET_OUT RESET_OUT# [6,18]
JTAG_TDO B55 A44 UPD_MRESET 100K_0402_5% 1 2 RZ41
GPIO146/I2C1K_CLK/JTAG_TDO GPIO125/GPTP-IN5/PECI_REQUEST#/GANG_BUSY H_VCCST_PW RGD_EC [34]
2 1 RE36 JTAG_CLK B56
[42,52] PBTN_SW# A53 GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK A54
1K_0402_5% JTAG_TMS AC_PRESENT [18]
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS GPIO151/GPTP-IN4/GANG_DATA2
1

JTAG_RST# B47 B58

JTAG_RST# GPIO152/GPTP-OUT4 SIO_PW RBTN# [6,18]
1

CE30 1 @ 2 SPK_DET#_EC
[20,52] SPK_DET#
CE29 1U_0402_6.3V6K 0_0402_5% RE139 B22 A3 USBC_MCP23017_SMBDAT
[42] FAN1_TACH GPIO050/FAN_TACH1/GTACH0/GANG_START GPIO003/I2C1A_DATA USBC_MCP23017_SMBDAT [49]
2

LID_CL_SIO# A21 B4 USBC_MCP23017_SMBCLK

1U_0402_6.3V6K GPIO051/FAN_TACH2/GANG _MODE GPIO004/I2C1A_CLK USBC_MCP23017_SMBCLK [49] MCP23017
2

B23 A4 UPD_MRESET
@ [42] FAN2_TACH GPIO052/FAN_TACH3/GTACH1/GANG_ERROR GPIO005/I2C1B_DATA/BCM_B_DAT UPD_MRESET [37,39]
1 @ 2 B_PW M_EC B24 B5
[35] BIA_PW M_EC [54] PS_ID GPIO053/PW M0 GPIO006/I2C1B_CLK/BCM_B_CLK SIO_EXT_W AKE# [20]
0_0402_5% RE122 A23 B7
[42] FAN2_PW M GPIO054/PW M1/GPW M1 GPIO012/I2C1H_DATA/I2C2D_DATA SUSACK# [18]
B_PW M_EC B25 A7
GPIO055/PW M2 GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA3 ENVDD_PCH [16,33]
A24 B48 UPD_GPU_SMBDAT
X06.14 [42] FAN1_PW M GPIO056/PW M3/GPW M0 GPIO130/I2C2A_DATA/BCM_C_DAT B49 UPD_GPU_SMBCLK
UPD_GPU_SMBDAT [23,39] UPD + GPU
GPIO131/I2C2A_CLK/BCM_C_CLK UPD_GPU_SMBCLK [23,39]
+3VALW_5085 A47 CHARGER_SMBDAT
GPIO132/I2C1G_DATA CHARGER_SMBDAT [56]
B50 CHARGER_SMBCLK PTP_INT#_EC 2 1
A43 GPIO140/I2C1G_CLK B52
CHARGER_SMBCLK
RE111 1
[56]
2 43K_0402_1%
Charger 0_0402_5%
@
RE138
PTP_INT# [17,42]
[17] EC_SLP_S0IX#
B45 GPIO123/BCM_A_CLK GPIO141/I2C1F_DATA/I2C2B_DATA A49
PBAT_PRES# [54,56]
SIO_SLP_SUS# [18] X06.14
DE11 [18] SIO_SLP_WLAN# GPIO122/BCM_A_DAT GPIO142/I2C1F_CLK/I2C2B_CLK
1

PD_I2C_ALERT# A42 B53 EDP_CTRL_EN

100K_0402_5%

1 2 [39] PD_I2C_ALERT# B20 GPIO121/BCM_A_INT# GPIO143/I2C1E_DATA A50

[55] DCIN_ACOK ACAV_IN_NB ACAV_IN_NB AC_DIS [55,56]
A18 GPIO032/BCM_E_CLK GPIO144/I2C1E_CLK
RE41

2
[18,34,52] SIO_SLP_S5# GPIO031/GPTP-OUT2/BCM_E_DAT 2
B19 A59 1 2
RB751S40T1G_SOD523-2 [52] BEEP GPIO030/GPTP-IN2/BCM_E_INT#/GANG_DATA7 SYSPW R_PRES +3VLP
A20 RE43 1K_0402_5% SIO_SLP_S3# 2 @ 1 RUN_ON_EC
[52] BC_CLK_ECE1117 GPIO047/LSBCM_D_CLK RUN_ON_EC [33,34]
2

1
BC_DAT_ECE1117 B21 B62 0_0402_5% RE35

100K_0402_5%
[52] BC_DAT_ECE1117 GPIO046/LSBCM_D_DAT/GANG_STROBE BGP0
A19 A64 ACAV_IN
[52] BC_INT#_ECE1117 GPIO045/LSBCM_D_INT# VCI_OVRD_IN ACAV_IN [56]
1 2 LID_CL_SIO# A60 ALW ON RUN_ON 2 @ 1

RE44
[52] LID_SW_IN# VCI_OUT ALW ON [57]
10_0402_5% RE45 SIO_EXT_SMI# A6 B67 POWER_SW_IN# 0_0402_5% RE37
1
[17]
[19]
SIO_EXT_SMI#
SIO_RCIN#
A27 GPIO011/nSMI VCI_IN0# A63 BATBTN# BATBTN# [50]
X06.14
GPIO061/LPCPD# VCI_IN1#

2
A28 B63 USB_DET_EC#_R
[19] IRQ_SERIRQ SER_IRQ VCI_IN2#
CE31 PCH_PLTRST#_EC B30 B68 USB_DET_EC#_L
[17,23,37,42,43,44,51] PCH_PLTRST#_EC LRESET# VCI_IN3#
0.047U_0402_25V7K CLK_PCI_MEC A29
2 [19] CLK_PCI_MEC PCI_CLK
LPC_FRAME# B31 B51 SIO_SLP_S4# 2 @ 1 SUS_ON_EC
[19] LPC_FRAME# LFRAME# VREF_PECI +VCCIO SUS_ON_EC [33,34]
LPC_AD0 A30 A48 EC_PECI 1 2 0_0402_5% RE38
[19] LPC_AD0 LAD0 PECI_DAT H_PECI [9,16]
LPC_AD1 B32 RE48 33_0402_5%

0.1U_0402_25V6
[19] LPC_AD1 LAD1
LPC_AD2 A31 B13 REM_DIODE1_N CE32 1 2 2200P_0402_25V7K SUS_ON 2 @ 1
[19] LPC_AD2 LAD2 DN1_DP1A/THERM X06.14

1
LPC_AD3 B33 A13 REM_DIODE1_P 0_0402_5% RE39

CE34
[19] LPC_AD3 LAD3 DP1_DN1A/VREF_T
A32 B14 REM_DIODE2_N CE33 1 2 2200P_0402_25V7K
[18] CLKRUN# CLKRUN# DN2_DP2A
+RTCVCC A33 A14 REM_DIODE2_P EDP_CTRL_EN 2 @ 1
[20] SIO_EXT_SCI# GPIO100/NEC_SCI DP2_DN2A EDP_CTRL_EN_C [35]

2
A15 REM_DIODE3_N CE35 1 2 2200P_0402_25V7K 0_0402_5% RE107
MEC_XTAL1 A61 DN3_DP3A B16 REM_DIODE3_P
XTAL1 DP3_DN3A
1

MEC_XTAL2 2 @ 1 MEC_XTAL2_R A62 A16 REM_DIODE4_N CE36 1 2 2200P_0402_25V7K

100K_0402_5%

+3VS RE51 0_0402_5% XTAL2 DN4_DP4A B17 REM_DIODE4_P

RE50

DP4_DN4A B15
X06.14 VIN A17
CE58, CE39, CE60, Place near UE5
VSET_5085 USBC_MCP23017_SMBDAT 0_0402_5% 2 @ 1 RE108
10K_0402_5%

VSET DOCK_TNY_SMB_DAT [35,39]

1

A12 EC_PECI USBC_MCP23017_SMBCLK 0_0402_5% 2 @ 1 RE109

VCP I_ADP [56] DOCK_TNY_SMB_CLK [35,39]
2

B34 THERMATRIP2# @
RE52

2 1 USB_DET_EC#_R +3VALW THERMTRIP2# A2 THERMATRIP3#

47P_0402_50V8J
CE39
[47] USB_DET#_R GPIO002/THERMTRIP3# THERMATRIP3# [23] 1
10K_0402_5% RE54 B29 THSEL_STRAP

VSS_ADC
GPIO024/THSEL_STRAP

VSS_RO
A46 H_PROCHOT#_EC RE96 1 2 100_0402_5%

VR_CAP
1U_0402_6.3V6K

100K_0402_5%

PROCHOT_IN#/PROCHOT_IO# H_PROCHOT# [9,56,64]

H_VSS
2
1

B61 1 2

AGND
RUNPWROK I_BATT [56]
V_ISYS0 2

VSS
CE37 A57 RE55 4.7K_0402_5%
CE38

RE56

EP
V_ISYS1 P_SYS [56,64]
1U_0402_6.3V6K
2

@ MEC5085-LZY-HST01_DQFN132_11X11

B66

B11

B60

+VR_CAP B12

B54

B18

C1
3
2

RUN_ON#
QE4B 15mil
5 DMN65D8LDW -7_SOT363-6
6

+RTCVCC

4.7U_0603_6.3V6K
4

Setting for Thermal Design

1
QE4A
1

RUN_ON_EC 2 DMN65D8LDW -7_SOT363-6

100K_0402_5%

CE40
RE90

2
1

ESR <2ohms
Thermal diode mapping
2

2 1 USB_DET_EC#_L
[47] USB_DET#_L
10K_0402_5% RE89 5085 Channel Location 5085 Channel Location
1U_0402_6.3V6K
1

CE71 DP1A/DN1A FAN1 DP1/DN1 OTP

CE70

1U_0402_6.3V6K
2

3 3
@ DP2A/DN2A Skin1 DP2/DN2 Skin2
VSET_5085

32 KHz Clock DP3A/DN3A JDIMM DP3/DN3 AR

0.1U_0402_25V6

1
YE1

1
RE58
+3VALW_5085 DP4A/DN4A SSD DP4/DN4 FAN2 1.33K_0402_1%

CE41
MEC_XTAL1 1 2 MEC_XTAL2
1 2

2
REM_DIODE1_P
X06.36

2
1
100K_0402_5%

1 1 QE7
32.768KHZ_12.5PF_CM7V-12520

100P_0402_50V8J
E MMBT3904W H_SOT323-3

1
CE42 CE43 C
RE59

100P_0402_50V8J
B

2
22P_0402_50V8J 22P_0402_50V8J 2 2

@ CE45
2 2 B

@ CE69
JDEG
C
2

1
E QE15

3
+3.3V_ALW _DEG +3VALW_5085 MMBT3904W H_SOT323-3
RE60 JTAG_RST# REM_DIODE1_N
Rest=1.33K , Tp=93 degree C
2 1
Place QE7 For FAN1 Place QE15 For OTP
1

49.9_0402_1% CLK_PCI_MEC
+3VALW_5085
8
7
6
5
10K_8P4R_5%

1U_0402_6.3V6K

EMC@ RE62
1

1
@SHORT PADS~D
JTAG1 @

100_0402_1%

10_0402_5%
1
RP20

@ RE61

REM_DIODE2_P THSEL_STRAP 1 2
CE44
1

RE57 1K_0402_5%
10K_0402_5%

10K_0402_5%

100K_0402_5%

QE5
1
2
3
4

JDEG1
@ RE65

100P_0402_50V8J
E
2

2
MMBT3904W H_SOT323-3

1
1 @ C
RE63

RE64

4.7P_0402_50V8C
EMC@ CE48

@ CE46

100P_0402_50V8J
1 B

1
2 JTAG_TDI 2 2

@ CE47
2

2 3 JTAG_TMS B
3 C
2

2
1
4 JTAG_CLK E QE6
4 1: Channel 1 will provide Thermistor Readings

3
5 JTAG_TDO MMBT3904W H_SOT323-3
11 5 6
G1 6
MSCLK REM_DIODE2_N 0: Channel 1 will provide Diode Readings

2
12 7 MSDATA
G2 7 8 HOST_DEBUG_TX EMI depop location
8 9
Place QE5 close to BOT Skin1 Place QE6 close to BOT Skin2
9 UARTT0_TX [20]
10
10 Pin8 5085_TXD for EC Debug
Place close pin A29
HB_A531015-SCHR21 pin9 5048_TXD for SBIOS
CONN@ debug REM_DIODE3_P +3VALW_5085
QE8

100P_0402_50V8J
E MMBT3904W H_SOT323-3

1
C

@ CE49

100P_0402_50V8J

8.2K_0402_5%
B

1
2 2
RE67 CE51 REV +3VALW_5085 +3VALW_5085

@ CE68
B

RE66
C

2
+3VS E QE11

3
JLPDE1
130K 4700p X00 MMBT3904W H_SOT323-3
1

1 REM_DIODE3_N
1

2
2
3
2
3 LPC_AD0 62K 4700p X01 RE67
1K_0402_5%
RE68
10K_0402_5% Place QE8 close to JDIMM Place QE11 close to Alpine Ridge
4
4
5
5
LPC_AD1
LPC_AD2 33K 4700p X02 X06.07 THERMATRIP2#
2

11 6 +VCCIO
8.2K 4700p X03
4 LPC_AD3 4
12 G1 6 7 LPC_FRAME# BOARD_ID FWP# REM_DIODE4_P

0.1U_0402_25V6
G2 7

1
8 PCH_PLTRST#_EC
4.3K 4700p X04
C
8 9 QE12 1 2 2

100P_0402_50V8J

100P_0402_50V8J
9 E MMBT3904W H_SOT323-3
2

1
2K 4700p X05
10 C RE69 2.2K_0402_5% B

CE52
10 PCI_CLK_LPC1 [19] B
1

2
CE51 2 2 QE10 E
@

@ CE72

@CE50

3
HB_A531015-SCHR21
1K 4700p A00 4700P_0402_25V7K RE70 MMBT3904W H_SOT323-3
B
C

2
CONN@ 10K_0402_5% E QE9
2

3
MMBT3904W H_SOT323-3
1

REM_DIODE4_N
[9,16] H_THERMTRIP#_R
Place QE12 For SSD Place QE9 close to FAN2
BOARD_ID rise time is measured from 5%~68%.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
HD Audio ALC3661/Audio Jack
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
O UT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 48 of 71
A B C D E F G H
 A B C D E

+3VALW +3VALW _23017

PJP1206
1 2
+3VALW _23017
PAD-OPEN1x1m

10U_0603_6.3V6M

0.1U_0402_25V6

0.1U_0402_25V6
1
1 @ 1

1
CE53
RE71 1 2 100K_0402_5% WLAN_WIGIG60GHZ_DIS#

CE54

CE55
2
RE72 1 2 100K_0402_5% BT_RADIO_DIS#

2
5
UE4

VDD
4 17
[35] PANEL_BKEN_EC GPB7 GPA0 USB_PWR_SHR_VBUS_EN_L [46]
[46] USB_ILIM_SEL 3 18 USB_PWR_SHR_VBUS_EN_R [46,47]
2 GPB6 GPA1 19
[55] PWR_SRC_ON GPB5 GPA2 USB_PWR_SHR_EN_R# [46]
[50] BATT_LED#_LV5 1 20 NB_MUTE# [52]
28 GPB4 GPA3 21
[50] BATT_LED#_LV4 GPB3 GPA4 PTP_DIS# [42]
27 22 WLAN_WIGIG60GHZ_DIS#
[50] BATT_LED#_LV3 GPB2 GPA5 W LAN_W IGIG60GHZ_DIS# [43]
[50] BATT_LED#_LV2 26 23 BT_RADIO_DIS#
25 GPB1 GPA6 24 BT_RADIO_DIS# [43]
[50] BATT_LED#_LV1 GPB0 GPA7 TP_PW_EN [42]

[48] USBC_MCP23017_SMBDAT 9
8 SDA
[48] USBC_MCP23017_SMBCLK SCL
16
15 INTA
INTB
Device Address: RE73 1 2 10K_0402_5% 11 10
b 0,1,0,0,A2,A1,A0,0 +3VALW _23017
RE74 1 2 10K_0402_5% 12 A0 NC/SO 7
A1 NC
0x42 RE75 1 2 10K_0402_5% 13
A2
14 6
RESET VSS(Ground)

+3VALW _23017 RE76 1 2 10K_0402_5%

MCP23017T-E-ML_QFN28_6X6

2
Ensure rise time within 66ms. 2
(fast than 0.05V/ms)

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
AMP TPA3113/SPK conn.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
C
LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 49 of 71

A B C D E
 5 4 3 2 1

BATT LED Power Button Battery Gauge LED

+5VALW
3 SW2 1
[48] BATBTN#
RP24 @ +5VALW

3
6 5
DL1 7 4
AZ5125-02S.R7G_SOT23-3 4 2 8 3
EMC@ 9 2
NTC311-EA1T-A160T_4P 10 1
+5VALW

2
D D
10K_1206_10P8R_5% LED5
27-21-T3D-CP1Q2B16Y-3C_WHITE

2
1
LED4
27-21-T3D-CP1Q2B16Y-3C_WHITE

2
LED3
27-21-T3D-CP1Q2B16Y-3C_WHITE

2
RL1 1 2 820_0402_5% BAT_LED#_LV5
[49] BATT_LED#_LV5
[49] BATT_LED#_LV4 LED2
[49] BATT_LED#_LV3 27-21-T3D-CP1Q2B16Y-3C_WHITE

2
[49] BATT_LED#_LV2
[49] BATT_LED#_LV1 LED1
RL2 1 2 820_0402_5% BAT_LED#_LV4 27-21-T3D-CP1Q2B16Y-3C_WHITE

1
EC GPIO set to OD output

1
RL3 1 2 820_0402_5% BAT_LED#_LV3

RL4 1 2 820_0402_5% BAT_LED#_LV2

RL5 1 2 820_0402_5% BAT_LED#_LV1

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
LED indicator
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
C
LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 50 of 71

5 4 3 2 1
 5 4 3 2 1

Card Reader +3VS_CR

Pin11, Pin12 trace fixed width is 40 mils.

Pin27 trace fixed width is 30mils.
Pin10, pin14, pin18 trace fixed width is 20 mils.
Pin 9 trace fixed width is 12 mils.

0.1U_0402_10V7K

10U_0603_6.3V6M

4.7U_0603_6.3V6K

0.1U_0402_10V7K
Trace routing length < 200mils. 1 1 1
Close to pin27 (3V3_AUX)

1
CR1

CR4
Via size: Pad>=28 mils, Finished hole>=16 mils.

CR12

CR11
2 2 2

2
D D

27
11
UR1
+ODR_PWR

3V3_IN
3V3aux
1 12
[17,23,37,42,43,44,48] PCH_PLTRST#_EC PERST# CARD_3V3
[17] CR_CLK_REQ# 2
CLK_REQ# DV33_18
18 DV33_18
CR3
1 2
1U_0402_6.3V6K
Close to JCR
5
[17] CLK_PCIE_CR REFCLKP
[17] CLK_PCIE_CR# 6 15 SD_RCLK_M_R RR2 1 @ 2 0_0402_5% SD_RCLK_M JCR
REFCLKN SP1 16 SD_RCLK_P_R RR3 1 @ 2 0_0402_5% SD_RCLK_P +ODR_PWR
CR7 1 2 0.1U_0402_10V7K PCIE_PTX_CARDRX_P2_C 3 RTS5242 SP2 17 SD_CLK_R RR4 1 @ 2 0_0402_5% SD_CLK SD_D2 1
[19] PCIE_PTX_CARDRX_P2 HSIP SP3 DAT2
CR9 1 2 0.1U_0402_10V7K PCIE_PTX_CARDRX_N2_C 4 19 SD_CMD_R RR5 1 @ 2 0_0402_5% SD_CMD SD_D3 2
[19] PCIE_PTX_CARDRX_N2 HSIN SP4 CD/DAT3/RSV
CR10 1 2 0.1U_0402_10V7K PCIE_PRX_CARDTX_P2_C 7 20 SD_D3_R RR7 1 @ 2 0_0402_5% SD_D3 SD_CMD 3
[19] PCIE_PRX_CARDTX_P2 HSOP SP5 CMD
[19] PCIE_PRX_CARDTX_N2 CR13 1 2 0.1U_0402_10V7K PCIE_PRX_CARDTX_N2_C 8 21 SD_D2_R RR8 1 @ 2 0_0402_5% SD_D2 4
HSON SP6 29 SP7_SDWP 5 VSS1
SP7 1 VDD/VDD1
RR10 1 @ 2 0_0402_5% SD_CLK 6
[17] MEDIACARD_IRQ# X06.11 CLK
RR1 1 2 10K_0402_5% CD_WAKE# 32
Close to UR1 CR8 7

10U_0603_6.3V6M

0.1U_0402_10V7K
+3VS_CR W AKE# VSS2
@ 31 10P_0402_25V8J SD_CD# 8
MS_INS# CARD DETECT
X06.11 SD_CD# 30
SD_CD# RTS5242 (SD4.0) 2 EMC@ 1 SD_RCLK_P 9
DAT0/RCLK+/DAT

1
SD_RCLK_M 10

CR14

CR15
22 SD_LN1_P +SD_VDD2 SP7_SDWP_C 11 DAT1/RCLK-
SD_LN1_P 23 SD_LN1_M 12 W RITE PROTEC
SD_LN1_M 2 VSS3

2
10 SD_LN0_P 13
+SD_VDD2 DV12S 14 AV12 26 SD_LN0_P SD_LN0_M 14 D0+
DV12S SD_LN0_P 25 SD_LN0_M 15 D0-
13 SD_LN0_M 16 VSS4
SD_VDD2 24 SD_REG2 CR16 1 2 1U_0402_6.3V6K SD_LN1_M 17 VDD2 20
SDREG2 D1- GND

E-PAD
1 2 RREF 9 28 1 2 EMC@ SD_LN1_P 18 21

4.7U_0603_6.3V6K

0.1U_0402_10V7K
RREF GPIO +3VS_CR D1+ GND
RR6 6.2K_0402_1% RR9 10K_0402_5% 1 1 19 22
VSS5 GND 23
RTS5242-GR_QFN32_4X4 GND

CR17

CR18
33
2 2
If GPIO not use for LED function, T-SOL_156-1001302601_NR
C
must be pull-high (Layout guide) CONN@ C

DV12S
4.7U_0603_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K

1 1 1

Close to pin10 (AV12)

CR6

CR2

CR5

2 2 2 For GPIO control SD_WP

L2N7002WT1G_SC-70-3
QR1

SP7_SDWP 1 3 SP7_SDWP_C

S
G
2
[20] HOST_SD_WP#

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
Card Reader
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Thursday, August 06, 2015 Sheet 51 of 71
5 4 3 2 1
 5 4 3 2 1

AUDIO Board Conn. Keyboard Controller board + DMIC

JKB
+5VALW 1
2 1
+5VS 2
3
+3VALW 3
JAUDIO +3VS 4
5 4
2 1 [20] KB_DET# 6 5
D 2 1 [48] BC_INT#_ECE1117 6 D
4 3 [48] BC_DAT_ECE1117 7
6 4 3 5 8 7
6 5 [48] BC_CLK_ECE1117 8
8 7 9
10 8 7 9
AUD_PWR_EN [20,54] White [48] BAT2_LED#
10 9
[49] NB_MUTE#
12 10 9 11
HDA_BITCLK_AUDIO [18]
DMIC_DAT_CODEC
Amber [48] BAT1_LED#
RE117 1 @ 2 0_0402_5% DMIC_DAT_CODEC_C 11 10
[48] BEEP 12 11 HDA_SYNC_AUDIO [18] 11
14 13 DMIC_CLK_CODEC RE116 1 @ 2 0_0402_5% DMIC_CLK_CODEC_C 12
[18] SPKR 16 14 13 15 HDA_RST#_AUDIO [18] 13 12
[20,48] SPK_DET# 16 15 HDA_SDIN0_AUDIO [18] 13
DMIC_CLK_CODEC 18 17 14

4.7P_0402_50V8C
@

4.7P_0402_50V8C
@

4.7P_0402_50V8C
@

4.7P_0402_50V8C
@
DMIC_DAT_CODEC 20 18 17 19 HDA_SDOUT_AUDIO
I2C0_SDA_DSP
[18]
[20,48]
X06.22 15 14
22 20 19 21 15 16
22 21 I2C0_SCK_DSP [20,48] GND

1
24 23 17
+3VALW 24 23 GND
26 25

CE81

CE82

CE73

CE74
26 25 +VSBP
+5VALW 28 27 E-T_6710K-Y15M-31L
28 27

2
30 29 CONN@
30 29
34 31
35 G4 G1 32
36 G5 G2 33
G6 G3

CONN@
APS CONN
E-T_1133K-R30C-01L~D

JAPS
+3V_PCH 1
2 1
[18,34,37,48] SIO_SLP_S3# 3 2
+3VALW 3
4
[18,34,48] SIO_SLP_S5# 5 4
[18,34,48] SIO_SLP_S4# 5
6
[18,48] SIO_SLP_A# 6
7
+3VALW 7
8
9 8
[18] PCH_RTCRST# 10 9 +5VALW
DMIC_DAT_CODEC
DMIC_CLK_CODEC 11 10
[42,48] PBTN_SW# 11
12
13 12
[6,18] SYS_RESET# 13
C 14 C
15 14 JUART
[18,34,42] SIO_SLP_S0# 15
16 1
16 1
2

17 2
17 [20] UART2_TXD 2
18 3
TVNST52302AB0_SOT523-3 19 18 [20] UART2_RXD 4 3
DE9 20 GND 4
GND 5
EMC@ CONN@ 6 GND
GND
1

ACES_50506-01841-P01
ACES_50207-00471-P01
CONN@

Lid Switch Screw Hole

+3VALW +3VALW
CPU x 4 GPU x 2 @ H1 @ H2 @ H9 @ H37 @ H38 @ H39 @ H40
1

H_2P3 H_2P3 H_2P5 H_3P0 H_3P0 H_2P5 H_2P5

@ H13 @ H16 @ H5 @ H6

1
@ RE15 H_3P9 H_3P9 H_3P2 H_3P2
47K_0402_5% 1

1
UE2
2

TCS20DLR_SOT23F-3 @ H10 @ H11 @ H12 @ H17 @ H41 @ H42 @ H43 @ H47

LID_SW_IN# LID_SW_IN# [48] @ H45 @ H46 H_2P5 H_2P1N H_6P0N H_2P1X2P5N H_2P8 H_2P8 H_2P3 H_6P0N
H_3P9 H_3P9
B

1
B
1 1
1

1
2

CE15 CE16
VOUT
VCC

.1U_0402_16V7K 10P_0402_25V8J @ H51 @ H50 @ H55 @ H54 @ H59 @ H49 @ H48

2 2 CLIP_C5P5 CLIP_C6 CLIP_C5P5 CLIP_C5P5 H_2P9X2P1N H_2P3 H_4P1
GND

1
NGFF x 2
1

FD1 FD2 FD3 FD4

EMI shilding clip x 21 @ FIDUCAL @ FIDUCIAL @ FIDUCAL @ FIDUCIAL

1
EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P

RTC Battery With Charge Function

@ H33 @ H26 @ H27 @ H32 @ H52 @ H53
1

1
EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P
@ H28 @ H29 @ H30 @ H31 @ H36 @ H56
+RTCBATT
1

1
JRTC
+RTCBATT +RTCBATT 1 EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P
2 1 @ H21 @ H18 @ H19 @ H20 @ H35 @ H57
2
2

RH67
1

1
1.3K_0402_5% 3
4 G1 EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P
+3VLP G2 @ H22 @ H23 @ H24 @ H25 @ H34 @ H58
1

A W=20mils E&T_3806K-F02N-03R A
CONN@
1

1
1

D122
BAS40-04_SOT23-3

W=20mils
2

W=20mils +RTCVCC
1 Security Classification Compal Secret Data Compal Electronics, Inc.
1

EMC@
CH44 CH196
Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title
1U_0402_6.3V6K
2
15P_0402_50V8J
TPM/BTB conn.
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
Size Document Number Rev
RF Reserved. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C. LA-C361P 0.1(X00)

Date: Thursday, August 06, 2015 Sheet 52 of 71

5 4 3 2 1
 5 4 3 2 1

B+
+5VALW
NVDC +3VALW TDC:5.7A
DC IN Switch CHARGER +5VALW TDC:7.4A +3VALW
Page 54
BQ24777 TPS51285B Page 57
D Page 56 D

Trinity
Battery PCH_1V TDC:5.1A +1VALW
(3S3P) SY8206D
Page 58

+1.2V_DDR
+1.2V TDC:4.2A
+0.6VS TDC:0.7A +0.6VS
G5616A Page 59

+1.35VSDGPU TDC: 10.2A +1.35VSDGPU

TPS51367
Page 60

C C

VCCIO_0.95V TDC: 3.9A +VCCIO

SY8206D
Page 61

+1.05VGPU TDC: 2.1A +1.05VSDGPU

SY8206D
Page 62

+GPU_CORE
VGA_CORE TDC: 51A
RT8813A
Page 63

B B

+VCC_CORE TDC: 56A +VCC_CORE

ISL95855
Page 65

+VCC_GT TDC: 39A +VCCGT

ISL95855
Page 66

+VCC_SA TDC: 10A +VCCSA

ISL95855
Page 66

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
Power Sequence diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Tuesday, August 11, 2015 Sheet 53 of 71
5 4 3 2 1
 A B C D

+3VALW

CONN@ ADP100 +DC_IN

ACES_50290-00701-001
1
1

1
2 @ PR100

PC114
0.1U_0402_25V6
2
0_0402_5%
PR101

1
3 1 2

0.1U_0402_25V6
3
2.2K_0402_1%

PC115
4 PSID PQ100
4

2
FDV301N-G_SOT23-3

EMC
5 PR102
5
1 3 33_0402_5%

S
EMC

D
6 PSID-3 1 2 PS_ID [48]

AZ5125-01H.R7G_SOD523-2
1
6 1

1
7 +5VALW
7

G
PR104

EMC PD100

2
1
10K_0402_1%
HCB2012KF-121T50_0805

PR103 PSID-2 1 2

0.1U_0402_25V6
HCB2012KF-121T50_0805
1

1
1 2 100K_0402_1%

PC106
BLM15AG102SN1D_2P
EMC PL106

EMC PL104

1
C
EMC PL105

2 PSID-1 2 PQ101
B MMBT3904W H_SOT323-3
EMC
2

1
E

3
PR105
15K_0402_1%
place near connect

2
VBATT EMC PL107 BATT++
HCB2012KF-121T50_0805
1 2 EMC
EMC PL108
HCB2012KF-121T50_0805 EMC
1 2
1

1
0.01UF_0402_25V7K
100P_0402_50V8J

100P_0402_50V8J
1000P_0402_50V7K

PQ1301
AON7409_DFN8-5
1

PD101 PD102
PC108

EMC PC109

EMC PC110

TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3 1
PC107

2
2 2
2

3 5 +VSBP
B+
2

3
EMC

0.22U_0603_25V7K
EMC

+3VALW

0.1U_0402_25V6
4
1
PR107

PC111

1
PR106 1M_0402_5%

PC112
100_0402_1%

2
PBAT_SMBCLK [48]

1
1 2 @ PR109

2
PR110

1VSB_N_003
CONN@ BAT100 PR108 100K_0402_1% 37.4K_0402_1%

EMC
ACES_50290-01201-P01 100_0402_1% 1 2 VSB_N_001
1 1 2 PBAT_SMBDAT [48]
1

2
2
2 3 PBAT_PRES# [48,56] @ PR113
3 4 0_0402_5% D
4 5 CLK_SMB PR112 1 2VSB_N_0022
PR111 PQ103
5 6 DAT_SMB [20,52] AUD_PW R_EN
100_0402_1% 10K_0402_1% G L2N7002WT1G_SC70-3
6 7 BATT_PRS# 1 2 1 2
+3VALW S
7

3
8
8 9
9

1
10 PC113
10 11 .1U_0402_16V7K
11 12
12

2
Battery
3 (3S3P) 3

JIMBTY battery connector

SMART
Battery:
01.BAT+
02.BAT+
03.BAT+
04.BAT+
05.CLK_SMB
06.DAT_SMB
07.BATT_PRS
08.SYS_PRS
09.GND
10.GND
11.GND
12.GND

4 4

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGAND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF EDLL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTE
N AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSWAY BE USED BY OR DISCLOSED TO ANY THIRD
PWR-DCIN / BATT CONN / OTP
Size Document Number Rev
Smart Adapter circuit (39.1) PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-C361P 0.1(X00)

Date: Tuesday, August 11, 2015 Sheet 54 of 71

A B C D
 5 4 3 2 1

remove source back

B+ POWER
S9 S8 Barrel Adapter

B+
P-MOSFET P-MOSFET
P-MOSFET
S1 P-MOSFET
S2 EMI soultion for layout placement space
@ PQ202 @ PQ203 +DC_IN
AON7409_DFN8-5 AON7409_DFN8-5 @ PR215 PQ200 PQ201 +SDC_IN
1 1 @ 0.01_1206_1% AON7409_DFN8-5 AON7409_DFN8-5 EMC
2 2 PR246 1 1 PL200
5 3 3 5 B+_IN 1 2 4 1 2 2 HCB2012KF-121T50_0805
3 5 +DC_IN_SS 5 3 DAUL_IN 1 2

100K_0402_5%

0.022U_0603_50V7K
1
3 2

NTR4502PT1G_SOT23-3

0.022U_0603_50V7K
0_1206_5%

1
1 2

1M_0402_5%

1M_0402_5%

1000P_0402_50V7K
PR244

100P_0402_50V8J

15P_0402_50V8J
4

4
1

1
EMC PL201

PR204

PC207

PC200

PR202

1000P_0402_50V7K
100K_0402_5%

100P_0402_50V8J
0.1U_0402_25V6
0.022U_0603_50V7K
4

1
HCB2012KF-121T50_0805

PR201

100K_0402_5%

100K_0402_5%

EMC PC205

EMC PC201

EMC PC206
3

1
@

PR200

PR243

EMC PC202

EMC PC203

EMC PC204
G

1
2

PQ215
@

PC220
2

2
3
@ G EMC PL202

2
D @ PR233 2 HCB2012KF-121T50_0805

100K_0402_5%

2
1
@ 0_0402_5% 1 2

1
2 1 1 2 D

NTR4502PT1G_SOT23-3
@ PR287 INA199_OUT

PR237

1M_0402_5%

TR 2N7002KW 1N SOT323-3

1
1M_0402_5%
D 0_0402_5% D

PR213

AC_DET
S

1
1 2 @ 1 2
PP_HV

100K_0402_5%
S TR 2N7002KW 1N SOT323-3

PQ204
EMC PL203

PR205

PR206
PD207 PR210 S

2
@ PR262 SDMK0340L-7-F_SOD323-2 22K_0402_5% HCB2012KF-121T50_0805
@

2
0_0402_5% @ PU200

1
VBUS_ACOK 1 2 2 1 6

S TR 2N7002KW 1N SOT323-3
REF Out

1 2

2
D
From EC

1
@ PR212 @ PR21 PR203

100K_0402_5%
1 2 @
D

PQ209

PQ207
@ PR266

PR240
0_0402_5% 44.2_0402_1% 100K_0402_5%
D

1
0_0402_5% G 2 1 2 1 2
1 2 3 PWR_SRC_ON [49] 2

PQ208
@ PR211

100K_0402_5%
S G

1 2
1
@ @ 0_0402_5% PR209

100K_0402_5%

S TR 2N7002KW 1N SOT323-3
S G

2
D

1
@ PD204 2 5 1 2 PR268

1M_0402_5%
0_0402_5%

PR292
S

S
GND IN-

3
D

1
1
DCIN_ACOK 2 2

PR299
0_0402_5%

S TR 2N7002KW 1N SOT323-3
1 2 3 4 1 2 DCIN_ACOK# 1 2 2

PQ206
BAT54CW_SOT323-3

PR217
+SDC_IN G
V+ IN+ G
S

3
@ PR208 INA199A1DCKR_SC70-6 @ PR207

S TR 2N7002KW 1N SOT323-3
@ S

3
1
0_0402_5% 0_0402_5%
@

2
@ PC209

PQ205
0.1U_0603_25V7K~D

S TR 2N7002KW 1N SOT323-3

PQ211
D
From TI PD GPIO

1
@ PR214
D

1
0_0402_5% 2
[48,56] AC_DIS
+3VALW USB type-C PD OCP 2 1 2
PWR_SRC_ON_PC [39]
G

PQ210
G S @

3
100K_0402_5%
S

1
@ 1 2

PR269
+3V_VC
@ PR274
@ PD205 @ 100K_0402_1%

2
D

1
SDMK0340L-7-F_SOD323-2
2 1 2 VBUS_ACOK

S TR 2N7002KW 1N SOT323-3
1 2

PQ234
G
@ PR280
221K_0402_1%~D

3
0_0402_5%
120K_0402_1%
1

@
PR236

1 2
PR256

PR239
1.8M_0402_1% @
2

@ @ to TI PD GPIO
8

INA199_OUT 3
P

+
2 O
1
PWR_SRC_ILIMIT [39] USB type-C Adapter / PD
-
S6 S7
G

S11
100K_0402_1%
2

@ PU201A
4

LM393DMR2G_MICRO8
PR238

P-MOSFET P-MOSFET
220P_0402_50V7K

C C
1000P_0402_50V7K

+VBUS_1
2

@ PR216
PC210

PC211

PQ214 PQ212 PQ213

1

0.01_1206_1%
AON7409_DFN8-5 AON7409_DFN8-5 AON7409_DFN8-5
1

@ 1 1 1 4 1
@ 2 +AC_IN 2 2

0.022U_0603_50V7K
5 3 3 5 5 3 3 2 1 2

NTR4502PT1G_SOT23-3
+VBUS_DC_SS

100K_0402_5%
1

1
PD_SENSEN [39]

1M_0402_5%

PR220
PR218

0.022U_0603_50V7K
1

1
PC221

PR219

0.022U_0603_50V7K
0_0402_5%

1M_0402_5%

PR223
100K_0402_5%
0.022U_0603_50V7K

0.022U_0603_50V7K
4

4
1

1
1 2

1M_0402_5%
PC208
2
PD_SENSEP [39]

1
PQ216
PR221

PR222

PR224

PC222
2

3
PC288

PC289
@ G G

2
2 @ 2 0_0402_5%

2
2

2
D @ @ D

1
1
1 2

NTR4502PT1G_SOT23-3
1M_0402_5%

PQ217
@

PR225

S TR 2N7002KW 1N SOT323-3
1

1
S @ PR227 S
0_0402_5% PR232 PR230
PD211 10K_0402_1% 100K_0402_5%
2

1
PR229 1 2

2
[48,55] VBUS_HV_DIS#

PQ219
100K_0402_5% PR226
SDMK0340L-7-F_SOD323-2 100K_0402_5%
PR290

2
D
1

0_0402_5% @ PR234

S TR 2N7002KW 1N SOT323-3
@

2
D

1
1 2 2 100K_0402_5%
[48,55] VBUS_HV_DIS# 1 2 2 PR267

PQ220
G

S11 OVP
D

1
S G 0_0402_5%
3

PQ218 VBUS_ACOK 1 2 2
+3VALW +3V_VC S

3
S TR 2N7002KW 1N SOT323-3 @ PR231 From TI PD GPIO PC225

S TR 2N7002KW 1N SOT323-3
G
100K_0402_1% 0.1U_0402_10V7K S PR228

3
D D

1
1 2 0_0402_5%
DCIN_ACOK 1 2 2 DCIN_ACOK 1 2 2 PQ221

PQ222
AO3413_SOT23-3

5
G PR235 G
D

1
S 0_0402_5% S

VCC
3

3
@ PQ223 1 DCIN_ACOK# 1 2 2 1 3
+3VALW

S
S TR 2N7002KW 1N SOT323-3 [39] EN_PD_HV IN1 4 1 2

100K_0402_1%

0.01U_0402_25V7K
G
OUT

1
DCIN_ACOK# 2
100K_0402_1%

100K_0402_1%

GND
IN2

3
2

1
@ PD201 PR282

PR275

PC223
S TR 2N7002KW 1N SOT323-3

G
2
SDMK0340L-7-F_SOD323-2 100K_0402_5%
PR241

PR242

1 2

2
130K_0402_1%

2
2

PQ232
PU204
1

@ PR291 MC74VHC1G08DFT2G_SC70-5
PR245

@ @

1
0_0402_5%
1 2 1 2 PR276
1 2 2K_0402_1%
1

PR247
B @ B
1.8M_0402_1% @ PR283

2
+VBUS_1 100K_0402_5%
@ PU201B
PR248 @ PQ226
8

150K_0402_1% LM393DMR2G_MICRO8 S TR 2N7002KW 1N SOT323-3 PR277

D D
1

1
1 2 5 0_0402_5%

S TR 2N7002KW 1N SOT323-3
P

+ 7VBUS_LPS_OVP 1 2 2 1 2 2

PQ231
6 O [55,57] ALW_PWRGD_3V_5V
@ G G
-
G

PR27 S PD202 S
3

3
0_0402_5% SDMK0340L-7-F_SOD323-2
1200P_0402_50V7K
100P_0402_50V8J

0.01U_0402_25V7K
4
1

200K_0402_1%

@ @
1

1
PC212

PC224
100K_0402_1%

2 1
PR249

PR250

PC213

+3V_VC +DC_IN
2

2
2

@ PR281
1

2 1 0_0402_5%
@
@ @
@ @
PP_HV 1 2

PD203
PQ224
+3V_VC
SDMK0340L-7-F_SOD323-2
+3V_LDO AO3413_SOT23-3
PU203
2
100K_0402_1%

100K_0402_1%

100K_0402_1%
2

LDO_EN 1 5 1 3
PR253

setting 5.5V

100K_0402_1%

S
VCC OUT
From EC

2
PR270
PR251

PR252

180K_0402_1%
D
1

1
0_0402_5% 2

PR255

100K_0402_1%
1U_0603_25V6
2 1 2 GND

PR254

PR278
180K_0402_1%

G
VBUS_HV_DIS#
1

2
2

1
3 4 1 2 LDO_EN

PC219
G
NC EN
1

1
1 2
PR257

S @ PC218
3

1
PQ227 PQ228 PR272 1U_0402_16V6K

2
S TR 2N7002KW 1N SOT323-3 1 2 S TR 2N7002KW 1N SOT323-3 PR258 100K_0402_1%

2
D
1

@ 1.8M_0402_1% RT9069-33GB_SOT23-5
1

1
PR259 DCIN_ACOK# 2
PU202A

1
1.8M_0402_1% G PR279

8
S PR260 LM393DMR2G_MICRO8 0_0402_5%
PU202B
3

1
PQ230 1 2 3 PR271
+VBUS_DC_SS

P
LM393DMR2G_MICRO8 +
8

PR261 S TR 2N7002KW 1N SOT323-3 1 VBUS_ACOK 100K_0402_1% 2

O ALW_PWRGD_3V_5V [55,57]

1 2
D
1

1 2 5 130K_0402_1% 2 G
+DC_IN_SS
P

+ -

2
D

G
7 DCIN_ACOK 2

S TR 2N7002KW 1N SOT323-3

S TR 2N7002KW 1N SOT323-3
S
O

3
6 2

PQ225

PQ233
140K_0402_1%
-
G
+3V_VC

4
G

S G
3
200K_0402_1%

200K_0402_1%
16.5K_0402_1%

16.5K_0402_1%
S
4

3
100P_0402_50V8J
1

2
PR263

PR273

PC215
2
PR264

PR265
2

100P_0402_50V8J

100P_0402_50V8J
1

1
PC214

1
VBUS_ACOK set 15V PC217 @ PQ229
PC216
2

1
100P_0402_50V8J S TR 2N7002KW 1N SOT323-3

3V LDO
2

2
D

1
DCIN_OK set 17V DCIN_ACOK 2
G
A S A

3
DCIN_ACOK [48] Vbus_AC Detector

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGAND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF EDLL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTE
N AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSWAY BE USED BY OR DISCLOSED TO ANY THIRD
Docking
Size Document Number Rev
Docking Power Control(41.1), Support component(41.2) PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-C361P
Date: Tuesday, August 11, 2015 Sheet 55 of 71
5 4 3 2 1
 5 4 3 2 1

+PW R_SRC_AC CHAGER_SRC

D PR300 D
+SDC_IN 0.01_1206_1% PL300 EMC
HCB2012KF-121T50_0805
4 1 1 2

3 2 PL301 EMC

22U_0805_25V6M
PC306 EMC
2200P_0402_50V7K
HCB2012KF-121T50_0805

0.1U_0402_25V6
1 2

22U_0805_25V6M

22U_0805_25V6M

22U_0805_25V6M

22U_0805_25V6M

22U_0805_25V6M
1

1
PC307

PC308

PC309

PC310

PC336

PC337
PC334
2

2
CSSN_1
CSSP_1
B+ Polymer cap for noise issue

1
PR399
@ PR301 @ PR302
2 1 1 2 0_0402_5% 0_0402_5%
+DC_IN_SS
@
0_0402_5%

2
PD304
SDMK0340L-7-F_SOD323-2 1

100U_D_20VM_R55M
PC313

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
2 1 PD302 PC311 0.1U_0402_25V6 PC314 +

PC312
+VBUS_DC_SS SDMK0340L-7-F_SOD323-2 1U_0603_25V6K 0.1U_0402_25V6

1
PD303 1 2 1 2 1 2 PQ300 PQ301

PC315

PC316

PC317

PC318
C C
2

SIR472DP-T1-GE3_POWERPAK8-5
5

5
SDMK0340L-7-F_SOD323-2 2 1
VBATT

SIR472DP-T1-GE3_POWERPAK8-5

2
GNDA_CHG GNDA_CHG

ACDET>14.5V 4 4
294K_0402_1%

10_1206_5%
2

PR304
PQ304 PR303 BQ24777_REGN
PR305

S TR 2N7002KW 1N SOT323-3 4.02K_0402_1%

3
2
1

3
2
1
PC320 low noise MLCC for noise issue

1
PC319 1U_0603_10V6K
1

D
1

1U_0805_25V6K 1 2

ACDRV

ACN
ACP
2 2 1 28
[48,55] AC_DIS VCC
BQ24777_REGN

G
B+
1

PR308 3 24 low noise MLCC for noise issue

100K_0402_5%

S
CMSRC REGN
3

59K_0402_1% PR307
PR327

2 1 6 PC321 +VCHGR
2.2_0603_5%
ACDET 25CHG_BTS 1 2 CHG_BTS_C 1 2
1 2 1 2 CHARGER_SDA 11 BTST
PL302 PR310
SDA
2

@ PR306 0_0402_5%
1 2 CHARGER_SCL 12 26 CHG_UGATE 0.047U_0603_25V7M 1 2 1 4
PC322
SCL HIDRV
1

0.1U_0402_25V6 @ PR309 0_0402_5%

PR311 GNDA_CHG 5 3.3UH_PIMB104T-3R3MS_10A_20% 2 3
ACOK 27 CHG_SW
100K_0402_1% [48] CHARGER_SMBDAT PHASE

5
7
IADP 0.01_2512_1%
[48] CHARGER_SMBCLK
2

SIRA06DP-T1-GE_POWERPAKSO-8-5
8 23 CHG_LGATE EMC

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
IDCHG LODRV

0.1U_0603_25V7K
2
1 2

PC323 EMC
[48] ACAV_IN 9
@ PR312 0_0402_5% PR313

PQ302
PMON

1
1 2 4 4.7_1206_5%

PC324

PC325

PC326
[48] I_ADP
1

@ PR314 0_0402_5% 1 2 10 22
1 2 /PROCHOT GND
PR316
[48] I_BATT

2
150K_0402_1% @ PR317 0_0402_5% PR318
1 2 PR315 10K_0402_1%
[48,64] P_SYS

1
2
3
@ PR324 0_0402_5% 100_0402_1% 13 21 1 2 BQ24777_REGN
CMPIN NC
2

100P_0402_50V8J

100P_0402_50V8J

B B
1

14
10K_0402_1%

CMPOUT
1

20 EMC
PR325
PC327

PC328

SRP

1
GNDA_CHG
15 19 PC329
/BATPRES SRN
2

PR319 1000P_0603_50V7K
1 BQ24777_REGN

2
4.02K_0402_1%
16 18 1 2 PC330 PC331 @ PC332
CELL /BATDRV
GNDA_CHG 0.1U_0402_25V6 0.1U_0402_25V6 0.1U_0402_25V6
29 17 1 2 1 2 1 2 1 2
PW PD BAT
PR320
[9,48,64] H_PROCHOT# PU300 10_0603_1%
2

BQ24777RUYR_WQFN28_4x4
PR321 GNDA_CHG
1U_0603_25V6K

1K_0402_1% GNDA_CHG
PC333

1 2
[48,54] PBAT_PRES#
@ PR322 0_0402_5% VBATT GNDA_CHG
2

GNDA_CHG
@ PJP300
1 2
1

@ PR323
121K_0402_1% @ PD301
PAD-OPEN1x1m 1 2
GNDA_CHG
SX34H_SMA2
PQ303
2

VBATT
+VCHGR AON7409_DFN8-5
1
2
GNDA_CHG 3 5

4
A BATDRV# A

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGAND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
Charger controller(40.1), Support component(40.2) TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF ELL
D
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTE
INC. ("DELL") THIS DOCUMENT MAY NOT
N AUTHORIZATION OF DELL. IN ADDITION, Charger
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSWAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-C361P 0.1(X00)

Date: Tuesday, August 11, 2015 Sheet 56 of 71

5 4 3 2 1
 A B C D E

+3VLP

1
@ PR400
0_0402_5%

2
4.7U_0603_6.3V6M

1
PC400

2
1 1

@ PC401 @ PC402
100P_0402_50V8J 100P_0402_50V8J
B+ 1 2 1 2

@ PL403 EMC PR401 PR402

HCB2012KF-121T50_0805 68.1K_0402_1% 154K_0402_1%
1 2 1 2 1 2

@ PL402 EMC PR404

PR403 B++
HCB2012KF-121T50_0805 B++
100K_0402_1%
1 2 1 2 FB_3V FB_5V 1 2

@ PJP400
JUMP_43X118 100K_0402_1%

10U_0805_25V6K
1 2
PR406

2200P_0402_50V7K
1 2 1 2

0.1U_0402_25V6
1 2

MDU1516URH_POWERDFN56-8-5
100U_D_20VM_R55M

2200P_0402_50V7K

1
10U_0805_25V6K

EMC PC409
PR405

PC407

PC408
MDV1528URH_PDFN33-8-5
1
0.1U_0402_25V6
15P_0402_50V8J

5
16.9K_0402_1%
EMC PC405

PQ401
10.2K_0402_1%
1

5
+
PC406
PC420

EMC PC403

PC404

2
PQ400

EMC
2
2

@ PR408 4
EMC

[55] ALW_PWRGD_3V_5V

1
4 0_0402_5%
3V/5VALW_EN 1 2 21

VREG3
VFB2

VFB1
CS2

CS1
TP @ PR409
@ PR407 0_0402_5%

3
2
1
2 0_0402_5% 6 20 1 2 3V/5VALW_EN 2
EN2 EN1
1
2
3
1 2
PR410
1 2 7 19 1 2
PL400
+3VALWP PR428 PGOOD VCLK
200_0402_1% PL401
3.3UH_6.3A_20%_7X7X3_M 100K_0402_1% PU400 1.5UH_ETQP3W 1R5W FN_9.5A_20% +5VALWP
+3VALWP 1 2 LX_3V 8 18 LX_5V 1 2
SW2 TPS51285BRUKR_QFN20_3X3 SW1 PR412 PC411
PC410 PR411 2.2_0603_5% 0.1U_0603_50V7K

1
1 2 BST1_3V 1 2 BST_3V 9 17 BST_5V 1 2 BST1_5V 1 2
MDV1524URH_PDFN33-8-5

4.7_1206_5%
VBST2 VBST1
1

PR414
EMCPR413 0.1U_0603_50V7K 2.2_0603_5%
4.7_1206_5% UG_3V 10 16 UG_5V

MDU1512RH_POWERDFN56-8-5
150U_B2_6.3VM_R35M

150U_B2_6.3VM_R35M
DRVH2 DRVH1
PQ402

1 1

VREG5
DRVL2

DRVL1

2
5

EMC
VO1
2

+ 4 +

VIN
PC412

PC413
SNUB_5V
PQ403
SNUB_3V

2 2

11

12

13

14

15
LG_3V LG_5V 4

680P_0603_50V7K
1
2
3

@ PC415

.1U_0402_16V7K
680P_0603_50V7K

1
.1U_0402_16V7K

PC416

PC417
2
1
PC414

3
2
1
@

2
EMC
2

EMC
3 3

4.7U_0603_6.3V6M
0.1U_0402_25V6
1

PC419
PC418
PR326 @ PR415
2.2K_0402_5% 0_0402_5%

2
1 2 3V/5VALW_EN
[48] ALWON 2

B++
4.7U_0603_6.3V6M
1

@ PC335

@ PJP402 @ PJP403
2

1 2 +3VALW 1 2
+3VALWP +5VALWP +5VALW
PAD-OPEN 4x4m PAD-OPEN 4x4m

3.3VALWP 5VALWP
TDC 5.7A TDC 7.4A
Peak Current 8.1A Peak Current 10.5A
OCP current 9.7A OCP current 12.6A
4 4

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGAND SPECIFICATIONS CONTAINS CONFIDENTIAL Title

3V/5V controller(35.1), Support component(35.2)

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF ELL
D
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTE
INC. ("DELL") THIS DOCUMENT MAY NOT
N AUTHORIZATION OF DELL. IN ADDITION, PWR-3VALWP/5VALWP
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSWAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-C361P 1.0(A00)

Date: Tuesday, August 11, 2015 Sheet 57 of 71

A B C D E
 5 4 3 2 1

D D

+1VSP
@ PR500
0_0402_5%
TDC 5.1A
1 2
PCH_ALW_ON [33,34,48]
Peak Current 7.2A
OCP current 8A

1
1M_0402_1%
@ PC500

PR501
0.22U_0402_10V6K

2
2
B+ EMC PR502 EMC PC501
4.7_1206_5% 680P_0603_50V7K

EMC PL500 1 2SNB_1V 1 2

HCB2012KF-121T50_0805 PU500
1 2 B+_1V 8 1 @ PR503 PC505 +1VSP +1VALW
IN EN 0_0402_5% 0.1U_0402_25V6
C 6 BST_1V 1 2 1 2 PL501 @ PJP500 C
2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

BS
1

1
EMC PC502

PC503

@ PC506

PC504

9 10 LX_1V 1 2 1 2
GND LX 1 2
2

1UH_6.6A_20%_5X5X3_M JUMP_43X118

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM
EMC

90.9K_0402_1%

1
4

PR504

220P_0402_50V8J
FB

PC507

PC508

PC509

PC510

PC511
ILMT_1V 3 7
Rup
ILMT BYP +3VALW

2
4.7U_0603_6.3V6K

2
2 5

4.7U_0603_6.3V6K
PG LDO

PC513
1
SYX196DQNC_QFN10_3X3

PC512
FB = 0.6V

2
2

1
PR508

Pin 7 BYP is for CS.

Rdown 133K_0402_1%

Common NB can delete +3VALW and PC513

2
B B

+3VALW

VFB=0.6V
1

@ PR510
0_0402_5%
Vout=0.6V* (1+Rup/Rdown)
Vout=1V
2

ILMT_1V
1

@ PR512
0_0402_5%
2

A A
The current limit is set to 6A, 8A or 12A when thispin
is pull low, floating or pull high
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
P40-PWR_+1VA
ION OF R&DSize Document Number Rev
PWR.Plane.Regulator(35.25), Support component(35.26) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
LA-C361P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
Date: Tuesday, August 11, 2015 Sheet 58 of 71
5 4 3 2 1
 5 4 3 2 1

B+

PL601 EMC

+1.2V_MEN_P
HCB2012KF-121T50_0805
1 2

@ PJP600
JUMP_43X118 @ PJP601
D 1 2 1.2V_B+ PC600 PR600 +VLDOIN_1.2V 2 1 +0.6VS D
1 2
0.22U_0603_16V7K 2.2_0603_5% +0.6VSP
1 2 1 2 BOOT_1.2V PAD-OPEN1x1m

2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
@ PJP602

1
DH_1.2V 1 2

PC601

PC602

PC603

PC604

MDV1527URH_POWERDFN33-8-5
PAD-OPEN 3x3m

5
SW _1.2V

10U_0805_6.3V6M

10U_0805_6.3V6M
EMC

EMC

1
PC605

PC606
PQ600

16

17

18

19

20

2
4

VLDOIN
BST

VTT
DH
LX
21
PAD
+1.2V_MEN_P

DL_1.2V 15 1
+1.2V_DDR DL VTTGND

1
2
3
@ PJP603 PL600 14 2 +V_DDR_REF
PR601 PGND VTTSNS
PAD-OPEN 4x4m 1UH_11A_20%_7X7X3_M
2 1 1 2 3.57K_0402_1%
1 2 CS_1.2V 13 PU600 3
CS GND
PC607 G5616ARZ1U_TQFN20_3X3
1U_0603_10V6K
1 1 2 12 4
4.7_1206_5%

MDV1522URH_PDFN33-8-5
VPP VTTREF

5
PR603
PR602
330U_D1_2VY_R9M

+ 5.1_0603_5%
1 2 11 5
PC608

C VDD_1.2V +1.2V_MEN_P C
+5VALW VCC VDDQSNS

1
PC609
2
1 SNUB_1.2V 2

.1U_0402_16V7K

VDDQSET
PQ601
EMC

1
4 PC610

PGOOD

2
1U_0603_10V6K

TON

S5

S3
2
680P_0603_50V7K

10
1
2
3

6
PC611

+5VALW PR604
16.2K_0402_1%
2

1.2V_FB 1 2
EMC

@ PC612
22P_0402_50V8J
@ PR609 1 2
1 2 +1.2V_PW ROK
+3VS PR605
100K_0402_5% 1M_0402_1%
@ PR606 1.2V_B+ 1 2
0_0402_5%
1 2 S5_1.2V
[34] SUS_ON_EC_P

1
PR607

1
@PC613 27K_0402_1%
0.1U_0402_10V7K

2
B B
@ PR608
0_0402_5%
1 2
[9] SM_PG_CTRL

@PR610

1
0_0402_5% @PC614
2 1 0.1U_0402_10V7K
[34,61] RUN_ON_P 2

FB sense trace

0.6Volt +/- 5%
1.2Volt +/- 5% TDC 0.7A
TDC 4.2A Peak Current 1A
Peak Current 6A OCP Current 1.2A
OCP current 7.2A

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL +1.35V_MEN/+0.675V_DDR_VTT
DDR controller(35.3), Support component(35.4) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C. LA-C361P 1.0(A00)

Date: Tuesday, August 11, 2015 Sheet 59 of 71

5 4 3 2 1
 5 4 3 2 1

+5VALW

B+
D DIS@ D
PC700
1U_0603_10V7K

+1.35V_VSNS
1 2 @ EMCPL701
HCB2012KF-121T50_0805
2 1

@ PJP700
PAD-OPEN 3x3m

4700P_0402_25V7K
+1.35V_RUN_B+ 2 1

1
DIS@ PC701

EMC PC702 DIS@

DIS@

EMC PC704 DIS@

210K_0402_1%

4.7U_0603_25V6K

4.7U_0603_25V6K

4.7U_0603_25V6K
.1U_0402_16V7K
47P_0402_50V8J

2200P_0402_50V7K
1

1
DIS@ PR700

PC705

PC706

PC707
EMC PC703
2

2
23

22

21

20

19

18

17

16

15
2

GSNS

VSNS

TRIP

GND

VIN

VIN

VIN
SLEW

V5

@
DIS@

DIS@
DIS@ PR701 24
C REFIN2 14
C
100K_0402_1%
1 2 PGND
25
REFIN 13
DIS@ PC708
PGND
.1U_0402_16V7K
1 2 REF_+1.35V_RUNP 26 DIS@ PU700
VREF 12
TPS51367RVER_QFN28_4P5X3P5
PGND
27
@ PR705 RA 11
0_0402_5% PGND
[23,32] FBVDD_EN 1 2 28
EN 10
PGND

PGOOD

MODE
29 DIS@
TP

BST

1
LP#
EMC PC709

SW

SW

SW

SW
NC
33P_0603_50V8J +1.35VSDGPU

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM
1

2
1 1 1 1

DIS@ PC710

DIS@ PC711

PC712

PC755
1
DIS@ @ PJP701
+3VS EMC PR702 1 2

BST_+1.35VRUN
2 2 2 2
210K_0402_1%

10_1206_5%
PAD-OPEN 4x4m

@
DIS@
B B
1
DIS@ PR704

2
DIS@ PL700
0.68UH_PCMC063T-R68MN_15.5A_20% @ PJP702
SW_+1.35VRUN 1 2 +1.35V_VSNS 1 2
2

PAD-OPEN 4x4m
.1U_0603_25V7K

[23] ALL_GPWRGD

5.1_0603_5%
1.35Volt +/-5%
1
PC713

PR703 TDC 10.2A

2

Peak Current 13.8A

2
DIS@

DIS@

OCP current 16A (Fix)

A
DELL CONFIDENTIAL/PROPRIETARY A

Compal Electronics, Inc.

Title

DDR controller(35.3), Support component(35.4)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR
Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D PWR_+1.5VDGPU
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
O UT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
LA-C361P 1.0(A00)

Date: Tuesday, August 11, 2015 Sheet 60 of 71

5 4 3 2 1
 5 4 3 2 1

+0.95V
D TDC 3.9A D

Peak Current 5.5A

@ PR800
0_0402_5%
OCP current 6A
1 2
RUN_ON_P [34,59]

1
PR801 @ PC800
1M_0402_1% 0.22U_0402_10V6K

2
2
PR802EMC PC801 EMC
B+ 4.7_1206_5% 680P_0603_50V7K
HCB2012KF-121T50_0805
EMC PL800 1 2SNB_0.95V1 2
PU800 PC805
1 2 B+_0.95V 8 1 @ PR803
IN EN 0_0603_5% +0.95VSP +VCCIO
0.1U_0603_25V7K
10U_0805_25V6K

10U_0805_25V6K

C 6 BST_0.95V1 2 1 2 C
PL801
0.1U_0402_25V6

BS
2200P_0402_50V7K
1

@ PJP800
EMC PC803

PC802

@PC804

PC806

9 10 LX_0.95V 1 2 1 2
GND LX 1 2
2

1UH_6.6A_20%_5X5X3_M JUMP_43X118
EMC

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM
1

100_0402_1%
1

1
4

PR813
FB

PC808

PC809

PC810

PC811
220P_0402_50V8J
ILMT_0.95V 3 7 FB = 0.6V

PC807
ILMT BYP +3VALW

2
4.7U_0603_6.3V6K

2
2 5

4.7U_0603_6.3V6K
PG LDO

PC812
1
SYX196DQNC_QFN10_3X3

PC813

2
2
1 2 1 2 VCCIO_SENSE [11]

PR804 @ PR808
36.5K_0402_1% 0_0402_5%

Pin 7 BYP is for CS. Rup

B Common NB can delete +3VALW and PC812 B

1
PR806
+3VALW
Rdown 62K_0402_1%

Vout=0.6V* (1+Rup/Rdown)

2
1

@ PR809
@ PR811 0_0402_5%
1 2 VSSIO_SENSE [11]
0_0402_5%

VFB=0.6V
2

ILMT_0.95V
PR810
Vout=0.95V
1

PR812 2 1
0_0402_5%

@ 100_0402_1%
2

A
The current limit is set to 6A, 8A or 12A when thispin A
is pull low, floating or pull high
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
P40-PWR_+0.95VA
1.05V controller(35.5), Support component(35.6) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C. LA-C361P 0.1

Date: Tuesday, August 11, 2015 Sheet 61 of 71

5 4 3 2 1
 5 4 3 2 1

+3.3V_GFX_RUN
D D
@ PR900
0_0402_5% +1.05VSP
1 2 TDC 2.1A
DIS@ PR913 Peak Current 2.9A
62K_0402_1% OCP current 6A

0.1U_0402_25V6
1 2
3V3_MAIN_EN [23,32,63]

PC900
DIS@ PR901
1M_0402_1%

DIS@
2
DIS@ DIS@
B+ EMCPR902 EMC PC901
DIS@ 4.7_1206_5% 680P_0603_50V7K
HCB2012KF-121T50_0805
EMC PL900 1 2SNB_1.05V1 2
PU900 DIS@ +1.05VSP
1 2 B+_1.05V 8 1 @ PR903 PC906 +1.05VSDGPU
IN EN 0_0603_5% 0.1U_0603_25V7K
10U_0805_25V6K

10U_0805_25V6K

C 6 BST_1.05V 1 2 1 2 DIS@ PL901 C

PC903
0.1U_0402_25V6

BS
2200P_0402_50V7K
1

@ PJP900
EMC PC905

PC902

DIS@ PC904

9 10 LX_1.05V 1 2 1 2
GND LX 1 2
2

@ 1UH_6.6A_20%_5X5X3_M JUMP_43X118

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM
1

100K_0402_1%
EMC

1
4

PR904

220P_0402_50V8J
DIS@ FB
Rup

PC907
DIS@

PC908

PC909

PC910

PC911
PR905 ILMT_1.05V 3 7
DIS@

ILMT BYP +3VALW

2
10K_0402_5%

DIS@
2
1 2 1.05VA_PG 2 5 @

DIS@
4.7U_0603_6.3V6K
+3VALW PG LDO

1
1
SYX196DQNC_QFN10_3X3 DIS@ PC913 FB = 0.6V

PC912
4.7U_0603_6.3V6K

1
DIS@

2
@ PR907 PR906
0_0402_5%

DIS@
133K_0402_1% DIS@ DIS@ DIS@
1 2
[23] 1.05V_DGPU_PG
DIS@
Pin 7 BYP is for CS. Rdown

2
Common NB can delete +3VALW and PC913
B B

+3VALW

VFB=0.6V
1

@ PR910
0_0402_5%
Vout=0.6V* (1+Rup/Rdown)
Vout=1.05V
2

ILMT_1.05V
1

PR912
0_0402_5%

@
2

A A
The current limit is set to 6A, 8A or 12A when thispin
is pull low, floating or pull high
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

GPU other power_Regulatorr(43.7), Support component(43.8) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR
Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
P40-PWR_+1.05VA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C. LA-C361P 0.1

Date: Tuesday, August 11, 2015 Sheet 62 of 71

5 4 3 2 1
 GPU_CORE (0.95V)
TDC 51A
Peak Current 87A
OCP current 100A
DCR 0.97mohm +/- 5%
@ PR1000

[23] GPU_VID_0
0_0402_5% TYP MAX
1 2
H/S Rds(on) : 7.4mohm , 8.8mohm
DIS@ EMCPL1004 L/S Rds(on) : 2.6mohm , 3.1mohm
HCB2012KF-121T50_0805
2 1
+3.3V_GFX_AON
DIS@ EMCPL1003
+VGA_B+ HCB2012KF-121T50_0805
2 1

1
DIS@ PR1001 B+

10U_0805_25VAK

10U_0805_25VAK
1

1
PC1000 10K_0402_1%

0.1U_0402_25V6
47P_0402_50V8J

2200P_0402_50V7K
DIS@ PC1001
0.1U_0402_25V6 PR1002

PC1006

EMC PC1007
DIS@ PC1002
19.6K_0402_1%

EMC PC1005
+GPU_CORE
2

1
+GPU_CORE (place under GPU)
DIS@
DIS@ DIS@ GPU_PSI [23]

2
@ @

2
PR1003 PR1004

EMC
2K_0402_1% 20K_0402_1% +GPU_CORE
1 2 1 2

DIS@ DIS@

4.7U_0603_6.3VAK

4.7U_0603_6.3VAK

4.7U_0603_6.3VAK

4.7U_0603_6.3VAK

4.7U_0603_6.3VAK

4.7U_0603_6.3VAK

4.7U_0603_6.3VAK

4.7U_0603_6.3VAK

4.7U_0603_6.3VAK

4.7U_0603_6.3VAK
+3.3V_GFX_RUN
Pull high by EE side
18.2K_0402_1%

.01U_0402_16V7K
1

1
PQ1000
PC1008

PC1012

PC1013

PC1014

PC1015

PC1016

PC1017

PC1018

PC1019

PC1020

PC1021
1

1
CSD87351Q5D_SON8-7
PR1005

DIS@ PC1009 @ PR1006 U2_UGATE1 2

2
2700P_0402_50V7K 47K_0402_1%
2

2
@ 1 2 DIS@ PR1007 DIS@ PC1010
2

DIS@ 2.2_0603_5% 0.1U_0603_50V7K 7 1 2

PR1028 U2_BOOT1 1 2 1 2 3 6
47K_0402_1% 5 0.22UH_24A_+-20%_7X7X4_M
DIS@ PL1000

1
1 2 4 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

10_1206_5%
3V3_MAIN_EN [23,32,62]

DIS@

EMC PC1025 EMC PR1008

330U_B2_2.5VM_R9M

330U_B2_2.5VM_R9M

330U_B2_2.5VM_R9M
DIS@ 1 1 1

GPU_REFADJ
U2_PHASE1

U2_UGATE1

1
+ + +

U2_BOOT1
PC1011

DIS@ PC1022

DIS@ PC1023

DIS@ PC1024

4.7U_0603_6.3VAK

4.7U_0603_6.3VAK

4.7U_0603_6.3VAK

4.7U_0603_6.3VAK

4.7U_0603_6.3VAK
8

2
GPU_VID

GPU_EN
0.01UF_0402_25V7K

1
PC1033

PC1027

PC1034

PC1028

PC1035
2 2 2

2
DIS@ U2_LGATE1

47P_0603_50V8J
1
DIS@

2
DIS@ PR1009 DIS@ PR1010 OCP set 100A
20_0402_1% 340K_0402_1%

2
+VGA_B+ 1 2 1 2

1
6 DIS@

1
PU1000 PR1011
PC1029
.01U_0402_16V7K
1

9.1K_0402_1% DIS@ DIS@ DIS@ DIS@ DIS@

REFADJ

UGATE1

BOOT1
PSI
VID

EN
@ PR1012 +VGA_B+
0_0402_5%
2

2
[24] GPU_VSS_SENSE 1 2 @ GPU_REFIN 7 24 U2_PHASE1
REFIN PHASE1
+5VS

1U_0402_6.3VAK

1U_0402_6.3VAK

1U_0402_6.3VAK

1U_0402_6.3VAK

1U_0402_6.3VAK

1U_0402_6.3VAK

1U_0402_6.3VAK

1U_0402_6.3VAK
DIS@ PR1013 GPU_VREF 8 23 U2_LGATE1 DIS@
VREF LGATE1

1
PC1070

PC1069

PC1063

PC1062

PC1044

PC1043

PC1004

PC1003
100_0402_1%

10U_0805_25VAK

10U_0805_25VAK
1 2 GPU_TON 9 22 U2_PWM3 PR1014

PC1041
0.1U_0402_25V6
TON GND/PW M3

2200P_0402_50V7K
2.2_0603_5%

EMC PC1039

PC1040
47P_0402_50V8J

2
@ PR1015 @ PC1036 10 21 1 2

PC1037

DIS@ PC1038
GPU_FBRTN GPU_PVCC
RGND PVCC

1
0_0402_5% 33P_0402_50V8J
[24] GPU_VDD_SENSE 1 2 1 2 1 2 GPU_FB 11 20 U2_LGATE2 @
TALERT/ISEN2

VSNS LAGTE2

1
DIS@ PC1042 @
TSNS/ISEN3

VCC/ISNE1

2
DIS@ PR1017 @ PR1016 GPU_COMP 12 19 U2_PHASE2 .1U_0603_25V7K

DIS@

EMC

EMC
SS PHASE2
UGATE2

100_0402_1% 0_0402_5% DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
PGOOD

BOOT2

2
+GPU_CORE 1 2
GND

DIS@
RT8813AGQW _W QFN24_4X4 DIS@
+GPU_CORE
25

13

14

15

16

17

18

+GPU_CORE (place near GPU)

@ PR1018 @ PC1045 PQ1001

1
15.8K_0402_1% .01U_0402_16V7K CSD87351Q5D_SON8-7
1 2 1 2 U2_UGATE2 2
DIS@ PL1001
PR1019 PC1047 0.22UH_24A_+-20%_7X7X4_M
2.2_0603_5% 0.1U_0603_50V7K 7 1 2

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K
GPU_PGOOD

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1 2 DIS@ DIS@ U2_BOOT2 1 2 1 2 3 6 1 1 1
U2_UGATE2

5
U2_BOOT2

PR1020

PC1053

PC1054

PC1050
10_1206_5%

1
@ PC1046 10K_0402_1% DIS@ DIS@ 4

EMC PR1021

PC1049

PC1051
1
0.01UF_0402_25V7K U2_PHASE3 1 2 U2_PHASE2
PR1022 2 2 2

DIS@

2
10K_0402_1%
U2_PHASE2 1 2 U2_LGATE2

8
PR1023

2
DIS@ 10K_0402_1%
U2_PHASE1 1 2

47P_0603_50V8J
1
DIS@ DIS@ DIS@ DIS@ DIS@

DIS@

EMC PC1055
DIS@ PR1024
1_0402_5%

2
1 2 DGPU_PWROK [18] +VGA_B+

DIS@

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
Pull high by EE side

10U_0805_25VAK

10U_0805_25VAK

1
PC1048

PC1052

PC1071

PC1072

PC1073

PC1074

PC1075

PC1076

PC1077

PC1079

PC1080

PC1081

PC1082

PC1083
0.1U_0402_25V6

2200P_0402_50V7K
PC1065

PC1066
47P_0402_50V8J
PC1060

DIS@ PC1061

EMC PC1064

2
1

1
@ @

2
EMC

EMC
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
DIS@

DIS@
DIS@
PU1001 DIS@
@ PR1025 RT9610BZQW _W DFN8_2X2~D PQ1002

1
0_0402_5% DIS@ DIS@ CSD87351Q5D_SON8-7 Under:

15P_0402_50V8J

15P_0402_50V8J

15P_0402_50V8J

15P_0402_50V8J
GPU_EN 1 2 1 3 U2_UGATE3 PR1026 PC1067 2

PC1056
EN UGATE 1. 4.7uF*15 (SE000008L80)

1
2.2_0603_5% 0.1U_0603_50V7K DIS@ PL1002

PC1057

PC1058

PC1059
+5VS 8 4 U2_BOOT3 1 2 1 2 0.22UH_24A_+-20%_7X7X4_M 2. 1uF*8(SE00000WV00)
U2_PWM3 5 VCC BOOT 7 1 2 Near:
PW M

2
2 U2_PHASE3 3 6 1. 4.7uF*5 (SE093475K80)
6 PHASE 5 @ @ @ @
GND 2. 22uF*14 (SE000001120)

1
9 7 U2_LGATE3 4 DIS@
GND LGATE
PR1027 EMC
10_1206_5%

2
DIS@

1
PC1068 EMC
47P_0603_50V8J

2
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.
Title

VGA_CORE controller(43.1), Support component(43.2) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR
Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL VGA_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D Size Document Number Rev
VGA_CORE Drivers (43.3), GPU Core Output CAP (43.9) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
LA-C361P 1.0(A00)

Date: Tuesday, August 11, 2015 Sheet 63 of 71

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH

OUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN
C.
 5 4 3 2 1

PROG sets (Base on FNTBD.6 July 25, 2014)

PROG1 Vboot :0V
slew rate :30 mV/uS
PROG2 IMAX VR A :70A
+VCCST +5VS Vcore_B+ PROG3 IMAX VR A :55A
PR1100
DROOP VR GT :Active
PROG4 DROOP VR A: Active
12.1K_0402_1%
DROOP VR SA :Active
VR A and VR GT SWITCHING FREQUENCY:583 (kHz)

1
1 2

1_0402_5%
0.1U_0402_10V7K
@ PR1102
PROG5 VR SA IMAX(A):12A

PR1101
D D
0_0402_5% PC1101

PC1137
VR SA SWITCHING FREQUENCY :450 (kHz)

1
PC1100

45.3_0402_1%

100_0402_1%

2
1

1
1 2 1U_0402_16V6K

PR1131

PR1145
2
1 2
4700P_0402_25V7K
PR1104

2
PR1318
1 2 10_0402_1% 1 2
PH1100 [9] VR_SVID_DATA 1 2 VR_SVID_DATA_C
470K_0402_5%_ TSM0B474J4702RE @ PR1132 PC1102
95.3K_0402_1% 1 2 0_0402_5% 0.22U_0603_16V7K
PC1103 1 2VR_SVID_ALERT#_C
[9] VR_SVID_ALERT#
1 2 NTC of GT at 100 deg
[9] VR_SVID_CLK 1 2VR_SVID_CLK_C
PR1319
330P_0402_50V7K PR1105 49.9_0402_1%
10.2K_0402_1% 1 2
[9,48,56] H_PROCHOT#
1 2 1 2 PR1103
100_0402_1%

16.9K_0402_1%

5.62K_0402_1%
+3VS

1
PR1106 PC1139 PR1114

1
27.4K_0402_1% 1000P_0402_50V7K 1.91K_0402_1% PR1110

PR1108

PR1109
165K_0402_1%
1 2 1 2 110K_0402_1%

PR1107
PC1104 @ PR1119
47P_0402_50V8J 0_0402_5%

2
1 2 1 2

2
[18] IMVP_VR_PG
PC1138 PR1143 @ PR1118 OCP of SA at 16.78A
470P_0402_50V7K 2K_0402_1% 0_0402_5%
PR1115
1 2 1 2 1 2 2 1 [34] VR_ON 1 2
1 2 ISUMN_SA [66]
PC1105 PR1111

1
8200P_0402_25V7K 3.6K_0402_1%
PU1100 1.18K_0402_1% 10K_0402_5%_B25/50 4250K
PC1106 PR1112 [48,56] P_SYS PC1108 PR1117 PH1101
680P_0402_50V7K 1K_0402_1% ISL95829HRTZ-T_TQFN48_6X6 PR1116

48
47
46
45
44
43
42
41
40
39
38
37
C C

11K_0402_1%
.1U_0402_16V7K

.047U_0402_16V7K
1

1
1 2 1 2 48.7K_0402_1% 2 1 2 1

1 2
1 2

PC1111

PC1136

PR1120
VR_ENABLE
VR_READY
VR_HOT#

ALERT#
SCLK

PROG1
PROG2
PROG3
PROG4
VCC
SDA

VIN

0.1U_0402_25V6

2.61K_0402_1%
1

1
2200P_0402_50V7K 1K_0402_1%

PC1110

2
PR1113

PR1121
PWM_SA [66]
2.94K_0402_1%

2
[12] VCCGT_SENSE 1 2 FCCM_SA [66] @
1 36
PSYS PROG5

2
Droop of GT at 2.65mV/A 2 35
[12] VSSGT_SENSE IMON_B PWM_C
3 34
NTC_B FCCM_C
1

4 33
5 COMP_B ISUMN_C 32
PC1109 ISUMP_SA [66]
6 FB_B ISUMP_C 31
0.01UF_0402_25V7K VSSSA_SENSE [11]
RTN_B RTN_C
2

7 30 1 2 1 2
ISUMP_B FB_C VCCSA_SENSE [11]
8 29
ISUMN_B COMP_C

1
9 28 PR1125 PC1118
10 ISEN1_B IMON_C 27
[66] ISUMP_GT 1K_0402_1% 220P_0402_50V8J PC1121
11 ISEN2_B PWM3_A 26 1 2 0.01UF_0402_25V7K

2.05K_0402_1%
FCCM_B PWM2_A

2
12 25

680P_0402_50V7K 2K_0402_1%
PWM1_B PWM1_A
2.61K_0402_1%
1

1
PR1128
PR1122

330P_0402_50V7K

1
2.49K_0402_1%
10K_0402_5%_B25/50 4250K

PR1124
PR1126
0.22U_0402_16V7K

PR1127 PC1113

ISUMN_A
ISUMP_A
PWM2_B

COMP_A

ISEN1_A
ISEN2_A
ISEN3_A
FCCM_A
0.033U_0402_16V7K
1

49

IMON_A
Droop of SA at 9.1mV/A

NTC_A

RTN_A
EP

68P_0402_50V8J
11K_0402_1%

1
1 2 1 2

FB_A
PR1123

PC1114
PC1133

PC1112

113K_0402_1%
1 2

1 2
1

1
PR1129

PC1115
2

2
1K_0402_1% 2200P_0402_50V7K PWM3_VCORE [65]

PC1116
2200P_0402_50V7K
PH1102

13
14
15
16
17
18
19
20
21
22
23
24
2

2
@ PWM2_VCORE [65]

PC1117
2

2
1
PR1130 PWM1_VCORE [65]
2

[66] ISUMN_GT 1 2

2
FCCM_VCORE [65]
470_0402_1%
1

PC1119
.1U_0402_16V7K

OCP of GT at 66.71A 1 2
2

PC1122 PC1120 0.022U_0402_25V7K

[65] ISEN3_VCORE
B ISEN2_GT [66] B
1 2
1 2
0.022U_0402_25V7K
PC1123 0.022U_0402_25V7K ISUMN_VCORE [65]
PC1125 [65] ISEN2_VCORE
0.022U_0402_25V7K 1 2
ISEN1_GT [66]

1
1 2

.1U_0402_16V7K
PC1124 0.022U_0402_25V7K PH1103

PC1126
PR1133

11K_0402_1%
[65] ISEN1_VCORE

1
[66] FCCM_GT 10K_0402_5%_B25/50 4250K

0.22U_0402_16V7K
2
1 2

PR1134

2.61K_0402_1%
.047U_0402_16V7K
1

1
[66] PWM1_GT

2
390_0402_1% OCP of Vcore at 83.2A

PC1127

PC1135
[66] PWM2_GT PC1128 PR1135

PR1136
1 2 1 2

2200P_0402_50V7K 1K_0402_1%

2
ISUMP_VCORE [65]
NTC of CORE at 100 deg
VSS_SENSE [10]
PR1144
10.2K_0402_1% 1 2 1 2 VCC_SENSE [10]
1 2

1
PR1140 PC1130 PC1107
90.9K_0402_1%

1K_0402_1% 470P_0402_50V7K 0.01UF_0402_25V7K

27.4K_0402_1%
1

2
PR1137

680P_0402_50V7K 2K_0402_1%

2
330P_0402_50V7K

2 1
470K_0402_5%_ TSM0B474J4702RE
PC1129

PR1138

PH1104

PR1139
2

PR1142
2

PR1141 2.43K_0402_1%
1

4.87K_0402_1%
1

1 2
1

68P_0402_50V8J

Droop of CORE at 1.8mV/A

PC1132
PC1131

2
2

A A
2

PC1134
8200P_0402_25V7K
1

Title
<Title>
CPU_Vcore controller(36.1),Drivers(36.2), Support component(36.3) Size Document Number Rev
Acoustic Noise B+ Bulk CAP(37.2) Custom LA-C361P <RevCode>

Date: Tuesday, August 11, 2015 Sheet 64 of 71

5 4 3 2 1
 5 4 3 2 1

B+ Vcore_B+
PWM1_VCORE [64]
VCC_core (Base on PDDG rev 0.7)
+5VS PL2 TDC__default):TB
@
PL1204 EMC PC1200
[64,65] FCCM_VCORE
PU1200 +5VS PL2 TDC_max (40Sec):56A
HCB2012KF-121T50_0805
1 2
4.7U_0402_6.3V6M Peak Current 68A
1 2 PC1201 PR1224 13 Vcore_B+ DC Load line -1.8mV/A
@ PL1203 EMC
HCB2012KF-121T50_0805
0.1U_0402_25V6 2.2_0402_1% 1
2 SMOD
PW M
EN
12
11
PL1200 +VCC_CORE
AC Load line -1.8mV/A
1 2 2 1 1 2 3 VCC
BOOT
VIN
CGND
10 0.22UH_24A_+-20%_7X7X4_M OCP Current 83.2A
@ PJP1200
4
5 GH GL
9
8 1 2
DCR 0.97mohm +/-5%
1 2 6 VSW H VSW H 7
1 2 VIN PGND

1
D D

1
JUMP_43X118

PR1200
47P_0603_50V8J 10_1206_5%
PR1218 PR1219
0_0402_5% 0_0402_5%

EMC
AOZ5019QI_QFN23_5X3P5 @ @

2
100U_D_20VM_R55M

2
1 1
100U_D_20VM_R55M

10U_0805_25VAK

1
2200P_0402_50V7K
V1N

0.1U_0402_25V6

EMC PC1209
10U_0805_25VAK

EMC
舖舖舖舖

1
+ +

EMC PC1214
PC1256

PC1210

PC1211

PC1212

1.5P_0402_50V8C
1

2
PC1277
2 2 2

PC1213

100K_0402_1%

100K_0402_1%
2

100K_0402_1%
1

1
PR1201

PR1213
2.2_0402_1%
3.65K_0603_1%

PR1203

PR1212
PR1202
EMC

2
[64] ISEN1_VCORE

[64] ISUMP_VCORE

Polymer cap for noise issue

[64] ISUMN_VCORE

ISEN2_VCORE

[64] PWM2_VCORE

[64,65] FCCM_VCORE ISEN3_VCORE

PC1227
+5VS PU1201 +5VS
4.7U_0402_6.3V6M
C C
1 2 PC1228 PR1225 13 Vcore_B+
1 PW M 12
0.1U_0402_25V6 2.2_0402_1% PL1201
2 SMOD EN 11
2 1 1 2 3 VCC VIN 10 0.22UH_24A_+-20%_7X7X4_M
4 BOOT CGND 9
5 GH GL 8 1 2
6 VSW H VSW H 7
VIN PGND

1
EMC PR1204
10_1206_5%
PR1220 PR1221
AOZ5019QI_QFN23_5X3P5 0_0402_5% 0_0402_5%
@ @

2
2200P_0402_50V7K
10U_0805_25VAK

2
EMC PC1237
0.1U_0402_25V6
10U_0805_25VAK
1

V2N
PC1238
PC1235

PC1236

舖舖舖舖

1
EMC PC1234
47P_0603_50V8J

100K_0402_1%

100K_0402_1%
2

2
2.2_0402_1%

100K_0402_1%
3.65K_0603_1%
2

1
PR1205

PR1215
PR1206
EMC

PR1207

PR1214
2

1
2

2
[64] ISEN2_VCORE

ISUMP_VCORE

[64,65] FCCM_VCORE ISUMN_VCORE

[64] PWM3_VCORE
ISEN1_VCORE
PC1249 +5VS +5VS
PU1202
B B
4.7U_0402_6.3V6M
ISEN3_VCORE
1 2 13 Vcore_B+
1 PW M 12 PL1202
2 SMOD EN 11
2 1 1 2 3 VCC VIN 10 0.22UH_24A_+-20%_7X7X4_M
4 BOOT CGND 9
5 GH GL 8 1 2
6 VSW H VSW H 7
VIN PGND
PC1250 PR1226
1

1
0.1U_0402_25V6 2.2_0402_1%
PR1208
10_1206_5%

PR1222 PR1223
AOZ5019QI_QFN23_5X3P5 0_0402_5% 0_0402_5%
@ @
2200P_0402_50V7K
10U_0805_25VAK

EMC
2

2
EMC PC1253
0.1U_0402_25V6
10U_0805_25VAK
1

EMC PC1254
PC1251

PC1252

舖舖舖舖
V3N
PC1255
47P_0603_50V8J
1
2

1
100K_0402_1%

3.65K_0603_1%
2

PR1210

100K_0402_1%
EMC

PR1209

100K_0402_1%
2

1
PR1217
2.2_0402_1%
PR1211

PR1216
2
2

[64] ISEN3_VCORE
1

2
ISUMP_VCORE

ISUMN_VCORE

ISEN1_VCORE

A A

ISEN2_VCORE

Title
<Title>
CPU_Vcore controller(36.1),Drivers(36.2), Support component(36.3),
Size Document Number Rev
CPU_Core output CAP(36.4),Acoustic Noise B+ Bulk CAP(37.2) C LA-C361P <RevCode>

Date: Tuesday, August 11, 2015 Sheet 65 of 71

5 4 3 2 1
 5 4 3 2 1

VCCGT (Base on PDDG rev 0.7)

PL2 TDC__default):TB
PL2 TDC_max (40Sec):39A
Max Current 55A
DC Load line -2.65mV/A
AC Load line -2.65mV/A
OCP Current 66.7A
DCR 0.97mohm +/-5%

[64,66] FCCM_GT
D D
[64] PWM1_GT
B+ +5VS

@ PL1304 EMC +5VS PU1300

HCB2012KF-121T50_0805 PC1302 AOZ5019QI_QFN23_5X3P5
1 2 1U_0402_16V6K
1 2 13 +VCCGT
@ PWM
PL1303 EMC 1
SMOD EN
12 PL1300
HCB2012KF-121T50_0805 2 11
1 2 VCC VIN
PC1308 2 1 1 2 3
BOOT CGND
10 0.22UH_24A_+-20%_7X7X4_M
0.1U_0402_25V6 4 9
GH GL
@ PJP1300 5 8 1 2
2 1 6 VSWH VSWH 7
2 1 PR1320 VIN PGND
VCCGT_B+

PR1300

4.7_1206_5%
1

1
JUMP_43X118 2.2_0402_1%
PR1312 PR1313
0_0402_5% 0_0402_5%

EMC
@ @
EMC

2
PC1317 EMC
2200P_0402_50V7K

680P_0603_50V7K
10U_0805_25VAK

舖舖舖舖

1
PC1319
0.1U_0402_25V6

PC1318
10U_0805_25VAK
1

1
PC1315

PC1316

2
2

3.65K_0603_1%
EMC

2
PR1301
PR1302

1
2.2_0402_1%
100K_0402_1%
PR1303

1
2
[64] ISUMP_GT

[64] ISEN1_GT

[64,66] FCCM_GT [64] ISUMN_GT

C [64] PWM2_GT C
+5VS
+5VS PU1301
PC1336 AOZ5019QI_QFN23_5X3P5
1U_0402_16V6K
1 2
13 PL1301
1 PWM 12
PC1337 SMOD EN
0.1U_0402_25V6 2 11 0.22UH_24A_+-20%_7X7X4_M
2 1 1 2 3 VCC VIN 10
4 BOOT CGND 9 1 2
5 GH GL 8
6 VSWH VSWH 7
VIN PGND

1
PR1307

4.7_1206_5%
1

PR1321 PR1314 PR1315

2.2_0402_1% 0_0402_5% 0_0402_5%
@ @
EMC

2
EMC

1 2
PC1346 EMC

舖舖舖舖
2200P_0402_50V7K

3.65K_0603_1%
10U_0805_25VAK

1
PC1345
0.1U_0402_25V6

680P_0603_50V7K
10U_0805_25VAK

PC1347
1

1
PR1306
PC1343

PC1344

PR1305

100K_0402_1%
2

PR1304
2.2_0402_1%
2

EMC

2
ISUMP_GT

[64] ISEN2_GT

ISUMN_GT

B+ @ PL1305 EMC
HCB2012KF-121T50_0805
1 2

@ PJP1301
2 1
2 1 PQ1300
B JUMP_43X118 B
FCCM_SA [64] AON7934_DFN3X3A8-10
4

PU1302 0.47UH_PCMB053T-R47MS_12A_20%
ISL95808HRZ-TS2378_DFN8_2X2 +VCCSA
EMC PC1357
2200P_0402_50V7K

10U_0805_25VAK

D1

D1

D1

G1
0.1U_0402_25V6

10U_0805_25VAK

PL1306
1

1 8
PC1355

PC1356

PC1358

UGATE PHASE +5VS 10 9 1 2

2 7 D1 D2/S1
BOOT FCCM
2

3 6
PR1308
G2

4.7_1206_5%

[64] PWM_SA
S2

S2

S2
EMC

PWM VCC
1

4 5
GND LGATE
5

8
TP

1
EMC

PR1316 PR1317
9

0_0402_5% 0_0402_5%
2

@ @
PC1364
2

2
1

1U_0402_16V6K
1

680P_0603_50V7K

舖舖舖舖
PC1365
2
EMC

@ PR1311
1

0_0402_5%
3.65K_0603_1%

1 2 2 1 @
PR1309

PR1310
PC1313 0_0402_5%
0.1U_0402_25V6
VCCSA (Base on PDDG rev 0.7)
2

PL2 TDC__default):TBD
[64] ISUMP_SA PL2 TDC_max (40Sec):10A
Max Current 11A
DC Load line -9.1mV/A
[64] ISUMN_SA AC Load line -9.1mV/A
A
OCP Current 20A A

DCR 7.4mohm/8.5mohm +/-5%

Title
<Title>
CPU_Vcore controller(36.1),Drivers(36.2), Support component(36.3),
Size Document Number Rev
GFX output CAP(36.5) Custom LA-C361P <RevCode>

Date: Tuesday, August 11, 2015 Sheet 66 of 71

5 4 3 2 1
 A

D
.1uF*15
1uF*6
220uF*1
22uF*9
470uF*2
+VCC_CORE
.1uF*15
1uF*6
22uF*26
47uF*9
470uF*2
+VCCGT
5

+VCC_CORE

5
+VCCGT
2 1 2 1

1
+
PC1221 PC1220 PC1207
1U_0402_6.3V6K 22U_0603_6.3V6M 470U_D2_2VM_R4.5M~D
PC1326 2 1
.1U_0402_16V7K 2 1

1
+
2 1 2 1 2 1 2 1 PC1261 PC1208

1
+
PC1307 PC1222 22U_0603_6.3V6M 470U_D2_2VM_R4.5M~D
PC1327 PC1320 PC1366 PC1314 470U_D2_2VM_R4.5M~D 1U_0402_6.3V6K 2 1
.1U_0402_16V7K 1U_0402_6.3V6K 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 PC1263

1
+
2 1 22U_0603_6.3V6M PC1262

@
2

1
+
PC1328 PC1363 PC1348 PC1301 PC1223 220U_D7_2VM_R6M
.1U_0402_16V7K PC1321 22U_0603_6.3V6M 22U_0603_6.3V6M 470U_D2_2VM_R4.5M~D 1U_0402_6.3V6K 2 1
2 1 1U_0402_6.3V6K 2 1 2 1

1
+
2 1 2 1 PC1274 PC1397
PC1329 2 1 PC1368 PC1350 22U_0603_6.3V6M 220U_D7_2VM_R6M
.1U_0402_16V7K 22U_0603_6.3V6M 22U_0603_6.3V6M PC1303 PC1224
2 1 PC1322 2 1 2 1 47U_0805_6.3V6M 1U_0402_6.3V6K 2 1
1U_0402_6.3V6K
PC1330 PC1367 PC1349 2 1 2 1 PC1264
.1U_0402_16V7K 2 1 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 PC1304 PC1225 2 1
4

4
PC1331 PC1323 47U_0805_6.3V6M 1U_0402_6.3V6K

ADD:220uF*1

DEL:47uF*9
.1U_0402_16V7K 1U_0402_6.3V6K PC1370 PC1352 PC1265
2 1 22U_0603_6.3V6M 22U_0603_6.3V6M 2 1 2 1 22U_0603_6.3V6M
2 1 2 1 2 1 2 1

22uF*13
PC1332 PC1305 PC1226
.1U_0402_16V7K PC1324 PC1369 PC1351 47U_0805_6.3V6M 1U_0402_6.3V6K PC1269
2 1 1U_0402_6.3V6K 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1
PC1333 2 1
.1U_0402_16V7K PC1373 PC1354 PC1300 PC1229 PC1271
2 1 PC1325 22U_0603_6.3V6M 22U_0603_6.3V6M 47U_0805_6.3V6M .1U_0402_16V7K 22U_0603_6.3V6M
1U_0402_6.3V6K 2 1 2 1
PC1334 2 1 2 1 2 1
.1U_0402_16V7K PC1372 PC1353
2 1 22U_0603_6.3V6M 22U_0603_6.3V6M PC1306 PC1230 PC1276
2 1 2 1 47U_0805_6.3V6M .1U_0402_16V7K 22U_0603_6.3V6M
PC1335 2 1 2 1
.1U_0402_16V7K PC1376 PC1360
2 1 22U_0603_6.3V6M 22U_0603_6.3V6M PC1309 PC1231
2 1 2 1 47U_0805_6.3V6M .1U_0402_16V7K
PC1338 2 1
.1U_0402_16V7K PC1374 PC1359 2 1
2 1 22U_0603_6.3V6M 22U_0603_6.3V6M PC1232
2 1 2 1 PC1310 .1U_0402_16V7K
PC1339 47U_0805_6.3V6M 2 1
.1U_0402_16V7K PC1377 PC1362
2 1 22U_0603_6.3V6M 22U_0603_6.3V6M 2 1 PC1233
2 1 2 1 .1U_0402_16V7K
PC1340 PC1311 2 1
3

3
.1U_0402_16V7K PC1375 PC1361 47U_0805_6.3V6M
2 1 22U_0603_6.3V6M 22U_0603_6.3V6M PC1239
2 1 2 1 2 1 .1U_0402_16V7K
PC1341 2 1
.1U_0402_16V7K PC1379 PC1378 PC1312
2 1 22U_0603_6.3V6M 22U_0603_6.3V6M 47U_0805_6.3V6M PC1240
.1U_0402_16V7K
2 1
PC1342
.1U_0402_16V7K PC1241
2 1 .1U_0402_16V7K
2 1

PC1242
.1U_0402_16V7K
2 1

PC1243
.1U_0402_16V7K
2 1

PC1244
.1U_0402_16V7K
2 1
+VCCSA

PC1245
.1U_0402_16V7K
2 1
2

2
PC1246
PC1384 .1U_0402_16V7K
.1U_0402_16V7K 2 1
2 1 2 1 2 1 2 1
PC1247
PC1383 PC1385 PC1391 PC1388 .1U_0402_16V7K
.1U_0402_16V7K 22U_0603_6.3V6M 22U_0603_6.3V6M 47U_0805_6.3V6M
2 1 2 1 2 1 2 1
2 1
PC1380 PC1396 PC1248
22U_0603_6.3V6M 22U_0603_6.3V6M PC1382 .1U_0402_16V7K
2 1 2 1 47U_0805_6.3V6M
PC1389 PC1386 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 PC1393
47U_0805_6.3V6M
PC1394 PC1390
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1

PC1395
22U_0603_6.3V6M
1

1
.1uF*2
22uF*9
47uF*3
+VCCSA
A

D
 5 4 3 2 1

Version Change List ( P. I. R. Page

Page# Title Date List Owner
Request ) Issue 1 Solution Rev.
Description Description
D D

C C

B B

A A

5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List ) Page 1

Request
Page# Title Date Owner Issue Description Solution Description Rev.

D D

C C

B B

A A

5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List ) Page 1

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
1 6 XDP 2014/12/12 EE Change Pull high power for leakage issue Change RH494,RH495,RH496 from +VCCST to +VCCSTG, de
-POP RH97,RH98,RH100, POP RH494,RH495. X01
2 18 GPIO 2014/12/12 EE Change Pull high power for double pull high the sam
e power rail Change RH571 power rail from +3VS to +3
V_PCH, de-pop RH571, delete RH532. X01
D D
3 18 SPI 2014/12/12 EE Change SPI ROM for ME register setting Change UH8 from W25Q128FVSIG_SO8 to W25Q128FVSIQ_SO
8 X01
4 18 S0iX 2014/12/12 EE Change by pass circuit design for CS mode function hange
C RZ58 connection from UZ11.2 to UZ11.4, ChangeRZ60 connection from UZ12.2 to UZ12.4 X01
5 18 +1V_MPHY 2014/12/12 EE Delete +1V_MPHY load switch & discharge circuit foruseless. Delete RH514,RH559,RH144,QH9,UH13,CH193,CH
194,CH195. Delete net MPHYP_PWR_EN, move RZ70 to pa
ge 21 X01
Update UT5 from W25Q80BLZPIG_WSON8 to W25Q80DVSSIG_
SO8,Delete RT166,Change net VCC3V3_TBTA_LDO to VCC3
V3_FLASH. Change net
6 18 PD 2014/12/22 EE Update TI PD controller circuit follow Mirama VCC3V3_SX_SYS to +3VA_TBT. Add RT198 to PWR_SRC_ILI
MIT.Swap UT4.B2/C2 net. Update RT165 from 1206 to 805,
0 RT167,RT168, X01
RT169.RT170,RT171,RT179,RT186,RT187,RT188,RT189,RT1
92,RT192,RT196,RT197 from 0402 to 0201. Add RT200,R
T201 to net
UPD_SMBDAT/UPD_SMBCLK" X01
7 18 EC 2014/12/15 EE Update Board ID for EC Update RE67 to 62K X01
8 18 PM 2014/12/15 EE modify for support deep sleep function De-pop RH506 X01
9 18 DDR 2014/12/15 EE change Power rail for correct design Change RH525 power rail from +3VALW to +3VS X01
10 18 SPK 2014/12/15 EE Add pull high resistor for MB side Add RH572 to +3VS for SPK_DET# X01
11 18 GPIO 2014/12/15 EE Change GPIO for sync common GPIO table Change net DGPU_PWR_EN from GPP_D13 to GPP_D12 X01
12 18 PD 2014/12/15 EE Pin swap for DFB review pin swap DT4,DT9 X01
13 18 PCH 2014/12/15 EE Add Capacitor for follow Schematic check list Add CH200 to +3V_PCH (Close to UH2.BA15) X01
C 14 18 DIS 2014/12/15 EE Add pull high resistor by vendor request Add RPH34 replace to RV520,RV521,RV522 and add netTHERMAL_ALERT#. X01 C

15 18 SPI 2014/12/15 EE Follow CRB XDP design Add RH574,RH575 for SPI to XDP connector X01
16 18 VDDQC 2014/12/16 EE Follow CRB boardfile POP RH473 X01
17 18 DEBUG 2014/12/16 EE Add Debug signal by EC request Change net BID_BC to GPP_C15, Add Net UARTT0_TX fro
m GPP_C9 to JDEG1.pin 9 X01
18 18 DEBUG 2014/12/16 EE Modify Debug UART from closed Chassis toOpen Chassis Delet UI6,RI29.Add JUART for UART2_TXD/UART2_RXD co
nnect. X01
19 18 SCI 2014/12/16 EE Change PU resistor follow Miramar RH383 change from 100K to 10K X01
20 18 HOLE 2014/12/16 EE Add 2 PAD for ME NUT Add H50, H51 X01
21 18 EC 2014/12/16 EE Add series resistor follow CRB Add RE111 43K series SIO_SLP_SUS# X01
22 18 PCH 2014/12/16 EE Change BOM to follow CRB Change RH88 from 10K to 47K, De-POP RE33. X01
Add RE112 and Connect net BID_DIS to UE3.A10, swapNet BAT1_LED#(UE3.B1=>UE3.A40)/BAT2_LED#(UE3.A55=>U
E3.B43)/
23 18 EC 2014/12/17 EE Modify GPIO for follow GPIO MAP by Dell PCH_PCIE_WAKE#(UE3.A40=>UE3.B46)/ME_FWP_EC(UE3.B46=
>UE3.B1)/USB_PWR_SHR_LFT_EN#(UE3.B43=>UE3.A55) X01
24 18 EC 2014/12/17 EE Update BOM for design change de-POP RE27, RE63, POP RH453 X01
25 18 NGFF 2014/12/17 EE Update NGFF from Key E. to Key A. Change JNGFF1 to CONCR_213AAAA32FA

26 18 PCH 2014/12/17 EE Change array resistor to resistor for routing Change RP21 to RH576,RH577,RH578,RH579. Add RE113,R
E114,RE115 for UE1.
B B

27 18 USB 2014/12/18 EE Change net name by EC request USB_PWR_SHR_VBUS_LFT_EN -> USB_PWR_SHR_VBUS_EN_L, SB_PWR_SHR_VBUS_RHT_EN1
U -> USB_PWR_SHR_VBUS_EN_R,
USB_PWR_SHR_LFT_EN# -> USB_PWR_SHR_EN_L#, USB_PWR_S
HR_RHT_EN1# -> USB_PWR_SHR_EN_R#,
USB2_DET_EC# -> USB_DET_EC_L#, USB1_DET_EC# -> USB_
DET_EC_R#

28 18 TS 2014/12/18 EE Update Touch Screen Connector by ME request Update JTS to ACES_50208-00601-P01

29 18 USB 2014/12/18 EE Add Pull down resistor for USB2.0 Add RH580,RH581 to UH2.AD10,UH2.AG2 to GND

30 18 AR 2014/12/19 EE Reserve test point for Alpine Ridge Add T199,T200,T201

31 18 PD 2014/12/22 EE Delete commmon mode chok & ESD for vendor feedback Delete LT10,DT5

32 18 EC 2014/12/22 EE Delete I2C signal from EC to Codec. Delete QE14

33
34
35
36
37
A A
38
39

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/04/10 Deciphered Date 2014/05/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
NOTE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
O UT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C. LA-B072P 1.0

Date: Thursday, August 06, 2015 Sheet 70 of 71

5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List ) Page 2

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
1 NA NA 2014/12/12 EE NA NA X01
2 EE X01
D D
3 EE X01
4 EE X01
5 EE X01
6 EE X01
7 EE X01
8 EE X01
9 EE X01
10 EE X01
11 EE X01
12 EE X01
13 EE X01
14 EE X01
C 15 EE X01 C

16 EE X01
17 EE X01
18 EE X01
19 EE X01
20 EE X01
21 EE X01
22 EE X01
23 EE X01
24 EE X01
25 EE X01
26 EE
27 EE
B B

28 EE
29 EE
30 EE
31 EE
32 EE
33 EE
34 EE
35 EE
36 EE
37 EE
38 EE
39 EE
A A
40 EE
41 EE

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/04/10 Deciphered Date 2014/05/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR

Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSCONFIDENTIAL
NOTE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BETRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH
CS, INC. NEITHER THIS SHEET NOR THE INFORMATION ITCONTAINS
O UT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C. LA-B072P 1.0

Date: Thursday, August 06, 2015 Sheet 71 of 71

5 4 3 2 1