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Manual
Revision 1.2
IC615
Assura 410
Incisive Unified Simulator 92
Developed By
University Support Team
Cadence Design Systems, Bangalore
1
Objective
Objective of this lab is to learn the Virtuoso tool as well learn the flow of
the Full Custom IC design cycle. You will finish the lab by running DRC,
LVS and Parasitic Extraction on the various designs. In the process you
will create various components like inverter, differential amplifier but we
won’t be designing every cell, as the time will not be sufficient, instead we
will be using some ready made cells in the process.
You will start the lab by creating a library called ―myDesignLib‖ and you
will attach the library to a technology library called ―gpdk180‖. Attaching
a technology library will ensure that you can do front to back design.
You will create a new cell called ―Inverter‖ with schematic view and
hence build the inverter schematic by instantiating various components.
Once inverter schematic is done, symbol for ―Inverter‖ is generated. Now
you will create a new cell view called ―Inverter_Test‖, where you will
instantiate ―Inverter‖ symbol. This circuit is verified by doing various
simulations using spectre. In the process, you will learn to use spectre,
waveform window options, waveform calculator, etc...
After completing the parasitic back- annotation flow, design is ready for
generating GDSII.
2
Table of Contents
General Notes ........................................................................................ 5
Lab 1: AN INVERTER............................................................................. 9
Schematic Entry ................................................................. 10
Building the Inverter_Test Design ....................................... 19
Analog Simulation .............................................................. 21
Creating Layout View of Inverter ......................................... 29
Parasitic Extraction ............................................................ 32
Creating the Configuration View ......................................... 37
Generating Stream Data ..................................................... 43
Lab 2: MOS DIFFERENTIAL
AMPLIFIER…………………………………………...45
Schematic Entry ................................................................. 46
Analog Simulation….. ......................................................... 51
Creating a Layout View of Diff_ Amplifier ..... Error! Bookmark
not defined.
Physical Verification ............... Error! Bookmark not defined.
Lab 3: COMMON SOURCE AMPLIFIER ............................................... 62
Schematic Entry ................................................................. 63
Symbol Creation ..................... Error! Bookmark not defined.
Building the Common Source Amplifier Test Design ........... 64
Analog Simulation with Spectre ............ Error! Bookmark not
defined.
Creating a layout view of Common Source Amplifier ...... Error!
Bookmark not defined.
Lab 4: COMMON DRAIN AMPLIFIER ...... Error! Bookmark not defined.
Schematic Entry ..................... Error! Bookmark not defined.
Symbol Creation ..................... Error! Bookmark not defined.
Building the Common Drain Amplifier Test Design ........ Error!
Bookmark not defined.
Analog Simulation with Spectre .......................................... 70
Creating a layout view of Common Drain Amplifier ............. 71
Lab 5: OPERATIONAL AMPLIFIER ...................................................... 72
Schematic Entry ................................................................. 73
Symbol Creation ................................................................. 73
3
Building the Operational Amplifier Test Design ................... 74
Analog Simulation with Spectre ............ Error! Bookmark not
defined.
Creating a layout view of Operational Amplifier .............. Error!
Bookmark not defined.
4
General Notes
There are a number of things to consider before beginning these lab
exercises. Please read through this section completely, and perform any
needed steps in order to ensure a successful workshop. These labs were
designed for use with Incisive Unified Simulator92, IC615 and Assura41.
Before running any of these labs, ensure that you’ve set up IUS92,
IC615, MMSIM101 and Assura41 correctly:
You will also need to ensure that the IUS92 is setup correctly for Mixed
Signal Simulation.
These labs were designed to be run using Cadence Virtuoso tool and
Assura tool.
5
The home directory has a cshrc file with paths to the Cadence
installation.
>which assura
>which ncsim
Use the installed database to do your work and the steps are as follows:
You will start the Cadence Design Framework II environment from this
directory because it contains cds.lib, which is the local initialization file.
The library search paths are defined in this file.
6
modifications of the cell locally without affecting your Source cell present
inside Solutions directory.
7
3. If the ―What’s New ...‖ window appears, close it with the
8
Lab 1: AN INVERTER
Schematic Capture
9
Schematic Entry
Objective: To create a library and build a schematic of an Inverter
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we going to create in the next labs. Execute Tools – Library Manager in
the CIW or Virtuoso window to open Library Manager.
1. In the Library Manager, execute File - New – Library. The new library
form appears.
4. In the field of Directory section, verify that the path to the library is set
to ~/Database/cadence_ms_labs_614 and click OK.
Note: A technology file is not required if you are not interested to do the
layouts for the design
5. In the next ―Technology File for New library‖ form, select option
Attach to an existing techfile and click OK.
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6. In the ―Attach Design Library to Technology File‖ form, select
gpdk180 from the cyclic field and click OK.
7. After creating a new library you can verify it from the library manager.
8. If you right click on the ―myDesignLib‖ and select properties, you will
find that gpdk180 library is attached as techlib to ―myDesignLib‖.
In this section we will learn how to open new schematic window in the
new ―myDesignLib‖ library and build the inverter schematic as shown in
the figure at the start of this lab.
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1. In the CIW or Library manager, execute File – New – Cellview.
Do not edit the Library path file and the one above might be different
from the path shown in your form.
3. Click OK when done the above settings. A blank schematic window for
the Inverter design appears.
You will update the Library Name, Cell Name, and the property values
given in the table on the next page as you place each component.
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3. After you complete the Add Instance form, move your cursor to the
schematic window and click left to place a component.
If you place a component with the wrong parameter values, use the
Edit— Properties— Objects command to change the parameters.
Use the Edit— Move command if you place components in the
wrong location.
You can rotate components at the time you place them, or use the
Edit— Rotate command after they are placed.
2. Type the following in the Add pin form in the exact order leaving space
Between the pin names.
Pin Names Direction
vin Input
vout Output
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Make sure that the direction field is set to input/output/inputOutput
when placing the input/output/inout pins respectively and the Usage
field is set to schematic.
3. Select Cancel from the Add – pin form after placing the pins.
In the schematic window, execute Window— Fit or press the f bindkey.
You can also press the w key, or execute Create — Wire (narrow).
3. Follow the prompts at the bottom of the design window and click left
on the destination point for your wire. A wire is routed between the
source and destination points.
4. Complete the wiring as shown in figure and when done wiring press
ESC key in the schematic window to cancel wiring.
Saving the Design
1. Click the Check and Save icon in the schematic editor window.
15
In this section, you will create a symbol for your inverter design so you
can place it in a test circuit for simulation. A symbol view is extremely
important step in the design process. The symbol view must exist for the
schematic to be used in a hierarchy. In addition, the symbol has
attached properties (cdsParam) that facilitate the simulation and the
design of the circuit.
The Cellview From Cellview form appears. With the Edit Options
function active, you can control the appearance of the symbol to
generate.
2. Verify that the From View Name field is set to schematic, and the
To View Name field is set to symbol, with the Tool/Data Type set
as SchematicSymbol.
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5. Click OK in the Symbol Generation Options form.
Editing a Symbol
17
In this section we will modify the inverter symbol to look like a Inverter
gate symbol.
1. Move the cursor over the automatically generated symbol, until the
green rectangle is highlighted, click left to select it.
2. Click Delete icon in the symbol window, similarly select the red
rectangle and delete that.
7. Execute Create — Selection Box. In the Add Selection Box form, click
Automatic. A new red selection box is automatically added.
8. After creating symbol, click on the save icon in the symbol editor
window to save the symbol. In the symbol editor, execute File — Close to
close the symbol view window.
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Building the Inverter_Test Design
Objective: To build an Inverter Test circuit using your Inverter
You will create the Inverter_Test cellview that will contain an instance of
the Inverter cellview. In the next section, you will run simulation on this
design
Note:Remember to set the values for VDD and VSS. Otherwise, your
circuit will have no power.
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2. Add the above components using Create — Instance or by pressing I.
Tip: You can also press the w key, or execute Create— Wire (narrow).
4. Click Create — Wire Name or press L to name the input (Vin) and
6. Leave your Inverter_Test schematic window open for the next section.
20
Analog Simulation with Spectre
Objective: To set up and run simulations on the Inverter_Test design
In this section, we will run the simulation for Inverter and plot the
transient, DC characteristics and we will do Parametric Analysis after the
initial simulation.
Choosing a Simulator
Set the environment to use the Spectre® tool, a high speed, highly
accurate analog simulator. Use this simulator with the Inverter_Test
design, which is made-up of analog components.
The Model Library file contains the model files that describe the nmos
and pmos devicesduring simulation.
21
Your Model Library Setup window should now looks like the below figure.
To view the model file, highlight the expression in the Model Library File
field and Click Edit File.
2. To complete the Model Library Setup, move the cursor and click OK.
The Model Library Setup allows you to include multiple model files.
It also allows you to use the Edit button to view the model file.
Choosing Analyses
This section demonstrates how to view and select the different types of
analyses to complete the circuit when running the simulation.
The Choosing Analysis form appears. This is a dynamic form, the bottom
of the form changes based on the selection above.
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2. To setup for transient analysis
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4. Click OK in the Choosing Analyses Form.
Value(Expr) 2u
Click Change and notice the update in the Table of Design Variables.
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Selecting Outputs for Plotting
1. Execute Outputs – To be plotted – Select on Schematic in the
simulation window.
start the
Simulation or the icon, this will create the netlist as well as run the
simulation.
25
Saving the Simulator State
We can save the simulator state, which stores information such as model
library file,
outputs, analysis, variable etc. This information restores the simulation
environment
without having to type in all of setting again.
2. Set the Save as field to state1_inv and make sure all options are
selected under
what to save field.
Parametric Analysis
Parametric Analysis yields information similar to that provided by the
Spectre® sweep feature, except the data is for a full range of sweeps for
each parametric step. The Spectre sweep feature provides sweep data at
only one specified condition.
Run a simulation before starting the parametric tool. You will start by
loading the state from the previous simulation run.
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Run the simulation and check for errors. When the simulation ends, a
single waveform in the waveform window displays the DC Response at
the Vout node.
3. In the selection window, double click left on wp. The Variable Name
field for Sweep 1 in the Parametric Analysis form is set to wp.
4. Change the Range Type and Step Control fields in the Parametric
Analysis form as shown below:
These numbers vary the value of the wp of the pmos between 1um and
10um at ten evenly spaced intervals.
5. Execute Analysis—Start.
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The Parametric Analysis window displays the number of runs remaining
in the analysis and the current value of the swept variable(s). Look in the
upper right corner of the window. Once the runs are completed the
wavescan window comes up with the plots for different runs.
Note: Change the wp value of pmos device back to 2u and save the
Schematic before proceeding to the next section of the lab. To do this use
edits property option.
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1. From the Inverter schematic window menu execute
Launch – Layout XL. A Startup Option form appears.
2. Select Create New option. This gives a New Cell View Form
LSW and a blank layout window appear along with schematic window.
Making interconnection
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1. Execute Connectivity –Nets – Show/Hide selected Incomplete Nets
or click the icon in the Layout Menu.
2. Move the mouse pointer over the device and click LMB to get the
connectivity information, which shows the guide lines (or flight lines) for
the inter connections of the components.
3. From the layout window execute Create – Shape – Path/ Create wire
or Create – Shape – Rectangle (for vdd and gnd bar) and select the
appropriate Layers from the LSW window and Vias for making the inter
connections
Creating Contacts/Vias
You will use the contacts or vias to make connections between two
different layers.
31
Physical Verification
Running a DRC
1. Open the Inverter layout form the CIW or library manger if you have
closed that. Press shift – f in the layout window to display all the levels.
The DRC form appears. The Library and Cellname are taken from the
current design window, but rule file may be missing. Select the
Technology as gpdk180. This automatically loads the rule file.
Your DRC form should appear like this
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3. Click OK to start DRC.
4. A Progress form will appears. You can click on the watch log file to see
the log file.
5. When DRC finishes, a dialog box appears asking you if you want to
view your DRC results, and then click Yes to view the results of this run.
6. If there any DRC error exists in the design View Layer Window (VLW)
and Error Layer Window (ELW) appears. Also the errors highlight in the
design itself.
8. You can refer to rule file also for more information, correct all the DRC
errors and Re – run the DRC.
9. If there are no errors in the layout then a dialog box appears with No
DRC errors found written in it, click on close to terminate the DRC run.
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ASSURA LVS
In this section we will perform the LVS check that will compare the
schematic netlist and the layout netlist.
Running LVS
1. Select Assura – Run LVS from the layout window. The Assura Run
LVS form appears. It will automatically load both the schematic and
layout view of the cell.
4. If the schematic and layout matches completely, you will get the form
displaying Schematic and Layout Match.
34
5. If the schematic and layout do not matches, a form informs that the
LVS completed successfully and asks if you want to see the results of
this run.
6. Click Yes in the form. LVS debug form appears, and you are directed
into LVS debug environment.
7. In the LVS debug form you can find the details of mismatches and
you need to correct all those mismatches and Re – run the LVS till you
will be able to match the schematic with layout.
Assura RCX
Before using RCX to extract parasitic devices for simulation, the layout
should match with schematic completely to ensure that all parasites will
be backannoted to the correct schematic nets.
Running RCX
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3. In the Extraction tab of the form, choose Extraction type, Cap
Coupling Mode and specify the Reference node for extraction.
4. In the Filtering tab of the form, Enter Power Nets as vdd!, vss! and
Enter Ground Nets as gnd!
The RCX progress form appears, in the progress form click Watch log
file to see the output log file.
5. When RCX completes, a dialog box appears, informs you that Assura
RCX run Completed successfully.
6. You can open the av_extracted view from the library manager and
view the parasitic.
36
Creating the Configuration View
In this section we will create a config view and with this config view we
will run the simulation with and without parasitic.
The Hierarchy Editor form opens and a New Configuration form opens
in front of it.
37
4. Click Use template at the bottom of the New Configuration form and
select Spectre in the cyclic field and click OK.
5. Change the Top Cell View to schematic and remove the default entry
from the Library List field.
The hierarchy editor displays the hierarchy for this design using table
format.
38
7. Click the Tree View tab. The design hierarchy changes to tree format.
The form should look like this:
39
To run the Circuit without Parasites
2. In the form, turn on the both cyclic buttons to Yes and click OK.
The Inverter_Test schematic and Inverter_Test config window appears.
Notice the window banner of schematic also states Config: myDesignLib
Inverter_Test config.
4. Now you need to follow the same procedure for running the
Simulation. Executing Session– Load state, the Analog Design
Environment window loads the previous state.
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2. From the functions select delay, this will open the delay data panel.
3. Place the cursor in the text box for Signal1, select the wave button
and select the input waveform from the waveform window.
4. Repeat the same for Signal2, and select the output waveform.
5. Set the Threshold value 1 and Threshold value 2 to 0.9, this directs
the calculator to calculate delay at 50% i.e. at 0.9 volts.
1. Open the same Hierarchy Editor form, which is already set for
Inverter_Test config.
41
2. Select the Tree View icon: this will show the design hierarchy in the
tree format.
5. From the Analog Design Environment window click Netlist and Run
to start the simulation again.
8. Calculate the delay again and match with the previous one. Now you
can conclude how much delay is introduced by these parasites, now our
main aim should to minimize the delay due to these parasites so number
of iteration takes place for making an optimize layout.
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Generating Stream Data
Streaming Out the Design
1. Select File – Export – Stream from the CIW menu and Virtuoso
Xstream out form appears change the following in the form.
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Streaming In the Design
1. Select File – Import – Stream from the CIW menu and change the
followingin the form.
5. From the Library Manager open the Inverter cellview from the
GDS_LIBlibrary and notice the design.
6. Close all the windows except CIW window, which is needed for the
next lab.
END OF LAB 1
44
Lab 2: DIFFERENTIAL AMPLIFIER
Schematic Capture
45
Schematic Entry
Objective: To create a new cell view and build Differential Amplifier
3. After you complete the Add Instance form, move your cursor to the
schematic window and click left to place a component.
46
This is a table of components for building the Differential Amplifier
schematic.
Use Create – Pin or the menu icon to place the pins on the schematic
window.
2. Type the following in the Add pin form in the exact order leaving space
between the pin names.
3. Select Cancel from the Add pin form after placing the pins.
In the schematic window, execute View— Fit or press the f bindkey.
2. Complete the wiring as shown in figure and when done wiring press
ESC key in the schematic window to cancel wiring.
1. Click the Check and Save icon in the schematic editor window.
Symbol Creation
The Cellview from Cellview form appears. With the Edit Options
function active, you can control the appearance of the symbol to
generate.
2. Verify that the From View Name field is set to schematic, and the To
View Name field is set to symbol, with the Tool/Data Type set as
Schematic Symbol.
48
6. A new window displays an automatically created Differential Amplifier
symbol.
8. Execute Create— Selection Box. In the Add Selection Box form, click
Automatic. A new red selection box is automatically added.
9. After creating symbol, click on the save icon in the symbol editor
window to save the symbol. In the symbol editor, execute File— Close to
close the symbol view window.
49
Objective: To build Differential Amplifier Test circuit using your
Differential Amplifier
Note: Remember to set the values for VDD and VSS. Otherwise your
circuit will have no power.
3. Click the Wire (narrow) icon and wire your schematic.
Tip: You can also press the w key, or execute Create— Wire (narrow).
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4. Click on the Check and save icon to save the design.
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In this section, we will run the simulation for Differential Amplifier and
plot the transient, DC and AC characteristics.
Choosing a Simulator
Note: Step 2 should be executed only if the model file not loaded by
default.
2. In the Model Library Setup form, click Browse and find the
gpdk180.scs file in the ./models/spectre directory.
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Choosing Analyses
The Choosing Analysis form appears. This is a dynamic form, the bottom
of the form
changes based on the selection above.
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4. To set up for AC Analyses form is shown in the previous page.
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a. In the Analyses section, select ac.
b. In the AC Analyses section, turn on Frequency.
c. In the Sweep Range section select start and stop frequencies as
150 to 100M
d. Select Points per Decade as 20.
e. Check the enable button and then click Apply.
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Running the Simulation
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To calculate the gain of Differential pair:
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Now, open the ADE L, from LAUNCH ADE L , choose the analysis set
the ac response and run the simulation, from Simulation Run. Next
go to ResultsDirect plot select AC dB20 and output from the
schematic and press escape. The following waveform appears as shown
below –
Open the calculator and select the bandwidth option, select the waveform
of the gain in dB and press Evaluate the buffer -
58
To Calculate the CMRR of the Differential pair :
In the ADE L, plot the ac response with gain in dB. Measure the gain at
100hz and at 100Mhz,note down the value of the gain in dB, as shown
below –
59
Configure the Differential pair schematic to calculate the common-mode
gain as shown below –
In the ADE L, plot the ac response with gain in dB. Measure the gain at
100hz and at 100Mhz, note down the value of the gain in dB, as shown
below –
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Calculate the CMRR = | | , add the gains in dB i.e., Ad – (-Ac). For the
output impedance note down the output resistance of the pmos and
nmos transistors at the ouput side, and use the necessary equation like
r01|| r02 .
We can save the simulator state, which stores information such as model
library file,
outputs, analysis, variable etc. This information restores the simulation
environment
without having to type in all of setting again.
2. Set the Save as field to state1_diff_amp and make sure all options
are selected underwhat to save field. Click OK in the saving state form.
The Simulator state is saved.
61
6: NCO(10 Bit number controlled oscillator)
There are a number of things to consider before beginning the lab
exercises. Please read through this section completely, and perform any
needed steps in order to ensure a successful workshop.
The NCO directory contains rclabs folder. Inside rclabs folder you
will see many other directories but for IUS, change the directory to
Simulation and for Synthesis and P&R select work directory
In this lab, you will simulate the design using the Incisive simulator. You
will Perform this lab in the Simulation directory. This directory contains
the following files (which you should briefly examine) describing the NCO
and its testbenches:
File(s) Description:
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2. Before proceeding to the next step analyze the messages in the
terminal window
The -gui option opens the Console and Design Browser windows.
a. You can use the Menu Bar to run or step the simulation, set scopes
and stops, show the value of objects, and start other graphical tools.
b. You can use the Tool Bar to run, interrupt, reset, step, or next the
simulation, and shut down the interface or the simulation, or disconnect
the simulation.
c. You can use the command line interface to the simulation in the
I/O Region.
a. Display the objects of a scope and their value in the Objects List
pane (Select any displayed scope in the Scope Tree pane).
63
b. Display the component instances of the scope (double-click the
scope in the Scope Tree pane).
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Examine the Design and Testbench Hierarchy
In this section of the lab you visit the Source Browser, Schematic
Tracer and
Waveform window.
1. In the Design Browser window select the top-level (mem_test) scope and select
the Source Browser button to send it to the target Source Browser
window. As no such window yet exists, this opens a Source Browser
window displaying the source of the
Top-level unit, and makes it the default Source Browser target window.
2. In the Source Browser window ensure that just the top-level scope is
selected (navigate up as needed and Select—This Scope) and send it
to the target Schematic Tracer window. As no such window yet exists,
this opens a Schematic Tracer window displaying the top-level unit, and
makes it the default Schematic Tracer target window, in which you:
a. Ensure that the top-level scope is still selected, and select the fill
3. In the Source Browser window ensure that just the top-level scope is
selected and send it tothe target Waveform window. As no such
window yet exists, this opens a Waveform window displaying the signals
of the top-level unit, and makes it the default Waveform target window.
a. In the left sidebar, select the Design Browser tab toexpand the
sidebar area and display the embedded Design Browser.
65
--- Move primary cursor to previous edge of select signal.
Once the simulation is done you can see the following waveform
window and console window with the outputs.
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2. Click on Trace and select Analog/Sample+Hold
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4. Drag and observe the waveform for different numerical values
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Lab7: Automatic layout generation
followed by post layout extraction and
simulation of the circuit studied in Lab 6
In this lab we will do the Synthsesis and Physical Design of NCO Design
for which simulation is done in Lab6. Synthesis will be done using RTL
Compiler and Physical Design will be done using Encounter Digital
Implementation System.
Go to directory /NCO/rclabs/work.
69
The terminal will look like the below image after the tool is invoked.
2. Give the path of the library w.r.t to the directory you are in using the
command: ―set_attribute lib_search_path ../library‖
3 Give the path of the RTL files with respect to the directory you are in
70
using the below command: ―set_attribute hdl_search_path ../rtl‖
4 Read the library from the directory specified in giving the path for the
library files in step 2 using the command: ―set_attribute library
slow_normal.lib‖ ―slow_normal.lib‖ is the name of the library file in the
directory ―library‖. There is another library there in that directory with
name ―slow_highvt.lib‖. Any one of these two libraries could be used at
a time.
5 Read the RTL files from the directory specified in the path in step 3.
The RTL files are in the directory name ―rtl‖:
―read_hdl {mem.v mux_2to1.v phase_inc.v top.v}.
6 Now Elaborate the design using ―elaborate‖command.
7 Give the command to see the circuit in Tool window:
The terminal window after the step 7 will look like
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―read_sdc ./constraints_top.g‖.
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10. Write the hdl code in terms of library components for the synthesized
circuit using the command: ―write_hdl > nco.hdl‖ ―nco.hdl‖ is the name
of file in which the code gets write.
11. Similarly write the constraint file using ―write_sdc > nco.sdc‖.
73
The tool starts as below image:
The terminal window and tool window can be seens as similar to images
on next page
74
75
18. Go the Tool window and click on the File and select Import Design. A
new window will open.
19. Select the verilog files using browse button. A new window ―Netlist
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files‖ will open.
20. Click on the arrow button and select the verilog File
―NCO_gatelevel_uniq.v‖ and click the Add button and then click the
close button.
22. Similarly select the lef file by clicking the browse button and then
add the lef file with name ―all.lef‖ in the lef directory.
23. Select the timing libraries. For maximum timing libraries select all
libraries with ―slow‖ in their name and for minimum timing libraries
select all libraries with fast in their names. Alternatively, instead of
selecting all the libraries for Maximum timing libraries, type
―../lib/*slow*.lib‖ in space in front of Maximum Timing Libraries. This
will select all the slow libraries. Similarly in front of Minimum Timing
Libraries write ―../lib/*fast*.lib‖.
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24. Similarly select ―NCO.sdc‖ for timing constraint file.
The Design Import window will look like the image on next page:
25. In the Design Import window click on Advanced Tab. Select Power
out of the list on the left side of window. Enter the power nets as VDD
and Ground nets as VSS.
26. Select OK. The tool window will look like image on next page.
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The pink colour blocks are the standard cells. This is floorplan view of
the design.
79
Select the Aspect Ratio as per the requirement. Give some dimension in
―Core to left‖, ―Core to right‖, ―Core to top‖,―Core to bottom‖. e.g. give 30
to each. This is to create the space for Power rings which will be created
in power planning. Click OK and the Tool window will be look like as
below.
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30. Select the top and bottom layer as Metal5, Left and Right as
Metal6. Set the width as per the requirement and taking the space
between core boundary and I/O pad considerations. Select the option
for offset as ―center in channel‖ and click OK.
The power ring will get created in between the channel. The image on
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31. The next step in power planning is to create power strips. Select
Power, click Power Planning and click Add Stripe.
32. For adding the stripes, select metal layer as Metal 6 and chose
direction as vertical(if direction chosen is horizontal, chose metal layer
as Metal 5). Click OK and the design will get the vertical thin strips of
type Metal 6.
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33. Click on Route Tab in main menu. Click on Special Route option.
34. Click OK with all default settings. This is done to provide power to
standard cells. The horizontal blue coloured metal1 stripes created as
a result of Special Route.
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35. For placement, click on place and select place and click on Place
Standard Cell.
36. Click OK on Place window and in physical view the blue coloured
standard cells can be seen as a result of placement of standard
cells.
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37. Before CTS, timing analysis has to be done for any setup
violations. Click on Timing, and select Report Timing. A Timing
analysis window will get open. In the window select the ―Pre-CTS‖ as
Design Stage and select the ―Setup‖ as Analysis Type.
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38. Click OK to complete the Timing analysis. The timing information
will get display on terminal in tabular form. In the table displayed on
the terminal under ―timeDesign Summary‖, check for any negative
value under WNS(Worst Negative Slack) and TNS(Total Negative
Slack). The terminal will look as the image below and Tool window as
on next page.
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The multi-coloured lines visible in the tool window are the connections
between standard cells using metal layers. If any part of this design is
Zoom-in, metal layers can be viewed easily.Different colours show
different metal layers.
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39. If there is any of the negative slack value under WNS or TNS, click
Optimize in Tool window and Select Optimize Design. A new window
―Optimization‖ will get open. Select ―Pre-CTS‖ as Design Stage and
―Setup‖ as optimization type and click OK. The tool will optimize the
design and the optimized timing results will be displayed over
terminal again.
In this case we did not get any negative slack, so this step is skipped
here.
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41. Click on Gen Spec and a new window ―Generate Clock Spec‖ will
open.
42. From Cells List, Select all clocks starting with ―CLK‖ and click on
Add button to add them to the Selected Cells. Select a name for
Output specification.
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43. Click OK. Then specify a name for Results Directory. and click OK.
The tool window looks like the image below.
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45. Click Ok to perform the timing. The timing information will be
displayed over the terminal window. Again check for any negative
slacks under WNS or TNS.
46. If there is any negative value found for either of WNS or TNS then
perform the Optimization Technique to reduce the negative slack. No
negative slack is found in the terminal image on previous page so this
step is skipped here.
47. Timing Analysis for ―Setup‖ as Analysis Type is done. Repeat Step
27 for performing timing for ―Post CTS‖ as Design Stage and ―Hold‖ as
Analysis Type. The tool will show the timing results in the terminal
window.
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48. After Timing Analysis is performed, the timeDesign Summary is
showing the negative slack values for both TNS and WNS. Perform the
Optimization. Go to Optimize and click on Optimize Design. Select
―Post-CTS‖ as and ―HOLD‖ as the Optimization Type
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49. Click OK to perform the Optimization and Tool will perform the
optimization and displays the optimized results in the terminal
window under timeDesign Summary. The results of Optimization can
be seen on the next page in tabular form for both Setup and Hold
mode. As compare to the Timng Results performed for Hold mode in
Step 30, the design has been optimized and tabular results shows
that all slack values are now positive values and no more negative
values for slack.
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50. Perform Routing by clicking Route, and select NanoRoute and then
click Route. A window NanoRoute will open.
51. Click Ok to Perform Routing. The tool will Perform the Routing and
the Routing statistics can be seen on terminal window including DRC
violations.
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52. After routing tool window looks like the below image.
53. Perform the timing again. Go to Timing, seelct Report Timing and a
Timing Analysis window will get open. Select ―Post-Route‖ as the
Design Stage and ―Setup‖ as Analysis Type. Click Ok. The timing
results will be displayed in terminal window for Set up mode.
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54. Repeat Step 36 for ―Post-Route‖ as Design Stage and ―Hold‖ as the
Analysis Type. Click OK. The timing results can be seen in the
terminal window for hold mode.
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