Design and Analysis of Power Efficient

Binary Content Addressable Memory

(PEBCAM) Core Cells

D. Jothi & R. Sivakumar

Circuits, Systems, and Signal

Processing

ISSN 0278-081X

Circuits Syst Signal Process

DOI 10.1007/s00034-017-0628-0

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Circuits Syst Signal Process
DOI 10.1007/s00034-017-0628-0

Design and Analysis of Power Efficient Binary Content

Addressable Memory (PEBCAM) Core Cells

D. Jothi1 · R. Sivakumar1

Received: 20 January 2017 / Revised: 29 July 2017 / Accepted: 1 August 2017

© Springer Science+Business Media, LLC 2017

Abstract This paper presents the design and the analysis of power efficient binary
content addressable memory (PEBCAM) core cells using the energy recovery principle
of adiabatic logic. Generally, in the design of adiabatic CAM, the storage array is
built by using a basic CAM cell, but the peripheral circuits are realized by using
different adiabatic logic structures. In this paper, we propose the design of 3 novel
power efficient binary content addressable memory core cells (PEBCAM core cells)
using adiabatic logic, namely improved efficient charge recovery logic (IECRL) CAM
core cell, positive feedback adiabatic logic (PFAL) CAM core cell and pass transistor
adiabatic logic (PAL) CAM core cell. Memory arrays of size 4 × 4 were designed and
implemented using the proposed PEBCAM core cells in 45nm CMOS technology. It
was found that recovery of dissipated power using adiabatic logic was better than the
other CAM structures. The simulation results of the PEBCAM-IECRL CAM proved to
be better with a power saving of 77.8% than the conventional adiabatic CAM structures.
The circuits were designed using 45nm CMOS technology with a sinusoidal power
clock of 1 V and other node voltages at 0.7 V using Cadence Virtuoso.

Keywords Content addressable memory (CAM) · Adiabatic logic · Energy recovery ·

Power efficient binary content addressable memory core cells (PEBCAM) · Improved
efficient charge recovery logic (IECRL) · Positive feedback adiabatic logic (PFAL) ·
Pass transistor adiabatic logic (PAL)

B D. Jothi
dji.ece@rmkec.ac.in
R. Sivakumar
rsk.ece@rmkec.ac.in

1 Department of Electronics and Communication Engineering, RMK Engineering College,

Chennai 601206, India
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1 Introduction

A content addressable memory (CAM) is a type of memory which behaves like a human
brain. Instead of retrieving the data based on the address of the memory locations, it
accesses the locations by using a part of the data itself. CAM is a type of memory that
compares the input data with the preloaded contents of the CAM block and generates
a given output depending on the kind of CAM. This kind of memory provides a
distinct speed advantage over RAM in systems requiring quick address comparison or
retrieval [17]. Like a normal RAM memory, it can perform read and write operation. In
addition to that, it performs the search or comparison operation. Basically, it performs
two functions: bit storage and bit comparison. Unlike RAM cell, it takes data as input
and gives the content location as an output in one clock period. The search operation
is performed in parallel among all memory cells, and the matched location is given
as the output for the given input data. This parallel processing of data, along with the
high switching activity, leads to large capacitance nodes of bit lines, word lines and
match lines resulting in very high power consumption [29]. Though there are a variety
of low-power techniques, the principle of adiabatic logic works well in the dwindling
of power dissipation by using the energy recovery process [33].
Numerous adiabatic logics have been explored over the past for the low-power
VLSI architectures. They are efficient charge recovery logic (ECRL), 2N2P / 2N-
2N2P logic, positive feedback adiabatic logic (PFAL), clocked adiabatic logic (CAL),
true single-phase adiabatic logic (TSEL), source coupled adiabatic logic (SCAL),
NMOS energy recovery logic (NERL), pass transistor adiabatic logic (PAL), split-
level charge recovery logic (SCRL), complementary pass transistor adiabatic logic
(CPAL), two-level adiabatic logic or 2LAL, quasi-adiabatic logic, pre-resolve and
sense adiabatic logic (PSAL), and two-phase adiabatic static clocked logic (2PASCL)
[4,7,13–16,20–22,24–26,28,30–32,34,36,37,41].
For combating the challenge of high power consumption in the design of CAM,
adiabatic logic can be used [1]. Usually, an adiabatic CAM is designed by using a
basic CAM cell and adiabatic logic decoders and drivers. Adiabatic logic helps to
recover energy on the match lines, address decoders and bit-line drivers of CAM
[1–3,6,9,11,27,39,42,43]. In [11], CAM structure is designed using the basic nine-
transistor CAM cell and used the Efficient Charge Recovery Logic in the design of its
peripheral circuits. In [12], both the CAM core cell and peripheral circuits are designed
using ECRL. It was implemented in 180 nm CMOS technology using Cadence,
which resulted in considerable power saving. In this paper, we propose the design
and implementation of fulsome adiabatic CAM cells using improved efficient charge
recovery adiabatic logic (IECRL) along with adiabatic address decoders. The CAM
storage cells are built by using IECRL, Improved Positive Feedback Adiabatic Logic
(IPFAL) and improved pass transistor adiabatic logic (IPAL). All other circuits such
as address decoders and bit-line drivers are also realized using the respective adiabatic
circuits. Functional simulations and power analysis of the proposed CAM structures
are performed using 45nm CMOS technology in Cadence. Section 2 describes the
conventional CAM in detail. Section 3 describes the adiabatic logic. In Sect. 4, the
different types of adiabatic logics that can be used for CAM are explored. In Sect. 5,
the design and implementation of the 3 novel PEBCAM core cells, namely IECRL
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CAM, IPFAL CAM and IPAL CAM, are analyzed and compared with the conventional
CAM design. Section 6 enumerates the simulation results of the proposed designs.

2 Conventional CAM

The construction of the conventional CAM storage cell is shown in Fig. 1. The Basic
9T CAM cell is taken as the conventional CAM storage cell. This structure resembles
an SRAM cell apart from the additional three transistors as depicted. These three
transistors facilitate the match function. The function of a single CAM cell is shown
in Table 1. The write and the read operations are carried out in the same way as that
of a typical RAM. The match operation is performed by activating either one of the
transistors MN3 or MN4 at a time [12].
The structure of the conventional CAM architecture is shown in Fig. 2. The CAM
array consists of an array of one-bit storage cell arranged in rows and columns. The
word-line and bit- line decoders are used for decoding the address and data inputs for
the write and search operation. 4 × 4 CAM architecture consists of 4 words with each
word containing 4 bits arranged horizontally. Each word has a match line, namely
ML0, ML1 , ML2 and ML3. Each bit of a search word has a differential search-line/bit-
line pair such as SLi /SLi or BLi /BLi. Match lines, on which all bits match, remain
in the pre-charged high state (VDD). Match lines that have at least one bit misses
discharge to ground (GND) [12].

Fig. 1 Conventional 9T CAM

storage cell [2]

Table 1 Functionality of a single CAM cell

Search bit (SL/BL) Stored bit (q) Match node (mn) Match line (ml)

0 0 0 1 (vdd)
0 1 1 0 (gnd)
1 0 1 0 (gnd)
1 1 0 1 (vdd)
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Fig. 2 Conventional CAM architecture [1]

The search operation is the major cause of power dissipation in CAM. For every
cycle of operation, all match lines are initially pre-charged and then discharged to
ground and the occurrences of mismatches are relatively more. Also, search lines or
bit lines and word lines contribute to large power dissipation due to high switching
activity with large node capacitances [29].

3 Adiabatic Logic

An adiabatic process is a thermodynamic process in which the amount of heat remains

constant and there is no exchange of energy with the environment. Adiabatic logic,
in the ideal sense, designates digital circuits without a loss (dissipation) of electrical
energy. In practice, it denotes the logic with minimal consumption of electrical energy
during the switching of states. Adiabatic switching is a charge/discharge mechanism
which returns accumulated energy to the source inside the load capacitor using the
dynamic power supply. Dynamic power supply or clocked power has a very important
role in adiabatic logic as it provides energy recovery [4].
For the purpose of distinction, a conventional CMOS structure and an adiabatic logic
structure are shown in Figs. 3 and 4, respectively. A conventional CMOS uses a constant
voltage supply, whereas in adiabatic logic, supply is a power clock. Unlike CMOS,
adiabatic logic reuses the dissipated energy, and hence, it works in 2 phases, a pre-
charge phase and a recovery phase. Most of the adiabatic circuits deliver energy in the
pre-charge phase and recover their energy during the recovery phase. Thus, adiabatic
logic is a good solution for acquiring low power dissipation [21,26,30,31,33,37].
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Fig. 3 Conventional CMOS

structure

Fig. 4 Adiabatic logic structure

There are different types of adiabatic logic design techniques [37], which can be
broadly classified as partial adiabatic logic and fully adiabatic logic. In partial adiabatic
logic, a part of the charge is allowed to be transferred to the ground, whereas in fully
adiabatic logic, all the charge on the load capacitance is recovered by the power supply.
The adiabatic circuits which utilize partial adiabatic logic are: efficient charge
recovery logic (ECRL), 2N2P / 2N-2N2P logic, positive feedback adiabatic logic
(PFAL), clocked adiabatic logic (CAL), true single-phase adiabatic logic (TSEL),
source coupled adiabatic logic (SCAL) and NMOS energy recovery logic (NERL).
Examples of fully adiabatic logic circuits are pass transistor adiabatic logic (PAL),
split-level charge recovery logic (SCRL) and complementary pass transistor adiabatic
logic (CPAL) [31].
Many authors [7,31–34,36,37] have shown that ECRL and PFAL are better adi-
abatic circuits among the partial adiabatic logic family because of their simplicity.
Thus, we have explored the partial adiabatic logic circuits using ECRL, PFAL and a
fully adiabatic logic PAL for our analysis and design of adiabatic CAM core cells.

3.1 Efficient Charge Recovery Logic

Efficient charge recovery logic was proposed as a contender for the low-energy adi-
abatic logic circuit by Moon and Jeong [16,25]. ECRL adopts a new method that
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performs pre-charge and evaluation simultaneously. It eliminates the pre-charge diode

and dissipates less energy than other adiabatic circuits. It is based on the cascode volt-
age switch logic (CVSL) with differential signals [25]. ECRL uses a cross-coupled
PMOS pair as a latching element. Logic blocks are constructed only with NMOS tran-
sistors and are connected from output to ground. This differential structure is more
accepted since the loading capacitance seen by the clock is held constant regardless
of their input combinations. It works with the help of hold phase, wait phase and
evaluation phase.
An ECRL gate consists of PMOS loads and NMOS pull-down transistors. This
structure needs differential inputs and is the same as CVSL except that all the gates
need specific clocks depending on their stages.
Adiabatic logic does not abruptly switch from ground to supply voltage (and vice
versa), but a voltage ramp is used to charge and recover the energy from the output.
The structure of a buffer/inverter gate in the ECRL [25] is shown in Fig. 5. It consists
of two cross-coupled PMOS devices that are used to store the information. The logic
function is constructed via two NMOS devices [33].
NMOS transistors MN1 and MN2 implement the inverter logic, whereas MP1 and
MP2 allow the output nodes to discharge into the ‘PC’ (ϕ). Assuming that the ‘in’
signal is at logic high and ‘inb’ is at logic low, when the power clock supply ‘PC’
rises from 0 to VDD, voltage at ‘out’ remains at ground level, because ‘in’ signal
turns on MN2 transistor. The voltage at the ‘outb’ node capacitance follows the ‘PC’
signal. When the power clock reaches VDD level, the outputs hold valid logic levels.
These values are maintained during the hold phase. After the evaluation or hold phase,
the ‘PC’ falls down to a ground level, and the ‘outb’ node capacitance discharges
adiabatically into the power clock supply recovering the energy. Thus, the clock PC
acts as both clock and power supply [25].
Most adiabatic circuits need diodes for pre-charging output nodes. When a diode
is used for pre-charging, it leads to an unavoidable energy loss due to a voltage drop

Fig. 5 Schematic diagram of the ECRL NOT gate

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Fig. 6 Schematic diagram of

the ECRL AND gate [25]

across the diode when turned on. The energy loss is given by [25]

Eloss = CVdd Vd,on

where Vd,on is the diode turn-on voltage.

ECRL always pumps charge on the output with a full swing. However, as the voltage
on the supply clock approaches to |Vtp|, the PMOS is turned OFF. So the recovery
path to the supply clock is disconnected, thus resulting in incomplete recovery. The
amount of loss is given by [25]

EECRL = C|Vtp|2 /2

Although nonzero, it is still more than ten times smaller than the energy loss of the
other adiabatic circuits with supply voltages greater than 1 V [25].
ECRL AND gate and ECRL decoder can be constructed by using the ECRL gate
design method. The schematic diagram of ECRL AND gate is shown in Fig. 6. ECRL
decoder is designed by replacing the logic gates in the CMOS decoder by ECRL logic
gates such as ECRL inverter and ECRL AND gate. The schematic diagram of ECRL
decoder is shown in Fig. 7.
One of the enticing advantages of ECRL circuits is its simplicity. Though only
partial energy can be recovered using this logic, it is the simplest and an elegant
adiabatic logic design since it is based on the CVSL family which has been in use for
over 4 decades. This means that various design methodologies for more complex logic
functions have been thoroughly investigated and published. But the disadvantage of
ECRL is that once the charge from the previous stage has been recovered from the
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Fig. 7 Schematic diagram of the ECRL decoder in Virtuoso [12]

gate of the NMOS devices, there is no pull-down path to ground. This has implications
for noise susceptibility [37].

3.2 Positive Feedback Adiabatic Logic

Positive Feedback Adiabatic Logic (PFAL) [36,38] is a partially adiabatic logic

technique. PFAL offers lower energy consumption when compared to other simi-
lar families, and a good robustness against technological parameter variations. It is a
dual-rail circuit which accepts complementary inputs with respect to each other and
provides outputs complemented with each other with partial energy recovery.
PFAL consists of cross-coupled inverters, with NMOS devices connected between
the outputs and the power clock. The core of all the PFAL gates is an adiabatic amplifier,
a latch made by two PMOS transistor and two NMOS transistor that avoids logic
degradation at output nodes out and /out. A latch element is formed by the two cross-
coupled inverters to store the output state when the input signals are ramped down
[36].
The schematic diagram of PFAL inverter gate is shown in Fig. 8. Initially, input ‘in’
is high and input ‘/in’ is low. When power clock (pck) rises from zero to VDD, output
‘out’ remains at ground level. Output ‘/out’ follows the power clock. When power clock
reaches VDD, outputs ‘out’ and ‘/out’ hold logic value zero and VDD, respectively.
These output values can be used for the next stage as inputs. When power clock falls
from VDD to zero, ‘/out’ returns its energy to the power clock. Thus, the delivered
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Fig. 8 Schematic diagram of

PFAL Inverter [36]

Fig. 9 Schematic diagram of PFAL AND gate in Virtuoso

charge is recovered. PFAL uses four-phase clocking rule to efficiently recover the
charge delivered by power clock.
When the power clock is in its recovery phase, the NMOS devices between the
outputs and the power clock can allow complete recovery of those outputs. This means
that the low-power performance of PFAL can be enhanced by making it fully reversible
[36–38].
The schematic diagram of PFAL AND gate designed and simulated using Cadence
Virtuoso at 45nm is shown in Fig. 9. It consists of cross-coupled inverters along with
NMOS devices implementing the AND logic connected between the outputs and the
power clock. The schematic diagram of PFAL 2–4 decoder designed using the PFAL
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Fig. 10 Schematic diagram of PFAL Decoder in Virtuoso

inverter and PFAL AND gate and simulated using Cadence Virtuoso at 45nm is shown
in Fig. 10.

3.3 Pass Transistor Adiabatic Logic

Pass transistor adiabatic logic (PAL) is a fully adiabatic logic technique. PAL is an
adiabatic CMOS logic based on the principle of recycling of energy between an AC
power clock and logic. The path for the energy transfer depends on the logic.
PAL is a dual-rail adiabatic logic with a relatively low gate complexity, and it
operates with a two-phase power clock. PAL uses a pair of cross-coupled PMOS as a
memory element. Logic blocks are constructed only with NMOS transistors and are
connected from output to ground [28].
A PAL gate consists of true and complementary pass transistor NMOS functional
blocks (f, /f) and a cross-coupled PMOS latch (MP1, MP2), as illustrated in Fig. 11.
Power is supplied through a sinusoidal power clock (Pclk ). When the power clock
(Pclk ) starts rising from low, input states make a conduction path from the power
clock (Pclk ) through one of the functional blocks to the corresponding output node
and allow it to follow the power clock. The other node will be kept close to 0V by
its load capacitance. This, in turn, causes one of the PMOS transistors to conduct and
charge the node that should go to one state, up to the peak of the power clock (Pclk ).
The output state is valid at around the top of the power clock. The power clock will then
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Vdd Pclk

Out_bar Out

Abar
A

Fig. 11 Schematic diagram of PAL inverter

ramp down toward zero, recovering the energy stored on the output node capacitance
[28].
Figure 12 shows the schematic diagram of PAL inverter simulated in Cadence
Virtuoso at 45 nm. A pair of PMOS transistors is used as a memory element and
NMOS transistors are used for implementing the inverter logic. Figure 13 shows the
schematic diagram of PAL AND gate simulated in Cadence Virtuoso at 45 nm. A pair
of cross-coupled PMOS is used as a memory element. AND logic is implemented
using NMOS transistors connected between the output and ground. Figure 14 shows
the schematic diagram of 2–4 PAL decoder simulated in Cadence Virtuoso at 45 nm.
It is constructed using 2 PAL inverters and 4 PAL AND gates.

4 Adiabatic Binary CAM

A binary content addressable memory (BCAM) performs content matching rather

than the address matching performed by standard memory cores. The content match-
ing approach enables faster data searches that can be achieved by sequentially checking
each address location in a standard memory for a particular value. The higher speed
searches are achieved by using content values as an index into a database of address
values. The additional ability to perform content comparisons in parallel enables even
higher speed searches[19]. Such high-speed searches result in high power consumption
in CAMs. Adiabatic logic can provide a better solution to this CAM power problem
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Fig. 12 Schematic diagram of PAL inverter in Virtuoso

[1–3,6,9,22,27,39,42,43]. In this section, a detailed survey of adiabatic CAM is pre-

sented.

4.1 Complementary Pass Transistor Adiabatic Logic (CPAL) CAM Structure

[39,42]

In [39,42], content addressable memory is designed using complementary pass tran-

sistor adiabatic logic circuits. All circuits except CAM core cells are realized using
CPAL circuits. The match lines are driven using bootstrapped NMOS switches. The
charge of large node capacitance on match lines, bit lines, word lines and address lines
is well recovered in fully adiabatic manner. Reduction in power consumption of the
CPAL CAM is shown for the frequency range of 10–100 MHz [39,42].
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Fig. 13 Schematic diagram of PAL AND gate in Virtuoso

4.2 Self-Timed Charge Recycling Search-Line (SL) Driver CAM [43]

In [43], a scheme of self-timed charge recycling search-line (SL) drivers for content
addressable memories is discussed. In the conventional charge recycling SL driving
scheme, an additional clock needs to be generated from the system clock with stringent
requirements for phase and pulse width to control the charge sharing the course. But, in
[43] a self-sense scheme is used at the end of the charge sharing. Besides, by entering
the high-resistant driving state in advance, this scheme reduces the delay overhead of
the control logic from 8 to 6 gates delay [43].

4.3 Clocked Adiabatic Logic (CAL) CAM Array [6]

In [6], a 16 × 16 CAM based on improved clocked adiabatic logic (CAL) circuits is

presented, which is realized using TSMC 0.18 um process. The CAL is a dual-rail
logic that operates from a single-phase AC power clock supply. It is shown that the
improved CAL CAM has a good power reduction for search operation at 100 MHz
[6].
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Fig. 14 Schematic diagram of PAL Decoder in Virtuoso

4.4 Adiabatic CAM Cell [27]

The structure of the adiabatic CAM cell is shown in Fig. 15. In a conventional CAM,
the match transistor N3 is grounded, whereas in adiabatic CAM, it is connected to the
power clock, Pclk or PC. The power clock causes adiabatic transitions in the match line,
thereby saving considerable energy. The bit lines are pre-discharged and the search
data are loaded onto the bit lines. The match line is pre-discharged initially. When
a mismatch occurs, the transistor N3 is ON and the match line follows PC, thereby
maintaining a very low potential drop across the match line capacitance. The swing in
the match line is maintained to a value of one threshold voltage less than the full rail,
to decrease the charge loss that would arise across the transistor N3. The charging and
the discharging paths are the same for the match line and the charge stored is recovered
in the same clock cycle. The match line is therefore held low after the evaluation phase
because the energy is recovered by ramping down the power clock [27].
When a match condition occurs, the transistor N3 is OFF leaving the match line in
a low state. This state causes no energy dissipation. For both conditions, the energy
dissipated is minimal and substantial energy savings are obtained. The output of this
CAM is adiabatic and is valid when the power clock is high [27].
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Fig. 15 Adiabatic CAM cell

[27]

Fig. 16 PAL CAM cell [1]

4.5 Pass Transistor Adiabatic Logic (PAL) CAM Cell [1]

The pass transistor adiabatic logic (PAL) CAM cell [1] is shown in Fig. 16. PAL is
a fully adiabatic logic family that uses dual-rail logic with true and complementary
NMOS functional blocks and cross-coupled PMOS latch [28]. A sinusoidal power
clock (PC) supplies the PAL. The output will be varied only around the peak of the
PC. When the PC ramps down toward zero, the energy stored on the capacitance is
recovered.
The data lines (bit and /bit) are pre-charged by the PC to recover the energy before
the write and the read operations. Separate data lines are used for writing and reading
the data. In the compare operation, the charging and the discharging paths are made the
same, which eliminates the need for pre-charging the match line. Whenever there is a
match/hit, the transistor connected to match line will be ON allowing the power clock,
PCcomp to charge the match line. If there is a mismatch, that transistor is switched
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OFF and the match line remains low. The power clocks PC and PCcomp need not be
the same. It is sufficient that the PCcomp should have a value greater than the threshold
voltage of the PMOS [1,2].
Thus, many researchers have used adiabatic logic in the design of decoders and
drivers [3,6,9,11,27,39,42,43] except [1–3,27]. Also, memory schemes with partial
energy recovery are preferred because of much simpler and area efficient implemen-
tation.

5 Proposed PEBCAM Core Cells

Many authors have used adiabatic logic in CAM to reduce its power. Most of the
researchers have used adiabatic logic in the implementation of the peripheral circuits of
CAM memory array [2,3,6,9,11,27,39,42,43]. Also, the peripheral circuits of CAM
implemented using ECRL have resulted in a reasonable power reduction [11]. In [12],
the design of a completely efficient charge recovery adiabatic logic content addressable
memory is presented. In this paper, we propose the design of a novel improved efficient
charge recovery logic-IECRL CAM core cell. Using this innovative IECRL CAM
cell, a comprehensive adiabatic logic CAM is developed. It has been found that this
PEBCAM-improved efficient charge recovery logic content addressable memory has
better energy recovery than its counterparts. Also, a novel improved positive feedback
adiabatic logic-IPFAL CAM core cell and an improved pass transistor adiabatic logic-
IPAL CAM core cell are also proposed. CAM arrays developed using the proposed
adiabatic CAM core cells are compared, and their performance is analyzed with respect
to power and frequency of operation.

5.1 Proposed IECRL CAM Cell

An innovative IECRL CAM storage cell is shown in Fig. 17. Its structure is similar to
that of the ECRL XOR/XNOR gate [25,33]. But it has one additional transistor (N7)
for match operation. It consists of 6 NMOS and 2 PMOS devices used for storage and
comparison and an nMOS pull-down device to drive the word match line. Here the
power clock signal ‘PC’ acts as a word line. Assume that the input ‘A’ which acts as
search data is at logic 0 and the dual input ‘Abar’ is at 1. The stored values are given
at ‘B’ and ‘Bbar’ with respect to transistors N5 and N6. Then, the NMOS device N2
will conduct and connect ‘outbar’ to ground, while N1 is disabled. If the input data
‘A’ matches with the values that are pre-stored in ‘B,’ then N7 in every cell in the
word remains OFF, and the match line will remain at a high value indicating a match.
Otherwise, the match line will be discharged to low.
As the power clock PC ramps from 0 to VDD, when it reaches the threshold voltage
Vth, p of the PMOS device, P1 will be turned on. Thus, the output signal–match line
will follow the power clock PC. Now the gate voltage of device P2 is equal to the
supply voltage, and the gate-to-source voltage is zero; thus, this device stays disabled.
As soon as PC reaches the maximum level VDD, the input signals are ramped down,
as the preceding gate recovers the energy at this time. A certain fraction of energy
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Fig. 17 Schematic diagram of the proposed IECRL CAM storage cell

2 remains on the output capacitance that is dissipated or reused in the next

1/2 Cout Vth,p
cycle, according to the succeeding input signals.
In [12], CAM array using ECRL CAM cell and ECRL peripheral circuits using
180nm technology is presented. Here we have proposed and designed a CAM array
using improved ECRL (IECRL) CAM core cell. Figure 18 shows the schematic dia-
gram of an improved efficient charge recovery adiabatic logic CAM cell. This IECRL
cell has an additional pair of cross-coupled NMOS devices (NM8 and NM9), which
provides a pull-down path to ground.
The schematic diagram of the 4 × 4 improved efficient charge recovery logic CAM
architecture is shown in Fig. 19. This novel PEBCAM-IECRL 4 × 4 CAM structure
is designed using ECRL address decoder, ECRL encoder and the innovative IECRL
CAM cells.
An IECRL CAM search operation begins with the charging of the word lines using
the power clock ‘PC,’ followed by pre-charging all match lines high, putting them all
temporarily in the match state. Next, the search-line decoders broadcast the search
word onto the differential search lines, and each CAM core cell compares its stored
bit against the bit on its corresponding search lines. Match lines remain in the pre-
charged high state if all bits get matched. Match lines that have at least one bit that
misses discharge to ground. Finally, the encoder generates the address of the match
line by sensing the lines with a high state.
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Fig. 18 Schematic diagram of PEBCAM-IECRL CAM cell in Virtuoso

Fig. 19 Schematic diagram of 4 × 4 IECRL CAM Architecture

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Fig. 20 Schematic diagram of IPFAL CAM cell in Virtuoso

5.2 Proposed IPFAL CAM Cell

A novel IPFAL CAM storage cell is shown in Fig. 20 Its structure is similar to that
of the PFAL XOR/XNOR gate. Its output is used for driving the match line. The 2
PMOS transistors and the 2 NMOS transistors NM0 and NM1 act as a latch which is
used for storage. The remaining transistors are for the compare operation. Here the
power clock signal ‘PC’ acts as a word line.

5.3 Proposed IPAL CAM Cell

A novel improved pass transistor logic content addressable memory, IPAL CAM stor-
age cell is shown in Fig. 21. Its structure is similar to that of the PAL XOR gate.
Its output is used for driving the match line. The 2 cross-coupled PMOS transistors
are used for storage. The remaining NMOS transistors are for the compare operation.
Here the power clock signal ‘PC’ acts as a word line. PAL CAM cell introduced in [1]
uses 11 transistors, whereas our proposal requires 10 transistors. A 4 × 4 IPAL CAM
array is constructed using PAL peripheral circuits and IPAL CAM cells.

6 Simulation Results

In this section, the simulation results of the proposed PEBCAM- IECRL CAM cell,
IPFAL CAM cell and IPAL CAM cell are discussed in detail. Simulation is performed
using CADENCE Virtuoso at 45nm CMOS technology with sinusoidal power clock
of 1 V and other node voltages at 0.7 V.

6.1 Simulation Results of IECRL CAM Cell

A conventional CAM is designed using 45nm CMOS technology with the power clock
voltage value of 1 V. When the stored values of q and qb (output) match bl and blb
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Fig. 21 Schematic diagram of IPAL CAM cell in Virtuoso

Fig. 22 Simulation result of conventional CAM cell

(bit line) values, then the ml line (match line) will go to the high state. If not, it
attains mismatch case with ml line remaining in a low value. Figure 22 shows the
schematic diagram and simulated output of the conventional CAM storage cell using
45nm CMOS technology. The waveform shown is for match operation. Here the match
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Fig. 23 Simulation result of the ECRL AND gate

Fig. 24 Simulation result of the ECRL decoder

operation occurs when the search data ‘bl’ matches stored data ‘q,’ indicating the match
line ‘ml’ as high value.
Simulation results of the ECRL AND gate and ECRL decoder are shown in Figs. 23
and 24, respectively. Simulation result of the IECRL CAM cell using 45nm CMOS
technology is shown in Fig. 25. Here the match operation occurs similar to the con-
ventional CAM cell, but the word line is treated as power clock.
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Fig. 25 Simulation result of IECRL CAM cell in Virtuoso

Fig. 26 Simulation output of PFAL AND gate

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Fig. 27 Simulation output of PFAL decoder

Fig. 28 Simulation output of IPFAL CAM storage cell

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6.2 Simulation Results of IPFAL CAM Cell

An IPFAL CAM cell is designed using 45nm CMOS technology with the power clock
voltage value of 1 V. Simulation results of the PFAL AND gate and PFAL Decoder
are shown in Figs. 26 and 27, respectively. Figure 28 shows the simulated output of
IPFAL CAM storage cell using 45nm CMOS technology. When the stored values of
q and qb (output) match bl and blb (bit line) values, then the ml line (match line) will
follow the power clock. If not, it attains mismatch case with the match line getting
a low value. The waveform shown is for match operation. Here the match operation
occurs when the search data ‘bl’ matches stored data ‘q,’ indicating the match line
‘ml’ as high value.

6.3 Simulation Results of IPAL CAM Cell

An IPAL CAM cell is designed using 45nm CMOS technology with the power clock
voltage value of 1 V. Simulation results of the PAL AND gate and PAL Decoder are
shown in Figs. 29 and 30, respectively. Figure 31 shows the simulated output of IPAL
CAM storage cell using 45nm CMOS technology. When the stored values of q and qb
(output) match bl and blb (bit line) values, then the ml line (match line) will follow the
power clock. If not, it attains mismatch case with the ml line getting a low value. The
waveform shown is for match operation. Here the match operation occurs when the
search data ‘bl’ matches stored data ‘q,’ indicating the match line ‘ml’ as high value.

Fig. 29 Simulation output of PAL AND gate

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Fig. 30 Simulation output of PAL Decoder

Fig. 31 Simulation output of IPAL CAM storage cell

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In this paper, we have presented the implementation of 3 novel PEBCAM cells,

namely IECRL CAM cell, IPFAL CAM cell and IPAL CAM cell. These adiabatic
cells were designed and simulated using cadence virtuoso at 45nm technology. Power
analysis of these cells was made and compared with the conventional 9T CAM cell.
Simulation results of these CAM cells have proved that adiabatic logic shows lower
power consumption than the conventional one. The frequency of the power clock used
for these adiabatic CAM cells is 125 MHZ.
Table 2 shows the energy consumption of the proposed PEBCAM cells in Joules/bit/
search at 125 MHz. Energy consumption in energy/bit/search can be calculated by
using the measured average power, frequency of operation and the size of the CAM
array. Its calculation is shown:

Energy = measured power × (1/frequency) × (1/size of memory)[35]

For example:

Measured power in IECRL CAM Array = 797.6nW

Operating frequency = 125MHz
Size of CAM array = 4 × 4
Energy/bit/search = (797.6 × 10−9 )/(125 × 106 × 4 × 4)
= 0.3988 × 10−15

Energy of IECRL CAM cell = 0.399fJ/bit/search. From Table 2, it is clear that

IECRL CAM cell has lesser power consumption compared to its other adiabatic coun-
terparts but at the cost of 2 additional transistors.
Table 3 shows the CAM array energy comparison table which lists the energy
consumption of the existing CAMs in an array and the proposed PEBCAM cell designs.
Compared to the conventional CAM specified in [42], which needs 1.8fJ/bit/search,
our proposed PEBCAM-IECRL CAM consumes only 0.399fJ/bit/search. This would
result in the power saving of 77.8%. LP CAM based on clustered-sparse networks [8]
is the only contender with energy consumption of 0.124fJ/bit/search.
In [10], PFAL CAM array was constructed using a basic CAM cell and PFAL
peripheral circuits. In this paper, we have presented a 4 × 4 IPFAL CAM array that
is constructed using PFAL peripheral circuits and IPFAL CAM cells. Table 4 shows
the energy consumption comparison of the proposed PEBCAM core cells at 125 MHz
with the existing CAM cells.
In the proposed design, a single IECRL CAM cell consumed only 2.43aJ/bit/search
at the circuit level. Parametric analysis of the PEBCAM cells was performed and found
that their average power consumption was almost constant for different RC values.
Also, the proposed PEBCAM cells had an optimum performance up to 500 MHz. A
sinusoidal power clock was used for energy recycling in the proposed designs.
Table 2 Energy consumption of the proposed PEBCAM cells at 125 MHz

Types of CAM cells Energy consumption at 125 MHz in Joules/bit/search Technology (nm) Frequency (MHZ) Area (No of transistors
used for each CAM cell)
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CAM storage cell 4 × 4 CAM array

Normal CAM cell with 2.39 pJ 2.67 pJ 180 125 9

ECRL peripheral circuits at
180 nm [11]
ECRL CAM cell with ECRL 1.38 pJ 2.37 pJ 180 125 10
peripheral circuits at
180 nm [12]
Conventional CAM cell with 0.63 pJ 1.6 pJ 45 125 9
ECRL peripheral circuits at
45 nm
Proposed PEBCAM-IPFAL 24 aJ 41.2 fJ 45 125 12
cell
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Proposed PEBCAM-IPAL 11 aJ 16.4 fJ 45 125 10

cell
Proposed IECRL CAM cell 2.43 aJ 0.3999 fJ 45 125 12
with ECRL peripheral
circuits
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Table 3 CAM array energy comparison table

Logic Energy/bit/search Technology (nm) Frequency/Delay

Low swing match line 4.2 fJ 180 3.1ns cycle time

sensing techniques [29]
CPALCAM [42] 9.5 fJ 180 100 MHz
2n-2n2p [42] 6.9 fJ 180 100 MHz
SPCAM [5] 4.48 fJ 180 1n
PNNCAM [40] 17.2 fJ 250 3.8
AND CAM [18] 2.33 fJ 180 2.10 n
IPCAM [23] 2.26 fJ 65 385 ps
LP CAM based on clustered- 0.124 fJ 130 0.7 ns
sparse networks [8]
Conventional CAM 1.6 pJ /1.8 fJ 45 125 MHz
Proposed PEBCAM-IPFAL CAM cell 41.2 fJ 45 125 MHz
Proposed PEBCAM-IPAL CAM cell 16.4 fJ 45 125 MHz
Proposed PEBCAM- IECRL CAM cell 0.399 fJ 45 125 MHz

Table 4 Comparison of the energy consumption of the proposed PEBCAM core cells at 125 MHz with
the existing CAM cells

Logic Energy/bit/search Technology (nm)

LP CAM based on clustered- 0.124 fJ 130

sparse networks [8]
Conventional CAM 1.6 pJ /1.8 fJ 45
Proposed PEBCAM-IPFAL CAM cell 24 aJ 45
Proposed PEBCAM- IPAL CAM cell 11 aJ 45
Proposed PEBCAM- IECRL CAM cell 2.43 aJ 45

7 Conclusion

The design and the analysis of 3 novel PEBCAM cells, namely IPFAL CAM cell,
IPAL CAM cell and IECRL CAM cell, were proposed in this paper. Simulation results
and power analysis showed that energy recovery in the proposed IECRL CAM cell
was better with a power saving of 77.8% compared to its counterparts. But the partial
adiabatic logic-IPFAL CAM cell and the fully adiabatic IPAL CAM cell which offered
a power saving of more than 90% when compared with the conventional CAM cell
we designed, effectuated more power consumption in array design compared to the
CAMs reported in the literature.
Thus, if we adopt the other low-power schemes at the architecture level for the
design of the CAM architecture reported in [8], then it would result in a greater power
saving. Also, we have designed only a 4 × 4 CAM for our analysis, but the actual CAM
size is larger. Hence in the future work, the CAM structure can be extended to larger
arrays. Thus, using adiabatic logic in binary content addressable memory, the huge
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power that is otherwise wasted can be reused effectively without compromising on the
speed resulting in power efficient binary content addressable memory (PEBCAM).

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