GHRCE NAGPUR.

MTECH- DEPARTMENT OF VLSI

Design Of Low Power 32 Bit Multicycle MIPS Processor Using HDL
NAME OF THE STUDENT: Tripti Mahajan
NAME OF THE GUIDE: Prof. N. Wyawhare

Abstract: This project aims to outline and mimic the elite multi-cycle pipelined 32-bit Microprocessor without Interlocked Pipeline Stages (MIPS),which is a Reduced Instruction Set Computing (RISC) design based processor. The explanation behind RISC chip is to execute a minor cluster of headings, with
the point of increasing the celerity of the processor. This processor was sketched out with5 times of pipeline particularly Instruction Fetch (IF), Instruction Decode& Enroll Fetch (ID), Execution& Address Calculation (EX), Memory Access (MEM) and Write Back (WB) modules.The masterminding methodology was
finished utilizing a crowd of modules which are the ALU, Control Unit, Program Counter, MUX, Instruction Memory, Information Memory, CPU, Register File, Sign Extension.The illustrating of this processor is made using the Hardware Description Dialect (HDL) - Verilog in Models test framework. The exceptional
purpose of this paper is to develop the RTL method of reasoning design using Xilinx instrument.

Introduction: PIPELINED CPU WAVEFORM

Power consumption and optimization has become a major issue in IC design.Weimplement a low power 32 bit
multicycle Microprocessor without Interlocked Pipeline Stages (MIPS) processor design using HDL. This project Instruction [31:26] [25:21] [20:16] [15:0] Operation Hex Value
targets the implementation design of a MIPS (Microprocessor without Interlocked Pipeline Stages) RISC (Reduced Instruction
Set Computer) Processor using HDL( Hardware Description Language). op rs rt offset

Furthermore, the goal ofthis work is to enhance the simulator-based approach by integrating some hardware design lw $2, 00($1) 100011 00001 00010 0000000000000000 Load Memory Word 8C220000

to help a better understanding of both the MIPS multicycle and pipelined processor. Microchips and lw $3, 04($1) 100011 00001 00011 0000000000000100 Load Memory Word 8C230004
Microcontrollers are for the most part composed in the region of two fundamental PC designs: Complex Direction-
lw $4, 08($1) 100011 00001 00100 0000000000001000 Load Memory Word 8C240008
Set Computing i.e. CISC design and Lessened Instruction Set Computing i.e. RISC design.
lw $5, 12($1) 100011 00001 00101 0000000000001100 Load Memory Word 8C2500012
The idea of CISC depends on Instruction Set Engineering (ISA) plan that increases performing further with a few
directions using a variable number of operands and an extended variety of tending to modes in different areas in its
NOTE:
Instruction $1: This register is initialized to 0 and is specified by rs.
 There are only five ALU Operations for now: add, sub, and, or and xor. The control sign
Set.Hence causing them to have fluctuating execution time and lengths in this way definitively commanding a $2,$3,$4 and $5: These are the destination registers which are specified by rt. are set to 'x' for any other values of op and func. This can be verified from ControlUnit.v.
 The instruction memory has now 5 instructions and rest of the locations of the memory
perplexing Control Unit, which occupies a hugely existent locale on the chip. Contrasted and their CISC simple, Instruction [31:26] [25:21] [20:16] [15:11] [10:6] [5:0] Operation Hex Value
initialized to 0. Depth of this Memory is 256 i.e. 256 instructions can be stored for now.
RISC processors commonly bolster a tiny arrangement of guidelines. A show that compares RISC processor with a The first 10 locations of the data memory have been initialised
op rs rt rd func
CISC processor, the number of guidelines in a RISC Processor is low while the number of broadly useful registers,
add $6, $2, $10 000000 00010 01010 00110 00000 100000 Register Add 004A3020
tending to modes, settled direction length and load-store design is more this, thus, encourages the execution of Conclusion
guidelines to be completed in a brief span in this manner accomplishing higher generally speaking execution. The $6: rd In the poster we have been able to design and simulate a Low Power 32-bit multicycle
MIPS is a RISC based chip design that was created by MIPS Computer Systems Inc. $2: rs MIPS processor by using Xilinx design suite and HDL . The processor executes more
number of instructions with less critical path delay. The reduction in critical path delay
$10: rt also led to the reduction in the execution time thus leading to a better processor

RTL Schematic I/O PLANNING: Package View

References:
[1] Mohammad Zaid, Prof. Pervez Mustajab, “DESIGN AND APPLICATION OF RISC
PROCESSOR”, in Proc. of IEEE Region 10 Conference, Vol. 1, pp. 36-39, 2017
[2] ShaikAfroz, M.Sumalatha, “IMPLEMENTATION OF RISC-BASED ARCHITECTURE FOR LOW
POWER APPLICATIONS”, IOSR Journal of Electrical and Electronics Engineering (IOSR-JEEE) e-
ISSN: 2278-1676,p-ISSN: 2320-3331, Volume 8, Issue 4 (Nov. - Dec. 2013), PP 01-06
Device View Floor Planning
[3] PriyavratBhardwaj ,SiddharthMurugesan, “DESIGN & SIMULATION OF A 32-BIT RISC BASED
MIPS PROCESSOR USING VERILOG”, IJRET: International Journal of Research in Engineering and
Technology eISSN: 2319-1163 | pISSN: 2321-7308
[4] Mohammad Zaid, Prof. Pervez Mustajab, “DESIGN AND APPLICATION OF RISC
PROCESSOR”, in Proc. of IEEE Region 10 Conference, Vol. 1, pp. 36-39, 2017