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C.M.R.I.T, Bangalore

EXPT NO:1

AIM: SIMPLIFY AND REALIZE THE BOOLEAN EXPRESSION USING

LOGIC/UNIVERSAL GATES .
For Ex. Simplify the Expression 1) y  ABC  AB  BC
2) y  F ( A, B, C )   m(0,1,4,5,7)
3) y  F ( A, B, C )   M (2,3,6)

COMPONENTS REQUIRED: IC Trainer kit, IC 7404, IC 7408, IC7432, IC7400, and

IC7402.

Method 1 for 1) :

Expand the expression by multiplying the 2nd term with (C  C ) and 3rd term with ( A  A)
as shown below
y  ABC  AB (C  C )  BC ( A  A)
 ABC  ABC  ABC  A BC  A BC.......... .1
 AC ( B  B )  AC ( B  B )  ABC
 AC  AC  ABC
 C ( A  A)  ABC
 C  AB

Method 2 using K-map for 1) :

Equation 1 can be mapped on to K-map as shown below.

BC
A
00 01 11 10

0 1 1 0
0
C
Y=AB+C
1 0 1 1 1
AB

Truth table:

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INPUTS OUTPUT

A B C Y

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

1) Realization using basic gates

1
A 3
2 7408
B
1
3 Y =AB + C
2 7432
C

2) Realization using Universal gates:

i) WITH NAND GATES ONLY:
1
A 7
40
0 3

B 2

Y = AB + C
4
6
7
40
0
5
A
9
8 A
C 7
40
0 A
1
0

ii)WITH NOR GATES ONLY:

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3
1
A 7
4
02
-1

2 8 1
0
A 7
4
02
-1

5 9 1
1 1
3 3
B A 7
4
02
-
1 4 7
4
02
-
1 7
4
02
-
2 1 Y = AB + C
1
2
6 2

Equation 2 can be mapped on to K-map as shown below.

A BC
00 01 11 10

0 0 0
1 1
B
1 1 1 1
0 Y = AC + B
AC
Truth table:

INPUTS OUTPUT

A B C Y

0 0 0 1

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 0

1 1 1 1

1) Realization using basic gates:

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1
A 3
2 7408

1
7432 3 Y
=A
CB
+
2

B 1
7404
2

C
2) Realization using Universal gates:
i) WITH NAND GATES ONLY:

1
3
A 2 7400 4
6 Y= B
5 7400
+AC

B
C
ii)WITH NOR GATES ONLY:

2
7402-1 1 11
A 7402-1 13 2 5 4
3 7402-2 1 7402-2 Y= B + AC
12
3 6 Y= B
5
+AC
7402-1 4
B
6

8
7402-1 10
C
9

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Equation-3 can be mapped on to K-map as shown below.

A BC
00 01 11 10

0 0 0
(A + B )
Y= (A + B )( B + C)

1 0 ( B + C)

Truthtable:

INPUTS OUTPUT

A B C Y

0 0 0 1

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 0

1 1 1 1
1) Realization using basic gates:

1
A 3
2 7432

1
B 1
7404
2
2
7408
3 Y= (A + B )( B + C)

4
6
5 7432
C

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2) Realization using Universal gates:

i)WITH NAND GATES ONLY:

ii) WITH NOR GATES ONLY:

C
B
5
A 4
7402
6
Y
Y== (A
(A + B )(
+ B B+
)( B + C)
C)
12
2 13
1 11 7402
B 7402
3

9
10
8 7402
C
Procedure:
1. Make connections as shown in the circuit diagram(include supply connections).
2. Apply inputs using toggle switches and verify the truth table using LEDs.

Result: Given Boolean expression is simplified and realized using logic gates and the truth
table has been verified
Conclusion: Simplifying and then realizing a given logic expression uses less number of
gates and thus helps in implementing more logic within the given area.
Probable Viva Questions:.
 Boolean laws, Identities, Properties, Huntington’s postulates.
 Realization of basic gates using universal gates and vice versa. Conversion of 2
input NAND into 3 input NAND and 4 input NAND gate. Decoding of the IC
number, Significance of Schottky Series.
 Noise Margin, Fan out, Fan in, Propagation delay, Speed Power product.
Comparison of different Logic families, Fastest logic family, TTL Logic family.
 Application of X-OR gate, realizing X-OR using minimum number of NAND
gates. Coincidence gate?
 Different methods of Simplification, which method is preferred when?
 State DeMorgan’s Theorem and prove them.

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EXPT NO:2
AIM: REALIZATION OF HALF/FULL ADDER AND HALF/FULL SUBTRACTOR
USING LOGIC GATES

COMPONENTS REQUIRED: IC Trainer kit , IC 7408 AND gate, IC7432 OR gate,

IC7400 NAND gate and IC7486 XOR gate.

Block diagram of Half Adder:

A Sum

Half Adder

B Carry

Truth table for Half Adder:

I/P O/P
A B S Co
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Expression for Sum and Carry:
S  A B  AB  A  B
C  AB

Logic diagram of Half Adder using Basic & X-OR gates:

A
1

2
7486 3 S=A  B
B

1
7408 3 Co = AB
2

Logic diagram of Half Adder using Universal NAND gates:

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4
6
7400-1
5

A S=A  B
1 12
7400-1 3 7400-1 11
2 13

9
7400-1 8
10

1
Co = AB
7400-2 3
2

Block diagram of Full Adder:

A
Sum
Full Adder
B
Co
Cin

Truth table for Full Adder:

Operation: S = A + B + Cin
INPUTS OUTPUTS
A B Cin S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

K-map for Sum:

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BCin
A
00 01 11 10

0 1 0 1
0 S=AB Cin + A B Cin+ ABCin + A B
Cin
= Cin(AB + A B ) + Cin ( A B + A B)
1 1 0 1 0 = Cin A  B + Cin (A  B)
= A  B  Cin
S  A  B  Cin

K-map for carry:

BC
A 00 01 11 10

0 0 0 1 0 Co = A B Cin + AB Cin + ABCin + A

BCin
= AB(Cin+ Cin ) + Cin ( A B + A B)
1 0 = AB +Cin(A  B)
1 1 1

Co= AB +Cin(A  B)

Logic diagram of Full Adder using Basic & X-OR gates (2 Half Adders):

Block diagram:

A
Sum1 Sum

Halfadder1 Carry1 Halfadder2

1 3
7432
Cin 2
Carry Out

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Logic diagram:

A
1
7486
3 Sum1 4
2 6
5
7486 Sum
B

Halfadder1
Halfadder2
11 4
7408
3 Carry1 7408
6
2 5

1 Carry out
3
7432
Cin 2

Logic diagram of Full Adder using Universal NAND gates:

4
6
5 7400-1 4
6
5 7400-2
A
1 12
7400-1 3 7400-1 11 Sum
2 13 1 12
3 11
B 2 7400-2 13 7400-2

9
7400-1 8
10 9
8
10 7400-2

1
3
2 7400-3
Carry out

Cin

Block diagram of Half Subtractor:

A Difference
Half
B Subtractor
Borrow

Truth table for Half Subtractor:

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I/P O/P
A B D Bo
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Expression for Difference and Borrow:

D  AB  A B  A  B
Bo  AB
Logic diagram of Half Subtractor using Basic gates:
A
1
7486 3 Difference
2

HalfSubtractor1

1 7404 2

1 Borrow
7408 3
2

Logic diagram of Half Subtractor using NAND gates only:

4
7400-1 6
5

A
1 12
Difference
7400-1 3 7400-1 11
2 13

9
7400-1 8
10

1
Borrow out
7400-2 3
2

Block diagram of Full Subtractor:

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A
D
Full
B Subtractor
Bo
Bin

Truth table for Full Subtractor:

Operation: D= A – B – Bin
INPUTS
OUTPUTS D=AB Bin + A B Bin+ ABBin + A B
A B Bin D Bo Bin
0 0 0 0 0 = Bin(AB + A B ) + Bin ( A B + A B)
0 0 1 1 1 = Bin A  B + Bin (A  Note:
B) K-map is not
0 1 0 1 1 = A  B  Bin shown, because the
simplified expression
0 1 1 0 1
Bo = A B Bin + A B Binuses more +
+ ABBin number
A of
1 0 0 1 0
BBin gates.
1 0 1 0 0
= A B(Bin+ Bin ) + Bin ( A B + A B
1 1 0 0 0
)
1 1 1 1 1 = A B +Bin( A  B )
Note: K-map is not shown, because the simplified expression uses more number of gates.

Expression for difference and borrow:

D  A  B  Bin
Bo  AB  Bin ( A  B )

Logic diagram of Full Subtractor using X-OR & Basic gates(2 Half Adders):
Block diagram:

A
Difference 1 Difference

HalfSub1 Borrow 1 HalfSub2

B

1
3
Bin 2 7432

Borrow out

Logic diagram:

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A
1
7486 3 Difference 1 4
2 7486 6 Difference
5
B

HalfSubtractor1
HalfSubtractor2
1 7404 2

3 7404 4

1 Borrow1
7408 3 4 Borrow out
2 7408 6 1
5 7432 3
2

Bin

Logic diagram of Full Subtractor using NAND gates only:

4
7400-1 6
5 4
7400-2 6
5
A
1 12 Difference
7400-1 3 7400-1 11
2 13 1 12
7400-2 3 7400-2 11
B 2 13

9
7400-1 8
10 9
7400-2 8
10

1 Borrow out
7400-3 3
2

Bin

Procedure:
1 Make connections as shown in the circuit diagram.
2 Apply inputs using toggle switches and verify the truth table using LEDs.

Result: Half adder, Full adder, Half Subtractor, Full Subtractor circuits are realized using
logic gates and the truth tables are verified.

Conclusion: Adder and Subtractor circuits are the most essential part of ALU. Workings of
these circuits at gate level are understood in this experiment.

ProbableVivaQuestions:.
 Applications of Adder and Subtractor circuits.

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 Definition of Half adder, Full Adder, Half Subtractor, Full Subtractor. Realizations
of the same. Derivation of truth table in each case. Obtaining the logic expression.
 Realizing FA using 2 Half adders, FS using 2 Half Subtractors.
 Application of X-OR gate, realizing X-OR using minimum number of NAND
gates. Coincidence gate?

EXPT NO: 3
AIM:
a. Realization of Parallel Adder/Subtractor using IC7483.
b. BCD to Excess-3 code conversion and vice versa.

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COMPONENTS REQUIRED: IC Trainer kit, IC 7483 Parallel Adder and IC7400 NAND
gate.

Realization of Parallel Adder/Subtractor using IC7483:

B3 B2 B1 B0

Cin

13 12 10 9 5 4 2 1

7486 7486 7486 7486

11 8 6 3

A3 A2 A1 A0

1 3 8 10 16 4 7 11
VCC +5V

5
7483 13

12

14 15 2 6 9

Cout
S3 S2 S1 S0

Procedure:
4 bit Binary Adder:

1. Make Cin = 0. The circuit works as an Adder.

2. Set A3A2A1A0 = Binary equivalent of the Augend using toggle switches.
B3B2B1B0 = Binary equivalent of the Addend using toggle switches.
3. Verify the Result on CoutS3S2S1S0 using LEDs.
Ex.1 Ex.2
A=4, B=8 A=13, B=9
S=A + B S=A + B

Augend Addend Augend Addend

A3A2A1A0 = 0 1 0 0 A3A2A1A0 = 1 1 0 1

B3B2B1B0 = 1 0 0 0 B3B2B1B0 = 1 0 0 1
CoutS3S2S1S0 = 0 1 1 0 0 = (12)10 CoutS3S2S1S0 =10110=
(22)10

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4 bit Binary Subtractor:

1. Make Cin = 1. The circuit works as a Subtractor.

2. Set A3A2A1A0 = Binary equivalent of the Minuend using toggle switches.
B3B2B1B0 = Binary equivalent of the Subtrahend using toggle switches.
3. Verify the Difference on S3S2S1S0 and Carry generated on Cout using LEDs.

Ex.1 Ex.2
A=4, B=8 A=15, B=9
D = A - B = A + (2’s Complement of B) D = A - B = A + (2’s
Complement of B)

Minuend Subtrahend Minuend Subtrahend

A3A2A1A0 = 0 1 0 0 A3A2A1A0 = 1 1 1 1
B3B2B1B0 = 1 0 0 0 B3B2B1B0 = 1 0 0 1
2’Complement of B = 1’ complement of B + 1 2’Complement of B = 1’
complement of B + 1
=0111 =0110
+1 +1

2’Complement of B = 1 0 0 0 2’Complement of B = 0 1 1 1
D = A - B = A + (2’s Complement of B) D = A - B = A + (2’s
Complement of B)
= 0100 = 1111
+(1 0 0 0) +(0 1 1 1)

CoutS3S2S1S0 = 0 1 1 0 0 CoutS3S2S1S0 =10110

Cout = 0 implies that answer is negative Cout = 1 implies that answer is positive,
ignore carry
& in 2’s Complement form. & in direct form.
Answer = (- 0 1 0 0) =(-4) 10 Answer = (+ 0 1 1 0) = (+6) 10

Result: Addition and subtraction for the given numbers is performed using 7483.
Conclusion: Addition of any two 4 bit binary numbers can be performed using 7483. It is
observed that subtraction also can be performed using the adder chip itself
with the help of small additional logic.
Note: Examiner may specify the numbers.
Probable Viva Questions:
 What are the different methods of representing –ve numbers, Which type is preferred and
why?
 Procedure for 1’s complement method of subtraction
 Procedure for 2’s complement method of subtraction
 State different methods of subtraction using complementary methods
 Why complementary methods are preferred?
 What are the advantages of 2’s complement method?
 Internal diagram of IC 7483, What is the significance of Cin and Cout pins.
 Types of Adders, advantages and disadvantages of different types, Explain Look ahead
carry adder.
BCD to Excess-3 code conversion and Excess-3 to BCD code conversion:

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Truth table:

BCD DATA EXCESS-3 DATA

A3 A2 A1 E3A0 E2 E1 E0 Procedure:
0 0 0 0 0 0 1 1
1. Make Cin = 0 for BCD to
0 0 0 0 1 1 0 0 Excess-3 code conversion
2. 0 0 1 0 0 1 0 1 Check the output at
0 0 1 0 1 1 1 0 S3S2S1S0 for all the valid
0 0 1 code as shown in the truth
0 1 0 1 1
table.
3. 0 1 0 1 1 0 0 0 Make Cin = 1 for Excess-3 to
0 1 1 1 0 0 0 1 BCD conversion.
4. 1 1 0 Check the output at
0 1 1 1 0
S3S2S1S0 for all the valid
1 0 0 1 0 0 1 1 code as shown in the truth
1 0 0 1 1 1 0 0 table.
BCD to Excess-3 code conversion
and Excess-3 to BCD code conversion:
Logic 0 Logic 1

Cin

13 12 10 9 5 4 2 1

7486 7486 7486 7486

11 8 6 3

A3 A2 A1 A0

1 3 8 10 16 4 7 11
VCC +5V

7483 13

12

14 15 2 6 9

Cout
S3 S2 S1 S0

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Probable Viva Questions:

 State properties of X’s- 3 code and BCD code.
 Application of BCD and X’S-3 code.
 Significance of X-OR gates in the above experiment.
 What is the expected value of Cout in each conversion and justify it value.
 Examples for other codes, significance of codes.
 What is the output if (10 to15) are given as inputs in BCD to X’S code
conversion?

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EXPERIMENT NO 04

AIM: - To realize binary to gray code converter and vice-versa.

COMPONENTS REQUIRED: - IC 7411, 7486, Digital IC trainer kit, patch chords

THEORY:-

BINARY TO GRAY:- The gray code is often used in digital systems because it has the
advantage that only one bit in the numerical representation changes between successive
numbers. Table shows decimal and binary codes and corresponding Gray code.

GRAY TO BINARY:-Gray codes are also called reflected codes. Gray code is an
example of unweighed code. Unweighted codes means there are no specific weights
assigned to the bit positions. BCD (8421) is an example of weighted code. Gray code can
be used to represent digital data in digital communication system. The advantage of gray
code over binary number is that a number in the gray code changes by only one bit as it
proceeds from one number to the next.

Truth Table

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

G0=B1B0+B1B0=B1 + B0
G1=B2B1+B2B1=B2 + B1
G2=B3B2+B3B2=B3 + B2
G3=B3

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B0
G0

B1
G1

B2
G2

B3 G3

B3 B2 B1 B0

G3

G2

G1

G0

TRUTH TABLE:

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G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

B0=G3 + G2 + G1 + G0
B1=G3 + G2 + G1
B2=G3 + G2
B3=G3

G0 B0

G1
B1

G2
B2

G3 B3

G3 G2 G G0

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B3

B2

B1

B0

PROCEDURE:
1. connections are made as per the circuit given

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2. Switch on the +5V power supply

3. verify the truth table
4. switch off the power supply and disconnect the circuit

RESULT:

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If you want truly to understand something, try to change it

http://www.mydreamworld.50webs.com/index.html
EXPT NO: 5

AIM: Mux/Demux, use of IC74153 and IC74139 for Arithmetic circuits and code
converters.

COMPONENTS REQUIRED: IC Trainer kit, IC 74153 Mux, IC 74139 Demux, IC

7400,7420 NAND gate and IC 7404 Inverter gate.

Theory: A digital Multiplexer is a combinational circuit that selects binary information from
one of many input lines and directs it to
a single output line. The selection of a particular input line is controlled by a set of
selection lines.
General Block diagram of Mux:
I0
I1
I2
2n:1 Y

I2n - 1

S0 S1 Sn-1

Block diagram of 4:1 Mux:

I0
I1 4:1
I2 Y
Mux
I3

Truth Table of 4:1 Mux: S1 S0

Realization of 4:1 Mux Using NAND gates(with Active low enable input
Y=ES1S0I0+ ES1S0I1+ES1S0I2+ES1S0I3)

SELECT
INPUTS OUTPUT
LINES
S1 S0 I3 I2 I1 I0 Y
0 0 X X X 0 0
0 0 X X X 1 1
0 1 X X 0 X 0
0 1 X X 1 X 1
1 0 X 0 X X 0
1 0 X 1 X X 1
1 1 0 X X X 0
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1 1 1 X X x 1
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E S1 S0

10
2

9
7400 7400 7400
Y=S1S0I0+S1S0I1+S1S0I2+S1S0I3

1
3

8
2
6
4 7420-1
I0 5

9
10
8
12 7420-1 1
I1 13 2
6 Y
1 4 7420-3
2 5
6
4 7420-2
I2 5

9
10
8
12 7420-2
I3 13

Procedure:
3. Make connections as shown in the circuit diagram.
4. Apply inputs using toggle switches and verify the Operation of Mux using LEDs.

IC 74153 – Dual 4 X 1 Mux

Truth table for Mux:

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Enable Select
Outputs
lines lines Inputs
Eb Ea S1 S0 Ib3 Ib2 Ib1 Ib0 Ia3 Ia2 Ia1 Ia0 Ya Yb
1 0 0 0 X X X X X X X 0/1 Ia0 0
1 0 0 1 X X X X X X 0/1 X Ia1 0
1 0 1 0 X X X X X 0/1 X X Ia2 0
1 0 1 1 X X X X 0/1 X X X Ia3 0
0 1 0 0 X X X 0/1 X X X X 0 Ib0
0 1 0 1 X X 0/1 X X X X X 0 Ib1
0 1 1 0 X 0/1 X X X X X X 0 Ib2
0 1 1 1 0/1 X X X X X X X 0 Ib3
Ia0 6 7 Ya
Ia1 5 1C0 1Y 9 Yb
Ia2 4 1C1 2Y
Ia3 3 1C2
1C3
Ib0 10
Ib1 11 2C0
12 2C1
74153

Ib2
Ib3 13 2C2
2C3
S0 14
S1 2 A
B
Ea 1
Eb 15 1G
2G

74153 - Dual 4 X 1 Mux

 Ea is enable input for Mux – 1 and Eb is enable input for Mux – 2. ( both are
active low).
 With Ea = 0 & Eb = 1 Mux – 1 will be enabled and Mux – 2 will be
disabled.
 With Ea = 1 & Eb = 0 Mux – 1 will be disabled and Mux – 2 will be
enabled.
 With Ea = 0 & Eb = 0 both Mux – 1 and Mux – 2 are enabled.
 With Ea = 1 & Eb = 1 both Mux – 1 and Mux – 2 are disabled.
 S1, S0 are select lines common to both multiplexers.
 Ia0 – Ia3 are inputs of Mux – 1 and Ya = output, Ib0 – Ib3 are inputs of Mux – 2
and Yb = output.

To test the IC 74153 :

1. Refer the pin details of 74153 and make connections.

2. Data inputs, enable inputs and select inputs are connected to the toggle switches and
outputs to LEDs.
3. Verify the truth table by applying different inputs.

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Arithmetic operations using 74153:

1) Half Adder

Truth table for Half Adder:

I/P O/P
A B S Co
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Design:
Here, 2 outputs need to be generated. Sum can be generated using Mux1 and Carry
out using Mux2 of 74153. By observing the truth table we see that if S1= A and S0=B,
required output can be obtained by connecting the inputs to appropriate logic levels. For Ex.
If S1S0= AB=00, Sum=0 and Co=0, hence make Ia0=0(i.e. the value of Sum when A=0 and
B=0), Ib0=0( i.e. the value ofQo when A=0 and B=0). Similarly we get Ia1=1, Ia2=1, Ia3=0
and Ib1=0, Ib2=0, Ib3=1.

Circuit diagram for Half Adder using 74153:

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Logic 0 Ia0 6 7 Ya=Sum

Ia1 5 1C0 1Y 9 Yb=Cout
Ia2 4 1C1 2Y
Logic 1 Ia3 3 1C2
1C3
Ib0 10
Ib1 11 2C0
Ib2 12 2C1

74153
Ib3 13 2C2
2C3
B S0 14
S1 2 A
A B
Ea 1
Eb 15 1G
2G

Procedure:
1. Make connections as shown in the circuit diagram(Include Supply Connections).
2. Apply inputs and verify the truth table.

2) Full Adder

Truth table for Full Adder:

I/P O/P
A B Cin S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Design:
Here, 2 outputs need to be generated. Sum can be generated using Mux1 and Carry
out using Mux2 of 74153. Concept of VEM technique can be applied to obtain the outputs.
By observing the truth table we see that if S1= A and S0=B, required output can be obtained
by representing the Sum and Carry in terms of Cin and applying inputs in terms of Cin. For
Ex. If S1S0= AB=00, Sum follows Cin hence make Ia0=Cin and Co=0 irrespective of Cin
hence make Ib0=0. Similarly we get Ia1=Cin, Ia2=Cin, Ia3=Cin and Ib1=Cin, Ib2=Cin,
Ib3=1.

Circuit diagram for Full Adder using 74153:

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Cin

Ia0 6 7 Ya=Sum
Ia1 5 1C0 1Y 9 Yb=Cout
Ia2 4 1C1 2Y
Ia3 3 1C2

1
1C3
7404 Logic 0 Ib0 10
Ib1 11 2C0
12 2C1

74153
Ib2
Logic 1 Ib3 13 2C2
2C3
2

B S0 14
S1 2 A
A B
Ea 1
Eb 15 1G
2G

Procedure:
Same as that of Half Adder.
3) Half Subtractor
Truth table for Half Subtractor:
Input
Output
A B D Bo
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Design:
Design Procedure is similar to that of Half Adder. Solution is S1=A, S0=B, Ia0=0,
Ia1=1, Ia2=1, Ia3=0 and Ib0=0, Ib1=1, Ib2=0, Ib3=0.

Circuit diagram for Half Subtractor using 74153:

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Logic 0 Ia0 6 7 Ya=Difference

Ia1 5 1C0 1Y 9 Yb=Bout
Logic 1 Ia2 4 1C1 2Y
Ia3 3 1C2
1C3
Ib0 10
Ib1 11 2C0
Ib2 12 2C1

74153
Ib3 13 2C2
2C3
B S0 14
S1 2 A
A B
Ea 1
Eb 15 1G
2G

Procedure:
Similar to that of half adder.

4) Full Subtractor:
Truth table for Full Subtracotor:
I/p O/p
A B Bin D Bo
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Design:
Similar to that of Full adder. Solution is S1=A, S0=B, Ia0=Bin, Ia1=Bin, Ia2=Bin,
Ia3=Bin and Ib0=Bin, Ib1=1, Ib2=0, Ib3=Bin.

Circuit diagram for Full Subtractor using 74153:

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Bin

Ia0 6 7 Ya=Difference
Ia1 5 1C0 1Y 9 Yb=Bout
Ia2 4 1C1 2Y
Ia3 3 1C2
1

1C3
7404 Ib0 10
Logic 1 Ib1 11 2C0
2C1

74153
Logic 0 Ib2 12
Ib3 13 2C2
2C3
2

B S0 14
S1 2 A
A B
Ea 1
Eb 15 1G
2G

Procedure: Same as that of Half Adder.

Probable Viva Questions:

1. Define Multiplexer 2.Design a 2X1Mux. 3. Realize a 4X1 Mux using 2X1 Mux
4. What is the significance of enable inputs 5. What is the relation between select
and I/P lines 6. State practical applications of Mux 7. What is the inference from
realizing arithmetic circuits using Mux.

Demultiplexer(Dmux):
Demultiplex means one into many. A Demultiplexer is a logic circuit with
one input and many outputs. By applying
Control signals, we can steer the input signal to one of the output lines.
IC74139 is a high speed dual 2 of 4 decoder/
Demultiplexer. The device has two independent circuits accepting two
binary weighted inputs S1,S0 and provides
four mutually exclusive active low outputs. Each decoder has an active low
enable input(E).

General Block diagram of DMux:

Y0
Y1
I Y2
1X2n
DMux

Y2n - 1

S0 S1 Sn-1

Block diagram of 1:4 DMux:

Y0
1:4 Y1
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DMux
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I
Y2
Y3

S1 S0
Truth Table of 1:4 DMux: Realization of 1:4 DMux Using NAND gates

S1 S0 I Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 Y0= S1 S0I
0 0 1 0 0 0 1 Y1= S1 S0I
0 1 0 0 0 0 0
Y2=S1 S0I
0 1 1 0 0 1 0
1 0 0 0 0 0 0 Y3=S1S0I

1 0 1 0 1 0 0
1 1 0 0 0 0 0
1 1 1 1 0 0 0
I S1 S0
2

7400-1 7400-1

1 9
3

2 12 8 Y0
13 7410-1 10 7400-1

3 1
4 6 3 Y1
5 7410-1 2 7400-2

9 4
10 8 6 Y2
1 7410-1 5 7400-2

1 9
2 12 8 Y3
13 7410-2 10 7400-2

Procedure:
1. Make connections as shown in the circuit diagram.
2. Apply inputs using toggle switches and verify the operation of Dmux using LEDs.
IC 74139 – is a Dual 1:4 Dmux and can be used as a 2:4 Decoder (A Decoder will not
have data input line)

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Truth table for 74139:

VCC +5V
INPUTS OUTPUTS
16
En S1 S0 Y0 Y1 Y2 Y3
X/Y
Soa 2 4 Yoa
S1a 3 1 5 Y1a
1 2 6 Y2a 1 X X 1 1 1 1
Ea EN
7 Y3a

Sob 14 12 Yob 0 0 0 1 1 1 0
S1b 13 11 Y1b
15 74LS139 10 Y2b 0 0 1 1 1 0 1
Eb 9 Y3b

8 0 1 0 1 0 1 1

0 1 1 0 1 1 1

 Enable pins operations are similar to that of 74153.

To test the IC 74139 Dual Dmux/Deocoder:

1 Refer the pin details of 74139 and make connections.
2 Data inputs, enable inputs and select inputs are connected to the toggle switches and
outputs to LEDs.
3. Verify the truth table by applying different inputs.

Arithmetic operations using 74139:

1) Half Adder

Truth table for Half Adder:

I/P O/P
A B S Co
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

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Design:
In a decoder outputs corresponding to all possible combinations of inputs will be
available. To realize any function it is required to tap the necessary outputs and sum them.
Since 74139 is an active low output device Nand gates are preferred to realize the function.
S = ∑m ( 1, 2) = m1 + m2 = m1 . m2 and Co= m3 = m3

Circuit diagram for Half Adder using 74139:

1 Sum
B 2 4 7400 3
3 A Y0 5 2

74LS139
A
B Y1 6
1 Y2 7
G Y3 4 Cout
7400 6
5

Procedure:
1. Make connections as shown in the circuit diagram(Include Supply
Connections).
2. Apply inputs and verify the truth table.

2) Full Adder

Truth table for Full Adder:

I/P O/P
A B Cin S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Design:
First convert 2:4 decoders into 3:8 decoder and follow the design procedure of Half
adder using decoder. S = ∑m ( 1, 2, 4,7) and Co= ∑m(3, 5, 6, 7).
Circuit diagram for Full Adder using 74139:

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Cin 2 4 1
3 A Y0 5 2

74LS139
Sum
B B Y1 6 6
1 Y2 7 4 7420
A G Y3 5
1

9
7404 10 Cout
8
14 12 12 7420
13 A Y0 1 13
B 74LS139 Y1 10
Y2
2

15 9
G Y3

Procedure:
Same as that of Half Adder.

3) Half Subtractor:Truth table for Half Subtractor:

Input Output
A B D Bo
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Design:
Design Procedure is similar to that of Half Adder. D=∑m(1, 2) and Bo=m1
Circuit diagram for Half Subtractor using 74139:

1 Difference
B 2 4 7400 3
3 A Y0 5 2
74LS139

A
B Y1 6
1 Y2 7
G Y3 4 Bout
7400 6
5

Procedure:
Similar to that of half adder.

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4) Full Subtractor
Truth table for Full Subtracotor:

I/p O/p
A B Bin D Bo
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Design:
It is similar to that of Full adder. D=∑m(1, 2, 4, 7) and Bo=∑m(1, 2, 3, 7)

Circuit diagram for Full Subtractor using 74139:

Bin 2 4 1
A Y0
74LS139

3 5 2 Difference
B B Y1 6 6
1 Y2 7 4 7420
A G Y3 5

9
1

10 Bout
7404 8
12 7420
14 12 13
13 A Y0 11
74LS139

B Y1 10
Y2
2

15 9
G Y3

Procedure: Same as that of Half Adder.

Code Converters Using 74139:

1) 3-bit Binary to Gray code converter:

Binary Code Gray Code

B2 B1 B0 G2 G1 G0
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 ꡷ 1 0
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0

Design: From the Truth table we observe that

G0=∑m(1, 2, 5, 6)
G1=∑m(2, 3, 4, 5)

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G2=∑m(4, 5, 6, 7) =B2

Circuit diagram for 3-bit Binary to Gray code converter using 74139:

B0 2 4 1
A Y0

74LS139
3 5 2
B1 B Y1 6 6 G0
1 Y2 7 4 7420
B2 G Y3 5
1

9
7404 10
8 G1
14 12 12 7420
13 A Y0 11 13
74LS139

B Y1 10
Y2
2

15 9
G Y3
G2

Procedure:
1. Make connections as shown in the circuit diagram.
2. Apply the inputs and verify the truth table.

2) 3-bit Gray to Binary code converter:

Gray Code Binary Code

G2 G1 G0 B2 B1 B0
0 0 0 0 0 0
0 0 1 0 0 1

0 1 0 0 1 1

0 1 1 0 1 0

1 0 0 1 1 1

1 0 1 1 1 0

1 1 0 1 0 0

1 1 1 1 0 1

Design: From the Truth table we observe that

B0=∑m(1, 2, 4, 7)

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B1=∑m(2, 3, 4, 5)
B2=∑m(4, 5, 6, 7) =G2

Circuit diagram for 3-bit Gray to Binary code converter using 74139:
G0 2 4 1
A Y0

74LS139
3 5 2
G1 B Y1 6 6 B0
1 Y2 7 4 7420
G2 G Y3 5
1

9
7404 10
8 B1
14 12 12 7420
13 A Y0 11 13
74LS139

B Y1 10
Y2
2

15 9
G Y3
B2
Procedure:
1. Make connections as shown in the circuit diagram.
2. Apply the inputs and verify the truth table.

Result: Operation of Mux and Dmux and their applications in Arithmetic circuits and Code
converters has been realized.
Conclusion: It is observed that any given function can be realized very easily realized using
Mux and Dmux.
Probable Viva Questions:
1. Define Dmux
2.What is the difference between Dmux and Decoder.
3.State practical Applicationsof Dmux and Decoder.
4. Realize 3:8 decoder using 2:4 decoders.
5. Can Decoder be used as Dmux.
6. Given a logic expression which is the best method of realizing it & why?
7. Is there any significance of enable lines being active low?
8. What do you mean by Active low and Active high logic?
9. what are the different methods of indicating active low signals?
10. State different properties Binary and Gray Code.
11. What is the significance of enble inputs
12. Design 1:2 decoder

Dept. of TCE 38
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EXPT NO: 6

AIM: Realization of one/two bit comparator and study of IC 7485 magnitude

comparator.

COMPONENTS REQUIRED: IC Trainer kit, IC 7485 Magnitude comparator, IC 7408

AND gate, IC 7432 OR gate, IC 7404 Inverter, 7486 XOR gate and IC 7400 NAND gate.

Theory: A magnitude comparator is a combinational circuit that compares 2 numbers A and

B, and determines their relative
magnitudes. The outcome of the comparison is either A < B or A > B or A = B.

A>B
A
Magnitude A=B
B Comparator A<B

One bit comparator: Expression

INPUT OUTPUT
(A = B) = A B + A B

A B A>B A<B A=B

A < B =A B

0 0 0 0 1 A > B =A B

0 1 0 1 0

1 0 1 0 0

1 1 0 0 1

Logic diagram of one bit comparator:

A
1 2 1
3
2 A <B
7404
7408

1
3 5 6
2 A =B
7432 7404

4
B 6 A >B
3 4 5

7408
7404

2 bit comparator:

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Truth table for 2 bit comparator: k – map:

Expressions:

IN P U T S OUTPUT
B1B0
A1 A0 B1 B0 A>B A<B A=B A1A0
00 01 11 10

0 0 0 0 0 0 1 00 1 0 0 0
(A = B )= (A 1 B 1 + A 1 B 1 )(A 0 B 0 + A 0 B 0 )
0 0 0 1 0 1 0 01 0 1 0 0
0 0 1 0 0 1 0 11 0 0 1 0
0 0 1 1 0 1 0 10 0 0 0 1
0 1 0 0 1 0 0
B1B0
0 1 0 1 0 0 1 A1A0
00 01 11 10

0 1 1 0 0 1 0 00 0 0 0 0
0 1 1 1 0 1 0 01 1 0 0 0 (A > B )= A 1 B 1 + A 0 B 1 B 0 + A 1 A 0 B 0
1 0 0 0 1 0 0 11 1 1 0 1
1 0 0 1 1 0 0 10 1 1 0 0
1 0 1 0 0 0 1
B1B0
1 0 1 1 0 1 0 A1A0
00 01 11 10

1 1 0 0 1 0 0 00 0 1 1 1
1 1 0 1 1 0 0 01 0 0 1 1 (A < B )= A 1 B 1 + A 0 B 1 B 0 + A 1 A 0 B 0
1 1 1 0 1 0 0 11 0 0 0 0
1 1 1 1 0 0 1 10 0 0 1 0

Logic diagram of 2 bit comparator:

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A 1 A o B 1 B o

3 5 9
1

4 6 8
2

1
3
2

7 400

1 9 A > B
2 12 10 8
13 11

7 410 7410

3
4 6
5

7 410

4
6
5

7 400

1
2 12
9
10 8 A < B
13 11

7 410 7410

3
4 6
5

7 410

1
3
2

7 486
2 A = B
1
3
4
6
7402
5

7 486

Realization of 4 bit Comparator using IC 7485:

Function table of 7485

Comparing Inputs Cascading Input Outputs

A3 B3 A2 B2 A1 B1 A0 B0 A> B A= B A< B A> B A= B A< B

A3 >B3 X X X X X X 1 0 0

A3 <B3 X X X X X X 0 0 1

A3 =B3 A2>B2 X X X X X 1 0 0

A3 =B3 A2<B2 X X X X X 0 0 1

A3 =B3 A2 =B2 A1>B1 X X X X 1 0 0

A3 =B3 A2 =B2 A1<B1 X X X X 0 0 1

A3 =B3 A2 =B2 A1=B1 A0>B0 X X X 1 0 0

A3 =B3 A2 =B2 A1=B1 A0<B0 X X X 0 0 1

A3 =B3 A2 =B2 A1=B1 A0=B0 1 0 0 1 0 0

A3 =B3 A2 =B2 A1=B1 A0=B0 0 0 1 0 0 1

A3 =B3 A2 =B2 A1=B1 A0=B0 0 1 0 0 1 0

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Realization of 8 bit comparator using IC 7485 in cascaded mode:

VCC+5V VCC+5V

10 16 10 16
AO A0 A4 A0
A1 12 A1 A5 12 A1
13 13
A2 A2 A6 A2
A3 15 A3 A7 15 A3
9 B0 9 B0
B0 11 B4
B1 B1 B5
B2 14 B2 B6 11
1
B3 2 B3 7 B7 14 B1
A<B A<B B2
1 A<B A<B A<B
VCC+5V 3 A=B A=B 6 A=B
2 A=B
4 5 B3 A=B 7 A>B
A>B 8 A>B 3 A>B 8 A>B 6
7485 47485 5

Procedure:
1. Make connections as shown in the circuit diagram.
2. Apply inputs and verify the truth table.
Note: Apply inputs such that
i) A>B Ex. A=10010011, B=01111110
ii) A=B Ex. A=00010011, B=00010011, in this case output depends on
Cascading inputs of first stage
iii) A<B Ex. A=0010011, B=01111110

Result: 1-bit, 2-bit Magnitude comparator operation has been verified using logic gates.
4-bit comparator operation is verified using 7485 and also 8-bit comparison using 4-bit
comparators is performed.
Probable Viva Questions:
1. Design 1-bit magnitude comparator
2. State applications of magnitude comparator
3. What is the significance of cascading inputs in 7485.
4. What is the principle used in comparing multi bit number.

EXPT NO:7

AIM: a) Use of Decoder chip to drive LED display.

b) Priority Encoder.

COMPONENTS REQUIRED: IC Trainer kit, IC 7447 LED Decoder, IC74147 Decimal to

BCD priority encoder, LT312 LED Display and IC74148 octal to binary priority encoder.

Use of IC 7447 LED Decoder:

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VC C +5V
O /P fro m 7 4 4 7 to D e c im a l
BC D I / P
7 S e g m e n ts num ber
D C B A a b c d e f g d is p la y
0 0 0 0 0 0 0 0 0 0 1 0 A
7
1 1
16
A
13
12
7
6 a
B 2 B
2 11
0 0 0 1 1 0 0 1 1 1 1 1 C
6 4 C 10
4
f b
0 0 1 0 0 0 1 0 0 1 0 2
D 8 D
2
g
4
5 B I/R B O E
9
15
1
9 e c
0 0 1 1 0 0 0 ` 0 1 1 0 3 RBI F
0 1 0 0 1 0 0 1 1 0 0 4
3
LT 8 G
14 10
d
0 1 0 1 0 1 0 0 1 0 0 5 7447 LT312 LED

0 1 1 0 1 1 0 0 0 0 0 6 Display

0 1 1 1 0 0 0 1 1 1 1 7
1 0 0 0 0 0 0 0 0 0 0 8
1 0 0 1 0 0 0 1 1 0 0 9

Procedure:
1. Connections are made as shown in the circuit diagram.
2. Apply BCD inputs on DCBA lines using toggle switches and observe the output
on 7 segment LED display unit.
3. Observe the outputs for the remaining combinations of the 4 bit code.

Note:
LT (LAMP TEST)  This is used to check the segments of LED. If it is connected
to logic zero level, all the segments of the display connected to the decoder will be
ON. For normal decoding operation, this terminal is to be connected to logic 1 level.

RBI (RIPPLE BLANKING INPUT)  It is to be connected to logic 1 for normal

decoding operation. If it is connected to 0 level, the segment o/ps will generate data
for normal 7-segement decoding for all BCD i/ps except zero. Whenever the BCD i/ps
correspond to zero, the 7-segment display switches off. This is used for blanking out
leading zeroes in Multi-digit displays.

BI (BLANKING INPUT)  If it is connected to logic 0, the display is switched off

irrespective of BCD i/ps. This is used for conserving power in multiplexed displays.

RBO (RIPPLE BLANKING OUTPUT) The o/p, which is normally at logic

1goes to logic 0 during zero blanking interval. This is used for cascading purposes
and is connected to RBI of the succeeding stage.

Decimal to BCD priority encoder:

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One of the most commonly used device for a digital system is a set of ten switches, one for
each numeral between 0 and 9. these switches generate 1 or 0 logic levels in response to
turning them OFF or ON. When a particular number is to be fed to the digital circuit in BCD
code, the switch corresponding to that number is pressed. The IC version of this is shown in
the following figure and the truth table is also given. It has active low inputs and outputs. The
meaning of the word priority can be seen from the truth table. For example, if inputs 3 and 7
are LOW, the output will be corresponding to 7 which has the higher priority than 3, that is
highest numbered input has highest priority than the lower numbered inputs.

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Logic diagram of IC 74147 Decimal to BCD priority encoder: Truth table of

74147 Decimal to BCD priority encoder:

VCC+5V
INPUTS OUTPUTS
I1 I2 I3 I4 I5 I6 I7 I8 I9 D C B A
0 0 1 1 0
I1 11 16 x x x x x x x x
I2 12 X X X X X X X 0 1 0 1 1 1
I3 13
I4 A
74147

1 9 X X X X X X 0 1 1 1 0 0 0
I5 2 7 B
I6 3 6 C
I7 D X X X X X 0 1 1 1 1 0 0 1
4 14
I8 5
I9 X X X X 0 1 1 1 1 1 0 1 0
10
8
X X X 0 1 1 1 1 1 1 0 1 1

X X 0 1 1 1 1 1 1 1 1 0 0

X 0 1 1 1 1 1 1 1 1 1 0 1

0 1 1 1 1 1 1 1 1 1 1 1 0

1 1 1 1 1 1 1 1 1 1 1 1

Procedure:
1. Connections are made as shown in the circuit diagram.
2. Apply Decimal inputs using toggle switches and observe the output on LED unit.

Octal to Binary priority encoder:

The octal code is often used at the inputs of digital circuits that require manual entering of
long binary words. Priority encoder 74148 IC has been designed to achieve this operation. Its
logic diagram and truth table is as shown below. This circuit also has active low inputs and
outputs. The enable input and carry outputs are also active low and they are used to cascade
circuits to handle more inputs.

Logic diagram of IC 74148 Octal to Binary priority encoder: Truth table of IC

74148 Octal to Binary priority encoder:

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INPUTS OUTPUTS
Ei I0 I1 I2 I3 I4 I5 I6 I7 A2 A1 A0 Gs Eo

1 X X X X X X X X 1 1 1 1 1

0 1 1 1 1 1 1 1 1 1 1 1 1 0

0 X X X X X X X 0 0 0 0 0 1

0 X X X X X X 0 1 0 0 1 0 1

0 X X X X X 0 1 1 0 1 0 0 1

0 X X X X 0 1 1 1 0 1 1 0 1

0 X X X 0 1 1 1 1 1 0 0 0 1

0 X X 0 1 1 1 1 1 1 0 1 0 1

0 X 0 1 1 1 1 1 1 1 1 0 0 1

0 0 1 1 1 1 1 1 1 1 1 1 0 1

Procedure: Similar to that of Decimal to BCD encoder.

Probable Viva Questions:

1. Design BCD to 7-segment display decoder driver circuit.
2. Why the decoder associated with the name driver?
3. What are the different types of decoder drivers available?
4. Mention the different types of display devices available.
5. Give the constructional details of common anode seven segment display.
6. Is there any relation between the type of display and the decoder to be used?
7. What are BI, RBI, RBO, LT pins? State their applications.
8. Justify the output for invalid BCD input.
9. Define Priority encoder.
10. State practical application of priority encoders.
Dept. of TCE 46
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11. How to apply an input of 0 using 74147. What is pin15 of 74147?

12. What if significance of EI, EO, GS in 74148.
13. Is it possible to design a priority encoder with 0 having highest priority? Justify your
answer.
14. Design a decimal to BCD priority encoder.

Dept. of TCE 47
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C.M.R.I.T, Bangalore

EXPT NO: 8
AIM: Truth Table Verification of MS - JK FF, T – FF, D – FF
COMPONENTS REQUIRED: IC Trainer kit, IC7400 NAND gate, IC 7404 INVERTER and
IC7476 MS JK – FF.

Master Slave J-K Flip Flop Using NAND gates only:

PR

1 9 Qm 12 Qn
2 12 10 8 4 7410 11
J 7420 7420
13 11 7400 6 13
5

1
7400 3
2
CLOCK
9
3 1 7400 8 1
4 7420 6 2 7420 12 10 7410 3
K 5 13 2
Qm Qn

CR

Truth Table –1:

Inputs Output Truth Table – 2:
Operation Performed
Clk cr pr Q
1 Inputs
1 1 QOutputNormal FF (table – 2)
Comments
x
CLK J 0 1 K 0Qn+1 FF cleared (Reset)
x0 1X 0 X 1 Qn FF preset
No change(Set)
0 0 Qn No change
0 1 0 Reset
1 0 1 Set
1 1 Qn Toggle

Note: Keep pr = 1 and cr = 1 for verifying the Truth Tables of JKMS FF, T and D FFs

Dept. of TCE 48
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Realization of T- Flip Flop using MS JK – FF:

PR

T
1 9 Qm 12 Qn
2 12 10 8 4 7410 11
13 7420 11 7410 6 13
5 7400

1
7400 3
2
CLOCK
9
3 1 7400 8 1
4 6 2 12 10 3
5
7420
13
7410  2
7410

Qm Qn

CR

Truth Table – T Flip flop:

Input Output
Comments
CLK T Qn+1
0 X Qn No change
0 Qn No change
1 Qn Toggles

Dept. of TCE 49
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Realization of D- Flip Flop using MS JK – FF:

D

7404
PR
2

1
2 12
9
10 8
Qm 4
12
11
Q
7420 7410 7410
14 11 6 13
7400
5

1
3
7400
2
CLOCK
9
3 1 8 1
4 6 2 12 10 7400 3
7420 7410 7410
5 13 2

Qm Qn

CR

Truth Table – D Flip flop:

Input Output
Comments
CLK D Qn+1
0 X Qn No change
Data
0 0
Transferred
Data
1 1
Transferred

Truth Table Verification of MS - JK FF, T – FF, D – FF using IC 7476:

Master - Slave - JK FLIPFLOP T FLIP - FLOP using MS-JK FLIPFLOP
(using 7476IC)

LOGIC 1 LOGIC 1

2
T- input
2

J - input 4 PR Q 15 4 15
J Q J Q Q
PR

1 1
CLOCK CLK CLK
16 CL 14 CLOCK 16 14
K Q K Q Q
CL

K - input
Q
3 7476 7476
3

LOGIC 1 LOGIC 1

Dept. of TCE 50
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D FLIP - FLOP using MS-JK FLIPFLOP

LOGIC 1

D - input

2
4 15
J Q Q

PR
CLOCK 1
CLK
16 14
1

K Q Q

CL
7404 7476

3
LOGIC 1
2

Probable Viva Questions:

1. Distinguish between the combinational & sequential circuits.

2. What are the two types of sequential circuits ?
3. What is a Flip-Flop & Distinguish between the flip_flop & Latch.
4. A Flip_Flop is a Divide By _____ Counter.
5. Can we use SR Flip_Flop as a D Flip_Flop ?
6. What is a Race condition ?
7. What is a Race_around condition ?

EXPT NO: 9

Dept. of TCE 51
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AIM: REALIZATION OF 3 – BIT COUNTERS AS A SEQUENTIAL CIRCUIT AND MOD - N

COUNTER DESIGN (7476,7490,74192,74193)

COMPONENTS REQUIRED: IC Trainer kit, IC7476 MSJK FF, IC7400 NAND gates,
IC7490 Decade counter, IC7493 Binary counter, IC74192 Decade Up-down counter and
IC74193 Binary Up-down counter.
MOD 8 UP COUNTER:
Counting Sequence:
Number of Flip Flop Outputs
Clock pulse
Q2 Q1 Q0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0

Excitation table:
Present Next
FlipFlops States
State State
Present Next
J K Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
State State
0 0 0 0 0 1 0 X 0 X 1 X
0 0 0 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 1 X
0 1 0 0 1 1 0 X X 0 1 X
1 0 X 1
0 1 1 1 0 0 1 X X 1 X 1
1 1 X 0 1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 0 0 0 X 1 X 1 X 1

K – Map for J0: K – Map for K0: K – Map for J1:

J0 = 1 K0 = 1 J1 = Q0

Q1Q0 Q1Q0 Q1Q0

Q2 Q2 00 01 11 10 Q2
00 01 11 10 00 01 11 10
0 1 X X 1 0 X 1 1 X 0 0 1 X X

1 1 X X 1 1 X 1 1 X
1 0 1 X X

Dept. of TCE 52
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K – Map for K1: K – Map for J2: K – Map for K2:

K1 = Q0 J2 = Q1Q0 K2 = Q1Q0

Q1Q0 Q1Q0 Q1Q0

Q2 00 01 11 10 Q2 Q2
00 01 11 10 00 01 11 10
0 X X 1 0 0
0 0 0 1 0 X X X X

1 X X 1 0
X X X X 1 0 0 1 0
1
Exercise:

 Design mod-5 Binary Up Counter.

 Design mod-3 Binary Down Counter.

Dept. of TCE 53
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( II )STUDY OF DECADE COUNTER IC 7490:

IC 7490 is a Divide-by 10 counter using 4 Master slave JK flipflops. It contains a Divide-by 2

and Divide-by 5 counters, which can be cascaded to give a Divide-by 10 counter.

Block Diagram
OUTPUTS

Q0 Q1 Q2 Q3

FF1 FF2 FF3

CLOCK A FF0
MOD-5
MOD-2
COUNTER
COUNTER

CLOCK B MR MR MS MS
RESET INPUTS SET INPUTS

Procedure for BCD counter using IC 7490:

 MS1, MS2, MR1and MR2 inputs are connected to GND (Active HIGH I/O’s).
 Clock input is given to Clock A
 Output Q0 and Clock B are shorted so that it acts as Divide-by 10 counter with
BCD count sequence.
 Verify the truth table and observe the waveforms on CRO.
Realization of MOD-6 Counter using 7490:

Clock 1 2 3 4 5 6
Clock I/P Input
5
6
4

7400 Q0
14
7

0 1 0 1 0 1 0
3
B

A
R9(2)

R9(1)

R0(2)

R0(1)

Q1
7490 0 0 1 1 0 0 0
7400
QD

QC

QB

QA

Q2
1 2 0 0 0 0 1 1 0
12
11

Q3
0 0 0 0 0 0 0
QD QC QB QA (LSB)

Truth Table:

Dept. of TCE 54
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Input
Q3 Q2 Q1 Q0
pulses
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 0 0 0

( III ) STUDY OF IC 7493 BINARY RIPPLE COUNTER:

IC 7493 is a Divide-by16 Asynchronous counter using 4 Master slave JK flipflops. It
contains a Divide-by 2 and Divide-by 8 counters which can be cascaded to give a
Divide-by 16 counter.

Block Diagram
OUTPUTS

Q0 Q1 Q2 Q3

FF1 FF2 FF3

CLOCK A FF0
MOD-8
MOD-2
COUNTER
COUNTER

CLOCK B MR MR
RESET INPUTS

Procedure for Binary counter using 7493:

 MR1 and MR2 are connected to ground (Active High)

 Clock input is given to Clock A
 Output Q0 and Clock B are shorted so that it acts as Divide-by 16 counter.
 Verify the truth table and observe the waveforms on CRO.

Dept. of TCE 55
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Realization of MOD-16 Binary counter using IC 7493:

Clock I/P Truth Table

Input
Q3 Q2 Q1 Q0
pulses
0 0 0 0 0

14

12
2

1
B 1 0 0 0 1
A
MR1

MR2

10 5 7410
2 0 0 1 0
GND VCC
7493 VCC
3 0 0 1 1
4 0 1 0 0
QD

QC

QB

QA

13
1
2
5 0 1 0 1
8

12
11

1
6 0 1 1 0
13
2 12
7 0 1 1 1
QD QC QB QA (LSB) 7410 8 1 0 0 0
9 1 0 0 1
Realization of MOD-14 Binary counter using IC 7493: 10 1 0 1 0
11 1 0 1 1
Clock I/P 12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
12
14
2

16 0 0 0 0
B

A
MR1

MR2

10
GND VCC
5 7410
7493 VCC
QD

QC

QB

QA

13
1
2
8

12
11

1
2 12
13

QD QC QB QA (LSB) 7410

Input
Q3 Q2 Q1 Q0
Truth Table: pulses
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 0 0 0 0

Dept. of TCE 56
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( IV ) Study of IC 74192 Decade Up – Down Synchronous Counter:

IC74192 is a synchronous 4 - bit decade up–down counter which can be cleared and preset to
any count.

( a ) Use of 74192 as Mod-10 Counter (Up– Down):

Vcc Clock Clock D C B A

(LSB) Function Table:

Load Clear Clk-up Clk-Down Mode

X 1 X X Reset to Zero
14

10

15
11

Vcc
4

1 0 1 Up Count
B

A
D

C
DN

UP
CLR

LOAD

8 1 0 1 16 Down Count
GND VCC
0 074192 X X Preset
1 0 1 1 Stop Count
CO

QD

QC
BO

QB

QA
7

3
13

12

Borrow Carry QD QC QB QA (LSB)

For Up Count: Give Clock only to Clock Up input (pin 5). Make Clock down input (pin 4)
logic HIGH. If the outputs QD to QA counts from 1001 to 0000, then carry is LOW. Else
carry is HIGH.

For Down Count: Give Clock only to Clock Down input (pin4). Make Clock up input (pin
5) logic HIGH. If the outputs QD to QA counts from 0000 to 1001, then borrow is LOW.
Else borrow is HIGH.

Note: The carry and the borrow outputs are normally at logic HIGH.
Carry and borrow are mainly used for cascading the counters.

Dept. of TCE 57
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( b ) Use of IC 74192 as Pre-settable Up counter:

b) To count from 8 to 5:

PRESET TO 5
Clock Clock 0 1 0 1 (LSB)

4 5
6 7420

2
14

15
10
11
Vcc

1
4

1
B

A
D

C
DN

UP
CLR

LOAD

8 16
GND VCC 2 4 6 8
74192

7404 7404 7404 7404

CO

QD

QC
BO

QB

QA
7

3
13

12

1 3 5 9

Borrow Carry
QD QC QB QA (LSB)

( c ) Use of IC 74192 as Pre-settable Down counter:

To count from 5 to 9:
PRESET TO 8
Clock Clock 1 0 0 0 (LSB)
4 5

6 7420
2
14

10

15
11

Vcc
4

1
B

A
D

C
DN

UP
CLR

LOAD

8 16
GND VCC 2 4 6
74192

7404 7404 7404

CO

QD

QC
BO

QA
QB
7

3
13

12

1 3 5

Borrow Carry
QD QC QB QA (LSB)

Dept. of TCE 58
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( V ) Study of IC 74193 Binary Up–Down Synchronous counter:

IC74193 is a Synchronous 4 – bit binary up–down Counter (MOD-16) which

can be cleared and preset to any count. The functional table and the pin
configurations is the same as IC74192.
Vcc Clock Clock D C B A
(LSB)
Exercise:

a)
14

10

15
11

Vcc
4

Design 4 to 15 up counter using IC74193

B

A
D

C
DN

UP

b)
CLR

LOAD

8 16
GND
74193
VCC Design 12 to 3 down counter using IC74193
c)
Design 15 to 6 down counter using IC74193
CO

QD

QC
BO

QB

QA
7

3
13

12

Borrow Carry QD QC QB QA (LSB)

Probable Viva Questions:

a) Define MOD of a counter ?

b) What is a difference between a Synchronous & Asynchronous Counters ?
c) Name the IC’s which are used as a Synchronous Counters ?
d) Define Triggering in the Counters ?

Dept. of TCE 59
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C.M.R.I.T, Bangalore

EXPT NO: 10

AIM: STUDY OF SHIFT REGISTER IC 7495 FOR SISO, SIPO, PISO, PIPO, SHIFT
RIGHT AND SHIFT LEFT OPERATIONS.

COMPONENTS REQUIRED: IC 7495

STUDY OF SHIFT REGISTER IC 7495:
VCC

Pin
14
1
SER
DS details
VCC

2
A
D3
3 QA
13
Q3 of
B
D2
4 QB
12
Q2 7495:
D1 C 7495 11
5 QC Q1
D
D0
QD
10
Q0 
DS serial input data to be
6
M MODE right shifted
CLOCK-LEFT 9
CLK1-L
 D3, D2, D1, D0 parallel data
CLOCK - RIGHT 8
CLK2-R
inputs to be loaded in to the
GND

shift reg.
7

 M - Mode control.
M = 1 for loading parallel data and
to enable Clock 2.
M = 0 for enabling clock 1.
 Clock 2 for loading parallel input data and for shift left of data.
 Clock 1 for right shift of data.
 Q3, Q2, Q1, Q0 parallel out put of the shift register.

Shift Right operation:

Serial input parallel output (SIPO) operation:

EX: To perform SIPO operation, consider a 4 bit data 1101.

 Mode control is made 0
 Clock 1 (pin 9) of 7495 is connected to the Pulser (Mono shot).
 The serial input to be converted to parallel output is given to serial input DS
(pin 1).
 After 4 clock pulses the serial input data appears in parallel form as Q3, Q2,
Q1, and Q0 as shown.

Clock Time Serial input data Outputs

CLK-1L DS Q3 Q2 Q1 Q0
1 T0 1(LSB) 1
2 T1 0 0 1
3 T2 1 1 0 1
4 T3 1 1 1 0 1
Parallel
data output after 4 clock pulses.
Dept. of TCE 60
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Serial input – serial output (SISO) operation:

 Mode control is made LOW.

 Clock 1 (pin 9) of 7495 is connected to the Pulser (Mono shot).
 The serial input to be converted to serial output is given to serial input DS (pin
1).
 After 4 clock pulses the serial input data appears in Parallel form as Q3, Q2,
Q1, Q0 as shown.
 The next 4 clock pulses move the data out of the shift register, serially at Q0.
Clock Time Serial input Outputs
CLK –1L data DS Q3 Q2 Q1 Q0
1 T0 1(LSB) 1
2 T1 0 0 1
3 T2 1 1 0 1
4 T3 1 1 1 0 1
5 T4 1 1 0
6 T5 1 1
7 T6 1

Serial data outputs after 7 clock

pulses at Q0.
Parallel input parallel output (PIPO) operation:

 Mode control is made HIGH.

 The parallel inputs to be loaded in to the Shift register are given to D3, D2,
D1, D0 inputs.
 Clock 2 (pin 8) is pulsed once. Now D3, D2, D1, D0 parallel inputs appears on
Q3, Q2, Q1, Q0 lines.

Dept. of TCE 61
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Parallel input serial output (PISO) operation:

 Mode control is made 1

 The parallel inputs to be loaded in to the Shift register are given to D3, D2,
D1, D0 inputs.
 Clock 2 (pin 8) is pulsed once. Now D3, D2, D1, D0 parallel inputs appears on
Q3, Q2, Q1, Q0 lines.
 CLK 1 (pin 9) is connected to the pulser.
 Mode control is made 0
 With each clock pulse, data shifts right by 1 bit and hence after 4 clock pulses,
parallel input data is converted into serial output data at Q0.

Clock Time Outputs

Q3 Q2 Q1 Q0
CLK 2 1 1 0 1 Shift
T0
register loaded
CLK 1 T1 1 1 0
with parallel data
T2 1 1
T3 1

Serial data output after 4 clock pulses at Q0.

Shift Left Operation

 Short Q0 and D1 input, Q1 and D2 input Q2 and D3 inputs.
 Mode control is made HIGH.
 Serial input data is entered at D0 input.
 CLK2 is pulsed and each time when it is pulsed, the shift register contents are left
shifted once as shown. Output is taken at Q3.

Serial Outputs
Clock Time input
D0 Q3 Q2 Q1 Q0
CLK2 T0 1(LSB 1
T1 0 1 0
T2 1 1 0 1
T3 1 1 0 1 1

Exercise: Verify the data 1010 in all the modes

Probable Viva Questions:
a) What is a difference between Counters & Shift registers ?
b) What is a Universal Shift registers ?
c) How many Flip_flops are there in the IC-7495 ?
d) What is a Bidirectional Shift registers ?

Dept. of TCE 62
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C.M.R.I.T, Bangalore

EXPT NO: 11

Aim: WIRING AND TESTING of Ring Counter / johnson Counter using

IC7495.

COMPONENTS REQUIRED: IC trainer kit, IC 7495 Universal Shift Register &IC

7404 Inverter gate.

Realization of Ring Counter using IC7495:


DS 1
SER 
D3 2
A 13 
QA
D2 3
B 12 
QB
D1 4
C
7495 11 
QC
D0 5
D 10 
QD
TOGGLE SWITCH 6 
MODE
CLOCK 9

CLK1-L
8

CLK2-R


 If the serial output Q0 of the shift register is connected back to the serial input
DS, then an injected pulse will keep circulating. This is known as ring counter.
 Mode control is made 1.
 Parallel inputs 0001 are given to D3D2D1D0 inputs.
 CLK 2 is pulsed once. Now D3D2D1D0 parallel inputs appear on QA, QB, QC, QD
lines.
 CLK 1 is connected to the pulser.
 Now mode control is made LOW.
 When clock pulses are applied, this ‘1’ circulates around the circuit as shown.
 Observe the output waveforms QA, QB, QC,QD on CRO.

Dept. of TCE 63
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Outputs
Clock Time
QA QB QC QD
CLK2 T0 0 0 0 1
CLK1 T1 1 0 0 0
T2 0 1 0 0
T3 0 0 1 0
T4 0 0 0 1

Realization of johnson Counter using ic7495:

 If the serial output Q0 of the shift register is connected back to the serial input DS
through an inverter as shown we get a Johnson counter.
 CLK 1 is connected to the pulser.
 Now mode control is made LOW.
 When clock pulses are applied, we get the output as shown in truth table.
 Observe the output waveforms Qd, Qc, Qb, Qa on CRO.

2 1

7404

1
2 SER 13
3 A QA 12
4 B QB 11
5 C QC 10
D QD
6
9 MODE
CLK CLK1-L
8
CLK2-R

7495

clk Qa Qb Qc Qd

0 0 0 0 0

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

Dept. of TCE 64
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Probable Viva Questions:

a) Ring Counter is generally called MOD -------- Counter ?
b) How many Flip_flops are present in the 7495 IC ?
c) How the Shift Register Counters are different from that of normal binary
counters ?
d) What is the other name for the Johnson Counter ? It is generally called MOD
------- Counter ?

Dept. of TCE 65
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EXPT NO: 12

Aim: WIRING AND TESTING OF Sequence Generator using Ic7495

COMPONENTS REQUIRED:IC TRAINER KIT,IC 7495, IC7486 EXOR gate and

IC7410 NAND gate.

A circuit which generates a prescribed sequence of bits in synchronism with a clock is

called as sequence generator. The output Y of the next state decoder is function of Qn-1,
Qn-2… Q1, Q0. This system similar to ring counter.
Y = Q0 or a twisted ring counter (Y = Q0bar) which are special cases of sequence
generator.

In order to build a sequence generator, capable of generating a sequence of length S, it

is necessary to use a minimum n number of Flip Flops where n satisfies the condition, S
<= 2n- 1.

Example1:
Design a sequence generator to generate the sequence S = …100010011010111…..
Here length S = 15. Hence we require at least 4 Flip Flops.

7486
2
3
1

1
SER
D3 2
A 13
QA Q3
D2 3
B 12
QB Q2
D1 4 7495
C 11
QC Q1
D0 5
D 10
QD Q0
TOGGLE SWITCH 6
MODE
CLOCK 9
CLK1-L
8
CLK2-R

Dept. of TCE 66
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Function table:
Serial inputs Y K- MAP for Y:
Clock Q3 Q2 Q1 Q0 =
f(Q0Q1Q2Q3)
Q1Q0
1 1 1 1 1 0
Q3Q2 00 01 11 10
2 0 1 1 1 0
3 0 0 1 1 0 00 X 1 0 1
4 0 0 0 1 1
5 1 0 0 0 0 01 0 1 0 1
6 0 1 0 0 0
7 0 0 1 0 1 11 0 1 0 1
8 1 0 0 1 1
9 1 1 0 0 0 0 1 0 1
10
10 0 1 1 0 1
11 1 0 1 1 0
12 0 1 0 1 1
13 1 0 1 0 1
14 1 1 0 1 1 Expression for Y:
15 1 1 1 0 1
1 1 1 1 1 0
Y  Q1Q 0  Q1Q 0
2 0 1 1 1 0 Y  Q1  Q 0
3 0 0 1 1 0
.
.
15

Dept. of TCE 67
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Example 2:
Design a sequence generator to generate the sequence S = … 1101011
Here the length of the sequence is S = 7, Hence we require at least 3 flip flops, We can
observe that here all the states are not distinct (i.e., the states are repeating) Therefore, N
= 3 Flip Flops are not sufficient, We assume N = 4 and prepare the truth table for the
sequence generator. Starting state Q3, Q2, Q1, Q0 is 1110.

7410

1 2 13
12

1
SER
D3 2
A 13
QA Q3
D2 3
B 12
QB Q2
D1 4 7495
C 11
QC Q1
D0 5
D 10
QD Q0
TOGGLE SWITCH 6
MODE
CLOCK 9
CLK1-L
8
CLK2-R

Serial inputs Y
Clock Q3 Q2 Q1 Q0 =
f(Q0Q1Q2Q3)
1 1 1 1 0 1
2 1 1 1 1 0
3 0 1 1 1 1
4 1 0 1 1 0
5 0 1 0 1 1
6 1 0 1 0 1
7 1 1 0 1 1

K- MAP for Y Q1Q0

Q3Q2 00 01 11 10
00 X X X X

01 X 1 1 X
Expression for Y:
11 X 1 0 1
Y  Q3  Q1  Q 0
Y  Q3Q1Q 0
10 X X 0 1

Dept. of TCE 68
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APPENDIX 1

AND GATE IC 7408 NOT GATE IC 7404

IC 7408 V
C
VCC
1 14
14 VCC
13 1
2
12 2 13
3
11 3 12
4
10 4 11
5
9 5 10
6
7 6 9
8
GND GND 7 8
NAND GATE (TWO INPUT) IC 7400 EXOR GATE IC7486

IC 7400 IC 7486

1 14 VCC
1 14 VCC
13
2
2
12 13
3 3 12
11
4 4
10 11
5
5 10
9 9
6 6
7 8 GND
GND 7 8

Dept. of TCE 69
 LD LAB
C.M.R.I.T, Bangalore

OR GATE 1
14 VCC
2
IC 7432
13
3 12
4
11
5
6 10
9
7
GN 8
D

NOR GATE IC7402

1 14 VCC
IC 7402

2 13
3 12
4
11
5 10

6 9

GN 7 8
D

NAND GATE (FOUR INPUT) 1

14 VCC
IC 7420 2
3 13
12
4
11
5
6 10
9
7
GN 8
D

Dept. of TCE 70
 LD LAB
C.M.R.I.T, Bangalore

AND GATE (THREE INPUT)

1
2 14 VCC
IC 7411
3 13
4 12

5 11
10

6 9

GN 8
7
D

NAND GATE (THREE INPUT) 1 14

VCC
2 13
IC 7410 3

4 12

5 11
10
6 9
7 8
GND

1 16
B3 VCC
2 15
A<B_IN A3
7476
3 14
2

A=B_IN B2
4 13
4 15 A>B_IN A2
PRE

J Q
5 7485 12
1 A>B A1
CLK
6 11
16 14 A=B B1
K Q
7 10
CLR

A<B A0
8 9
GND B0
3

4 Bit Ripple Counter Divide by 10 Counter

Dept. of TCE 71
 LD LAB
C.M.R.I.T, Bangalore

1 14
1 14 CKB CKA
I/P B I/PA
2 13
2 13
R1 NC R01 NC
3 12 3 12
R2 QA R02 QA
4
NC
7493
QD
11 4 11
NC 7490 QD
5 10 5 10
VCC GND
VCC GND
6 9
NC QB 6 9
R91 QB
7 8
NC QC 7 8
R92 QC

PIN DETAILS of LTS 542

1 Segment E
10 9 8 7 6 2 Segment D
6 3 Common Cathode
a
4 Segment C
b 5 DIP (Dual In Package)
f g 6 Segment B
7 Segment A
e c 8 Common Cathode
9 Segment F
d 10 Segment G

1 2 3 4 5
5

1 4 VCC 16
2 5 7 NC 15
3 6 4 D 14
4 7 1 3 13
5 8 4 2 12
6 C 7 1 11
7 B 9 10
8 GND A 9

Dept. of TCE 72
 LD LAB
C.M.R.I.T, Bangalore

4 Bit Decade Up-Down Counter

VCC

GND
P1 VCC
1 16

8
Q1 P0 P0 Q0

16
2 15 15 3
Q0 CLR P1 Q1
3 14 1 2
Clk-DN 74192 Borrow P2 Q2
4 13 10 6
74193
P3 Q3
Clk-UP Carry 9 7
5 12
Clk-UP Carry
Q2 Load 5 12
6 11
Clk-DN Borrow
Q3 P2 4 13
7 10

14

11
GND P3
8 9

Load
CLR
Pin details of 74192 IC Shift Register

14
6

VCC
1 MODE
9 SER
8 CLK1
2 13
3 A QA
B
7495 QB
12
4 11
5 C QC 10
D QD

7 GND
U1
16

3
I3A
VCC

4
I2A
MUX1
5 7
I1A ZA
1
INB OUTE
9 1
A4 SUM1
9 4-1
6
I0A
2 10 2 10
INC OUTD SUM3 A1 1
EA
3 11 3 11
LT OUTC A3 B1
10
74153
4 12 5 12 I0B
BI/RBO OUTB VCC GND
7483A
7446

5 13 4 13 11 9
RBI OUTA B3 C0 I1B ZB
6 14 6 14 12 MUX2
IND OUTG SUM2 C4 I2B
7 15 7 15 13 4-1
INA OUTF B2 SUM4 I3B
8 16 8 16 15
GND VCC A2 B4 EB
GND
S0

S1
14

Dept. of TCE 73
 LD LAB
C.M.R.I.T, Bangalore

VIVA-VOCE QUESTIONS

1. Mention the difference between Analog and Digital Signals. Give Ex.
2. What is an Analog circuit and digital circuit. Give Ex.
3. What is positive logic and negative logic?
4. What is a Gate? Name different types.
5. Give Ex. For Basic Gates.
6. Why NAND and NOR gates are called universal gates?
7. Mention the merits of using Digital Systems.
8. What is truth table?
9. Name different types of Logic families.
10. What is the difference between Algebra and Boolean algebra?
11. State De-Morgan’s theorems.
12. For a gate with N inputs, how many combinations of inputs are possible?
13. What is Inhibit or disable condition of a gate? How it is achieved.
14. Why Semiconductor devices are preferred for making digital switches instead of relays
and mechanical switches?
15. What are the advantages of ICs over discrete circuits?
16. Why Schottky diodes are preferred than PN junction diodes in digital circuits
17. What are the differences between Linear and Digital ICs?
18. What are the methods to represent negative numbers in digital systems
19. Why Binary number system is used in digital systems
20. Define the terms Fan out, Fan in, Propagation delay, Noise margin w.r.t logic gates.
21. Define the term figure of merit of a digital IC.
22. What is tri-state logic?
23. Name the different types of TTL ICs available
24. Which type of Logic family is faster?
25. Give the typical values of Fan in, Fan out, Propagation delay, Power dissipation in TTL
gates.
26. Explain the meaning the symbol used in 74 series TTL ICs
27. What is half adder and full adder. Why it is called so?
28. What are the applications of half adder and full adder?
29. Why subtractor IC is not available?
30. What is meant by a 7 segment LED display?
31. Which are the different types of LED displays?
32. Mention the common anode and common cathode display numbers?
33. Mention the different types of displays?
34. What are the difference between LED display and LCD display?
35. Explain the importance of BI/RBO, RBI and LT in 7447 decoder chip
36. What do you mean by dp in the display?
37. What do you mean by decoder/driver?
38. Mention the applications of LED and LCD displays
39. What is the difference between MUX and Encoder?
40. What is the type of display device used in your calculator?
41. What is the difference between Demux and decoder?
42. Why 2:4 decoder is sometimes called as a 1-of-4 decoder?
43. What is multiplexer?
44. What is de multiplexer?
45. Is the display device used in a digital wristwatch is LED or LCD? Why?
46. Mention the application for MUX and DEMUX?

Dept. of TCE 74
 LD LAB
C.M.R.I.T, Bangalore

47. What are combinational circuits? Give examples?

48. What is sequential circuit? Give examples?
49. Differentiate between combinational circuits and sequential circuits?
50. What is a flip-flop?
51. What is a latch?
52. What is meant by race around condition in flip-flop?
53. Mention the different types of flip-flops?
54. What are the expansions for R-S, D, T, J-K and MS J-K flip flop?
55. Mention the applications for flip-flops?
56. Explain the functions of preset and clear inputs in flip-flops?
57. What is a counter?
58. Which counter is called a ripple counter and why it is called like that?
59. What are the differences between synchronous and asynchronous counters?
60. Which counter has a more propagation delay?
61. What is a Glitch? How it can be removed?
62. What is lockout in counter
63. What is shift register?
64. Mention some applications of shift registers?
65. What is meant by “modulus” of a counter?
66. What do you mean by state table, Excitation table and transition table?
67. What is Excess-3 code?
68. What is BCD code?
69. Write the transistor circuit diagram for R-S flip-flop?
70. Which multivibrator is called flip-flop?
71. Write the transistor version circuit diagram for TTL NAND gate IC.

72. Write the transistor version circuit diagram for TTL NOT gate IC
73. Write the internal block diagram for four-bit full adder chip?
74. Which code is called reflected or cyclic or unit-distance code?
75. Which code is called self-complementing code?
76. Where we use Excess-3 codes?
77. Why code conversion is required?
78. What is Ring counter?
79. What is Johnson counter?
80. Which counter is called twisted ring counter or switch-tail counter or moebious counter?
81. Which codes using in the k-map to represent the blocks?
82. Mention the application for Ring counter and Johnson counters?
83. State distributive law, commutative law and associate law with examples?
84. What is don’t care condition means?
85. How many states are possible in 4-bit ring counter and 4 bit Johnson counters?
86. What is o/p frequency of 4-bit ring counter and 4 bit Johnson counters?
87. Where do we use down counter?
88. Where do we use counters?
89. What is strobe?
90. What are the various methods used for triggering flip-flops?
91. What is meant by active low and active high?
92. Differentiate between S-R, J-K and M/S J-K flip-flops?
93. Differentiate T Flip flop and D flip-flop
94. Write down the internal block diagram for IC 7490?
95. How do you represent –5 and +5 in binary form?

Dept. of TCE 75
 LD LAB
C.M.R.I.T, Bangalore

96. Which codes are called weighted codes and which codes are called weighted codes?
97. What are pre-settable counters? What are the applications?
98. What is the use of Tcu and Tcd pins in IC 74193?
99. What is a multivibrator circuit? Classify.
100. Why IC 555 is called timer chip.
101. Mention the features of IC 555
102. What is the use of RESET pin in IC 555?
103. Why a diode is connected in parallel with R B in symmetrical Astable multivibrator
circuit.
104. Can we make RA = 0 for getting 50% duty cycle in Astable mode? Justify your answer.
105. Why a 0.01f capacitor is connected at pin 5 of IC 555? Can we replace with any
other value?
106. Mention some of the applications of IC 555 used as Astable and Monostable
multivibrator circuits.
107. What are the applications of Magnitude comparators?
108. What is the significance of cascading inputs?
109. Why cascading inputs A=B is made 1, A<B and A>B is made 0
110. What is a shift register? Classify.
111. Name different modes of operations of shift registers.
112. What is sequence generator? Name different types. Mention the applications of
sequence generators.
113. Write the block diagram of sequence generator Ckt.
114. What is priority encoder? Mention the applications of priority encoder.
115. What is the difference between encoder and priority encoder?

Dept. of TCE 76