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# 1.

## Explain the advantages and disadvantages of NAND ROMs as compared to NOR

ROMs.
2. Sketch a dot diagram for a 2-input XOR using ROM.
3. Sketch a dot diagram for a 2-input XOR using PLA.

4. Implement the 8 input boolean function Z=AB+CD(E+F)+GH using CMOS and Domino CMOS logic

5. Sketch a 3-input XOR functions using each of the following circuit techniques:
a) static CMOS b) pseudo-nMOS c) CPL
6. Repeat the above question (5) for a 2-input NAND gate.

## 9. (a) Design a 2-input XOR gate using a 4:1 MUX.

(b) Design a 2-input XNOR gate using a 4:1 MUX.
(c) A full adder accepts inputs a,b, and c and calculates the sum bit
s = a xor b xor c
Use your MUX-based gates to design a circuit with this output.

## using the smallest number of transistors.

11. Design a CMOS circuit for the OAI expression

## using series-parallel logic. The objective is to minimize the transistor count.

13. Design the 4:1 multiplexer circuit using TG switches.
14. Design a 4:1 MUX using three 2:1 TG multiplexers.
15. (i) Consider a complex CMOS logic gate that implements the function

Design the logic circuit and size with βn= βp is used as a reference.

## is needed in a control network.

(a) Design the logic circuit.
(b) Find the device sizes in the gate if we choose to equalize the nFET and pFET resistances.
17. Design a layout diagram for two input pMOS NOR gate.
18. Design a digital BiCMOS circuit that implements the function

19. Consider a CMOS process that is characterized by VDD = 5 V, Vtn = 0.7 V, Vtp = -0.85 V, kn’ = 120
µA/V2 , kp’ = 55 µA/V2. A pseudo-nMOS inverter is designed using an nFET aspect ratio of 4.
(a) Find the pFET aspect ratio needed to achieve VOL = 0.3 V.
(b) Suppose instead that we select a pFET aspect ratio of (W/L)p = 3. Find VOL for this case.

20. Draw the pseudo-nMOS circuits that provide the following logic operations.

## 21. Consider the dual expressions

Which form (AOI or OAI) would provide the best performance when built using pseudo-nMOS design?

## 22. Design a clocked CMOS circuit that implements the function

23. Draw the circuit diagram for a dynamic logic gate that has an output of

## using the smallest number of transistors.

24. Draw the circuit diagram for a dynamic logic gate that has an output of
25. Design a FET-programmable ROM that contains the following data.
0 1011
1 1101
2 1110
3 1111
4 0001
5 1000
6 1100
7 0101

26. Draw the circuits for pi and gi needed for a 4-bit CLA in each of the following CMOS technologies:
(a) Static CMOS ; (b) Domino CMOS ; and (c) TG logic.
27. Construct the CMOS circuits for the CLA bits using series-parallel nFET-pFET
structuring.

28. Design a dynamic CMOS AND-OR PLA using NOR gates as a basis. Design the circuitry such that
inputs are a,b,c and outputs are

29. Design a dynamic CMOS NOR-NOR PLA that has a,b,c as inputs and outputs the POS functions.
30. Sketch a transistor-level (use only nmos and pmos transistors) schematics for the following logic
functions. You may assume you have both true and complementary versions of the inputs available.
A 2:4 decoder defined by

## 31. Sketch a layout diagram for a CMOS 4-input NOR gate.

32. Design a layout diagram for two input pMOS NOR gate.

33. Consider the design of a CMOS compound OR-AND-INVERT (OAI) gate computing

.
a) Sketch a transistor-level schematic
b) Sketch a layout diagram

## 36. Sketch a Domino CMOS gate that implements the function

37. Sketch a 3-input XNOR functions using each of the following circuit techniques:
a) static CMOS b) pseudo-nMOS c) CPL

38. Draw the Static CMOS circuits that provide the following logic operations.

## 40. How multiplication can be done using Wallace tree?

41. Write short notes on
a) Gallium Arsenide technology
b) GaAs devices
42. Explain how the MESFET act as a inverter.
43. Write short notes on : Clocking strategies, latches and registers.
44. How the Latch up is encountered in MOSFET fabrication and what are the steps taken to prevent it,
explain in device and circuit level?

## 45. Draw the 2-input BiCMOS XOR gate.

46. Compare CMOS, Bipolar, and GaAs technologies.
47. Discuss the charge sharing problem in CMOS dynamic logic circuit and how it can be eliminated?

## 48. Write short notes on Layout design rules.

49. Compare ASIC vs FPGA.
50. Design a layout diagram for the PMOS logic shown below Y = ( A + B ).C

51. Write short notes on : Design rule checkers and layout extractions
52. Explain clocked CMOS logic, domino logic and n-p CMOS logic.
53. Describe the operation of SRAM in read and write mode?

54. Design a layout diagram for the PMOS logic shown below Y = ( A + B ).C
55. Design a layout diagram for two input pMOS NOR gate.
56. How the output voltages vary with time in NMOS pass transistor logic during Logic ‘0’ and Logic’1’
transfer?

## 57. Implement Full Subtractor using Domino logic.

58. Implement Single-bit Full adder using TG logic.
59. Implement 4-bit x 4-bit ROM array (NOR based).

## 60. Write short notes on : Semiconductor Memories.

61. Explain clocked CMOS logic, domino logic and n-p CMOS logic.

## 62. Compare CMOS, Bipolar and GaAs technologies.

64. Compare Static CMOS, pseudo nMOS, Dynamic CMOS.

## 65. Write short notes on : Field Programmable Gate Arrays.

66. Write short notes on : CMOS layout lamda based design rules.
67. Compare FPGA Vs ASIC Design styles.

68. Write short notes on : Ground rules for successful VLSI Design.
69. Write short notes on : Design Rule Checkers and Simulators.
70. Draw the Transmission gate mux and its layout?
71. Design and explain 4X4 Barrel shifter, 4X4 NAND based ROM?
72. Design an AND – OR PLA that has the following outputs
F1= mo+m1+m6
F2 =m3+m4+m7
73. Design the two phase clocking using D latch?

74. Design the CMOS full adder circuit and make alayout?
75. Derive the equivalent resistance of CMOS transmission gate and plot the Req as a function of output
voltage?
76. Explain the Dynamic RAM read and write operation?

## 77. Write short notes on Layout design rules?

78. Explain clocked CMOS logic, domino logic and n-p CMOS logic?
79. Draw the Static CMOS circuits that provide the following logic operations.

## 80. Compare Static CMOS, pseudo nMOS, Dynamic CMOS.

81. Implement Single-bit Full adder using TG logic.
82. Explain how the MESFET act as a inverter.

## 83. Describe the operation of SRAM in read and write mode?

84. Consider the design of a CMOS compound OR-AND-INVERT (OAI) gate computing

.
a) Sketch a transistor-level schematic
b) Sketch a layout diagram