CMOS Design Assignment (2019)

You are required to design a simple CMOS circuit consisting of a two-input NOR gate.
You need to calculate the aspect ratios of all transistors based on circuit design rules for
minimum size inverter and NOR gate (Lecture 6, Lecture 10).
You are required to show the layout (plan view) of the circuit, indicating all layers (masks)
using layout design rules (Lecture 9). You need to calculate feature sizes and their separation.
The layout of the circuit should include the VDD and ground lines.
Marks will be awarded for the calculations, the explanation of the calculations, the layout, the
quality of the drawing, and the clarity of calculations and explanations.
You need to hand in the print out of your assignment on maximum four A4 size pages (plus
one additional cover page) to the Students Support Office, not later than the date and time
indicated below. The layout should be on one A4 size page and printed in color. The
calculations and explanations are maximum three A4 pages.
Design specification
VDD = 3 V, threshold voltage of NMOS and PMOS transistors are VTn = |VTp| = 0.25 V, oxide
capacitance C0 = 8×10-4 F/m2 , electron mobility 1000 cm2/Vs, hole mobility 500 cm2/Vs,
minimum feature size 0.2 m, and maximum alignment error 0.1 m. The area of the circuit
should be minimum. The fine grids on the layout drawing should have been turned on (or
printed on find grid paper) and important dimensions (feature sizes and gaps) should be shown
on the drawing with units of m or nm.
Minimum feature size is the smallest dimension of a feature a chip. This is usually the channel
length, L.
Maximum alignment error is the maximum error in aligning a mask layer to a previous layer
on the sample. You need to consider this in your design and indicate the base layer which the
other layers have been aligned too. Remember that for multilayer layouts the alignment error
between two layers could be more than maximum alignment error or two subsequent layers
(refer to Lecture 9).
For more guidance on design assignment refer to Design Assignment Guidance document in
Vital/Assessment/Design Assignment 2019.

The assignment (maximum four A4 pages) has to be handed in to the Student Support
Office, 5th floor of EEE Building, on the week 11 of this semester not later than 4 pm
on Tuesday 30th of April 2019. After this date, the standard university late submission
policy (5% deduction for each working day late) will be applied.