Академический Документы
Профессиональный Документы
Культура Документы
LOGIC LIBRARIES
Logical libraries :format is .lib
1. Timing information of Standard cells,Soft macros,Hard macros.
2. functionality information of Standard cells,Soft macros.
3. And design rules like max transition ,max capacitance, max fanout.
4. In timing information Cell delays ,Setup,Hold time are present.
5. Cell delay is Function of input transition and output load.
6. Cell delay is calculated based on lookup tables.
7. Cell delays are calculated by using linear delay models, Non linear delay models,CCS models.
8. functionality is used for Optimization Purpose.
9. And also Contain Power information.
10. And contains Leakage power for Default cell,Leakage Power Density for cell,Default Input voltage , Out
put voltage.
And PVT contains ------->Cell leakage Power
-------->Internal Power
--------->Rise Transition
----------->fall transition
---------->>Setup rise
----------->setup fall
-------------->Hold rise
------------->Hold fall
----------------->cell rise
---------------->cell fal
-------------------->Pin Capacitance
TECHNOLOGY FILE
Technology file: format is .tf:
1. It contains Name,Number conventions of layer and via
2. It contains Physical,electrical characteristics of layer and via
3. In Physical characteristics Min width,area,height are present.
4. In Electrical characteristics Current Density is present.
5. Units and Precisions of layer and via .
6. Colors and pattern of layer and via .
7. Physical Design rules of layer and via
8. In Physical Design rules Wire to Wire Spacing,Min Width between Layer and via are present.
TLU+
TLU+ files: format is .TLUP:
1. R,C parasitics of metal per unit length.
2. These(R,C parasitics) are used for calculating Net Delays.
3. If TLU+ files are not given then these are getting from .ITF file.
4. For Loading TLU+ files we have load three files .
5. Those are Max Tlu+,Min TLU+,MAP file.
6. MAP file maps the .ITF file and .tf file of the layer and via names.
NETLIST
Netlist: Format is .V
It contains Logical connectivity Of all Cell(Std cells,Macros).
It contain List of nets.
In the design for Knowing connectivity by using Fly lines.
SDC
SDC :Format is .SDC :
These Constraints are timing Constraints .
These Constraints used for to meet timing requirements.
Constraints are
OPTIMIZATION CONTROLS
Design Optimization Controls :
FLOOR PLAN
FLOOR PLAN:
AT CHIP LEVEL:
FLOOR PLAN IS A STEP WHERE WE CREATING THE PAD CELLS AND SPACIFYING POSITIONS,
PLACING PAD CELLS AND INSERTING PAD FILLER CELLS,FOR WELL CONTINITY.
WELL CONTINITY MEANS IF THE WELL IS NOT CONTINOUS THEN WE HAVE TO CREATE SPECIAL
MASKS. IF WELL IS CONTINOUS THEN THERE IS NO NEED OF CREATING SPECIAL MASKS.
HARD MACRO:THE CIRCUIT IS FIXED.AND WE DON'T NO WHICH TYPE OF GATES USING INSIDE.WE
KNOW THE ONLY TIMING INFORMATION.WE DON'T KNOW THE FUNCTIONALITY INFORMATION.
SOFT MACRO:THE CIRCUIT IS NOT FIXED.WE KNOW WHICH TYPE OF GATES USING INSIDE.WE KNOW
THE TIMING INFORMATION.WE KNOW THE FUNCTIONALITY INFORMATION.
BLOCKAGES:BLOCKAGES ARE THE IF LET TAKE WE WANT SOME AREA WHERE NO ONE STD
CELL PLACE.FOR THAT PURPOSE WE ARE USING BLOCKAGES.
SOFT BLOCKAGES MEANS ONLY BUFFERS ARE PLACED, NO STD CELL PLACED,AND THESE ARE
USED AT (i)BETWEEN TWO MACROS,
(ii)AND BETWEEN MACRO AND BOARDERS.
HARD BLOCKAGES MEANS NO ONE STD CELLS PLACED.AND THESE ARE USED AT THE AROUND
THE MACRO.BECAUSE PIN ACCESSING.
CORE AREA :CORE AREA IS DEFINED FOR THE PLACEMENT OF STD CELLS,AND MACROS.
----->I/O PLACEMENT.
IN I/O PLACEMENT WE HAVING PADS.
PADS ARE USED FOR INTERFACING PURPOSE,AND THESE ARE USED FOR PROVIDING POWER
SUPPLY, DATA SIGNAL,CLOCK SIGNAL.
1. CREATE PHYSICAL ONLY PAD CELLS.PHYSICAL ONLY CELLS MEANS ONLY THOSE HAVING
PHYSICAL INFORMATION ONLY.NO LOGICAL INFORMATION PRESENT.AND THEY DON'T HAVE TIMING
INFORATION ALSO.
2. PHYSICAL ONLY PAD CELLS ARE (i)VDD,VSS PADC CELLS,(ii)CORNER PAD CELLS.
3. PAD CELLS ACTS LIKE AS PORTS.
4. CHIP OUTSIDE PINS ARE CONNECTED TO THE INNER CHIP PADS.
5. PADS TYPES:(i)POWER PADS, (ii)DATA PADS .
6. FOR THE POWER SUPPLY TO THE ALL PADS CREATING A PAD POWER RING .
7. VDD,VSS PADS ARE CONNECTED TO THE CORE VDD,VSS POWER RINGS.
8. FOR FILLING THE GAPS BETWEEN THE PADS FILLED BY PAD FILLER CELLS.
9. THESE PAD FILLER CELLS ARE FOR WELL CONTINUITY.
PHYSICAL ONLY CELLS ARE:
1. PAD CELLS.
2. END CAP CELLS.
3. TAP CELLS.
4. DECAP CELLS.
POWER PLANNING
IN POWER PLANNING
IR DROP :VOLTAGE TRANSFER IN METAL A DROP OCCURS DUE TO RESISTANCE
OF METAL.THIS IS KNOWN AS IR DROP.
STATIC IR DROP:INDEPENDENT OF THE CELL SWITCHING THE DROP IS CALCULATED WITH THE
HELP OF WIRE RESISTANCE.
DYNAMIC IR DROP:IR DROP IS CALCULATED WITH THE HELP OF THE SWITCHING OF THE CELLS.
POWER CALCULATIONS:
----->NUMBER OF THE CORE POWER PAD REQUIRED FOR EACH SIDE OF CHIP=(TOTAL CORE
POWER)/{(NUMBER OF SIDE)*(CORE VOLTAGE)*MAXIMUM ALLOWABLE CURRENT FOR A I/O PAD)} .
Wtotalstrap = Itotal/(2*Rj)
L<(Vmax)/(Rj*Rs)
IR DROP:
------>AVG CURRENT THROUGH EACH STRAP=IstrapAvg=(Itotal)/(2*Nstraps)mA
-------->APPROPRIATE IR DROP AT THE CENTER OF THE STRAP=Vdrop or IRdrop
=IstrapAvg*Rs*(W/2)*(1/Wstrap)
POWER
-------->TOTAL POWER=STATIC POWER+DYNAMIC POWER
=LEAKAGE POWER+[INTERNAL POWER+EXT SWITCHING POWER]
=LEAKAGE POWER+[{SHORTCKT+INT POWER}]+EXT SWITCHING POWER]
=LEAKAGE POWER+[{(Vdd*Isc)+(C*V*V*F)+(1/2*C*V*V*F)]
FLOORPLAN (CONGESTION)
CONGESTION: REQUIRED NO.OF ROUTING RESOURCES ARE GREATER THAN THE NO.OF
AVAILABLE ROUTING RESOURCES
AFTER ACCEPTING THE CONGESTION, TIMING THEN WRITE OUT THE .def file
SAVE THE DESIGN .AND THESE .def FILE IS GIVEN AS INPUT TO THE PLACEMENT
PLACEMENT
IN PLACEMENT STEPS ARE
1. PLACEMENT CHECKS,
2. DFT SETUP.
3. POWER SETUP.
4. PLACEMENT OPTIMIZATION.
PLACEMENT :
AFTER GOING TO PLACEMENT WE HAVE TO CHECKS ,FIX
-->NON DEFAULT RULES ARE SPECIAL RULES.LIKE DOUBLE SPACING, DOUBLE WIDTHING.THESE
ARE APPLIED FOR CLOCK WIRES.BECAUSE THOSE HIGH ACTIVITY NETS.
-->BUT HERE WE ARE ONLY SPECIFYING NON DEFAULT ROUTING RULES[NDR'S].
1. FLOOR PLAN ,
2. NETLIST,
3. NARROW PLACEMENT REGIONS,
4. R,C FOR ROTING LAYERS,
5. DESIGN CONSTRAINTS.
THE ISSUE IS PREEXISTING SCAN CHAINS ARE CONNECTED FAR AWAY , BECAUSE THEY ARE
CONNECTED BASED ON THE FUNCTIONALITY BASED,
INSERT THE SCAN CHAINS FILE. IF PROBLEM WITH PREEXISTING SCAN CHAINS THEN REORDER
THE NAMES OF THE SCAN REGISTER NAMES.
THE LEAKAGE IS DUE TO THE JUNCTION LEAKAGE, TUNNELING , SUB THRESHOLD LEAKAGE.
FOR REDUCING THE STATIC POWER DISSIPATION REPLACING THE LVT CELLS WITH HVT CELLS.
FOR REDUCING THE DYNAMIC POWER DISSIPATION WE HAVE A LOT OF TECHNIQUES THOSE ARE :
REDUCING THE HIGH TOGGLE RATE NET LENGTHS.THESE TOGGLE RATE IS GETTING FROM
SWITCHING FILE THIS IS GETTING FROM SIMULATION PEOPLE.
AND CONNECTED NEARER TO IT.
ANOTHER TECHNIQUE IS ADDING THE BUFFER IN BETWEEN THE HIGH NET LENGTH NETS.FOR
REDUCING THE HIGH COUPLING CAPACITANCE.(REDUCE THE LOAD CAPACITANCE)
ANOTHER TECHNIQUE IS CONNECT HIGH COUPLING CAPACITANCE NET TO THE LOW CAPACITANCE
PIN OF THE CELL.(SWAPPING THE PIN).
ANOTHER TECHNIQUE IS CLONING ,IT IS CREATING THE SAME CELL AND CONNECT THE SOME OF
THE OUTPUT NET TO THESE.
PLACEMENT OPTIMIIZATION
PLACEMENT OPTIMIZATION:
PLACEMENT OPTIMIZATION WITH WE HAVE OPTIONS (i)CONGESTION,(ii)AREA RECOVERY
,(iii)POWER,(iv)DFT,(v)TIMING.
BY USING THE POWER OPTION WE CAN REDUCE THE STATIC POWER DISSIPATION,DYNAMIC
POWER DISSIPATION.
BY USING THE AREA RECOVERY OPTION WE CAN REDUCE THE CELLS ,POWER,TIMING.
BY USING THE DFT OPTION WE CAN REDUCE THE ROUTING RESOURECES BY REORDER THE SCAN
CHAINS.
------->A BUFFER TREES IS BUILT TO BALANCE THE LOADS AND MINIMIZE THE SKEW.
-------->A CLOCK TREE WITH BUFFER LEVELS BETWEEN THE CLOCK SOURCE AND CLOCK SINKS(END
POINTS).
-------->CLOCK PINS ARE DIFFERENT TYPES, THOSE ARE (i) STOP PINS,
(ii)FLOAT PINS,
(iii)EXCLUDE PINS.
SETUP TIME :THE MINIMUM AMOUNT OF TIME THE DATA SHOULD BE STABLE BEFORE ARRIVAL OF
SENSITIVE CLOCK.
HOLD TIME :THE MINIMUM AMOUNT OF TIME THE DATA SHOULD BE STABLE AFTER ARRIVAL OF
SENSITIVE CLOCK.
SETUP CHECK:THE DATA LAUNCHED AT SENSITIVE EDGE OF THE LAUNCH FLOP SHOULD BE
CAPTURED AT NEXT SENSITIVE EDGE OF THE CAPTURED FLOP.
BY THE COMBINATION OF THE THESE START AND END POINTS WE HAVE THE PATHS
LIKE ARE
BY DEPENDING ON THE START POINTS AND END POINTS WE HAVE FOUR TIMING GROUPS PRESENT.
1. INPUT GROUP
2. REGISTER GROUP
3. FEED THROUGH GROUP.
4. OUTPUT GROUP.
REGISTER GROUP:
START POINT IS CLOCK PIN OF LAUNCH FLOP.
END POINT IS DATA INPUT PIN OF CAPTURE FLOP
SETUP CHECK EQUATION IS :
OUTPUT GROUP:
START POINT IS CLOCK PIN OF LAUNCH FLOP.
END POINT IS OUTPUT PORT.
SETUP CHECK EQUATION IS :
UNCERTAINITY:
UNCERTAINTY = SKEW + ZITTER + MARGIN
JITTER: IT IS THE VARIATIONS IN THE CLOCK CYCLE AT THE CLOCK EDGES BEFORE
(OR) AFTER
SKEW:
SKEW IS THE DIFFERENCE IN THE ARRIVALS TIMES AT THE END POINTS OF THE CLOCK
TREE.
SKEW = Tc - Tl = Tskew
SKEW TYPES:
1. POSITIVE SKEW
2. NEGATIVE SKEW
POSITIVE SKEW:
NEGATIVE SKEW:
Tcq + Tcomb < Tclk - Tsu + (Tc - Tl)
Tcq + Tcomb < Tclk - Tsu - Tskew
Tcq + Tcomb < Tclk - Tsu - SKEW
WHEN (Tc < Tl) IT IS NEGATIVE SKEW.
1. ARRIVAL TIME
2. REQUIRED TIME
SLACK = REQUIRED TIME - ARRIVAL TIME
IF IN THE DESIGN WE HAVE NEGATIVE SLACK THEN WE HAVING TIMING VIOLATIONS IN THE DESIGN.
LATENCY'S:
IT IS DELAY DIFFERENCE FROM THE CLOCK GENERATION POINT TO THE CLOCK END POINTS.
1. SOURCE LATENCY
2. NETWORK LATENCY
SOURCE LATENCY :IT IS THE DELAY DIFFERENCE FROM THE CLOCK GENERATION POINT TO THE
CLOCK DEFINITION POINTS.
NETWORK LATENCY:IT IS THE DELAY DIFFERENCE FROM THE CLOCK DEFINITION POINTS TO
THE CLOCK END POINTS.
CTS OPTOMIZATION
OPTIMIZATIONS TECHNIQUES:
ROUTING
ROUTING:
---->CREATE PHYSICAL CONNECTIONS TO ALL DATA SIGNAL PINS,CLOCK PINS THROUGH METAL
INTERCONNECTIONS.
(i)GLOBAL ROUTING
(ii)TRACK ASSIGNMENT
(iii)DETAIL ROUTING
ROUTING (GLOBAL ROUTING)
GLOBAL ROUTING:
--->FIRST THE DESIGN IS DIVIDED INTO SMALL BOXES EVERY BOX IS CALLED GLOBAL ROUTING
CELLS (GCELLS OR BUCKETS)
----->EVERY GCELL HAVING THE A NUMBER OF HORIZONTAL ROUTING RESOURCES AND VERTICAL
ROUTING RESOURCES.
------->IF ANY GCELL HAVE CONGESTION THEN DETOURING(AVOID THE GCELL ROUTING THROUGH
ANOTHER GCELL).
TRACK ASSIGNMENTS :
---->ASSIGNS EACH NET TO THE SPACIFIC TRACKS.
----->TRACES=METAL CONNECTIVITY..
----->DETAIL ROUTING DOES NOT WORK ON THE ENTIRE CHIP AT THE SAME TIME LIKE TRACK
ASSIGNMENT.
SBOX : DIVIDE THE BLOCK INTO MINI BOXES THESE ARE USED FOR THE DETAIL ROUTE.
---------->AFTER ROUTING IF WE WANT ANY CHANGES OR ADDING NEW CELLS , THESE ALL ARE
DONE AT THE ECO STAGE.
--------->IN FREEZE SILICON ECO WE HAVE NO CHANCE OF ADDING CELL, HERE SPARE CELLS ARE
USED FOR THESE.
----------->IN NON FREEZE SILICON ECO WE CAN ADD THE CELLS AFTER ROUTING.
CHIP FINISHING
CHIP FINISHING:
IN THE CHIP FINISHING:
WE NEED TO DO:
REDUNDANT VIA IS THE TECHNIQUE FOR REDUCING VOIDS IN THE METAL LAYER.
FILLER CELL INSERTION
FILLER CELL INSERTION IS THE ONE OF THE TECHNIQUE FOR UTILIZING THE TOTAL AREA WITH OUT
GAPS .
IT IS GOOD TECHNIQUE BECAUSE IN THE FUTURE WE CAN REPLACE FILLER CELLS WITH SPARE
CELLS WITH A LOGIC.
METAL FILL INSERTION
AT THE TIME OF ETCHING THEY USE SOME TYPE OF CHEMICALS DUE TO THAT CHEMICALS METAL
LOSSES MORE FOR THAT ONE WE ARE INSERTING THE METAL FILLS.
METAL SLOTTING
METAL SLOTTING IS TECHNIQUE FOR AVOIDING THE PROBLEMS LIKE METAL LIFT OFF , METAL
EROSION.
FINAL VERIFICATION:
1. PARASITICS EXTRACTION:IT EXTRACT R,C VALUES FOR GETTING ORIGINAL DELAYS. TOOL:STAR RC
XT LICENCE
2. TIMING VERIFICATION:IT IS FIND BY USING PRIME TIME TOOL.
3. LVS ,ERC CHECKS:THESE IS FIND OUT BY USING CALIBRE,HERCULIES TOOLS.
4. DRC CHECKS:THESE IS FIND OUT BY USING CALIBRE,HERCULIES TOOLS.
AFTER VERIFICATION:
1. AFTER THIS WE RELEASE THE GDS FILE
2. IN THIS WE HAVE ALL POLYGONS INFORMATION IS PRESENT.
AFTER GDS
CALCULATIONS:
POWER CALCULATIONS:
----->NUMBER OF THE CORE POWER PAD REQUIRED FOR EACH SIDE OF CHIP=(TOTAL CORE
POWER)/{(NUMBER OF SIDE)*(CORE VOLTAGE)*MAXIMUM ALLOWABLE CURRENT FOR A I/O PAD)} .
Wtotalstrap = Itotal/(2*Rj)
L<(Vmax)/(Rj*Rs)
IR DROP:
------>AVG CURRENT THROUGH EACH STRAP=IstrapAvg=(Itotal)/(2*Nstraps)mA
-------->APPROPRIATE IR DROP AT THE CENTER OF THE STRAP=Vdrop or IRdrop
=IstrapAvg*Rs*(W/2)*(1/Wstrap)
POWER
-------->TOTAL POWER=STATIC POWER+DYNAMIC POWER
=LEAKAGE POWER+[INTERNAL POWER+EXT SWITCHING POWER]
=LEAKAGE POWER+[{SHORT CIRCUIT POWER + POWER+INT POWER}]+EXT SWITCHING
POWER]
=LEAKAGE POWER+[{(Vdd*Isc)+(C*V*V*F)+(1/2*C*V*V*F)]
CORE P/G RING WIDTH=(TOTAL CURRENT)/(NO OF SIDES *MAXIMUM CURRENT DENSITY OF THE
METAL LAYER USED FOR P/G PAD RING)
TIE CELLS--------------------->It is used for preventing Damage of cells; Tie High cell(Gate One input is
connected to Vdd, another input is connected to signal net);Tie low cells Gate one input is connected to
Vss, another input is connected to signal .
END CAP CELLS------------->To Know the end of the row,and At the edges endcap cells are placed to avoid
the cells damages at the end of the row to avoid wrong laser wavelength for correct manufacturing.
DECAP CELLS---------------->Charge Sharing; To avoid the Dynamic IR drop ,charge stores in the cells and
release the charge to Nets.
FIXING DRC'S
DRC'S FIXING
1. LOGICAL DRC'S.
2. PHYSICAL DRC'S.
LOGICAL DRC'S:
1. MAX TRANSITION
2. MAX CAPACITANCE
3. MAX FANOUT
MAX TRANSITION:
FIXING TECHNIQUES:
FIXING TECHNIQUES:
FIXING TECHNIQUES:
CLONNING=ADDING A SAME CELL LOAD WILL BE DIVIDED.
PHYSICAL DRC'S:
1. WIRE TO WIRE SPACING(MIN SPACING)
2. MIN WIDTH OF WIRES
3. VIA TO VIA SPACINGS
4. NOTCH AVOIDING
FIXING TECHNIQUES:
FIXING CROSSTALK
CROSS TALK:
REDUCING TECHNIQUES:
VICTIM NET WIDTH INCREASING THEN RESISTANCE DECREASE IT IS USED AT ROUTING ALSO.
SPACING BETWEEN AGGRESSOR NET AND VICTIM NET INCREASE.
BUFFERING ON CONSTANT NETS (OR) VICTIM NETS.
PLACING AN GROUND NETS ON BETWEEN THE AGGRESSOR NET AND VICTIM NET THEN VOLTAGE
DISCHARGE ON GROUND NET THEN NO SIGNAL INTEGRITY PROBLEM.THIS IS CALLED SHIELDING .
MAINTAIN STABLE SUPPLY.
FAST SLEW RATE.
JOGING(INCRAESE HALF TRACK BY HALF ITCH).
LAYER JUMPING(JUMP ONE LAYER ABOVE LAYER AND COMES TO SAME LAYER)
INCREASE DRIVE STRENTH OF CELL
CELL SIZING(UP SIZING)
DEEP N-WELL.
GUARD RING.
FIXES
SETUP CHECK:THE DATA LAUNCHED AT THE SENSITIVE EDGE OF THE LAUNCH FLOP SHOULD BE
CAPTURED AT THE NEXT SENSITIVE EDGE OF THE CAPTURED FLOP.
HOLD TIME: THE MINIMUM AMOUNT OF TIME THE DATA SHOULD BE STABLE AFTER ARRIVAL OF
SENSITIVE CLOCK.
HOLD CHECK: THE DATA LAUNCHED AT THE SENSITIVE EDGE OF THE LAUNCH FLOP SHOULD NOT
BE CAPTURE AT THE SAME SENSITIVE EDGE OF CAPTURED FLOP.
SETUP FIXES:
1. BUFFER INSERTION
2. REDUCE NET LENGTH
3. CELL UP SIZING.
4. DRIVE STRENGTH OF LAUNCH FLOP INCREASE.
5. LOGICAL OPTIMIZATION ON DATA PATH.
6. USEFUL SKEW.
7. PIPELINING.
8. USE SYNC CELLS.
9. NET WIDTH INCREASE.
10. USE LVT CELLS.
11. SPLITTING THE COMBINATIONAL LOGIC.
12. INCREASE CLOCK PERIOD.
13. USING DOUBLE SYNCHRONIZER USING FLIP FLOPS.
14. REDUNDANT VIA.
HOLD FIXES:
VERIFICATION'S
PHYSICAL VERIFICATION:
IN PHYSICAL VERIFICATION IT CHECKS:
EXTRACT ERRORS :
SHORTS
OPENS
FLOATING NETS.
COMPARE ERRORS:
PIN ERRORS
PARAMETRIC ERRORS
DEVICE MISMATCH
NET MISMATCH
MALFORMED DEVICES
PORTS MISMATCH
CHECKS:
CHECKS ARE:
WELL AND SUBSTRATE AREAS FOR PROPER CONTACTS AND SPCINGS THERE BY ENSURING
CORRECT POWER CONTACTS AND GROUND CONNECTIONS.
TO LOCATE FLOATING DEVICES AND FLOATING WELLS.
TO LOCATE DEVICE WICH ARE SHORTED.
TO LOCATE DEVICES WITH MISSING CONNECTIONS.
GATE CONNECTRD DIRECTLY TO SUPPLIES.
FLOATING INPUTS.
FORMAL VERIFICATIONS:
IN FORMAL VERIFICATION CHECKS ARE LEC(LOGICAL EQUIVALENCE CHECK).
SCENARIO'S
SCENARIO
SCENARIO = MODE + CORNER.
MODES TYPE:
1. FUNCTIONAL MODE.
2. TEST MODE.
IT CONTAINS SDC CONSTRAINTS.
IN DESIGN DIFFERENT FUNCTIONALITY MODES CONTAINS DIFFERENT SDC'S.
IN DESIGN DIFFERENT FUNCTIONALITY MODES ARE PRESENT.
CONSTRAINTS IN TEST MODE WHILE THE CHIP IS A DEVICES UNDER TEST:
VOLTAGE--------------------->HIGH
TEMPERATURE------------>LOW
VOLTAGE-------------------->LOW
TEMPERATURE----------->HIGH