IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO.

4, APRIL 2013 271

Design and Implementation of 32 Bit Unsigned

Multiplier Using CLAA and CSLA

V.Vijayalakshmil, R.Seshadd, Dr.S.Ramakrishnan3

1,2 3
Arunai Engineering College, Sakthi Mariannnan Engineering College,
1,2 3
Tiruvannamalai, Thandalam, Chennai.
I 2 3
viji5818@gmail.com, seshadriaec@gmail.com, jkang69@yahoo.com

Ahstract-This project deals with the comparison of the VLSI
design of the carry look-ahead adder (CLAA) based 32-bit
unsigned integer multiplier and the VLSI design of the carry
select adder (CSLA) based 32-bit unsigned integer multiplier.
Both the VLSI design of multiplier mUltiplies two 32-bit
unsigned integer values and gives a product term of 64-bit
values. The CLAA based multiplier uses the delay time of 99ns
for performing mUltiplication operation where as in CSLA
based multiplier also uses nearly the same delay time for
mUltiplication operation. But the area needed for CLAA
multiplier is reduced to 31 % by the CSLA based multiplier to
complete the mUltiplication operation. These multipliers are
implemented using Altera Quartus II and timing diagrams are
viewed through avan waves.
Keywords-CLAA; CSLA; Delay; Area; Array Multiplier;
VHDL Modeling & Simulation.
T. INTRODUCT I ON
Digital computer arithmetic is an aspect of logic
design with the objective of developing appropriate
algorithms in order to achieve an efficient utilization of the
available hardware. The basic operations are addition,
subtraction, multiplication and division. In this, we are going
Adders are also very important component in digital systems
because of their extensive use in these systems.
In this project we are going to compare the
performance of different adders implemented to the
multipliers based on area and time needed for calculation.
On comparison with the carry look-ahead adder (CLAA)
based multiplier the area of calculation of the carry select
adder (CSLA) based multiplier is smaller and better with
nearly same delay time. Here we are dealing with the
comparison in the bit range of n*n (32*32) as input and 2n
(64) bit output.
Hence, to design a better architecture the basic
adder blocks must have reduced delay time consumption and
area efficient architectures. The demand is of DSP style
systems for both less delay time and less area requirement
for designing the systems. Our interest is in the basic
building blocks of arithmetic circuits that dominate in DSP
applications, VLSI architectures, computer applications and
where ever reduced area computation is needed.
IT. CARRY LOOK-AHEAD ADDER

to deal with the operation of additions implemented to the

Carry Look Ahead Adder can produce carries faster
operation of multiplication. The repeated form of the
due to parallel generation of the carry bits by using
addition operations and shifting results in the multiplication
additional circuitry. This technique uses calculation of carry
operations.
Given that the hardware can only perform a signals in advance, based on input signals. The result is
reduced carry propagation time. For example, ripple adders
relatively simple and primitive set of Boolean operations,
are slower but use the least energy.
arithmetic operations are based on a hierarchy of operations
that are built upon the simple ones. In VLSI designs, speed,
power and chip area are the most often used measures for
determining the performance and efficiency of the VLSI
architecture.
Multiplications and additions are most widely and
more often used arithmetic computations performed in all
digital signal processing applications. Addition is a
fundamental operation for any digital multiplication. A fast, Figurel. Carry Look-Ahead Adder
area efficient and accurate operation of a digital system is
greatly influenced by the performance of the resident adders.

978-1-4673-5301-4/13/$31.00 ©2013 IEEE

273 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 4, APRIL 2013

v. MULTIPLICATION ALGORITHM
40.0ns 500ns 601
I I I

Let the product register size be 64 bits. Let the

multiplicand registers size be 32 bits. Store the multiplier in
the least significant half of the product register. Clear the
3782682799 X 4230476960
1 3048485111 )
1404927549 X 1699019376 1 1908060884 )
most significant half of the product register.
Repeat the following steps for 32 times: 531439527344 3529651 X 718766223 4761576960 + 5816695195755493124 )
1. If the least significant bit of the product register is "1"
then add the multiplicand to the most significant half of the FigureS. Waveform for a CLAA based multiplier
product register.
2. Shift the content of the product register one bit to the right
40.0ns 5O.0ns 601
I I I
(ignore the shifted-out bit.)
3. Shift-in the carry bit into the most significant bit of the
product register. Figure 4.Shows a block diagram for such a
multiplier [2].
3782682799
1 4230476S60 X 3048485111

1404927549 1699019376 X 1908060884

Multiplicand 5314395273443529651 t 7187662324761576960 X 5816695195755493124 j.

Figure6. Waveform for a CSLA based multiplier

Timing Analyzer Summary

To
I�� If IT I
ReqJred from F��d
Shll'land Add Type Slack Time rom 0
.. Tine C� Cb:k P�tm
Con 11'01 Lugie .

1 Worst·case t� �/A Nooe T9Il.5b5�a[3] -"-lIl{S:3] .. } 0

Figure7. Timing Analysis for CLAA based multiplier

Timing Analyzer Summary

Required Actual From To Failed
Type Slack From To
Time Time Clock Clock Paths
I Worst·case tpd NIA None 99.553 m all] suml63] .. .. 0

Figure4. Multiplier of two n-bit values. FigureS. Timing Analysis for CSLA based multiplier

Quartus II Version 8.1 Build 163 1012812008 SJ Web Ed�ion

VI. VHDL SIMULATIONS
Revision Name CLAmuttiplier
Top-level Entrty Name CLAmultiplier

The VHDL simulation of the two multipliers is Family Cyclone II

Device EP=35F672C6
presented in this section. Tn this, waveforms, timing Timing Models Rnal
Met timing requirements Yes
diagrams and the design summary for both the CLAA and Total logic elements 2.957/33.216(9%)

CSLA based multipliers are shown in the figures. The Total combinational functions 2.957 I 33.216 (9%)
Dedicated logic registers 0/ 33.216(0%)
VHDL code for both multipliers, using CLAA and CSLA, Total registers 0
Total pins 129/475(27%)
are generated. The VHDL model has been developed using Total virtual pins 0
Altera Quartus IT and timing diagrams are viewed through Total memory b�s 0/48.3.840 (0%)
Embedded Multiplier 9-bit elements 0/ 70 ( 0%)
avan waves. The multipliers use two 32-bit values. Total PLLs 0/4(0%)

Figure9. Design summary ofCLAA multiplier

 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 4, APRIL 2013

Figurel4. Analysis Table [4] A. Sertbas and R.S. Ozbey, "A performance analysis of classified
binary adder architectures and the VHDL simulations", J Elect.
Electron. Eng., Istanbul,Turkey,vol. 4,pp. 1025-1030,2004.
[5] P. S. Mohanty, "Design and Implementation of Faster and Low Power
Delay Delay Area
Multiplier type Area Multipliers", Bachelor Thesis. National Institute of Technology,
(ns) Product Rourkela, 2009.
[6] S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL
2957 Design, 2nd ed. , McGraw-Hill Higher Education, USA, 2005. ISBN:
CLAA based
98. 5 logic 291264.5 0072499389.
multiplier
cells [7] J. R. Armstrong and F.G. Gray, VHDL Design Representation and
2039 Synthesis, 2nd ed. ,Prentice Hall, USA, 2000. ISBN: 0-13-021670-4.
CSLA based
99. 5 logic 202880.5 [8] Z. Navabi, VHDL Modular Design and Synthesis of Cores and
multiplier
cells Systems, 3rd ed. , McGraw-Hill Professional, USA, 2007. ISBN:
9780071508926.
[9] P. C. H. Meier, R. A. Rutenbar and L. R. Carley, "Exploring

VITI. CONCLUSION Multiplier Architecture and Layout for low Power",CIC'96,1996.

[10] Software Simulation Package: Direct VHDL, Version 1.2, 2007,
Green Mounting Computing Systems, Inc., Essex, VT, UK.
A design and implementation of a VHDL-based 32- [II] Hasan Krad and Aws Yousi( "Design and Implementation of a Fast
bit unsigned multiplier with CLAA and CSLA was Unsigned 32-bit Multiplier Using VHDL",20IO.

presented. VHDL, a Very High Speed Integrated Circuit

Hardware Description Language, was used to model and Dr.S.Ramakrishnan was born in Tirunelveli, India in 1969. He
received his Bachelors of Engineering degree fi'om the deprniment
simulate our multiplier. Using CSLA improves the overall of Electronics and Instrumentation fi'om Annamalai University,
performance of the multiplier. Chidambaram, India and Masters Degree & Ph.D in Electrical
Thus a 31% area delay product reduction is Engineering fi'om Anna University, Chennai India. He has over 15
years of teaching experience after 5 years experience in the
possible with the use of the CSLA based 32 bit unsigned
industry. He is currently working as Principal & HeadlDeprniment
parallel multiplier than CLAA based 32 bit unsigned parallel of IT in Sakthi MrnTiamman Engineering College, Chennai,
multiplier. India.He is the member of IEEE & IETE. He has published in many
peer refelTed international and national journals and conferences.

IX. FUTURE WORK

Mr.R.Seshadri received the B.E and M.E degrees, both in
Electronics and communication engineering fi'om the S.K.P
This 32 bit multiplier can be further extended to 64 Engineering College, Tiruvannamalai, Tamilnadu, India. He has
bit multiplier and 128 bit multiplier using the proposed doing the Ph.D degree in Digital Signal Processing Architecture
at Anna University, India. Currently, he is working as a Assistant
method for multiplication operation can be done as future
Professor in Arunai Engineering College, Tiruvannamalai,
work. Tamilnadu, India. He has having 4 years of teaching Experience.

REFERENCES
V.Vijayalakshmi was born on October 12, 1990 in
Tiruvannamalai, Tamilnadu, India. She has received the B.E degree
in Electrical and Electronics Engineering from Arunai College of
[I] P. Asadi and K. Navi, "A novel highs-speed 54-54 bit multiplier",
Engineering, Anna University, Chennai, Tamilnadu, India, in May
Am. J Applied Sci., vol. 4 (9), pp. 666-672. 2007. 2011. She is currently pursuing her M.E degree in Applied
[2] W. Stallings, Computer Organization and Architecture Designing for Electronics fi'om Arunai Engineering College, Anna University,
Peljormance, 71h ed., Prentice Hall, Pearson Education International, Chennai, Tamilnadu, India from 2011 to 2013. She has published a
USA,2006,ISBN: 0-13-185644-8. journal in National conference conducted by Sri Balaji
[3] 1. F. Wakerly, Digital Design-Principles and Practices, 4th ed. , Chockalingam Engineering College on January, 2013. Her areas of
Pearson Prentice Hall,USA, 2006. ISBN: 0131733494. interest include VLSI and Control Systems.