Interlayer Short IC Layout Verification
Based CMOS Technology 0,35μm
Robby Kurniawan Harahap Eri Prasetyo Wibowo
Study Center Of Microelectronic Study Center Of Microelectronic
Gunadarma University Gunadarma University
Depok, Indonesia Depok, Indonesia
robby_kurniawan@staff.gunadarma.ac.id eri@staff.gunadarma.ac.id
Abstract— Layout in CMOS-based IC design is a set of layers
forming into an IC circuit. In drawing a layout one thing to be
considered the geometry interlayer so there is no short. Shorts on
layout is simple problem but can be major problem when it has
been detected after the layout is made. In the verification stage
IC design, process checks shorts have become an early stage
before the Design Rules Check (DRC) and Layout Versus
Schematic (LVS) is executed. Objective of this paper is to
describe the process steps for detecting shorts interlayer with a
circuit in cmos layout design. These shorts technique using
multiplexer circuit as a experiment on EDA tools use
ICshortchecker with design rules based on 0,35μm CMOS
technology.
Keywords— CMOS, Interlayer, Short, Verification Layout
I. INTRODUCTION
Layout Design is a part of CMOS Design become
interesting job. Looks easy but is very complex, because for
ensure a layout works as expected or not is not easy. The part
or stage to ensure the layout can works called verification. In
verification the layout design must be process with technology
are used. The checking process with design rules cmos
technology is DRC (Design Rule Check) and the matching
prosess between layout and schematic is LVS (Layout Verus
Schematic). But before run that two process there is a process
that must be run is called short check.
Basically short check become first step must be done after
the layout made, because if any path or net in a layout have
shot can make the CHIP defect. In layout design with analog
and mixed signal analog/digital, to check and correction short
performed directly and manually in layout. Different layout
design by digital design, can correction short using source code
for example HDL code [2].
Several research about short condition in layout cmos such
as short check using interactive CAD tool called shortfinder,
this shortfinder works to matching between designer
knowledge and intuition about layout with the computer
capability to reconstruction and find complex connectivity
graph [2]. Then the other research give an analysis short in
cmos cell, this study investigated causes short in Standard cell
CMOS design [3]. Other study is analysis defect in cmos
circuit based oriented testing with method hierarchical
approach[4]. Therefore this paper same work with study [2],
Hamzah Afandi
Departement of Electrical Engineering
Gunadarma University
Depok, Indonesia
hamzah@staff.gunadarma.ac.id
but the difference is this paper discussion about interactive
EDA tool to check short in layout called ICShortchecker. This
tool provided in IC-Station layout by mentor graphics software.
The discussion are presented in tutorial to use, with using a
multiplexer circuit built from inverter[5] as implementation test
layout. The CMOS technology are used in this paper is
0,35μm from austriamicrosystem (AMS).
This paper consists of 5 section. First section discuss about
introduction. Second section discuss methods are used. Third
section discuss about layout design made. Fourth section
discuss result of layout short check. Then the end section or
fifth section is conclusion this paper.
II. METHOD
A. ICShortchecker
One of tools in IC-Station Layout software are used to find
path or net in layout a potentially short circuit before run DRC
and LVS on ICtrace or Calibre [1]. The ICShortchecker work
with examines geometries in the layout cell. The geometry can
be shapes, paths, pin and via.
This short happens from overlapping and coincident nets
with different names shown figure 1 [1]. The result from this
checking process is a message contains errors with location
where is the short circuit happen. This error must be corrected
by designer then can reprocess checking short to ensure the
layout does not have overlapping or coincident nets. potential
short. If there are still short, must be recorrection. This result
marking with location and will be write in DRC database.
As the following example is a result from short check in a
layout.
// Note: [Current DRC] Result 1 of 2 in RuleCheck
net_0_3: Nets: /OUTB & VDD
The Above example describes that happened short in a
layout. There are two error from two different nets, path or net
with name port VDD and OUTB are overlapping geometries.

Figure 1. ICshortchecker exampleoverlapping
To check short using ICShortchecker using two method
[1]:
 $check_shorts_all(): Checks all nets for layout
shorts
 $check_shorts_selected(): Checks nets of selected
objects for layout shorts
To using ICShortChecker in IC-Station Layout can be
access menu in ICPalette, shown on figure 2.
Figure 2. ICShortchecker Menu On IC-Station Layout
B. CMOS Inverter
Basic circuit dan other word is switch, consists of two
transistor are PMOS and NMOS. The inverter can be called
CMOS, because consists two transistor and the simple
definition of CMOS is the circuit which contain PMOS and
NMOS. The inverter system work like a switch (open and
close). If input value 0 or low then NMOS transistor will be
close or ON then the output result is 1 or high. On the other
hand if input value 1 then PMOS close and result 0 or low. The
inverter cicuits can be simple layout test to implement
ICShortcircuit. The inverter schematic shown on figure 3.
Figure 3. CMOS Inverter Schematic
C. Multiplexer 2 to 1
The other word multiplexer is data selector. The
multiplexer circuit consists of more then 1 input value and
resulting 1 output. For resulting, multiplexer select the binary
information from one of input value. The Selection depends
on input value called selector. In [5] the multiplexer 2 : 1 built
from variations inverter, just needed 4 inverter circuits. With
using layout inverter which has been made can construct a
layout multiplexer. The challenge is to connect between
inveter. This condition sometimes happen an error connecting
nets/path, because the layout greater than inverter layout.
Figure 4 shown multiplexer schematic from [5].
Figure 4. Multiplexer 2:1 Schematic [5].
D. Stick Diagram
One of method to create a layout is using stick diagaram.
The stick diagram is a sketches are made manually can use by
hand or using computer drawing software. Stick diagram to
facilitate designer create nets and mapping components such
as transistor, resistor, capacitor, and diode layout easily.
Figure 5. Stick Diagram CMOS Inverter
E. Interlayer The multiplexer is combination 4 inverter layout
The relations between layers CMOS according to the interconnecting using via. Figure 8 shown multiplexer stick
CMOS technology rules consists of intralyer and interlayer. diagram
The different between intralayer and interlayer are object
relations. Intralayer for relations with same layer and
interlayer for different layer. this paper discuss interlayer,
especially in splicing nets. Figure 6 Shown Layers 0,35 μm
CMOS Technology.

Figure 8. Multiplexer stick diagram

Figure 6. Layers 0,35 μm CMOS Technology
B. Short Check
III. LAYOUT DESIGN After layout has made, then short check process can run.
For Layout Design and to implement short check, then Checking process using two method from ICShortchecker.
several stages can be performed as follows: Checking by all area layout and Checking by selected area
layout.
A. Create Sketch
First step in layout design make sketch using stick diagram.
1. Sketch Interlayer
To test simple short check can use two different layer
as metal 1 and metal 2. The stick diagram for this simple
layout as shown figure 7.

Figure 9. Short Check Flow

IV. RESULT
After stick diagram has designed, then create layout using
IC-Station Layout with following stick diagram. Below are the
results of design layout.

Figure 7. Simple test short stick diagram A. Interlayer Layout

2. Sketch Inverter
The inverter stick diagram made adjust color of layers
in CMOS technology. Port VDD and GND using orange
color as metal2, because that port will be connected to
PADS that use metal 2 as input, gate using poly 1 with
yellow color and drain and source using metal1 with red
color such as figure 5.
Figure 10 as layout result, then perform ICShortcheker.
From the process short check, 2 errors occur. The errors happen
because 2 different nets are connect by using via. Net Out and
net VDD. This transcript message error in IC-station Layout in
figure 11.

3. Multiplexer Stick Diagram


Figure 10. Simple test short layout
Figure 11. Result ICShortchecker for Simple layout
B. Inverter Layout
By using stick diagram, potential short nets in layout can be
avoided by knowing the location via.
Figure 12. Inverter Layout
The short check result by using check all or check selected,
there is no potential short. This transcript message error in IC-
Station Layout in figure 13.
Figure 13. Short Check result of Inverter Layout
C. Inverter Layout
Multiplexer layout shown on figure 14, with connected 4
inverter layout by using via. This connection process should
carefully, because if connection incorrect then make potential
short. The result , there is no potential short.
Figure 14. Multiplexer 2:1 layout
V. CONCLUSION
From test short check in section IV can be concluded, short
in layout occur because fault placement of via, that two
different nets are connect. This condition short may occur
when connecting between nets, device to device, net to device.
simply to prevent short can use sketch by stick diagram. After
the short problem clear, then can continue to next verification
DRC and LVS
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