International Journal of Computer Engineering & Technology (IJCET)

Volume 8, Issue 5, Sep-Oct 2017, pp. 23–30, Article ID: IJCET_08_05_004

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8 BIT CUSTOM MIPS MICROPROCESSOR

Mohit Rane, Arjav Naik and Kalpan Mehta
Electronics and Communication Engineering,
Institute of Technology, Nirma University, Ahmedabad, Gujarat, India

ABSTRACT
MIPS is a RISC instruction set architecture which has gained popularity over
many year and has found many uses in various embedded systems. This paper
describes how to implement the instruction execution unit of a single cycle 8-bit RISC
architecture having a custom instruction set which is based on 32 bit microMIPS
architecture, a type of MIPS architecture and also explains the functioning and
execution of each type of instruction supported. The paper also describes various
functional units in the 8 bit custom architecture. The custom instruction set includes 9
instructions and implementation of the proposed architecture is done using Verilog on
Field Programmable Gate Array (FPGA) Altera Cyclone II. A different approach for
the implementation of these execution units for a subset of instructions is presented in
detail.
Key word: MIPS, RISC, microMIPS, FPGA.
Cite this Article: Mohit Rane, Arjav Naik and Kalpan Mehta, 8 Bit Custom MIPS
Microprocessor. International Journal of Computer Engineering & Technology, 8(5),
2017, pp. 23–30.
http://www.iaeme.com/ijcet/issues.asp?JType=IJCET&VType=8&IType=5

1. INTRODUCTION
The microMIPS architecture has many functional units and each of them plays a unique role
in processing an instruction. The conventional architecture has standardized execution units
for the instructions supported by it. The 8-bit microprocessor is based on load store
architecture and supports register, immediate and jump type of instruction. As it is a 8 bit
architecture there are 8 registers each of 8 bits r0 to r7, the data bus is of 8 bits, the data
memory has 256 addresses each can store data of 8 bits and the instruction memory can have
256 instructions and instructions length is 16 bit wide [1]. Various changes are made to the
conventional design to make an architecture which will be capable of supporting 9
instructions. The implementation is done in Verilog and it is realized on Altera Cyclone II.
The flow of the paper starts with an insight in conventional microMIPS architecture
followed by custom RISC architecture. The microprocessor elements, its instruction format
and instruction set is explained. After which the methodology and dataflow explains the
functioning of the custom architecture. Analysis of microprocessor is done and conclusion is
drawn.

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 Mohit Rane, Arjav Naik and Kalpan Mehta

2. CONVENTIONAL MICROMIPS ARCHITECTURE

The abstract view of the single cycle microMIPS instruction execution unit is shown in the
Figure 1. The data flow starts from the left side where the Program Counter (PC) provides the
next instruction address. Then the instruction is fetched from the instruction memory, which
will be a 32 bit data which will be decoded thereafter. Opcode and Function which are
decoded from the instruction are then sent to the control unit which provides various control
signals for the different units of the instruction execution unit. The content of source and
destination registers are fetched from the register file and supplied to the ALU. In case of
register type of instruction the destination register is modified in the register file, the flip flop
in the register file are edge triggered so that reading and writing into same register will not be
a problem. In case of immediate type of instruction, the immediate operand is decoded from
the 32 bit instruction directly and that is delivered to the ALU [2]. In case of load and store
instruction, only the data memory is accessed otherwise it is bypassed.

Figure 1 Single cycle microMIPS instruction execution unit

The function of next address box is to compute the next instruction’s address depending
upon the instruction type whether it is a conditional jump or a un-condition jump.

3. CUSTOM RISC ARCHITECTURE

The custom architecture of the simple 8 bit RISC processor as shown in the Figure 2 is based
upon load store architecture and is capable of executing 9 instructions which are of Register,
Immediate and Jump format, the format and the instruction set are discussed in detail later in
this paper. The Program Counter provides the next instruction address and the instruction will
be fetched from the instruction memory. The fields will be decoded and various control
signals are also generated by the Control unit depending upon the opcode and function. For
the decoder to know which type of instruction is being provided, the opcode of the instruction
will be pre-decoded. After the instruction is decoded the execution is done almost in the same
manner as it is done in the 32 bit microMIPS [3].
As can be interpreted from the Figure 2, the difference is there in the execution of the
jump type of instruction, the next address box is absent in the custom 8 bit architecture which
is present in the 32 bit microMIPS. The function of the next address box is to compute the
next instruction address by comparing the operands in case of conditional branch or to
provide the address to the PC in case of un-conditional branch. The comparison of the
operand is done in the ALU and a control signal is sent to the PC where further procedure of
adding the immediate operand to the current address is done. If it is an un-conditional jump

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 8 Bit Custom MIPS Microprocessor

instruction, then a signal from the control unit is sent to the PC and the further procedure is
taken place in the PC.

Figure 2 Custom microMIPS instruction execution unit

4. MICROPROCESSOR ELEMENTS
The various microprocessor elements that are required for the working of the custom
microMIPS instruction execution unit are as follows:

4.1. Program Counter

It is a 4x1 multiplexer in which the selection lines will be the branch (br) and next instruction
address (nia) control signals. The 4 data inputs will be immediate, pc+1, don’t care,
pc+immediate.
The s0 selection line represents br and s1 represents nia.
 00: When jump will be there br and nia will be both 0 so the output will be immediate value
where we have to jump.
 01: When there will be no jump and no branch instruction the output will be pc+1 which will
go to next instruction.
 10: The selections line are invalid so this is not possible.
 11: When there is no jump but branch is satisfied the output will be pc+immediate which is
where we have to branch.

4.2. Instruction Memory

The size of instruction memory is 256x16 i.e. there are 256 lines of instructions each of which
is of 16 bits. So each address in instruction memory will have complete instruction. The
inputs of instruction memory will be PC’s output. The output will go to the decoder.

4.3. Decoder
The main function of decoder is to decode the instruction that is provided to it by the
instruction memory. It detects whether the instruction is of R, I or J type depending upon the
opcode it get from the instruction. And according to the instruction type various fields will be
sent further to the respective blocks for further process. Sign extension will also be done in
this block for I type of instruction’s immediate value. Opcode and function will go to Control
Unit.

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 Mohit Rane, Arjav Naik and Kalpan Mehta

4.4. Control Unit

The control unit will generate the control signals according to the opcode and function
provided by the decoder as shown in the Table 1.
The unit that actually makes the entire custom processor work as expected. The input to
this is the instruction word, and the output is a set of control signals that decide, for example,
whether the register file is to updated, what operation is to be done by the ALU, whether
memory read or write is required, etc.
 MemToReg: It determines the register input data whether it will be provided from the ALU or
from the Data Memory.
 RegWrite: It determines whether the instruction will update the value of the register.
 MemWrite: It determines if present operation is going to write into memory.
 MemRead: It determines if present operation is going to read from memory.
 ALUfn: It determines which operation ALU will perform according to the instruction.
 ALUSrc: This control signal determines if an immediate or register data is to be provided to
the ALU.
 Br: If the current instruction is a branch, then use this signal is selected for a multiplexer to
feed the pc.
 NIA: It controls the PC input MUX if BEQ is the instruction and if condition is satisfied then
it will be asserted 1 by ALU So PC will give PC + Immediate as the output.
 Regdst: This signal gives the destination where the output will be written.

Table 1 Control signals generated by Control Unit

Instructi Op Fn Mem to Regds Mem ALUf Reg Mem ALU B NI

on Reg t Write n Write Read/ Src r A
Mem
Write
add 000 00 1 1 0 000 1 0/0 0 x 1
sub 000 01 1 1 0 001 1 0/0 0 x 1
and 000 10 1 1 0 010 1 0/0 0 x 1
or 000 11 1 1 0 011 1 0/0 0 x 1
addi 001 xx 1 0 0 100 1 0/0 0 x 1
lw 010 xx 0 0 0 101 1 1/0 0 x 1
sw 011 xx x 0 1 110 0 0/1 0 x 1
beq 100 xx x x 0 111 0 0/0 0 x 1
j 101 xx x x 0 xxx 0 0/0 0 x 0

4.5. Register Destination

It is a 2x1 multiplexer. The function of this mux is to select appropriate location of register
file according to the type of instruction (R or I type).

4.6. Register File

The size of register is 8x8 i.e. there are total 8 registers and they are of 8 bits each. As register
size is of 8 bits, total 3 bits are required in instruction to identify any register. The read
function of the register file will be performed each and every time [4]. And the write function
will be initiated whenever there is register write control from the control unit. The output of
the register file will be the register’s data according to the input operand.

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 8 Bit Custom MIPS Microprocessor

4.7. ALU Source

It is a 2x1 mux. The selection lines will be from the control unit signals (alusrc) [5]. The
inputs will be register data and immediate value depending upon the instruction type (R or I).

4.8. ALU
ALU is stands for arithmetic logical unit and it performs 5 functions:
 Addition (R and I type)
 Subtraction (R type)
 Bitwise AND (R type)
 Bitwise OR (R type)
 Compare (I type)

It will perform one of this five functions according to the input control signal which it
gets from the control unit. The opcode , function and ALU control signal for the supported 9
instructions by the custom architecture is shown in Table 2.

Table 2 Instruction’s opcode, function and ALU control signal

Instruction op fn alufn Function
add 000 00 000 It will be addition
sub 000 01 001 It will be Subtraction
and 000 10 010 It will be bit wise and
or 000 11 011 It will be bit wise or
addi 001 - 100 It will be addition
lw 010 - 101 It will be addition
(Address Calculation)
sw 011 - 110 It will be addition
(Address Calculation)
beq 100 - 111 Comparison for BEQ
(branch if equal)
j 101 - - -

4.9. Data Memory

The size of data memory is 256x8. There are 256 data lines each of which is of 8 bits. It will
perform read when memory read control signal is provided by the control unit in case of load
instruction. Write will be performed when memory write control signal is provided by the
control unit in case of store instruction. The output will go to the MemtoReg mux.

4.10. Memory to Register

It is a 2x1 mux. The input is taken from the data cache and ALU. The selection line is
decided by the control unit. The output will go to the register file depending upon the
instruction.

4.11. Display
This block does not have any use in the actual processing of instruction. The main function of
this block is to display the final output of R or I or J type instruction. It will take the final
value of the processed instruction and use it for display purposes.

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 Mohit Rane, Arjav Naik and Kalpan Mehta

5. INSTRUCTION FORMAT CHANGES

The 16 bit instruction is divided in the following way:

R type Op Fn Unused Rd Ra Rb
instruction 3 bits 2 bits 2 bits 3 bits 3 bits 3 bits
15-13 12-11 10-9 8-6 5-3 2-0

I type Op Immediate Ra Rb
instruction 3 bits 7 bits 3 bits 3 bits
15-13 12-6 5-3 2-0

J type Op Unused Immediate

instruction 3 bits 5 bits 8 bits
15-13 12-8 7-0

6. INSTRUCTION SET
The operations performed by the 9 instructions supported by the custom 8 bit microprocessor
are in Table 3 [6].

Table 3 Supported instructions by custom 8 bit microprocessor

Instruction Type Operation
add R rd <--- ra + rb
sub R rd <--- ra - rb
and R rd <--- ra AND rb
or R rd <--- ra OR rb
addi I rd <--- ra + imm
lw I rd <--- DMEM[ra + imm]
sw I DMEM[ra + imm] <--- rd
beq I if (ra == rb) pc <--- pc + imm
j J pc <--- address

7. METHODOLOGY
Each of the block shown in the Figure 2 is implemented as a separate module with suitable
input and output port definitions and they are instantiated to make the dataflow in Verilog [7].
Each block will be triggered by a positive edge of clock for synchronization. A mix of
behavioral modeling and data flow modeling in Verilog was used to develop the circuit
components.

8. DATAFLOW
Address bus will be of 8 bits and data bus will be also of 8 bits. The execution of the R, I, J
instruction is described below.

8.1. R type
 R type of instruction will be fetched and forwarded to decoder.

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 8 Bit Custom MIPS Microprocessor

 The decoder comes to know that the instruction is of R type from 3 bit opcode.
 Decoder will provide opcode and function to control unit and control unit will then generate
appropriate control signals.
 Register Destination will let rd or rb to be the final destination of R type instruction.
 Alu Source will let the value of register indicated by rb to be forwarded to ALU.
 ALU performs the appropriate operation on the two data coming from the register (ra) and
register destination (rb).
 The calculated output produced by ALU will be forwarded to the MemtoReg mux.
 This output will then be finally stored in the register destination (rd).
 The data present in the register destination is forwarded to the Display block to show the
value.

8.2. I type
 I type of instruction will be fetched and forwarded to decoder. The decoder comes to know
that the instruction is of I type from 3 bit opcode.
 Decoder will provide opcode to control unit and control unit will then generate appropriate
control signals.
 Register Destination will let rb to be the final destination of R type instruction.
 Alu Source will let the immediate value of register to be forwarded to ALU.
 ALU performs the appropriate operation on the two data coming from the register (ra) and
register destination (rb). For beq instruction, comparison is done. If comparison is satisfied
then branch will occur in the next instruction and PC value will be updated. For addi, lw and
sw, it will add the immediate and value from ra register.
 Data Memory will only be used in lw and sw type of instruction. This will be the last stage for
sw instruction as it will only store the value provided by the rb register to the location
indicated from ALU output.
 The calculated output produced by ALU will be forwarded to the MemtoReg mux. Also the
output of Data Memory will be forwarded to this mux.
 MemtoReg mux will decide which input needs to be forwarded further. In case of lw type, it
will select input from Data Memory. In case of addi type, it will select input from ALU. This
mux will not be used for sw and beq type of immediate instructions.
 This output will then be finally stored in the register destination (rb) (if instruction is lw or
addi).
 The data present in the register destination is forwarded to the Display block to show the
value for lw and addi instruction. For sw instruction, data stored in data memory is forwarded
and for beq, the final PC value is forwarded.

8.3. J type
 The decoder comes to know that the instruction is of J type from 3 bit opcode.
 Decoder will provide opcode to control unit and control unit will then generate appropriate
control signal i.e. NIA indicating that it is an un-conditional Jump.
 Decoder will send this 8 bit immediate value to the PC, and in next instruction PC will jump
to that address.

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 Mohit Rane, Arjav Naik and Kalpan Mehta

9. ANALYSIS OF DESIGN OF THE MICROPROCESSOR

The custom architecture that was implemented for the 9 instructions in Verilog was analyzed
using RTL view and Technology Map View [8]. The summary of the resources utilization of
the custom architecture is given in Table 4.

Table 4 Resource utilization by custom 8 bit micrprocessor

Family Cyclone II
Device EP2C35F672C6
Timing Models Final
Total logic elements 176 / 33,216 (< 1 %)
Total combinational functions 138 / 33,216 (< 1 %)
Dedicated logic registers 134 / 33,216 (< 1 %)
Total pins 10 / 475 ( 2 % )
Total virtual pins 0
Total memory bits 0 / 483,840 ( 0 % )
Embedded Multiplier 9-bit elements 0 / 70 ( 0 % )
Total PLLs 0/4(0%)

10. CONCLUSIONS
The custom architecture implemented was successful in executing all the 9 instructions. The
design was verified by loading the instruction memory with instructions and the results were
observed on the Altera Cyclone II FPGA kit with the help of display function element. The
design is verified through exhaustive simulations. Very less amount of resources were
utilized in implementation of the architecture. The conventional microMIPS architecture
supports many instructions but also uses many resources. This custom architecture provides
better management of logical units for execution of a limited set of instructions.

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[5] Microprocessor Design, CSIT Laboratory.
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