A

Practical Activity Report

Submitted for
Embedded System (UCS614)

Mid Semester Lab Evaluation

Submitted by:
(101603281) Riya Garg
BE Third Year
Batch: 3COE19

Submitted to:
Ms. Aman Ma’am

Computer Science and Engineering Department

TIET, Patiala

Jan-May,2019
Ques 1 Write a program to display Hello World.

CODE:

module hello;
initial begin
$display("Hello");
#10;
end
endmodule

Ques 2 Write a program for and gate using gate level logic.

CODE:

module mand(a,b,oand);
input a,b;
output oand;
and iand(oand,a,b);
endmodule

module test;
reg ra,rb;
wire wo;
mand m(ra,rb,wo);
initial begin
$display("a\tb\tOutput");
 $monitor("%b\t%b\t%b",ra,rb,wo);
ra=0;rb=0;
#10;
ra=0;rb=1;
#10;
ra=1;rb=0;
#10;
ra=1;rb=1;
#10;
end
endmodule

Ques 3 Write a program for or gate using gate level logic.

CODE:

module mand(a,b,oor);
input a,b;
output oor;
or ior(oor,a,b);
endmodule

module test;
reg ra,rb;
wire wo;
mand m(ra,rb,wo);
initial begin
$dumpfile("org.vcd");
$dumpvars(0,test);
$display("a\tb\tOutput");
 $monitor("%b\t%b\t%b",ra,rb,wo);
ra=0;rb=0;
#10;
ra=0;rb=1;
#10;
ra=1;rb=0;
#10;
ra=1;rb=1;
#10;
end
endmodule
Ques 4 Write a program for half adder using dataflow logic
CODE:

module halfadder(a,b,o,c);
input a,b;
output o,c;
assign o=a^b;
assign c=a&b;
endmodule

module test;
reg ra,rb;
wire wo,wc;
halfadder m(ra,rb,wo,wc);
initial begin
$display("a\tb\tSum\tCarry");
$monitor("%b\t%b\t%b\t%b",ra,rb,wo,wc);
ra=0;rb=0;
#10;
ra=0;rb=1;
#10;
ra=1;rb=0;
#10
ra=1;rb=1;
end
endmodule

Ques 5 Write a program for full adder using data flow logic
CODE:
module fulladder(a,b,cin,o,cout);
input a,b,cin;
output o,cout;
 assign x=a^b;
assign o=x^cin;
assign y=a&b;
assign w=x&cin;
assign cout= y | w;
endmodule
module test;
reg ra,rb,wcin;
wire wo,wout;
fulladder m(ra,rb,wcin,wo,wcout);
initial begin
$display("a\tb\tCin\tSum\tCarry");
$monitor("%b\t%b\t%b\t%b\t%b",ra,rb,wcin,wo,wcout);
ra=0;rb=0;wcin=0;
#10;
ra=0;rb=1;wcin=0;
#10;
ra=1;rb=0;wcin=0;
#10;
ra=1;rb=1;wcin=0;
#10;
ra=0;rb=0;wcin=1;
#10;
ra=0;rb=1;wcin=1;
#10;
ra=1;rb=0;wcin=1;
#10;
ra=1;rb=1;wcin=1;
end
endmodule
Ques 6 Write a program for half subtractor using data flow logic
CODE:

module halfsub(a,b,o,c);
input a,b;
output o,c;
assign o=a^b;
assign x=~a;
assign c=x&b;
endmodule

module test;
reg ra,rb;
wire wo,wc;
halfsub m(ra,rb,wo,wc);
initial begin
$display("a\tb\tDifference\tBorrow");
$monitor("%b\t%b\t %b\t\t%b",ra,rb,wo,wc);
ra=0;rb=0;
#10;
ra=0;rb=1;
#10;
ra=1;rb=0;
#10;
ra=1;rb=1;
end
endmodule

Ques 7 Write a program for full subtractor using data flow approach
CODE:

module fullsub(a,b,cin,o,cout);
input a,b,cin;
 output o,cout;
assign x=a^b;
assign o=x^cin;
assign n=~a;
assign y=n&cin;
assign z=n&b;
assign q=b&cin;
assign r=y|z;
assign cout= r | q;
endmodule

module test;
reg ra,rb,wcin;
wire wo,wout;
fullsub m(ra,rb,wcin,wo,wcout);
initial begin
$display("a\tb\tCin\tSum\tCarry");
$monitor("%b\t%b\t%b\t%b\t%b",ra,rb,wcin,wo,wcout);
ra=0;rb=0;wcin=0;
#10;
ra=0;rb=1;wcin=0;
#10;
ra=1;rb=0;wcin=0;
#10;
ra=1;rb=1;wcin=0;
#10;
ra=0;rb=0;wcin=1;
#10;
ra=0;rb=1;wcin=1;
#10;
ra=1;rb=0;wcin=1;
#10;
ra=1;rb=1;wcin=1;
end
endmodule
Ques 8 Write a program for full adder using half adder.
CODE:

module halfadder(a,b,o,c);
input a,b;
output o,c;
assign o=a^b;
assign c=a&b;
endmodule

module fulladder(a1,b1,c1,sum,carry);
input a1,b1,c1;
output sum,carry;
wire wo1,wc1,wc2;
halfadder h1(a1,b1,wo1,wc1);
halfadder h2(wo1,c1,sum,wc2);
assign carry=wc1 | wc2;
endmodule

module test;
reg ra,rb,rc;
wire wo,wc;
fulladder m(ra,rb,rc,wo,wc);
initial begin
$display("a\tb\tc\tSum\tCarry");
$monitor("%b\t%b\t%b\t%b\t%b",ra,rb,rc,wo,wc);
ra=0;rb=0;rc=0;
#10;
ra=0;rb=1;rc=0;
#10;
 ra=1;rb=0;rc=0;
#10;
ra=1;rb=1;rc=0;
#10;
ra=0;rb=0;rc=1;
#10;
ra=0;rb=1;rc=1;
#10;
ra=1;rb=0;rc=1;
#10;
ra=1;rb=1;rc=1;
end
endmodule

Ques 9 Write a program for 2X1 MUX

CODE:

module mux(a,b,s,o);
input a,b,s;
output o;
assign x=~s;
assign y=a&x;
assign z=b&s;
assign o=y|z;
endmodule

module test;
reg ra,rb,rc;
wire wo;
mux m(ra,rb,rc,wo);
initial begin
 $display("a\tb\ts\tOutput");
$monitor("%b\t%b\t%b\t%b",ra,rb,rc,wo);
ra=0;rb=0;rc=0;
#10;
ra=0;rb=1;rc=0;
#10;
ra=1;rb=0;rc=0;
#10;
ra=1;rb=1;rc=0;
#10;
ra=0;rb=0;rc=1;
#10;
ra=0;rb=1;rc=1;
#10;
ra=1;rb=0;rc=1;
#10;
ra=1;rb=1;rc=1;
end
endmodule

Ques 10 Write a program for 2X1 MUX using conditional operator.

CODE:

module mux(a,b,s,o);
input a,b,s;
output o;
assign o=s?b:a;
endmodule

module test;
 reg ra,rb,rc;
wire wo;
mux m(ra,rb,rc,wo);
initial begin
$display("a\tb\ts\tOutput");
$monitor("%b\t%b\t%b\t%b",ra,rb,rc,wo);
ra=0;rb=0;rc=0;
#10;
ra=0;rb=1;rc=0;
#10;
ra=1;rb=0;rc=0;
#10;
ra=1;rb=1;rc=0;
#10;
ra=0;rb=0;rc=1;
#10;
ra=0;rb=1;rc=1;
#10;
ra=1;rb=0;rc=1;
#10;
ra=1;rb=1;rc=1;
end
endmodule

Ques 10: Write a program for 4X2 encoder using behavioural operator
CODE:
//encoder
module encoder(i1,o1);
input [3:0] i1;
 output [1:0] o1;
reg [1:0] o1;
always @ (*)
begin
case(i1)
4'b0001:o1=2'b00;
4'b0010:o1=2'b01;
4'b0100:o1=2'b10;
4'b1000:o1=2'b11;
endcase
end
endmodule

module test;
reg [3:0]ra;
wire [1:0]wo;
encoder m(ra,wo);
initial begin
$dumpfile("first.vcd");
$dumpvars(0,test);
$display("a3\ta2\ta1\ta0\to1\to2");
$monitor("%b\t%b\t%b\t%b\t%b\t%b",ra[3],ra[2],ra[1],ra[0],wo[1],wo[0]);
ra=4'b0001;
#10;
ra=4'b0010;
#10;
ra=4'b0100;
#10;
ra=4'b1000;
end
endmodule
Ques 11: Write a program for 3X8 decoder using behavioural operator
CODE:
module decoder(in, out);
input [2:0]in;
output [7:0]out;
reg [7:0]out;
always @(*)
begin
case (in)
3'b000:out=8'b00000000;
3'b001:out=8'b00000001;
3'b010:out=8'b00000010;
3'b011:out=8'b00000100;
3'b100:out=8'b00001000;
3'b101:out=8'b00010000;
3'b110:out=8'b00100000;
3'b111:out=8'b01000000;
endcase
end
endmodule
module dis ;
reg [2:0]in;
wire [7:0]out;
decoder a1(in, out);
initial
begin
$dumpfile("first.vcd");
$dumpvars(0,dis);
$display("y2 y1 y0 a7 a6 a5 a4 a3 a2 a1 a0");
$monitor("%b %b %b %b %b %b %b %b %b %b
%b",in[2],in[1],in[0],out[7],out[6],out[5],out[4],out[3],out[2],out[1],out[0]);
in=3'b000;
#10 in=3'b000;
#10 in=3'b001;
#10 in=3'b010;
#10 in=3'b011;
#10 in=3'b100;
#10 in=3'b101;
#10 in=3'b110;
#10 in=3'b111;
#10
end
endmodule
Ques 12 Write a program for 1X4 demux using behavioural operator
CODE:
module demux(i,s,o1,o2,o3,o4);
input i;
input [1:0]s;
output o1,o2,o3,o4;
reg o1,o2,o3,o4;
always @(*)
 begin
if(s==2'b00)
begin
o1=i;
o2=0;
o3=0;
o4=0;
end
else if(s==2'b01)
begin
o1=0;
o2=i;
o3=0;
o4=0;
end
else if(s==2'b10)
begin
o1=0;
o2=0;
o3=i;
o4=0;
end
else if(s==2'b11)
begin
o1=0;
o2=0;
o3=0;
o4=i;
end
end
endmodule

module test;
reg ra;
reg [1:0]rs;
wire wo1,wo2,wo3,wo4;
demux m(ra,rs,wo1,wo2,wo3,wo4);
initial begin
$display("I\ts1\ts0\to3\to2\to1\to0");
$monitor("%b\t%b\t%b\t%b\t%b\t%b\t%b",ra,rs[1],rs[0],wo4,wo3,wo2,wo1);
 ra=0;rs=2'b00;
#10;
ra=0;rs=2'b01;
#10;
ra=0;rs=2'b10;
#10;
ra=0;rs=2'b11;
#10;
ra=1;rs=2'b00;
#10;
ra=1;rs=2'b01;
#10;
ra=1;rs=2'b10;
#10;
ra=1;rs=2'b11;
#10;
end
endmodule

Ques 13 Write a program for D flip-flop.

CODE:
module df(d,clk,q,qb);
input d;
input clk;
output q,qb;
reg q,qb;
initial begin q=0;
qb=~q;
end
 always @ (posedge clk)
begin
q=d;
qb=~q;
end
endmodule

module test;
reg d;
reg clk;
reg i;
wire q,qb;
df m(d,clk,q,qb);
initial begin
$display("clk\td\tq\t\qb");
$monitor("%b\t%b\t%b\t%b",clk,d,q,qb);
d=0;
#10;
d=1;
#10;
$finish;
end
initial begin
clk=0;
for(i=0;i<100;i=i+1)
begin
#5; clk=~clk;
end
end
endmodule
Ques 14 Write a program for JK flipflop
CODE:
module jkf(jk,clk,q,qb);
input [1:0] jk;
input clk;
output q,qb;
reg q,qb;
initial q=0;
always @ (posedge clk)
begin
case(jk)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=~q;
endcase
qb=~q;
end
endmodule

module test;
reg [1:0] jk;
reg clk;
reg i;
wire q,qb;
jkf m(jk,clk,q,qb);
initial begin
$display("clk\tj\tk\tq\t\qb");
$monitor("%b\t%b\t%b\t%b\t%b",clk,jk[1],jk[0],q,qb);
jk=2'b00;
#10;
jk=2'b01;
#10;
jk=2'b10;
#10;
jk=2'b11;
#10;
$finish;
end
initial begin
 clk=0;
for(i=0;i<100;i=i+1)
begin
#5; clk=~clk;
end
end
endmodule

Ques 15: Write a program for SR flipflop

CODE:
module srf(sr,clk,q,qb);
input [1:0] sr;
input clk;
output q,qb;
reg q,qb,x;
initial q=0;
always @ (posedge clk)
begin
case(sr)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=x;
endcase
qb=~q;
end
endmodule
module test;
reg [1:0] sr;
reg clk;
reg i;
wire q,qb;
srf m(sr,clk,q,qb);
initial begin
$display("clk\ts\tr\tq\t\qb");
$monitor("%b\t%b\t%b\t%b\t%b",clk,sr[1],sr[0],q,qb);
sr=2'b00;
#10;
sr=2'b01;
#10;
sr=2'b10;
#10;
sr=2'b11;
#10;
$finish;
end
initial begin
clk=0;
for(i=0;i<100;i=i+1)
begin
#5; clk=~clk;
end
end
endmodule

Ques 16: Write a program for T flipflop

module tf(t,clk,q,qb);
input t;
input clk;
output q,qb;
reg q,qb;
initial q=0;
always @ (posedge clk)
begin
case(t)
0:q=q;
1:q=~q;
endcase
qb=~q;
end
endmodule

module test;
reg t;
reg clk;
reg i;
wire q,qb;
tf m(t,clk,q,qb);
initial begin
$display("clk\tt\tq\t\qb");
$monitor("%b\t%b\t%b\t%b",clk,t,q,qb);
t=0;
#10;
t=1;
#10;
$finish;
end
initial begin
clk=0;
for(i=0;i<100;i=i+1)
begin
#5; clk=~clk;
end
end
endmodule
Ques 17: Write a program for BCD to EXCESS
CODE:
module logic1(a,b);
input [3:0]a;
output [3:0]b;
assign b=a+4'b0011;
endmodule

module test;
reg [3:0]a;
wire [3:0]b;
logic1 h1(a,b);
initial
begin
$display("a \t b");
$monitor("%b \t %b",a,b);
a=4'b0000;
#10;
a=4'b1000;
#10;
a=4'b1100;
$finish;
end
endmodule
Ques 18: Write a program for counter
CODE:
module counter(clk,reset,enable,count);
input clk,reset,enable;
output [3:0]count;

reg [3:0]count;
always @(posedge clk)
begin
if(reset==1 && enable==0)
count=4'b0000;
else if(enable==1 && reset==1)
count=count+4'b0001;
end
endmodule

module test;
reg clk,reset,enable;
integer i;
wire [3:0]count;
counter m1(clk,reset,enable,count);
initial begin
$display("Clock\t Reset\t Enable\t Count");
$monitor("%b\t%b\t%b\t%b\t",clk,reset,enable,count);

enable=0;
#1
reset=1;
#3;
enable=1;
#300;
reset=1;
$finish;
end

initial begin
clk=1;
for(i=0;i<100;i=i+1)
#1 clk=~clk;
end
endmodule
Ques 19: Write a program for seven segment display.
CODE:
module sevenseg(in,out);
input [3:0] in;
output [6:0] out;
reg [6:0] out;
always @(*)
begin
case(in)
4'b0000:out=7'b1111110;
4'b0001:out=7'b0110000;
4'b0010:out=7'b1101101;
4'b0011:out=7'b1111001;
4'b0100:out=7'b0110011;
4'b0101:out=7'b1011011;
4'b0110:out=7'b1011111;
4'b0111:out=7'b1110000;
4'b1000:out=7'b1111111;
4'b1001:out=7'b1111011;
4'b1010:out=7'b1110111;
4'b1011:out=7'b0011111;
4'b1100:out=7'b1001110;
4'b1101:out=7'b0111101;
4'b1110:out=7'b1001111;
4'b1111:out=7'b1000111;

endcase
end
endmodule

module test;
reg [3:0] in;
wire [6:0] out;
sevenseg m1(in,out);
initial begin
$display("Input\tOutput");
$monitor("%b\t%b\t",in,out);

in=4'b0000; #10;
in=4'b0001; #10;
in=4'b0011; #10;
in=4'b0100; #10;
in=4'b0101; #10;
in=4'b0110; #10;
in=4'b0111; #10;
in=4'b1000; #10;
in=4'b1001; #10;
in=4'b1010; #10;
in=4'b1011; #10;
in=4'b1100; #10;
in=4'b1101; #10;
in=4'b1110; #10;
in=4'b1111; #10;
end
endmodule