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Assignment 0

The due date for submitting this assignment has passed.

Due on 2019-02-04, 23:59 IST.


As per our records you have not submitted this assignment.

1 point

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(b)

(c)

(d)

No, the answer is incorrect.


Score: 0

Accepted Answers:

(a)

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(d)

No, the answer is incorrect.


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No, the answer is incorrect.


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No, the answer is incorrect.


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No, the answer is incorrect.


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No, the answer is incorrect.


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No, the answer is incorrect.


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No, the answer is incorrect.


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No, the answer is incorrect.


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1 point
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(d)

No, the answer is incorrect.


Score: 0

Accepted Answers:

(b)

End
Assignment 1
The due date for submitting this assignment has passed.

Due on 2019-02-13, 23:59 IST.


Assignment submitted on 2019-02-13, 22:01 IST

1 point

a.

b.

c.

d.

No, the answer is incorrect.


Score: 0

Accepted Answers:
d.

1 point

a.

b.

c.

d.

Yes, the answer is correct.


Score: 1

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b.

1 point
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b.

c.

d.

No, the answer is incorrect.


Score: 0

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a.

1 point

a.
b.

c.

d.

Yes, the answer is correct.


Score: 1

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c.

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b.

c.

d.

Yes, the answer is correct.


Score: 1
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b.

1 point

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b.

c.

d.

Yes, the answer is correct.


Score: 1

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b.

c.

d.

No, the answer is incorrect.


Score: 0

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1 point
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b.

c.

d.

Yes, the answer is correct.


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1 point

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b.
c.

d.

Yes, the answer is correct.


Score: 1

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b.

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d.

Yes, the answer is correct.


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Yes, the answer is correct.


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d.

Yes, the answer is correct.


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Yes, the answer is correct.


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No, the answer is incorrect.


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No, the answer is incorrect.


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b.

Previous Page
End

Assignment 2
The due date for submitting this assignment has passed.

Due on 2019-02-13, 23:59 IST.


Assignment submitted on 2019-02-13, 21:44 IST
1 point

Number of valid bit patterns in 8085 instructions is?

a) 210

b) 247

c) 256

d) 246

Yes, the answer is correct.


Score: 1

Accepted Answers:

d) 246

1 point

A program that uses mnemonics is called

a) Object program

b) Fetch cycle

c) Assembly language

d) Micro instruction

Yes, the answer is correct.


Score: 1

Accepted Answers:
c) Assembly language

1 point

After the execution of the instruction XRA A the contents of A, carry and zero flags are respectively

a) A = 00, CY = 1, Z = 1

b) A = 00, CY = 0, Z = 0

c) A = 00, CY = 1, Z = 0

d) A = 00, CY = 0, Z = 1

Yes, the answer is correct.


Score: 1

Accepted Answers:

d) A = 00, CY = 0, Z = 1

1 point

In an 8085 processor, suppose the accumulator content is FFH and the carry flag is 0. What will be the content
of the accumulator after RAL and RLC instructions?

a) Both FFH

b) Both FEH

c) RAL - FFH, RLC – FEH

d) RAL - FEH, RLC – FFH

No, the answer is incorrect.


Score: 0
Accepted Answers:

d) RAL - FEH, RLC – FFH

1 point

Which register pair of 8085 is NOT accepted in LDAX instruction?

a) BC

b) DE

c) HL

d) All pairs are acceptable

No, the answer is incorrect.


Score: 0

Accepted Answers:

c) HL

1 point

In 8085, ALE signal is activated during

a) Code access

b) Data access

c) Both code and data accesses

d) Idle cycles
No, the answer is incorrect.
Score: 0

Accepted Answers:

c) Both code and data accesses

1 point

“INR M” instruction which register pair act as memory pointer?

a) BC

b) DE

c) HL

d) Any of BC, DE or HL

No, the answer is incorrect.


Score: 0

Accepted Answers:

c) HL

1 point

If A register of 8085 contains 4EH, the parity flag is

a) Reset

b) Set

c) Not decidable
d) Don't care

Yes, the answer is correct.


Score: 1

Accepted Answers:

b) Set

1 point

In 8085 ALE signal is generated in clock cycle

a) T1

b) T2

c) T1 and T2

d) T3

Yes, the answer is correct.


Score: 1

Accepted Answers:

a) T1

1 point

What is the difference between MOV and MVI instructions of an 8085 microprocessor?

a) MOV instruction copies data between two registers, whereas MVI instruction transfers an
immediate data into a register.

b) MVI instruction copies data between two registers, whereas MOV instruction transfers an
immediate data into a register.
c) Both MOV and MVI instructions copy data between two registers.

d) Both MOV and MVI instructions transfer an immediate data into a register.

Yes, the answer is correct.


Score: 1

Accepted Answers:

a) MOV instruction copies data between two registers, whereas MVI instruction transfers an immediate data
into a register.

1 point

Which of the following relations among bits, nibbles, bytes, and words for an 8086 microprocessor is a valid
one?

a) 1 byte = 2 nibbles; 1 word = 2 bytes; 1 long-word = 8 nibbles; 1 nibble = 4 bits

b) 1 byte = 2 nibbles; 1 word = 2 nibbles; 1 nibble = 2 bytes; 1 long-word = 4 bytes

c) 1 byte = 8 bits; 1 nibble = 4 bits; 1 word = 2 nibbles; 1 long-word = 4 nibbles

d) 1 byte = 4 bits; 1 nibble = 2 bytes; 1 word = 4 nibbles; 1 long-word = 8 bytes

Yes, the answer is correct.


Score: 1

Accepted Answers:

a) 1 byte = 2 nibbles; 1 word = 2 bytes; 1 long-word = 8 nibbles; 1 nibble = 4 bits

1 point

Suppose initially the accumulator content is 95 H and carry flag is 0. What will be the contents of accumulator
and carry flag after the execution of the instruction RAR? (H stands for hexadecimal representation)
a) A = 4A H, Carry flag = 1

b) A = CA H, Carry flag = 0

c) A = CA H, Carry flag = 1

d) A = 2A H, Carry flag = 1

No, the answer is incorrect.


Score: 0

Accepted Answers:

a) A = 4A H, Carry flag = 1

1 point

Suppose initially the accumulator content is 95H and carry flag is 0. What will be the contents of accumulator
and carry flag after the execution of the instruction RLC? (H stands for hexadecimal representation)

a) A = 2A H, Carry flag = 1

b) A = 2A H, Carry flag = 0

c) A = 2B H, Carry flag = 0

d) A = 2B H, Carry flag = 1

No, the answer is incorrect.


Score: 0

Accepted Answers:

d) A = 2B H, Carry flag = 1
1 point

Which of the following instructions will multiply the contents of the accumulator by 2?

a) ADD A

b) RAR

c) XRA A

d) ANA A

Yes, the answer is correct.


Score: 1

Accepted Answers:

a) ADD A

1 point

Which of the following set of instructions moves the contents of memory location 3500H to register C? The
contents of memory location 3500 H is 46 H.

a) LXI H, 3500 H
MOV M, C

b) LXI C, 3500 H
MOV C, M

c) LXI C, 46 H
MOV C, M

d) LXI H, 3500 H
MOV C, M
No, the answer is incorrect.
Score: 0

Accepted Answers:

d) LXI H, 3500 H
MOV C, M

Assignment 3
1 point

In a 8085 processor, suppose the DE register pair contains value 2. In the following code, how many times is
the JNZ instruction executed?
....
....
Loop: DCX D
JNZ Loop

(A) 1 or infinity

(B) 2 or infinity

(C) Infinity

(D) Cannot be determined

No, the answer is incorrect.


Score: 0

Accepted Answers:

(A) 1 or infinity

1 point
In a 8085 processor, suppose the D register contains value 2. In the following code, how many times is the
JNZ instruction executed?

Loop: DCR D
JNZ Loop

(A) 1

(B) 2

(C) Infinity

(D) Cannot be determined

No, the answer is incorrect.


Score: 0

Accepted Answers:

(B) 2

1 point

8085 instruction that is equivalent to the non-existent instruction "LDAX H" is

(A) LDAX B

(B) LDAX D

(C) MOV A, M

(D) All of the other three options

No, the answer is incorrect.


Score: 0
Accepted Answers:

(C) MOV A, M

1 point

Which of the following is NOT a valid 8085 instruction?

(A) PUSH A

(B) PUSH B

(C) PUSH C

(D) PUSH D

No, the answer is incorrect.


Score: 0

Accepted Answers:

(C) PUSH C

1 point

Which of the following is NOT a valid 8085 instruction?

(A) POP A

(B) POP B

(C) POP C

(D) POP D
No, the answer is incorrect.
Score: 0

Accepted Answers:

(C) POP C

1 point

Suppose that the stack pointer (SP) of 8085 contains 2004H. If the instruction "PUSH PSW" is used, the value
of SP will be

(A) 2002H

(B) 2000H

(C) 2006H

(D) 2008H

No, the answer is incorrect.


Score: 0

Accepted Answers:

(A) 2002H

1 point

Suppose that the stack pointer (SP) of 8085 contains 2000H. If the instruction "POP D" is used, the value of
SP will be

(A) 2002H

(B) 2000H

(C) 2006H
(D) 2008H

No, the answer is incorrect.


Score: 0

Accepted Answers:

(A) 2002H

1 point

Interrupt vector table of 8085 ranges over

(A) 0010H-0100H

(B) 0000H-FFFFH

(C) 0000H-00FFH

(D) 0100H-01FFH

No, the answer is incorrect.


Score: 0

Accepted Answers:

(C) 0000H-00FFH

1 point

Number of bytes reserved for interrupt vector table of 8085 is

(A) 16

(B) 128
(C) 256

(D) 512

No, the answer is incorrect.


Score: 0

Accepted Answers:

(C) 256

1 point

Suppose that the stack pointer (SP) of 8085 contains 2004H. After executing a CALL instruction, the value of
SP will be

(A) 2002H

(B) 2000H

(C) 2006H

(D) 2008H

No, the answer is incorrect.


Score: 0

Accepted Answers:

(A) 2002H

1 point

The Program Status Word register pair in an 8085 microprocessor is realized as the pair of which of the
following registers?

(A) Program Counter and Accumulator


(B) Program Counter and Stack Pointer

(C) Accumulator and Flag Register

(D) Program Counter and Flag Register

No, the answer is incorrect.


Score: 0

Accepted Answers:

(C) Accumulator and Flag Register

1 point

How many bytes does the following set of instructions occupy?


MVI A, 35H
MVI B, 23H
ADD B

(A) Three bytes

(B) Six bytes

(C) Five bytes

(D) Four bytes

No, the answer is incorrect.


Score: 0

Accepted Answers:

(C) Five bytes

1 point
Determine the operand type of the following 8085 instruction.
ADD C

(A) Implied operand

(B) Immediate data

(C) Memory address

(D) Register

No, the answer is incorrect.


Score: 0

Accepted Answers:

(D) Register

1 point

What are the status of the ZERO flag and the contents of the accumulator after the execution of the following
8085 assembly code? Assume that contents of all other registers and memory locations are unknown.
MVI A, 65H
MVI B, 32H
CMP B

(A) 0, 65H

(B) 1, 65H

(C) 0, 00H

(D) 1, 00H

No, the answer is incorrect.


Score: 0
Accepted Answers:

(A) 0, 65H

1 point

If an 8085 microprocessor works at a frequency of 1 MHz, determine the total delay of the following sequence
of instructions (in seconds).
MVI A, 0FH
MVI B, 0FH
L1: DCR B
JNZ L1

(A) 224 μs

(B) 222 μs

(C) 223 μs

(D) 221 μs

No, the answer is incorrect.


Score: 0

Accepted Answers:

(D) 221 μs

Unit 6 - Week 4
Register for Certification exam

Course outline

How to access the portal

Week 0

Week 1

Week 2
Week 3

Week 4


Lecture 17: 8085 Microprocessors (Contd.)



Lecture 18: 8085 Microprocessors (Contd.)



Lecture 19: 8085 Microprocessors (Contd.)



Lecture 20: 8085 Microprocessors (Contd.)



Lecture 21: 8085 Microprocessors (Contd.)



Week 4 : Lecture Material



Quiz : Assignment 4



Feedback for Week 4


Week 5

Week 6

Week 7

Week 8

Week 9

Week 10

Week 11

Week 12

DOWNLOAD VIDEOS

Solution

Assignment 4
The due date for submitting this assignment has passed.

Due on 2019-02-27, 23:59 IST.


As per our records you have not submitted this assignment.

1 point

With respect to 8085, match Column X with Column Y.


Column X Column Y
1. INTR 1. Non-maskable
2. RST 5.5 2. Maskable
3. TRAP 3. Software
4. RST 1 4. Non-vectored

a) X1-Y2, X2-Y1, X3-Y4, X4-Y3

b) X1-Y4, X2-Y2, X3-Y1, X4-Y3

c) X1-Y3, X2-Y2, X3-Y4, X4-Y1

d) X1-Y1, X2-Y4, X3-Y2, X4-Y3

No, the answer is incorrect.


Score: 0
Accepted Answers:

b) X1-Y4, X2-Y2, X3-Y1, X4-Y3

1 point

Interrupt vector table of 8085 ranges over

a) 0010H-0100H

b) 0000H-FFFFH

c) 0000H-00FFH

d) 0100H-01FFH

No, the answer is incorrect.


Score: 0

Accepted Answers:

c) 0000H-00FFH

1 point

With respect to 8085, match Column X with Column Y.


Column X Column Y
1. RST 5.5 1. Edge-triggered
2. RST 6 2. Level-triggered
3. RST 7.5 3. Edge and level triggered
4. RST 4.5 4. Software

a) X1-Y3, X2-Y1, X3-Y4, X4-Y2

b) X1-Y4, X2-Y2, X3-Y1, X4-Y3

c) X1-Y2, X2-Y4, X3-Y1, X4-Y3


d) X1-Y3, X2-Y4, X3-Y2, X4-Y1

No, the answer is incorrect.


Score: 0

Accepted Answers:

c) X1-Y2, X2-Y4, X3-Y1, X4-Y3

1 point

To be surely sensed, in 8085, INTR must be high for number of T-states equal to

a) 1.5

b) 17.5

c) 18.5

d) 19.5

No, the answer is incorrect.


Score: 0

Accepted Answers:

b) 17.5

1 point

Number of bytes reserved for interrupt vector table of 8085 is

a) 16

b) 128
c) 256

d) 512

No, the answer is incorrect.


Score: 0

Accepted Answers:

c) 256

1 point

The instruction RST 7 is a:

a) Restart instruction that begins the execution of a program.

b) One-byte call to the memory address 0038H.

c) One-byte call to the memory address 0007H.

d) Hardware interrupt.

No, the answer is incorrect.


Score: 0

Accepted Answers:

b) One-byte call to the memory address 0038H.

1 point

The opcode of the instruction RST 6 in an 8085 microprocessor is:

a) F7
b) 7F

c) FE

d) EF

No, the answer is incorrect.


Score: 0

Accepted Answers:

a) F7

1 point

What does the following set of instructions do in an 8085 microprocessor?


EI
MVI A, 08H
SIM

a) Resets the 7.5 interrupt in an 8085 system.

b) Enables all the interrupts in an 8085 system.

c) Enables the 5.5 interrupt and masks all other interrupts in an 8085 system.

d) Enables the 6.5 interrupt and masks all other interrupts in an 8085 system.

No, the answer is incorrect.


Score: 0

Accepted Answers:

b) Enables all the interrupts in an 8085 system.

1 point
After the execution of instruction RIM, the accumulator contained 49H. Which of the following statement is
TRUE in this case?

a) RST 5.5 is enabled and is pending.

b) RST 6.5 is enabled and is pending.

c) RST 7.5 is enabled and is pending.

d) None of the given options.

No, the answer is incorrect.


Score: 0

Accepted Answers:

c) RST 7.5 is enabled and is pending.

1 point

Which of the following statement is true in the context of Simplex, Half-duplex, and Full-duplex transmission?

Statement I: Both Half-duplex and Full-duplex are bidirectional communication and in both the cases,
data flows in two directions at the same time

Statement II: Both Half-duplex and Full-duplex are bidirectional communication where data flows in
two directions in Full-duplex; however, data flows in one direction in Half-duplex

Statement III: Simplex and Half-duplex requires one wire for data transmission

Statement IV: Both Half-duplex and Full-duplex require two wires for data transmission

a) I and III are true

b) Only II is true

c) Only IV is true
d) II and III are true

No, the answer is incorrect.


Score: 0

Accepted Answers:

d) II and III are true

1 point

Which of these are not error checking methods?

a) Parity Check

b) Checksum

c) Cyclic Redundancy Check

d) Huffman Code

No, the answer is incorrect.


Score: 0

Accepted Answers:

d) Huffman Code

1 point

Which of the following statement is correct:

Statement I: Asynchronous Serial Data transfer is used for data transfer rates ≤ 20K bits/second.
Statement II: Synchronous Serial Data transfer is used for data transfer rates ≥ 20K bits/second.

a) Only Statement I
b) Only Statement II

c) Both Statement I and II

d) None of the above

No, the answer is incorrect.


Score: 0

Accepted Answers:

c) Both Statement I and II

1 point

To which pin external DMA controller sends a control signal to an 8085 microprocessor.

a) HOLD

b) HLDA

c) INTR

d) INTA

No, the answer is incorrect.


Score: 0

Accepted Answers:

a) HOLD

1 point

The READY pin of 8085 is used


a) By the microprocessor to tell the device when it is ready

b) By the devices to tell the microprocessor when it is ready

c) For input/output operations

d) All of the other three options

No, the answer is incorrect.


Score: 0

Accepted Answers:

b) By the devices to tell the microprocessor when it is ready

1 point

Which of the following is the correct ordering of the priority of the interrupts in 8085

a) TRAP > RST 7.5 > RST 6.5 > RST 5.5

b) RST 7.5 > RST 6.5 > RST 5.5 > TRAP

c) TRAP > RST 5.5 > RST 6.5 > RST 7.5

d) RST 5.5 > RST 6.5 > RST 7.5 > TRAP

No, the answer is incorrect.


Score: 0

Accepted Answers:

a) TRAP > RST 7.5 > RST 6.5 > RST 5.5

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Courses » Microprocessors And Microcontrollers

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Unit 7 - Week 5
Register for Certification exam

Course outline

How to access the portal

Week 0

Week 1
Week 2

Week 3

Week 4

Week 5


Lecture 22: 8085 Microprocessors (Contd.)



Lecture 23: 8051 Microcontroller



Lecture 24: 8051 Microcontroller(Contd.)



Lecture 25: 8051Microcontroller (Contd.)



Lecture 26: 8051 Microcontroller(Contd.)



Week 5 Lecture Material



Quiz : Assignment 5



Feedback for Week 5

Week 6

Week 7

Week 8

Week 9

Week 10

Week 11

Week 12

DOWNLOAD VIDEOS

Solution

Assignment 5
The due date for submitting this assignment has passed.

Due on 2019-03-06, 23:59 IST.


Assignment submitted on 2019-03-04, 21:09 IST

1 point

If the crystal connected to 8051 is of 5 MHz, length of machine cycle is

a) 1.4 microseconds

b) 2.4 microseconds

c) 3.4 microseconds

d) 2.0 microseconds

Yes, the answer is correct.


Score: 1

Accepted Answers:
b) 2.4 microseconds

1 point

Which port of 8051 is dedicated exclusively for I/O operations?

a) P0

b) P1

c) P2

d) P3

No, the answer is incorrect.


Score: 0

Accepted Answers:

b) P1

1 point

In the bit-addressable RAM of 8051, among the byte addresses 88H and 89H

a) Both are bit-addressable

b) Only 88H is bit-addressable

c) Only 89H is bit-addressable

d) None is bit-addressable

No, the answer is incorrect.


Score: 0
Accepted Answers:

b) Only 88H is bit-addressable

1 point

Which port of 8051 needs external pull-up resistances to be connected?

a) P0

b) P1

c) P2

d) P3

Yes, the answer is correct.


Score: 1

Accepted Answers:

a) P0

1 point

If RS0 = 1 and RS1 = 0, the register bank address range is

a) 00H-07H

b) 08H-0FH

c) 10H-17H

d) 18H-1FH
Yes, the answer is correct.
Score: 1

Accepted Answers:

b) 08H-0FH

1 point

If RS0 = 0 and RS1 = 0, the register bank address range is

a) 00H-07H

b) 08H-0FH

c) 10H-17H

d) 18H-1FH

Yes, the answer is correct.


Score: 1

Accepted Answers:

a) 00H-07H

1 point

In 8051, compared to on-chip RAM locations, register access is

a) Faster

b) Slower

c) Same speed
d) Not comparable

No, the answer is incorrect.


Score: 0

Accepted Answers:

c) Same speed

1 point

In the bit-addressable RAM of 8051, among the byte addresses 99H and 89H

a) Both are bit-addressable

b) Only 88H is bit-addressable

c) Only 89H is bit-addressable

d) None is bit-addressable

Yes, the answer is correct.


Score: 1

Accepted Answers:

d) None is bit-addressable

1 point

The width of the Program Counter in an 8051 microcontroller is

a) 8 bits

b) 16 bits
c) 32 bits

d) None of the given options

Yes, the answer is correct.


Score: 1

Accepted Answers:

b) 16 bits

1 point

The number of timers in an 8051 microcontroller is

a) 2

b) 5

c) 1

d) 0

Yes, the answer is correct.


Score: 1

Accepted Answers:

a) 2

1 point

The size of On-Chip ROM in an 8051 microcontroller is

a) 4k Bytes
b) 8k Bytes

c) 16k Bytes

d) 32k Bytes

Yes, the answer is correct.


Score: 1

Accepted Answers:

a) 4k Bytes

1 point

Which of the following pins is the external data memory write strobe in 8051?

a) P3.4

b) P3.5

c) P3.6

d) P3.7

Yes, the answer is correct.


Score: 1

Accepted Answers:

c) P3.6

1 point

Which of the following two pins provide external clock to 8051 microcontroller?
a) Pin 1 and 2

b) Pin 10 and 11

c) Pin 18 and 19

d) Pin 20 and 40

Yes, the answer is correct.


Score: 1

Accepted Answers:

c) Pin 18 and 19

1 point

Which of the following task is performed by ALE in 8051?

a) It latches the Address inputs at Port 0 and port 1

b) It latches the Address inputs at Port 0 and port 2

c) It latches the Address outputs at Port 0 and port 1

d) It latches the Address outputs at Port 0 and port 2

No, the answer is incorrect.


Score: 0

Accepted Answers:

d) It latches the Address outputs at Port 0 and port 2

1 point
If the crystal connected to 8051 is of 15MHz, length of machine cycle is

a) 0.8 microseconds

b) 0.6 microseconds

c) 1.0 microseconds

d) 1.2 microseconds

Yes, the answer is correct.


Score: 1

Accepted Answers:

a) 0.8 microseconds

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Unit 7 - Week 5
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Course outline

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Week 0

Week 1

Week 2

Week 3

Week 4

Week 5


Lecture 22: 8085 Microprocessors (Contd.)



Lecture 23: 8051 Microcontroller



Lecture 24: 8051 Microcontroller(Contd.)



Lecture 25: 8051Microcontroller (Contd.)



Lecture 26: 8051 Microcontroller(Contd.)



Week 5 Lecture Material



Quiz : Assignment 5



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Solution

Assignment 5
The due date for submitting this assignment has passed.

Due on 2019-03-06, 23:59 IST.


Assignment submitted on 2019-03-04, 21:09 IST

1 point

If the crystal connected to 8051 is of 5 MHz, length of machine cycle is

a) 1.4 microseconds

b) 2.4 microseconds

c) 3.4 microseconds

d) 2.0 microseconds

Yes, the answer is correct.


Score: 1

Accepted Answers:

b) 2.4 microseconds

1 point

Which port of 8051 is dedicated exclusively for I/O operations?

a) P0
b) P1

c) P2

d) P3

No, the answer is incorrect.


Score: 0

Accepted Answers:

b) P1

1 point

In the bit-addressable RAM of 8051, among the byte addresses 88H and 89H

a) Both are bit-addressable

b) Only 88H is bit-addressable

c) Only 89H is bit-addressable

d) None is bit-addressable

No, the answer is incorrect.


Score: 0

Accepted Answers:

b) Only 88H is bit-addressable

1 point

Which port of 8051 needs external pull-up resistances to be connected?


a) P0

b) P1

c) P2

d) P3

Yes, the answer is correct.


Score: 1

Accepted Answers:

a) P0

1 point

If RS0 = 1 and RS1 = 0, the register bank address range is

a) 00H-07H

b) 08H-0FH

c) 10H-17H

d) 18H-1FH

Yes, the answer is correct.


Score: 1

Accepted Answers:

b) 08H-0FH

1 point
If RS0 = 0 and RS1 = 0, the register bank address range is

a) 00H-07H

b) 08H-0FH

c) 10H-17H

d) 18H-1FH

Yes, the answer is correct.


Score: 1

Accepted Answers:

a) 00H-07H

1 point

In 8051, compared to on-chip RAM locations, register access is

a) Faster

b) Slower

c) Same speed

d) Not comparable

No, the answer is incorrect.


Score: 0

Accepted Answers:

c) Same speed
1 point

In the bit-addressable RAM of 8051, among the byte addresses 99H and 89H

a) Both are bit-addressable

b) Only 88H is bit-addressable

c) Only 89H is bit-addressable

d) None is bit-addressable

Yes, the answer is correct.


Score: 1

Accepted Answers:

d) None is bit-addressable

1 point

The width of the Program Counter in an 8051 microcontroller is

a) 8 bits

b) 16 bits

c) 32 bits

d) None of the given options

Yes, the answer is correct.


Score: 1

Accepted Answers:
b) 16 bits

1 point

The number of timers in an 8051 microcontroller is

a) 2

b) 5

c) 1

d) 0

Yes, the answer is correct.


Score: 1

Accepted Answers:

a) 2

1 point

The size of On-Chip ROM in an 8051 microcontroller is

a) 4k Bytes

b) 8k Bytes

c) 16k Bytes

d) 32k Bytes

Yes, the answer is correct.


Score: 1
Accepted Answers:

a) 4k Bytes

1 point

Which of the following pins is the external data memory write strobe in 8051?

a) P3.4

b) P3.5

c) P3.6

d) P3.7

Yes, the answer is correct.


Score: 1

Accepted Answers:

c) P3.6

1 point

Which of the following two pins provide external clock to 8051 microcontroller?

a) Pin 1 and 2

b) Pin 10 and 11

c) Pin 18 and 19

d) Pin 20 and 40
Yes, the answer is correct.
Score: 1

Accepted Answers:

c) Pin 18 and 19

1 point

Which of the following task is performed by ALE in 8051?

a) It latches the Address inputs at Port 0 and port 1

b) It latches the Address inputs at Port 0 and port 2

c) It latches the Address outputs at Port 0 and port 1

d) It latches the Address outputs at Port 0 and port 2

No, the answer is incorrect.


Score: 0

Accepted Answers:

d) It latches the Address outputs at Port 0 and port 2

1 point

If the crystal connected to 8051 is of 15MHz, length of machine cycle is

a) 0.8 microseconds

b) 0.6 microseconds

c) 1.0 microseconds
d) 1.2 microseconds

Yes, the answer is correct.


Score: 1

Accepted Answers:

a) 0.8 microseconds

Assignment 6
1 point

In 8051 microcontroller, which of the following instruction means “Decrement register R0 and then jump to
address ‘LOOP’ if not zero” ?

(A) DJNZ R0, LOOP

(B) CJNE R0, #4, LOOP

(C) DJNE 52H, LOOP

(D) DJNZ @R0, LOOP

Yes, the answer is correct.


Score: 1

Accepted Answers:

(A) DJNZ R0, LOOP

1 point

With respect to an 8051 microcontroller, match Column X with Column Y.


Column X Column Y
1. MOV A, #25H 1. Indexed Addressing Mode
2. MOV R6, A 2. Register Indirect Addressing Mode
3. MOV 56H, A 3. Register Addressing Mode
4. MOV @R0, #3 4. Direct Addressing Mode
5. MOVC A, @A+DPTR 5. Immediate Addressing Mode

(A) X1 – Y1, X2 – Y2, X3 – Y3, X4 – Y4, X5 – Y5

(B) X1 – Y2, X2 – Y3, X3 – Y4, X4 – Y5, X5 – Y1

(C) X1 – Y5, X2 – Y3, X3 – Y4, X4 – Y2, X5 – Y1

(D) X1 – Y5, X2 – Y4, X3 – Y3, X4 – Y2, X5 – Y1

Yes, the answer is correct.


Score: 1

Accepted Answers:

(C) X1 – Y5, X2 – Y3, X3 – Y4, X4 – Y2, X5 – Y1

1 point

Which of the following flags are affected by the instruction ‘DIV AB’ of an 8051 microcontroller?

(A) OV, CY, AC

(B) OV, AC

(C) OV, CY

(D) CY, AC

Yes, the answer is correct.


Score: 1
Accepted Answers:

(C) OV, CY

1 point

Bit address 42H belongs to the byte address in 8051 RAM

(A) 26H

(B) 28H

(C) 2AH

(D) None of the other options

Yes, the answer is correct.


Score: 1

Accepted Answers:

(B) 28H

1 point

Bit address 67H belongs to the byte address in 8051 RAM

(A) 2CH

(B) 2DH

(C) 2FH

(D) None of the other options


Yes, the answer is correct.
Score: 1

Accepted Answers:

(A) 2CH

1 point

In a 8051 program, it is required to configure the least significant four bits of port P0 as input. The statement
for this is

(A) MOV P0, #0FH

(B) MOV P0, 0FH

(C) MOV P0, #F0H

(D) MOV P0, 0F0H

Yes, the answer is correct.


Score: 1

Accepted Answers:

(A) MOV P0, #0FH

1 point

What is the value of the MSB bits 4-7 of the memory location specified by R0 after the following set of
instructions are executed?
MOV @R0, #04H
MOV A, #11H
XCHD A, @R0

(A) 0H

(B) 4H
(C) 5H

(D) 1H

Yes, the answer is correct.


Score: 1

Accepted Answers:

(A) 0H

1 point

In a 8051 program, it is required to configure the MSB and LSB of port P0 as input. The statement for this can
be

(A) MOV P0, #81H

(B) MOV P0, #FFH

(C) MOV P0, #8FH

(D) All of the three options

No, the answer is incorrect.


Score: 0

Accepted Answers:

(D) All of the three options

1 point

Which of the following is NOT a valid status word bit in 8051?

(A) Z
(B) OV

(C) CY

(D) AC

Yes, the answer is correct.


Score: 1

Accepted Answers:

(A) Z

1 point

Which of the following is NOT a valid 8051 instruction?

(A) MOV R4, R7

(B) MOV A, R7

(C) MOV A, 7

(D) MOV 4, 7

Yes, the answer is correct.


Score: 1

Accepted Answers:

(A) MOV R4, R7

1 point

In 8051 if GATE of TMOD register is set, the timer run can be controlled by
(A) Only INT

(B) Only TR

(C) Both INT and TR

(D) None of INT or TR

Yes, the answer is correct.


Score: 1

Accepted Answers:

(C) Both INT and TR

1 point

The size of offset in AJMP instruction of 8051 is

(A) 11 bits

(B) 12 bits

(C) 13 bits

(D) 14 bits

Yes, the answer is correct.


Score: 1

Accepted Answers:

(A) 11 bits

1 point
What can one infer from the instruction ‘MOV TMOD, #02H’ in an 8051 microcontroller?

(A) Set Timer 1 in 16-bit timer operating mode

(B) Set Timer 0 in 16-bit timer operating mode

(C) Set Timer 1 in 8-bit auto reload timer mode

(D) Set Timer 0 in 8-bit auto reload timer mode

Yes, the answer is correct.


Score: 1

Accepted Answers:

(D) Set Timer 0 in 8-bit auto reload timer mode

1 point

In 8051 microcontroller, which of the following instruction would force the most significant two bits of PSW to
be high?

(A) anl PSW, #0x18

(B) orl PSW, #0x18

(C) anl PSW, #0xC0

(D) orl PSW, #0xC0

Yes, the answer is correct.


Score: 1

Accepted Answers:
(D) orl PSW, #0xC0

1 point

How many times the ‘RL’ instruction needs to be executed, in order to mimic the ‘SWAP’ instruction in an 8051
microcontroller?

(A) 24

(B) 26

(C) 28

(D) 30

Yes, the answer is correct.


Score: 1

Accepted Answers:

(C) 28

Assignment 7
1 point

In 8051, timer 1 run can be controlled by

(A) TR1

(B) TF1

(C) IE1

(D) IT1
Yes, the answer is correct.
Score: 1

Accepted Answers:

(A) TR1

1 point

The delay produced by 8051 Mode 1 timer with TH=FF and TL=00, crystal frequency 11.0592MHz is

(A) 277.00 microsecond

(B) 277.76 microsecond

(C) 278.00 microsecond

(D) 278.76 microsecond

Yes, the answer is correct.


Score: 1

Accepted Answers:

(B) 277.76 microsecond

1 point

In 8051, the instruction "MOV IP, #00011000" sets priorities of interrupts as

(A) RI + TI > TF1 > INT0 > TF0 > INT1

(B) TF1 > RI + TI > INT0 > TF0 > INT1

(C) INT0 > TF0 > INT1 > TF1 > RI + TI


(D) INT0 > RI +TI > TF1 > TF0 > INT1

No, the answer is incorrect.


Score: 0

Accepted Answers:

(B) TF1 > RI + TI > INT0 > TF0 > INT1

1 point

The 8051 instructions to start and stop Timer 0 are respectively

(A) SETB TR0, CLR TR0

(B) SETB TR0, CLR TF0

(C) SETB TF0, CLR TR0

(D) SETB TF0, CLR TF0

Yes, the answer is correct.


Score: 1

Accepted Answers:

(A) SETB TR0, CLR TR0

1 point

8051 counters in mode 2 are

(A) 8-bit

(B) 16-bit
(C) 12-bit

(D) Size programmable

No, the answer is incorrect.


Score: 0

Accepted Answers:

(A) 8-bit

1 point

The delay produced by 8051 Mode 1 timer with TH=F0 and TL=00, crystal frequency 11.0592MHz is

(A) 4444.16 microsecond

(B) 2444.16 microsecond

(C) 3444.16 microsecond

(D) 5444.16 microsecond

Yes, the answer is correct.


Score: 1

Accepted Answers:

(A) 4444.16 microsecond

1 point

Which register in an 8051 microcontroller contains the SMOD bit?

(A) SBUF
(B) TMOD

(C) PCON

(D) TCON

Yes, the answer is correct.


Score: 1

Accepted Answers:

(C) PCON

1 point

In 8051, the instruction "MOV IP, #00000101" sets priorities of interrupts as

(A) RI + TI > TF1 > INT0 > TF0 > INT1

(B) TF1 > RI + TI > INT0 > TF0 > INT1

(C) INT0 > INT1 > TF0 > TF1 > RI + TI

(D) INT1 > INT0 > TF1 > TF0 > RI + TI

No, the answer is incorrect.


Score: 0

Accepted Answers:

(C) INT0 > INT1 > TF0 > TF1 > RI + TI

1 point

In Timer Control Register of 8051, Mode 1 uses


(A) 8-bit timer

(B) 16-bit timer

(C) 13-bit timer

(D) 32-bit timer

Yes, the answer is correct.


Score: 1

Accepted Answers:

(B) 16-bit timer

1 point

What is the default interrupt priority in 8051?

(A) INT0 > TF0 > RI + TI> INT1 > TF1

(B) INT01> TF1 > RI + TI> INT0 > TF0

(C) INT0 > TF0 > INT1 > TF1 > RI + TI

(D) INT1> TF1 > INT0 > TF0 > RI + TI

Yes, the answer is correct.


Score: 1

Accepted Answers:

(C) INT0 > TF0 > INT1 > TF1 > RI + TI

1 point
Which bits in the PCON register of an 8051 microcontroller correspond to the idle and power-down modes?

(A) PCON.0 – Idle mode, PCON.1 – Power-down mode

(B) PCON.1 – Idle mode, PCON.0 – Power-down mode

(C) PCON.0 – Idle mode/Power-down mode

(D) PCON.1 – Idle mode/Power-down mode

No, the answer is incorrect.


Score: 0

Accepted Answers:

(A) PCON.0 – Idle mode, PCON.1 – Power-down mode

1 point

In Serial control (SCON) Register, SCON.5 is used to

(A) Transmit interrupt flag

(B) Receive interrupt flag

(C) Used for multi processor communication

(D) Receive enable

Yes, the answer is correct.


Score: 1

Accepted Answers:

(C) Used for multi processor communication


1 point

In idle mode of power control register, which of the following is not true?

(A) All of registers , ports and internal RAM maintain their data

(B) The ALE and PSEN output are held low

(C) The internal CPU clock is gated off

(D) Interrupt, Timer, and Serial Port functions act normally

Yes, the answer is correct.


Score: 1

Accepted Answers:

(B) The ALE and PSEN output are held low

1 point

The following program generates a square wave on pin P1.5 Using timer 1. Find the frequency.
Consider XTAL = 11.0592 MHz.
MOV TMOD, #10H
AGAIN: MOV TL1, #26H
MOV TH1, #71H
SETB TR1
BACK: JNB TF1, BACK
CLR TR1
CPL P1.5
CLR TF1
SJMP AGAIN

(A) 12.087 Hz

(B) 12.601 Hz

(C) 13.504 Hz
(D) 14.705 Hz

Yes, the answer is correct.


Score: 1

Accepted Answers:

(B) 12.601 Hz

1 point

In power down mode of power control register which of the following is not true?

(A) All functions are stopped, the contents of the on-chip RAM and Special Function Registers are
lost

(B) The ALE and PSEN output are held low

(C) Last instruction executed before going into the power down mode

(D) The on-chip oscillator is stopped

No, the answer is incorrect.


Score: 0

Accepted Answers:

(A) All functions are stopped, the contents of the on-chip RAM and Special Function Registers are lost

Assignment 8
1 point

Which register bank of R0 – R7 do we have access to when the 8051 is powered up?

a) Bank 0
b) Bank 1

c) Bank 2

d) Bank 3

Yes, the answer is correct.


Score: 1

Accepted Answers:

a) Bank 0

1 point

Determine which of the register banks of R0 – R7 is selected if the following instruction is executed just after
powering an 8051 up: SETB PSW.3

a) Bank 0

b) Bank 1

c) Bank 2

d) Bank 3

No, the answer is incorrect.


Score: 0

Accepted Answers:

b) Bank 1

1 point

Which of the following statements is FALSE regarding an 8051?


a) The stack pointer in the 8051 is only eight bits wide.

b) When the 8051 is powered up, the SP register contains the value 07.

c) The storing of a CPU register in the stack is called a PUSH.

d) As we push data onto the stack, the stack pointer is decremented by one.

Yes, the answer is correct.


Score: 1

Accepted Answers:

d) As we push data onto the stack, the stack pointer is decremented by one.

1 point

Determine the contents of the top of the stack and the value of the stack pointer (SP) after the following
instructions are executed in an 8051.
MOV SP, #6FH
MOV R1, #10H
MOV R6, #0FH
MOV 3, #03H
MOV 2, #FFH
PUSH 3
PUSH 2
PUSH 1
PUSH 6

a) SP = 74H, Top of the stack = 03H

b) SP = 73H, Top of the stack = 03H

c) SP = 74H, Top of the stack = 0FH

d) SP = 73H, Top of the stack = 0FH


Yes, the answer is correct.
Score: 1

Accepted Answers:

d) SP = 73H, Top of the stack = 0FH

1 point

How many times the instruction CPL A is executed in the following program of an 8051?

MOV A, #F0H

MOV R1, #60

NEXT: MOV R6, #10H

AGAIN: CPL A

DJNZ R6, AGAIN

DJNZ R1, NEXT

a) 600 times

b) 900 times

c) 690 times

d) 960 times

Yes, the answer is correct.


Score: 1

Accepted Answers:
d) 960 times

1 point

What is the maximum delay that can be generated with the crystal frequency of 22MHz, if connected to an
8051?

a) 2978.9 sec

b) 0.011 msec

c) 11.63 sec

d) 2.97 msec

Yes, the answer is correct.


Score: 1

Accepted Answers:

d) 2.97 msec

1 point

Find out the roll over value for the timer in Mode 0, Mode 1 and Mode 2 of an 8051?

a) 00FFH,0FFFH,FFFFH

b) 1FFFH,0FFFH,FFFFH

c) 1FFFH,FFFFH,00FFH

d) 1FFFH,00FFH,FFFFH

Yes, the answer is correct.


Score: 1
Accepted Answers:

c) 1FFFH,FFFFH,00FFH

1 point

Which control signal/s is/are generated by timing and control unit of 8051 microcontroller in order to access the
off-chip devices apart from the internal timings?

a) ALE

b) PSEN

c) RD & WR

d) All of the above

No, the answer is incorrect.


Score: 0

Accepted Answers:

d) All of the above

1 point

ARM was originally known as

a) Acron RISC Machine

b) Advanced RISC Machine

c) Ashton Raggatt McDougall

d) Automatic RISC Machine


No, the answer is incorrect.
Score: 0

Accepted Answers:

a) Acron RISC Machine

1 point

RISC stands for _______________

a) Restricted Instruction Sequencing Computer

b) Restricted Instruction Sequential Compiler

c) Reduced Instruction Set Computer

d) Reduced Induction Set Computer

Yes, the answer is correct.


Score: 1

Accepted Answers:

c) Reduced Instruction Set Computer

Assignment 9

An ARM instruction is

a) 8 bits long
b) 16 bits long

c) 32 bits long

d) 64 bits long

Yes, the answer is correct.


Score: 1

Accepted Answers:

c) 32 bits long

1 point

ALE signal in ARM is

a) Input to the processor

b) Output from the processor

c) Bidirectional

d) Configurable

No, the answer is incorrect.


Score: 0

Accepted Answers:

a) Input to the processor

1 point

In ARM, FIQ processing is faster than IRQ since FIQ


a) Saves one jump instruction and uses duplicate set of registers

b) Saves one jump instruction and clock speed doubles

c) Uses duplicate set of registers and spare ALU

d) Saves one jump instruction and uses a spare ALU

Yes, the answer is correct.


Score: 1

Accepted Answers:

a) Saves one jump instruction and uses duplicate set of registers

1 point

Suppose the contents of registers R1, R2, R3 and R4 in an ARM processor are 1, 2, 3 and 4 respectively.
Following two instructions are executed in sequence.
STMFD SP!, {R1, R3, R4, R2}
LDMFD SP!, {R4, R1, R3, R2}
The contents of the registers R1, R2, R3 and R4 will be

a) 1, 3, 4, 2

b) 3, 1, 2, 4

c) 1, 2, 3, 4

d) 4, 3, 2, 1

No, the answer is incorrect.


Score: 0

Accepted Answers:
c) 1, 2, 3, 4

1 point

Which instruction set in ARM has higher code density?

a) ARM

b) THUMB

c) Same for ARM and THUMB

d) Cannot be predicted

Yes, the answer is correct.


Score: 1

Accepted Answers:

b) THUMB

1 point

In multiplication of a positive number by a negative number in ARM processor, which one should be placed in
source register to achieve higher speed?

a) Positive number

b) Negative number

c) Either of them

d) Not possible to predict

Yes, the answer is correct.


Score: 1
Accepted Answers:

a) Positive number

1 point

In ARM, conditional execution is supported in

a) Both ARM and THUMB mode

b) Only ARM mode

c) Only THUMB mode

d) A programmable manner

Yes, the answer is correct.


Score: 1

Accepted Answers:

b) Only ARM mode

1 point

Which register in ARM holds return address in case of procedure calls?

a) R12

b) R13

c) R14

d) R15
Yes, the answer is correct.
Score: 1

Accepted Answers:

c) R14

1 point

An ARM processor writes the 32-bit number 22292F3FH into memory and then reads a byte from the same
address. The value read in big-endian convention will be

a) 22H

b) 29H

c) 2FH

d) 3FH

Yes, the answer is correct.


Score: 1

Accepted Answers:

a) 22H

1 point

Number of software interrupts in ARM processor is

a) 1

b) 24
Yes, the answer is correct.
Score: 1

Accepted Answers:

1 point

Which Exception in ARM has the highest address in ARM vector table?

a) RESET

b) IRQ

c) FIQ

d) SWI

No, the answer is incorrect.


Score: 0

Accepted Answers:

c) FIQ

1 point

The instruction set used by an ARM processor on reset is

a) ARM

b) THUMB
c) Can be either ARM or THUMB

d) None of ARM or THUMB

Yes, the answer is correct.


Score: 1

Accepted Answers:

a) ARM

1 point

Which of the following instructions corresponds to loading a signed half word in ARM architecture?

a) LDR

b) LDRS

c) LDRSH

d) LDRH

Yes, the answer is correct.


Score: 1

Accepted Answers:

c) LDRSH

1 point

ARM10TDMI is a

a) 3-stage pipeline processor


b) 5-stage pipeline processor

c) 6-stage pipeline processor

d) 8-stage pipeline processor

Yes, the answer is correct.


Score: 1

Accepted Answers:

c) 6-stage pipeline processor

1 point

Which of the following statements is TRUE for 6-stage pipeline ARM architecture?

a) Both instruction and data buses are 32-bit wide

b) Instruction bus is 32-bit wide, but data bus is 64-bit wide

c) Instruction bus is 64-bit wide, but data bus is 32-bit wide

d) Both instruction and data buses are 64-bit wide

Yes, the answer is correct.


Score: 1

Accepted Answers:

d) Both instruction and data buses are 64-bit wide

Assignment 10
(A)

(B)

(C)

(D)

Yes, the answer is correct.


Score: 1

Accepted Answers:

(B)

1 point

(A)

(B)

(C)

(D)

Yes, the answer is correct.


Score: 1
Accepted Answers:

(D)

1 point

(A)

(B)

(C)

(D)

Yes, the answer is correct.


Score: 1

Accepted Answers:

(B)

1 point

(A)

(B)
(C)

(D)

Yes, the answer is correct.


Score: 1

Accepted Answers:

(C)

1 point

(A)

(B)

(C)

(D)

Yes, the answer is correct.


Score: 1

Accepted Answers:

(A)

1 point
(A)

(B)

(C)

(D)

Yes, the answer is correct.


Score: 1

Accepted Answers:

(D)

1 point

(A)

(B)

(C)

(D)
Yes, the answer is correct.
Score: 1

Accepted Answers:

(A)

1 point

(A)

(B)

(C)

(D)

Yes, the answer is correct.


Score: 1

Accepted Answers:

(C)

1 point

(A)
(B)

(C)

(D)

Yes, the answer is correct.


Score: 1

Accepted Answers:

(D)

1 point

(A)

(B)

(C)

(D)

Yes, the answer is correct.


Score: 1

Accepted Answers:

(D)
1 point

(A)

(B)

(C)

(D)

Yes, the answer is correct.


Score: 1

Accepted Answers:

(B)

1 point

(A)

(B)

(C)

(D)
Yes, the answer is correct.
Score: 1

Accepted Answers:

(C)

1 point

(A)

(B)

(C)

(D)

Yes, the answer is correct.


Score: 1

Accepted Answers:

(C)

1 point

(A)
(B)

(C)

(D)

Yes, the answer is correct.


Score: 1

Accepted Answers:

(B)

1 point

Yes, the answer is correct.


Score: 1

Accepted Answers:

(C)256

Assignment 11
In 8255, BSR mode works with bits of port

a) A
b) B

c) C

d) D

Yes, the answer is correct.


Score: 1

Accepted Answers:

c) C

1 point

In 8255, bit addressability is available with port

a) A

b) B

c) C

d) D

Yes, the answer is correct.


Score: 1

Accepted Answers:

c) C

1 point

Which of the following representations related to the AVR microcontrollers is correct?


a) Timer/Counter 0 is an 8-bit up counter and timer/counter 1 is an 8-bit up counter

b) Timer/Counter 0 is an 8-bit up counter and timer/counter 1 is a 16-bit up counter

c) Timer/Counter 0 is a 16-bit up counter and timer/counter 1 is an 8-bit up counter

d) Timer/Counter 0 is a 16-bit up counter and timer/counter 1 is a 16-bit up counter

Yes, the answer is correct.


Score: 1

Accepted Answers:

b) Timer/Counter 0 is an 8-bit up counter and timer/counter 1 is a 16-bit up counter

1 point

Which of the following representations related to the AVR microcontrollers is correct?

a) An AVR timer/counter 0 has dual output compares A and B

b) An AVR timer/counter 1 has a single output compare A

c) An AVR timer/counter 1 has a single output compare B

d) An AVR timer/counter 1 has dual output compares A and B

Yes, the answer is correct.


Score: 1

Accepted Answers:

d) An AVR timer/counter 1 has dual output compares A and B

1 point
Which of the following represents the best description of an AVR timer/counter source when CS02 = 0, CS01 =
1, and CS00 = 1?

a) Stop, the timer/counter is stopped

b) CPU frequency is divided by 8 (CK/8)

c) CPU frequency is divided by 64 (CK/64)

d) CPU frequency is divided by 256 (CK/256)

Yes, the answer is correct.


Score: 1

Accepted Answers:

c) CPU frequency is divided by 64 (CK/64)

1 point

Which of the following registers holds the counter value of timer/counter 0 in an AVR microcontroller?

a) TCCR0

b) TCNT0

c) TCCR1A

d) TCNT1

Yes, the answer is correct.


Score: 1

Accepted Answers:
b) TCNT0

1 point

In an AVR microcontroller, interrupts are used for

a) RESET

b) Timers and Time-Critical Code

c) Hardware Signalling

d) All of the above

Yes, the answer is correct.


Score: 1

Accepted Answers:

d) All of the above

1 point

Why interface chips are necessary in a microcontroller based system?

a) To resolve the speed problem

b) To synchronize the data transfers between the CPU and the I/O device

c) To synchronize the data transfers between the CPU and the I/O device, as well as to resolve the
speed problem

d) None of the given options

Yes, the answer is correct.


Score: 1
Accepted Answers:

c) To synchronize the data transfers between the CPU and the I/O device, as well as to resolve the speed
problem

1 point

Which of the following can be associated with bouncing contacts?

a) Push-button switches

b) Toggle switches

c) Both push-button switches and toggle switches

d) Neither push-button switches nor toggle switches

Yes, the answer is correct.


Score: 1

Accepted Answers:

c) Both push-button switches and toggle switches

1 point

Which of the following is a hardware solution to suppress a switch bounce in a microcontroller based system?

a) An RC time constant whose value is smaller than the switch bounce

b) An LC time constant whose value is smaller than the switch bounce

c) An RC time constant whose value is larger than the switch bounce

d) An LC time constant whose value is larger than the switch bounce


Yes, the answer is correct.
Score: 1

Accepted Answers:

c) An RC time constant whose value is larger than the switch bounce

1 point

The term DIP in the phrase ‘DIP switch’ stands for

a) Double In-lane Package

b) Double In-line Package

c) Dual In-line Package

d) Dual In-lane Package

Yes, the answer is correct.


Score: 1

Accepted Answers:

c) Dual In-line Package

1 point

Find the control word of the 8255 for resetting BIT 7 of Port C.

a) 00001111

b) 10001111

c) 00001110
d) 10001110

Yes, the answer is correct.


Score: 1

Accepted Answers:

c) 00001110

1 point

To get 6 displayed by a 7 Segment display, what should be the combination of 8051 pins (P1.7 – P1.0)?

a) 01111101

b) 10111110

c) 01111111

d) 01100000

Yes, the answer is correct.


Score: 1

Accepted Answers:

a) 01111101

1 point

Which of the following is the correct combination to select Port A in an 8255 chip?

a) CS = 0, A1 = 0, A0 = 0

b) CS = 0, A1 = 0, A0 = 1
c) CS = 0, A1 = 1, A0 = 0

d) CS = 1, A1 = 0, A0 = 0

Yes, the answer is correct.


Score: 1

Accepted Answers:

a) CS = 0, A1 = 0, A0 = 0

1 point

With respect to ADC 0804, find out which of the following statement(s) are false.

1. CS is active high pin.

2. D7-D0 are output pins.

3. The Chip has a voltage range of 0 - 5 V.

a) Option 1.

b) Option 2.

c) Option 3.

d) All the options.

Yes, the answer is correct.


Score: 1

Accepted Answers:

a) Option 1.