Digital Systems Design Using Verilog

Charles Roth, Lizy Kurian John, Byeong Kil Lee

1st Edition
978-1-285-05107-9
Errata for First Printing

Page Number Correction Description

20 In the bottom-right example, “0010” should be “0011”
37 In Equation (1-38), the “+” between “fmax” and “1” should be “=”
39 For Question (a) of the example, “minimum clock period” should be “maximum clock frequency”
46 At the bottom of the page, “The last waveform in Figure 1-45 illustrates” should be “The last
waveform in Figure 1-52 illustrates”
70 In the middle of the page, the second logic equation should be “Cout = XY + YCin + XCin”
80 On line 16, “{“ should be inserted so that it reads { else if (condition)
82 8 lines from the bottom, “@” should be “wait” so that it reads
wait(posedge CLK);

86 In line 7, add “//” before “will be”

103 In line 4 of Section 2.13.2, “Sel” should be “(Sel)”
103 In the last line of the page, remove semicolon
126 In line 9, “reg [7:0]” should be removed
138 For Problem 2.14, the last line of code should be “B <= B + 7;”
154 For Problem 2.56, “=” should be “<=” for the following instances:
sel <= 0;
sel <= sel + 1;
sel <= sel + 2;
F <= I0;
F <= I1;
F <= I2;
F <= I3;
167 In Equation (3-1), “ A’B’+AC ” should be “ A’B’ + AC’ ”
203 In line 4, “[TomaHawk reference]” should be “[34]”
225 In line 9 of Section 4.5, the em-dash between “1” and “0” should be replaced by two normal dashes
so that it reads “1- -0/0110”
319 In the caption for TABLE 5-3, remove “b” after “Figure 5-29”
319 In the second-to-last line, “muliplexer” should be “multiplexer”
326 In the second paragraph, the line “The two-address microcode entry is based on Table 5-7, and the
single-address microcode entry is based on Table 5-6.” should be “The two-address microcode entry
is based on Table 5-6, and the single-address microcode entry is based on Table 5-7.”
335 In the table at the top of the page, the second “X1” should be “X2” and the third “X1” should be “X3”
355 The paragraph under “The Xilinx Kintex Configurable Logic Block” should read:
“The Xilinx Kintex FPGA uses four copies of the basic block shown in Figure 6-13 to form a slice. Two
such slices are combined to form a Configurable Logic Block (CLB). Each slice thus contains four six-
input Look Up Tables (LUT6), 8 flip-flops, the carry chain, and several multiplexers.”
355 The paragraph under Figure 6-13 should read:
“Each LUT6 can be used to generate one 6-variable function or two 5-variable functions. The 6-
variable function is generated by combining two 5-variable functions using a 2-to-1 multiplexer.
There are 2 outputs from the LUT6, namely O6 and O5. One of the outputs (O6) can use up to 6 input
variables. The second output (O5) can use only up to 5 input variables. It should be noted that these
are not independent variables or independent functions. Five of the variables are common between
O6 and O5 and the function O5 has to be a sub-function of the function O6. There are 3 external
outputs from the slice, AMUX, A and AQ, but only two of them can be used simultaneously. One of
the outputs, A is a combinational output, while the AQ output is always a registered output. The
AMUX output can be either combinational or registered. The O6 function can be brought out
through any of the 3 output lines, however, the O5 output can be brought out only via AMUX and
AQ. There are several multiplexers and other gates to allow this routing. The slices also support carry
chaining. The Kintex chips use two slight variations of this slice structure, which they call SLICEL and
SLICEM.”
377 In the third line after “Synthesis of a Case Statement”, “inputs a and b are each implemented with 2-
bit binary numbers.” should be “input a and output b are 2-bit binary numbers.”
384 In the top left block of Figure 6-31b, “4-Bit Counter” should be “4-Bit Adder” The second instance
should remain as is
385 In the “Major Vendors of FPGA CAD Tools” box, “XIlinx” should be “Xilinx”
419 In Figure 7-12, the No path from Step 7 of the flowchart should go back to Step 4 instead of Step 2
433 In Figure 8-2, the “end” after “cin = cout;” should be aligned with the “begin” three lines above it
441 In the first line following Figure 8-9, “The first 12” should be “The first 14”
462 In the middle of the page, “Figure 8-22 shows a Verilog code that read a file” should be “Figure 8-22
shows Verilog code that reads a file”
483 In the second row and last column of Table 9-7, “$s3” should be “$3”
483 In the second row and first column of Table 9-7, “Add” should be “add”
483 In the third row and first column of Table 9-7, “Sub” should be “sub”
490 Three lines from the bottom, “R-format” should be “I-format”
490 Two lines from the bottom, “I-format” should be “R-format”
495 In Figure 9-7, Line 8 should be deleted:
reg[6:0] counter; should be deleted.
495 In Figure 9-7, “//” should be added to Line 14 so it reads:
//$readmemh(“MIPS_Instructions.txt”, RAM):

503 14 lines from the bottom, “$16” should be “16”

508 In Problem 9.1, delete “Pentium 4 ->” and “Pentium 3 ->”
521 In line 5, “S5” should be “S2”
553 In the middle of the page, “LSFR” should be “LFSR”
555 For (e) case expression, remove the semicolon after “endcase”