DIGITAL ELECTRONICS AND MICROPROCESSOR

Experiments List

1. Realization of all Basic gates using Universal Gates (Both NAND and NOR) using multisim.

2. Simplification , Realization of Boolean Expressions by using Logic gates/Universal Gates using

multisim

3. Realization of half/full adder and half/full subtractor using logic gates using multisim.

4. Design of a combinational circuit to convert from Binary to grey code converter and vice
versausing multisim.

5. Realization of MUX / DEMUX using NAND gates using multisim.

6. To verify the truth table of one bit and two bit comparators by using logic Gates using multisim.
7. Design of MOD N counter (synchronos/Asynchronous) using IC 7476 using multisim.

8. A. ALP to Byte and word data transfer in different addressing modes .

B. ALP to transfer a block of data with out overlap
C. ALP for Block Exchange.

9. A. 16 bit Addition/ Subtraction/ Multiplication

B. LCM of Two Numbers.

10. Program to find Largest /Smallest in the Array.

11. Sorting Array in Ascending/Descending Order.

12. Program to transfer a String from one location to another.

Experiment 1
AIM: Realisation of all the Basic Gates using Universal Gates.

Theory: In electronics, a logic gate is an idealized or physical device implementing a Boolean

function; that is, it performs a logical operation on one or more logical inputs, and produces a single
logical output. Depending on the context, the term may refer to an ideal logic gate, one that has for
instance zero rise time and unlimited fan-out, or it may refer to a non-ideal physical device.

Logic gates are primarily implemented using diodes or transistors acting as electronic switches. With
amplification, logic gates can be cascaded in the same way that Boolean functions can be
composed, allowing the construction of a physical model of all of Boolean logic, and therefore, all of
the algorithms and mathematics that can be described with Boolean logic.

Logic circuits include such devices as multiplexers, registers, arithmetic logic units (ALUs),
and computer memory, all the way up through complete microprocessors, which may contain more
than 100 million gates.

NAND and NOR gates can be used to realize all the operations of the basic gates. Hence it is called
as Universal gates.

i) Realisation of AND Operation using NAND GATE

Realisation of OR Operation

Realisation of NOT Operation

Realisation of Ex-Or Operation

REALIZATION OF NOR As

AND Operation

OR Operation

NOT Operation
Questions:

 Define LOGIC DESIGN?

 What are the different kinds of gates available to us?
 What are universal gates? Give an example.
 Define an Integrated Circuit (IC)?
 How are IC’s classified according to the number of gates available in to it?
 Define Moore’s law?
 Experiment 2
AIM:

 To Simplify and realize a given Boolean Expression by using logic gates and universal gates.

BOOLEAN EXPRESSION:

1) Y  A B C  A BC  A BC  AB C  AB C  ABC
SIMPLIFICATION:

Y  A B C  A BC  A BC  AB C  AB C  ABC
 A C ( B  B )  A BC  AB (C  C )  ABC
 A C  A BC  AB  ABC
 A (C  BC )  A( B  BC )
 A (C  B )(C  C )  A( B  B )( B  C )
 A C  A B  AB  AC
 C ( A  A )  A B  AB
 C  A B  AB
 C  A B

SIMPLIFICATION BY USING NAND GATES ONLY:

Y  C  A B  AB
Y  C  A B  AB
 C  A B  AB
 C  A B  AB
Y  Y  C  A B  AB

Truth Table for Y= C  A  B

A B C C A B Y=

C  A B

0 0 0 1 0 1

0 0 1 0 0 0
0 1 0 1 1 1

0 1 1 0 1 1

1 0 0 1 1 1

1 0 1 0 1 1

1 1 0 1 0 1

1 1 1 0 0 0

1. REALIZATION BY USING BASIC GATES:

REALIZATION BY USING NAND GATE

Questions:

 Define Boolean algebra?

 State the principle of Duality?
 State the following laws Idempotent, Involution, Commutative, absorption, distributive,
associative law?
 State Demorgan’s law of Boolean Simplification?
 What are the different methods available in Boolean Simplification?
 Define K-MAP?

Experiment 3
AIM:

 To Realize Half and Full adder by using

I. X-OR and Basic Gates

II. Nand Gate only Truth Table

INPUTS OUTPUTS
Realisation of Half Adder Using Basic Gates

A B Sum (s) Carry(c)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1
Realisation of Half Adder using NAND gates

Realisation of Full Adder using Gates Full Adder Truth Table

 INPUTS OUTPUTS

A B C Sum(S) Carry(Cin)

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0
Realisation of Full Adder using NAND gates.
0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

1. Half Subtractor by using basic gates:

INPUTS OUTPUTS

A B Difference(D) Borrow(Br)

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0
Half Subtractor by using NAND gates only:

Full Subtractor by using basic gates:

INPUTS OUTPUTS

A B C Difference(D) Borrow(Br)

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0
Full Subtractor by using NAND gates only:

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

Truth Table for full Subtractor

Experiment 4
AIM:

 To Convert Binary to Gray Code and Gray to Binary Code Conversion.

Truth Table for Binary to Gray Code Conversion:

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0
CIRCUIT DIAGRAM:

Binary to Gray code Conversion by using Basic Gates

B3
G3
B2

G2
B1
G1
B0
Go

Binary to Gray code Conversion by using Nand Gates

Questions:

 Define Binary Code

 Define Gray Code
 What are Reflected Codes? Give an example for reflected code
 What is self Complementary Code? Give an for Self Complementary code
 Explain binary logic?
 Represent the following Decimal number 8620 in Gray Code
Experiment 5
 AIM: To verify the truth table of MUX and DEMUX using NAND.

Circuit Diagram
Truth Table MUX/DEMUX
MUX USING NAND GATES ONLY:
INPUTS OUTPUT

A B I0 I1 I2 I3 Y

0 0 0 x x x 0

0 0 1 x x x 1

0 1 x 0 x x 0

0 1 x 1 x x 1

1 0 x x 0 x 0

1 0 x x 1 x 1

DEMUX USING NAND GATES ONLY: 1 1 x x x 0 0

1 1 x x x 0 1
Questions:

 Define Multiplexer
 Define Demultiplexer
 Explain the logic of implementing the Boolean function by using Multiplexer

 Implement F ( A, B, C)   (1,3,5,6) by using a Multiplexer

 Obtain an 8 1 multiplexer with a dual 4-line to 1- line multiplexer having separate enable
inputs but common selection lines
Experiment 6

AIM:

To verify the truth table of one bit comparators by using logic Gates

CIRCUIT DIAGRAM:

ONE-BIT COMPARATOR:

INPUT OUTPUT

A B Y1(A>B) Y2(A=B) Y3(A<B)

0 0 0 1 0

0 1 0 0 1

1 0 1 0 0

1 1 0 1 0

EXERCISE:

 Obtain the Expressions for one bit comparator by using K-Map method
 Obtain the Expressions for two bit comparator by using K-Map method
 Implement one bit comparator by using Nand gates only.
 Implement the two bit comparator by using Nand gates only.
 Define Magnitude Comparator
 What are the functions of Cascading inputs in IC7485
Experiment 7

Aim: To design a mod 8 asynchronous counter or Ripple counter.

Circuit Diagram of a Mod 8 Rilpple counter.

WAVE FORMS

TRUTH TABLE

Number of clock Flip Flop outputs

pulses
Qc Qb Qa

0 0 0 0

1 0 0 1
 2 0 1 0

3 0 1 1

4 1 0 0

5 1 0 1

6 1 1 0

7 1 1 1

8 0 0 0

Design a synchronous mod 6 up counter.

In MOD-6 counter invalid state is 110

PRESENT STATE NEXT STATE EXCITATION

Qc Qb Qa Qc Qb Qa JC KC JB KB JA KA

0 0 0 0 0 1 0 X 0 X 1 X

0 0 1 0 1 0 0 X 1 X X 1

0 1 0 0 1 1 0 X X 0 1 X

0 1 1 1 0 0 1 X X 1 X 1

1 0 0 1 0 1 X 0 0 X 1 X

1 0 1 0 0 0 X 1 0 X X 1

simplifications
CIRCUIT DIAGRAM

WAVE FORMS
Questions

 Define Counter?
 What is Binary ripple Counter?
 What are synchronous counters?
 What are Asynchronous counter?
 Differentiate Between synchronous and Asynchronous counter
 What are the applications of Counters?
 What are the functions of MR1, MR2, MS1 and MS2 in IC7490?
 What are clocked flip flop?
 Define Excitation table?
 Define State table?
 Obtain the excitation table for JK Flip Flop , T- Flip Flop,D-Filp Flop
 What are the functions of load and clear?
Experiment 8

Aim:
A. ALP to Byte and word data transfer in different addressing modes

B. ALP to transfer a block of data with out overlap

C. ALP for Block Exchange.

A. ALP for the Byte and word data transfer in different addressing modes.

.MODEL SMALL .DATA

Array DB 5 DUP (0)
DB 78h
DB 20 DUP (0) .CODE
MOV AX,@DATA
MOV DS,AX
MOV BX, offset Array
MOV SI,05h
MOV CL,[BX+SI]
MOV SI,11H
MOV [BX+SI],CL
MOV AH,4Ch
INT 21h
END

B. ALP to transfer a block of data without overlap.

.MODEL SMALL .DATA

Array1 DW 1111h,2222h,3333h,4444h,5555h
Array2 DW 5 DUP (0)
Count DW 0005H
.CODE
MOV AX,@DATA
MOV DS,AX
LEA SI,Array1
LEA DI,Array2
MOV CX,Count
NEXT: MOV AX,[SI]
MOV [DI],AX
INC SI
INC SI
INC DI
INC DI
LOOP NEXT
MOV AH,4Ch
INT 21h
END

C. ALP for Block Exchange

.MODEL SMALL .DATA

Array1 DW 1111h,2222h,3333h,4444h,5555h
Array2 DW 1010h,2020h,3030h,4040h,5050h
Count DW 0005h
.CODE
MOV AX,@DATA
MOV DS,AX
LEA SI,Array1
LEA DI,Array2
MOV CX,Count
NEXT: MOV BX,[SI]
MOV DX,[DI]
XCHG BX,DX
MOV [SI],BX
MOV [DI],DX
INC SI
INC SI
INC DI
INC DI
LOOP NEXT
MOV AH,4Ch
INT 21h
END

Question

1. What are the various Addressing modes present in 8086.

2. What is Real mode addressing

3. What are the various general purpose registers.

Experiment No.9

Aim: . A. ALP to perform 16 bit Addition/ Subtraction/ Multiplication

B. ALP to perform LCM of Two Numbers.

Assembly Language program to compute the 16 bit addition/ Subtraction.

.MODEL TINY .CODE

MOV BX,1234h
MOV CX,7698h
MOV AL,BL ; for subtraction replace with
ADD AL,CL ; SUB AL,CL
DAA ; DAS
MOV DL,AL
MOV AL,BL
ADC AL,CH ; SBB AL,CH
DAA ; DAS
MOV DH,AL
MOV AH,4Ch
INT 21h
END

16 bit Multiplication/ Division

.MODEL TINY
.CODE
MOV AX,1234h
MOV BX,7698h
ADD AL,31h ; for Division replace with
MUL BX ; DIV BX
MOV AH,4Ch
INT 21h
END
LCM of two numbers

.MODEL SMALL
.DATA
Num1 DW 0005h
Num2 DW 0002h
Ans DW ?
.CODE
MOV AX,@DATA
MOV DS, AX
MOV AX, Num1
MOV BX, Num2
MOV DX, 0000h
NEXT: PUSH AX
PUSH DX
DIV BX
CMP DX, 0000h
JZ LAST
POP DX
POP AX
ADD AX, Num1
JNC NEXT
INC DX
JMP NEXT
LAST: POP Ans+2
POP Ans
MOV AH, 4Ch
INT 21h
END
Experiment No.10

Aim: Program to find Largest /Smallest in the Array

.MODEL SMALL
.DATA
Array DB 10h, 20h, 30h, 40h, 50h
Count DW 0005h
Result DB 00h
.CODE
MOV AX,@DATA
MOV DS, AX
LEA SI, Array
DEC Count
MOV CX, Count
MOV AL, [SI]
NEXT: INC SI
CMP AL, [SI] ; for smallest replace with
JC DOWN ; JNC DOWN
LOOP NEXT
JMP LAST
DOWN: XCHG AL, [SI]
LOOP NEXT
MOV Result, AL
LAST: MOV AH, 4Ch
INT 21h
END
Experiment No. 11

Aim: Sorting Array in Ascending/Descending Order.

.MODEL SMALL
.DATA
Array DW 2233h, 8899h, 6677h, 0011h, 4455h
Count DW 0005h
.CODE
MOV AX, @DATA
MOV DS, AX
MOV CX, Count
LEA SI, Array
NEXT: MOV BX, [SI]
INC SI
INC SI
CMP BX, [SI] ; for descending order replace with
JNC DOWN ; JC DOWN
LOOP NEXT
DOWN: XCHG BX, [SI]
DEC SI
DEC SI
MOV [SI], BX
LOOP NEXT
MOV AH, 4Ch
INT 21h
END
Experiment No.12

Aim: Program to transfer a String from one location to another.

.MODEL SMALL
.DATA
String1 DB 'BMSCE DEPT OF ECE$'
Length EQU ($-String1)
String2 DB LEN DUP (0)
.CODE
MOV AX, @DATA
MOV DS, AX
MOV ES, AX
MOV CX, Length
CLD
LEA SI, String1
LEA DI, String2
REP MOVSB
MOV AH, 4Ch
INT 21h
END