MIDDLE EAST TECHNICAL UNIVERSITY NORTHERN CYPRUS CAMPUS

ELECTRICAL & ELECTRONICS / COMPUTER ENGINEERING PROGRAM

EEE-347/CNG-336 INTRODUCTION TO
MICROPROCESSORS / EMBEDDED SYSTEMS DEVELOPMENT
Spring-2017

Midterm Exam 2

May 15th, 2017

Time Allowed: 100 min.

 This is a closed book examination.

 No additional handout material will be provided..
 Attempt all 4 questions of equal grade.
 Use of cellular phones or any other electronic device is strictly prohibited.

Full Name:...................................................................................................

Student Number:.........................................................................................

SCORE

Q-1

Q-2

Q-3

Q-4

TOTAL
Q-1 (25 pts.)

a) (2 pts.) State two advantages of programming in assembly level in comparison to programming

in C.

Advantage 1: smaller code size

Advantage 2: faster code execution

b) (2 pts.) State two advantages of programming in C in comparison to programming in assembly

level.

Advantage 1: easier and less time consuming code development

Advantage 2: easier to modify and update code

c) (4 pts.) Fill in the following table.

Data type Size in bits Data range

16 -(216) to (216-1)
int [-32,768 to +32,767)]
32 0 to (232-1)
unsigned long [0 to 4,294,967,295]

d) (4 pts.) Which of the following codes run faster? Circle (i) or (ii) ?

(i) (ii)

#include <avr/io.h> #include <avr/io.h>

int main(void) int main(void)
{ {
unsigned int z; long z;

DDRB = 0xFF; DDRB = 0xFF;

for (z=0; z<50000; z++) for (z=0; z<50000; z++)

{ {
PORTB = 0x55; PORTB = 0x55;
PORTB = 0xAA; PORTB = 0xAA;
} }
return(0); return(0);
} }
e) (4 pts.) Write a one line statement in C, which complements only the least significant odd-
numbered bits in the high byte and most significant even-numbered bits in the low byte of an
unsigned int variable named z.

z = z ^ 0x0A50;

f) (9 pts.) Write a complete C program, which performs as follows:

PORTC is either an 8-bit counter or shift register. If it is a counter, it could be an up or down

counter. If it is a shift register, it could be a left or right shift register. Here is the operation table:

PORTB3=0 => PORTC is a counter

PORTB3=1 => PORTC is a rotate shift register

PORTB5=0 => PORTC is an up counter or a rotate left shift register

PORTB5=1 => PORTC is an down counter or a rotate right shift register

PORTC changes state every 1 sec. When the mode of operation changes, PORTC continues
counting or shifting from its current state.

Assume that there exists a library function void Delay_1sec(void) and the operation
continues forever. Also assume that status register SREG and the carry bit CARRY are also
defined in the header file io.h.

One possible solution:

#include <avr/io.h>

int main(void)
{
DDRB = DDRB & ~(1<<3);
DDRB = DDRB & ~(1<<5);
DDRC = 0xFF;
while (1)
{
if (~(PINB & (1<<3)) & ~(PINB & (1<<5))) PORTC++;
if (~(PINB & (1<<3)) & (PINB & (1<<5))) PORTC--;
if ((PINB & (1<<3)) & ~(PINB & (1<<5)))
{
PORTC = PORTC << 1;
if (SREG.Carry) PORTC = PORTC | 0x01;
}
if ((PINB & (1<<3)) & (PINB & (1<<5)))
{
PORTC = PORTC >> 1;
if (SREG.Carry) PORTC = PORTC | 0x80;
}
Delay_1sec();
}
return(0);
}
 Q-2 (25 pts.)

A memory system for a processor whose address bus is 16-bit wide is given below (data bus
connections, control signal connections, etc. are not shown for simplicity).

2x4 Decoder ROM1 (4K)

0 CS
A14 A (LSB) 1
A15 B (MSB) 2
3
E 2x4 Decoder ROM2 (2K)

0 CS
A12 A (LSB) 1
A13 B (MSB) 2
3
E
2x4 Decoder RAM1 (1K)

0 CS
A10 A (LSB) 1
A11 B (MSB) 2
3
E
2x4 Decoder RAM2
(512 Byte)
0 CS
A9 A (LSB) 1
0 B (MSB) 2
3
E

Note that:
CS CS

a) Give the memory map from $0000 to $FFFF by clearly indicating the address ranges
corresponding to each chip also indicating clearly the overlay area and the unused area.
A15 A14 A13 A12 A11 A10 A9 A8 ……… A1 A0
0 0 X X X X X X ……… X X ROM1 (with overlay)
1 1 0 0 X X X X ……… X X ROM2 (with overlay)
1 1 1 1 0 0 X X ……… X X RAM1 (no overlay)
1 1 1 1 1 1 0 X ……… X X RAM2 (no overlay)

0x0000 – 0x0FFF ROM1 (4K)

0x1000 – 0x3FFF ROM1 (overlay) (3x4K=12K)
0x4000 – 0xBFFF NOT USED
0xC000 – 0xC7FF ROM2 (2K)
0xC800 – 0xCFFF ROM2 (overlay) (2K)
0xD000 – 0xEFFF NOT USED
0xF000 – 0xF3FF RAM1 (1K)
0xF400 – 0xFBFF NOT USED
0xFC00 – 0xFDFF RAM2 (512B)
0xFEFF – 0xFFFF NOT USED

b) How much memory space (physical + overlay) is used in this system?

7,5K (physical) + 14K (overlay) = 21,5K total; 42,5K unused
Q-3 (25 pts.)

a) (6 pts.) The following is the functional block diagram of Timer/Counter0 in AVR family
microcontrollers. Describe briefly how the circuit functions, clearly stating the role of each block
and signal separately.
b) (2 pts.) State the two major differences between Timer/Counter0 and 1.

Difference 1: Timer0 is 8 bit whereas Timer1 is 16 bit

Difference 2: Timer0 has one OC structure whereas Timer1 has three.

c) (2 pts.) State the difference between timer and counter modes.

Timer mode uses internal CPU clock and the clock can be pre-scaled.

Counter mode uses an external signal as the clock and active transition can be defined
to be positive or negative edge.

d) (15 pts.) Write a program in AVR assembly language that will generate a 694 Hz square wave
at PORTB.3 using CTC mode of Timer0 by ignoring the instruction overheads and by assuming
XTAL = 8 MHz.

Tclk = 1/8 MHz = 0,125 microsec

Treq = 1/694Hz = 1440 microsec Treq/2 = 720 microsec

Treq/2/Tclk = 720 microsec / 0,125 microsec = 5760 ticks per timer period

To determine the required prescaler setting:

Prescaler Timer Tick

1 --- 5760 not possible
8 --- 720 not possible
64 --- 90 possible (required TCCR0 configuration data 0BH)
256 --- 23 possible (required TCCR0 configuration data 0CH)
1024 --- 11 possible (required TCCR0 configuration data 011H)
Q-4 (25 pts.)

a) (20 pts.) Analyze the following code and describe its function in a couple of sentences. What
does it do? Assume XTAL = 8 MHz.

#include <avr/io.h>
#include <avr/interrupt.h>

int main()
{
DDRA = 0xFF;
DDRC = 0x00;
PORTC = 0xFF;
DDRD = 0xFF;
DDRB |= 0x40;
PORTB &= ~(0x40);

TCNT0 = -200;
TCCR0 = 0x06; //normal mode, falling edge, no prescaler

TCNT1H = (-31250) >> 8;

TCNT1L = (-31250) & 0xFF;
TCCR1A = 0x00; //normal mode
TCCR1B = 0x04; //internal clock, prescaler 1:256

TIMSK = (1<<TOIE0)|(1<<TOIE1);
sei();

while (1)
PORTD = PINC;
}

ISR (TIME0_OVF_vect)
{
TCNT0 = -200;
PORTB ^= 0x40;
}

ISR (TIME1_OVF_vect)
{
TCNT1H = (-31250) >> 8;
TCNT1L = (-31250) & 0xFF;
PORTA++;
}

The following are performed in a multitasking fashion by the help of interrupts:

1- The program transfers PORTC contents to PORTD continuously.

2- PORTA simultaneously counts up each time Timer1 overflows, which overflows once
every second (1 sec = 31250 x 1 / (8 x 106 / 256))

3- A pulse that is fed into T0 pin is also simultaneously counted. Whenever this count
value reaches 200, pin PORTB.6 is toggled.
a) (5 pts.) State whether the following statements are true or false.

i) Polling avoids tying down the microcontroller.

True / False

ii) The AVR programmer cannot change the memory address location assigned to the interrupt
vector table.
True / False

iii) Upon reset, all interrupts are enabled by the AVR.

True / False

iv) An address location is assigned to each of the external hardware interrupts INT0, INT1 and INT2.
True / False

v) If two interrupts arrive at the same time, one of them is arbitrarily chosen and served.
True / False
TIMER RELATED REGISTERS
 INTERRUPT RELATED REGISTERS

SREG I T H S V N Z C

ISCn1,ISCn0
00: low-level
10: falling edge
11: rising edge
(01: reserved)

TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0

ETIMSK - - TICIE3 OCIE3A OCIE3B TOIE3 OCIE3C OCIE1C