2IN35 – VLSI Programming – Lab Work

Assignment 1: Hardware design using Verilog

Hrishikesh Salunkhe, h.l.salunkhe@tue.nl,

Alok Lele, a.lele@tue.nl

April 28, 2015

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Contents
1 Introduction 3

2 Hardware design 3
2.1 Introduction to Xilinx ISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Creating a new project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Examining the design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Hardware synthesis 8

4 Hardware simulation 10
4.1 Examining the test module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 Simulate the design on the test input . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 Examining the output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5 Filter design 11
5.1 Analyzing the filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2 Designing filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6 Signal analysis 12

7 A different filter implementation 13

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1 Introduction

In the first assignment you will get to know the tool set that is used during the labs by:

• Examining and synthesizing 2 Verilog FIR filter implementations using Xilinx ISE.

• Simulating an FIR filter on an audio stream, and examining the result using Audacity.

• Designing and analyzing the coefficients that go into a FIR filter using Matlab.

For this assignment you will need the following files from the website:

• The 2 FIR filter implementations that will be examined: filter1.rar and filter2.rar.
Make sure you unpack them to different directories.

• input audio file input.bin

2 Hardware design

2.1 Introduction to Xilinx ISE

Xilinx ISE is a graphical front end for a collection of command line utilities. Whenever you
instruct ISE to perform an action, it will invoke a (sequence of) utilities in the background.
The interface consists of 3 parts as shown in Figure 1

Figure 1: Xilinx ISE GUI

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Transcript: The transcript window is located on the bottom of the ISE window, demarcated
by the green rectangle. It shows the output of the most recently finished process. The
transcript is often quite verbose. By selecting the Errors or Warnings tab, the console is
filtered to show only the errors or warnings respectively.
Panel: The panel window is located in the upper left part of the ISE window, demarcated
by the red rectangle. By default, it has 4 tabs as shown in Figure 2

Figure 2: Xilinx ISE Panel Window

• Start: This tab shows various options of creating projects.

• Design: This tab is divided into two panes or parts which are View and Processes as
shown in Figure 2.

– View: The view pane is located inside the design tab of the ISE window, de-
marcated by light green rectangle. In the view pane you can select either the
Implementation or Simulation view of the Verilog modules. In the implementation
view there is always one Verilog module that is the top-level module. If this is set
incorrectly, you can manually set any Verilog module to be the top-level module
in its context menu. Only the top-level module can be synthesized.
View pane also consists of a vertical bar on the left side where you can see various
options such as New Source, Add Source, Add Copy of Source etc. into the existing
project. You can also see the same options by right clicking inside the view pane.
Option Add Source adds the symbolic links into the project that points to the

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 location of original source files whereas Add Copy of Source option copies the
source files into the current project. This is generally a good idea to have source
files present in the current project directory.
– Processes: The processes pane is located inside the design tab of the ISE window,
below the view pane shown using the violet rectangle. It shows all processes that
can be run on the selected Verilog module in the sources window. Most processes
have a properties menu accessible from the context menu to set the parameters for
execution. When the simulator is active, the processes window also contains a tab
listing all the signals that can be added to the simulation.

• Files: This tab lists all files that are currently in the project.

• Libraries: This tab lists all libraries including all the files that are currently in the
project.

2.2 Creating a new project

Start Xilinx ISE and create a new project by selecting File → New Project. A wizard will
pop up, which will collect all the required information to get started. The first step asks for
some information about the project:

• Project Location: select a directory to store your projects in, but make sure that the
full path of the directory does not contain any spaces, so do not use any sub-directory
of My Documents. For each design you create, a new sub-directory is created in this
directory.

• Project Name: type in a name for your project, but make sure that it does not contain
any spaces, because it will be used as the name for the sub-directory.

• Top-Level Source Type: select “HDL”. This tells ISE that you will implement your
project using a Hardware Description Language. The alternative is to design a schematic,
which is only a good idea for low-level designs.

In the next step, you have to select the hardware for which you will be designing. The FPGA
on the lab boards is the Xilinx Spartan-6 XC6SLX45. Set the following properties, and leave
the others to their defaults:

• Family: ”Spartan6”.

• Device: ”XC6SLX45”.

• Package: ”CSG324”.

• Speed : ”-3”.

• Simulator : ”ISim (VHDL/Verilog)”.

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In the next step, you will be presented with a summary of the project creation. Read and
check it (you can cancel the current project creation and start again if something is wrong)
and then press Finish to finish the wizard.
In the next step, you can create new source files for your project or add existing source files to
your project. For this assignment, you will be working on an existing design. To add existing
files into the project, go to the design tab of the panel window. In the view pane, you can
add the extracted files from filter1.rar, by pressing Add Copy of Source, navigating to
the location where you have unpacked them, and selecting the files fir.v, firstage.v, and
firtest.v. The 3 files will be added to the list. ISE will present you with a dialog in which
you can define the contents of the different source files. The file firtest.v is should be set
for Simulation, while the files fir.v and firstage.v can be used for both implementation
and simulation i.e. set them with the All option. If it has not correctly detected then you can
make corresponding changes to the file association using the dialog box. Press OK to finish.

2.3 Examining the design

Let’s take a look at the source files. In the sources window, expand the node fir (fir.v), which
will show you comp - firstage (firstage.v). By double clicking on firstage.v, it will be opened
in an editor in the workspace. As you can see, it contains a Verilog module named firstage.
The line ‘timescale 1ns / 1ps is for the simulator, you can ignore it.

Modules The line starting with module declares a module, which represents a hardware
component. A module contains a list of parameters, a list of I/O channels and a body. The
module firstage has 2 parameters, 7 I/O channels and a body containing 6 lines of code
and some comment.
A module can be instantiated as often as desired in other modules. This allows you to build
up a hierarchy of modules. For example, an FIR filter will typically instantiate as many
firstage modules as the number of taps it has. The convention is to have 1 Verilog module
per file, but this is not required.

Parameters Parameters are used to create generic hardware components in much the same
way as generic programming facilities in a high level programming language allow you to create
a generic software component. When a module is instantiated by the synthesizer, the default
values of each parameter is overridden by the actual value set at the instantiation point. The
firstage module is parametrized in the data width DWIDTH of the samples and coefficients,
which has a default value of 16. This allows this module to be used in a FIR filter of arbitrary
precision without modifying the firstage code.

Channels The i/o channels (also called i/o ports or simply ports) will be used by the module
to communicate with the rest of the system. For each channel, a direction has to be specified:
input, output or inout. Each channel has a width, which specifies the number of wires
of that channel. The width is specified as [a:b], where a and b are integers. For example
[15:0] and [0:15] both denote and 16-wire channel, but with indices reversed. By default,
channels have a width of 1, i.e. they consist of a single wire (clk and enabled in firstage for

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example). Unless specified otherwise, channels of width [a:b] are interpreted to be unsigned
integers where a is the index of the most significant bit, and b is the index of the least
significant bit. The signed qualifier indicates that the wires should be interpreted as a signed
2’s-complement integer. The interpretation of a channel is important when mathematical
operations are applied to them.

Registers & Wires Internal registers reg and wires wire are declared in the body of a
module, in a similar way as channels are declared. A wire is just that: a wire. An n-bit register
is composed of n state holding elements called flip flops. All the registers of a module together
are usually called the state of that module (just as all variables in a computer program are
usually called the state of the program). The module firstage only contains 1 register,
namely x. An array of registers or wires can be specified by adding a range [a:b] behind the
name of the register or wire. Note that inputs and outputs can never be arrays.

Assignment The firstage module contains 2 assignment statements. They have the form
assign destination = expression, and indicate that the result of evaluating expression
should be assigned to destination at every point in time. The destination can either be
a wire or an output channel.
Note that this behavior is very different from the behavior of an assignment statement in an
imperative language such as C or Pascal, where the assignment is executed only when program
control reached it. In firstage for example, assign a out = x states that the a out output
channel always has the same value as the register x, essentially creating a wired connection
from the output of register x to the channel a out. The second assignment statement is a
bit more complex, since it includes an addition and a multiplication. You cannot have more
than 1 assignment to the same wire.

Behavior The last part of the source file specifies the behavior of the component: it specifies
what the next state of the component (composed of all its registers) is in terms of the current
state and current inputs. This requires the introduction of time, to separate “current” from
“next”, which is accomplished by using a clock. The clock is simply a signal that alternates
between 0 and 1 with fixed period. During each period of the clock (typically called a clock
cycle), the state remains the same and the next state is computed. Then at the transition to
the next clock cycle, all registers are updated instantly with their new values.
There is only 1 requirement: the clock period should be large enough to compute the next
state. If not, the registers will capture incorrect values at clock transitions, resulting in a
faulty system. This behavior is specified by an always-block: always @(posedge clk) ...,
where an up-going transition of the clock, also called a “posedge”, is seen is the separator
between 2 clock periods. The always-block in firstage.v contains only 1 statement, saying
the register x should be updated with the value of a in on positive clock edges if the enabled
signal is 1.
After synthesizing the design, ISE will indicate what the minimum clock period should be in
order to guarantee that all register inputs have time enough to reach their final values (to
stabilize). This minimum period gives an upper bound on the clock rate at which the system
will perform correctly.

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Generate Now take a look at the source file fir.v. This module is more elaborate, but
you should be able to understand it. The only new part, is the generate statement, which
instantiates a number of firstage modules. These instances are called comp, which is why the
source tree in ISE shows “comp - firstage (firstage.v)”: it show the local name of the module
instance, followed by the module name, followed by the file name.
There are many books available on Verilog, and there are many tutorials and guides available
on the web, see for example: http://www.asic-world.com/verilog/index.html. Note that
Verilog 2001 is used during the labs, which has some extended features compared to earlier
versions of Verilog. The Verilog 2001 standard can be found at http://ieeexplore.ieee.
org/iel5/7578/20656/00954909.pdf?arnumber=954909

Questions

1. How many firstage modules are instantiated in the filter module?

3 Hardware synthesis
As you might have guessed the Verilog source files define a finite impulse response (FIR) filter.
Let’s examine some properties of the hardware implementation of this filter by synthesizing
it.
The first step in translating your design from an HDL design to a format which can be loaded
into an FPGA is called synthesis. Synthesis generates a net list, which is a graph of hardware
components similar to a block diagram, from the Verilog sources. This is not always possible,
because not all Verilog constructs are synthesizable: some are only meant for simulation
or specification. Furthermore, not all constructs that could in principle be synthesized are
supported by the Xilinx synthesizer XST.
In order to synthesize the design, select the Verilog module fir in the source window (it
should be the top level module), en then double click on Synthesize - XST in the process
window. The transcript is cleared automatically and the output of the synthesize process is
directed to it. Synthesis might take a while depending on your system. When the process
has finished, the last line should be Process "Synthesize" completed successfully.
You can examine the generated net list by invoking one of the processes View RTL Schematic
or View Technology Schematic under Synthesize - XST. The former one gives an abstract
graphical representation of the design (in terms of adders, multipliers, registers, etc.), while
the latter gives a more detailed design (in terms of LUTs, flip-flops, etc.) targeted to the
FPGA you have selected for your project.
The design summary has now been extended and you can navigate the extensive synthesis
report. Select Synthesis Messages to get an overview of the warnings. The warnings for this
project should refer to signals that are defined but never used and registers with unconnected
output ports. In this case there are no serious warnings, but when you are debugging your
own designs, it is a good idea to look at them and verify that all warnings are as expected.
If for example a signal isn’t used, while it should be, you probably did something wrong.
Now select Synthesis Report in the design summary and find the section called “TIMING
REPORT”. In it is a subsection “Timing Summary” that contains four very important timing

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figures. They represent the largest delays in the design which gives a lower bound for the
clock period, and hence an upper bound for the clock frequency at which the design operates
correctly. Note however that these numbers are only an estimate, because the synthesizer
assumes that all of the components of your design can be placed closely together on the
FPGA. This might not always be possible and therefore the real delays of your design can be
a lot higher. The reported delays are:

• Minimum period: the largest delay among all combinational paths (paths with no reg-
isters on them) starting at a register and ending at a register.

• Minimum input arrival time before clock: the largest delay among all combinational
paths starting at an input channel and ending at a register.

• Maximum output required time after clock: the largest delay among all combinational
paths starting at a register and ending at an output channel.

• Maximum combinational path delay: the largest delay among all combinational paths
starting at an input channel and ending at an output channel.

These values are computed for the system as a whole, not for individual sub-components. If
in the environment all inputs and outputs are directly connected to registers, all these values
collapse into 1 value, namely the first one. Because this assumption is usually valid, one
should take the maximum of these 4 values as being the real minimum clock period, and not
simply the minimum period as the synthesizer states.
The Synthesis report contains much more information. You will need to browse through it to
find some of the answers to the questions below.

Questions

2. Draw block diagrams of the following systems, and classify each combinational path in
it as 1 of the 4 possibilities mentioned above:

(a) The firstage module in isolation.

(b) A 32-tap FIR filter based on this FIR-stage module.

3. What is the maximum sample frequency of the 32-tap filter design according to the
synthesis report?

4. Find out how many of the following resources are used by the design, and justify the
number:

(a) 16x16 bit Multipliers.

(b) Slice registers.

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4 Hardware simulation

Before translating a Verilog design to actual hardware, it is usually simulated on a computer

to verify its functional correctness. This requires a test bench that determines what is to
be simulated and a simulator that actually simulates the design and the test bench. ISE
contains a simulator, but a test bench has to be written specifically for each module you want
to simulate. The file firtest.v contains a test bench for the module fir that executes the
FIR filter on the samples from a given file.

4.1 Examining the test module

In the source window select the Behavioral Simulation source view. The source tree should
now change, with firtest being at the top of the tree. Examine the firtest.v file. As
you can see, it differs from the other Verilog modules: it doesn’t have any i/o ports and it
contains simulator commands, which start with a $ symbol.
If you select the firtest module in the sources window, the process window should display
the ISim Simulator process node. Expand this node and then double click on Simulate
Behavioral Model to simulate your design. A new ISim simulator window will open. If you
click on the run (play) button on the toolbar, then you will observe in the console pane at
the bottom of the simulator window that the simulation runs with ”‘File Descriptor” error
and warning messages. This is because the file input.bin could not be opened. This file is
used to get the samples from that are fed into the filter. We must thus first copy input.bin
to source directory of our design.

4.2 Simulate the design on the test input

Once you have copied input.bin to your source directory, click on re-launch on the toolbar
and then run the simulation again. This time, the simulation should end successfully. Now
view Default.wcfg in the workspace. The workspace should show the signals for the first
1000ns of the simulation. The process window has been expanded with the hierarchy of
firtest. You can drag signals from this hierarchy to the workspace to see their values. Note
however that the simulator only records the values of the signals in the simulation from the
point where they were added. Adding a signal to the workspace will require resetting the
simulation to time 0 to see the actual values of the new signals.
You can control the simulation with the buttons that have been added to the toolbar. The
blue play button with an X executes the simulation for a specified number of nanoseconds.
The blue play button without the X executes the simulation until it terminates. Press this
button now to finish the simulation. The simulation will take a couple of minutes. When
the simulation stops with an error message, it is probably out of memory because of all the
signals it needs to keep track of. This can be fixed by removing all signals from the simulation
except 1 that doesn’t change very often and resetting the simulation.

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4.3 Examining the output

When the simulation is finished, it writes the output to a file named output.bin. This file
has the same format as the input file. Import the input and output files in Audacity and
compare them. You can visualize the differences by zooming in on both tracks until you can
see the individual samples, or by selecting ”Plot Spectrum” in the ”Analyze” menu for both
tracks.
Finally, export the raw input and output files to wave files called “input.wav” and “out-
put.wav” respectively, which we will use later-on in Matlab.

Questions

5. (a) What was the duration of the sound in your original sound file?
(b) How much simulated time did the design take to filter your sound file?
(c) What was the sample rate of the simulated system?
(d) What is relationship between sample rate and clock rate of the simulation?
(e) What are the filter coefficients used in the test module?
(f) What changes are observed in the frequency spectrum when the first and last 2
coefficients are made zero from the test module’s filter?

5 Filter design

In this section, we will use Matlab to analyze the filter from the test module, and design a
better one.

5.1 Analyzing the filter

Start Matlab and type fdatool in the workspace followed by an enter. The filter design and
analysis tool will start, in which we will analyze the filter coefficients from firtest.v. Select
File → Import Filter from Workspace. Enter “[1]” in the Denominator field and enter the
list of filter coefficients in the Numerator field enclosed by square brackets, i.e. [a b c d
...]. All other settings can be left at their default values. Press Import Filter to see the
magnitude response of this filter. The horizontal axis of the graph represents the frequency
(normalized to half the sampling frequency) and the vertical axis represents the magnitude
in dB. Remember that dB is a logarithmic scale. Where an increase of 10dB means a 10 fold
increase in amplitude, and a 20dB increase means a 100 fold increase in amplitude.

5.2 Designing filters

Besides analyzing filters, the tool can also be used to generate a filter according to some
specifications. Press the Design Filter button in the lower left corner. Then press the Filter
Specifications button in the toolbar and set:

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 • Response Type to “Lowpass”.
• Design Method to “FIR - Equiripple”.
• Filter Order to “Minimum Order”.
• Fs to “44100” (the sampling frequency).
• Fpass to “3000” (the frequency at which attenuation should start).
• Fstop to “4000” (the frequency from where on no signal should be present).

Press the Design Filter button to generate a filter with the lowest possible tap-count that
satisfies the specifications. When the process finishes, the magnitude response of the resulting
filter is shown. Note that this filter is more strict than the one used in the verilog test module:
frequencies below 3000 Hz are hardly affected, and frequencies above 4000Hz are heavily
attenuated (the difference is 80dB). The disadvantage is that more coefficients are used. In
general: the more strict the filter specifications, the more coefficients are required.

Questions

6. (a) What is the order of the filter you just designed?

(b) How many filter stages would be required to implement this filter?

6 Signal analysis
Matlab can also be used to analyze signals. In the Matlab workspace, select File → Import
Data.... Select the file input.wav and press OK, and then Finish. Copy the data to the
variable sample by typing the command sample=data;. Repeat this process for the file
output.wav, but now copy the data to the output variable.
Issue the command sptool, which starts the signal processing toolbox. To import a signal
into the tool, select File → Import. In the Data field enter “sample” and in the Sampling
Frequency field enter “44100”. Under Name you have to enter “sample” again. Now press
OK. The sample signal has now been imported into the sptool. Repeat this process for the
output signal (using “output” instead of “sample”).
In the SPTool you can view the signals by clicking on the View button below the signals
column. This shows the time-domain waveform, which doesn’t give much insight into the
signal except its amplitude. It is usually more interesting to look at a signal in the frequency
domain, because it tells us how much of each frequency is present in a signal.
Select the sample signal and press Create in the spectra column. In the new window that
opens, press Apply and then close it. Select the output signal and repeat the procedure.
Now select both spect1 and spect2 in the spectra column and press View. You now see the
power spectral density (PSD) of both signals. In the graph right-click and select spect2 →
Line Properties. Select “Red” and press OK. The PSD of the original signal is now shown
in blue, while the PSD of the filtered signal is shown in red. As you can see the power of
the frequencies above 3kHz has been reduced significantly in the output. The power in the
higher frequencies may have risen because of noise introduced by the filter.

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Questions

7. What is the stop frequency of the filter, judging from the PSD?

8. (a) What is the highest frequency displayed on x-axis of the PSD graph?
(b) Briefly explain the relationship between this frequency and the sampling frequency
of 44.1kHz.

7 A different filter implementation

To answer the questions below you will need to examine the filter design from the file
filter2.zip. Make sure you create a new project for this filter.

Questions

9. One of the filter designs is a direct-form implementation, and the other one is a trans-
posed direct-form implementation. Which of the zip-files contained which implementa-
tion?

10. Answer questions 1 through 4 again but now for the second design instead of the first
one.

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