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III SEMESTER
LABORATORY MANUAL
LIST OF EXPERIMENTS
1. APPLICATION OF OP-AMP I
2. APPLICATION OF OP-AMP II
8. CODE CONVERSION
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1. APPLICATIONS OF OP-AMP-I
AIM:
To design an inverting amplifier, non-inverting amplifier and voltage follower for the
given specifications using Op-Amp IC 741
REFERENCE BOOKS:
APPARATUS REQUIRED:
5 Bread Board 1
6 Resistors As required
THEORY:
Summing amplifier is a type operational amplifier circuit which can be used to sum
signals. The sum of the input signal is amplified by a certain factor and made available at the
output .Any number of input signal can be summed using an op-amp. The circuit shown is a
three input summing amplifier in the inverting mode.
In the circuit, the input signals Va, Vb, Vc are applied to the inverting input of the op-
amp through input resistors Ra, Rb, Rc. Any number of input signals can be applied to the
inverting input in the above manner. Rf is the feedback resistor. Non inverting input of the op-
amp is grounded using resistor Rm. RL is the load resistor.
A non inverting summing amplifier circuit with three inputs is shown above. The
voltage inputs Va, Vb and Vc are applied to non inverting input of the op-amp. Rf is the
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feedback resistor. The output voltage of the circuit is governed by the equation;
VOLTAGE FOLLOWER
A unity gain buffer amplifier may be constructed by applying a full series negative
feedback (Fig. 2) to an op-amp simply by connecting its output to its inverting input, and
connecting the signal source to the non-inverting input (Fig. 3). In this configuration, the entire
output voltage (β = 1 in Fig. 2) is placed contrary and in series with the input voltage. Thus the
two voltages are subtracted according to Kirchhoff's voltage law (KVL) and their difference is
applied to the op-amp differential input. This connection forces the op-amp to adjust its output
voltage simply equal to the input voltage (Vout follows Vin so the circuit is named op-amp
voltage follower).
PRECAUTIONS:
Output voltage will be saturated if it exceeds ± 15V.
PROCEDURE:
PIN DIAGRAM:
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CIRCUIT DIAGRAM:
DESIGN:
OBSERVATIONS:
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CIRCUIT DIAGRAM:
DESIGN:
Assume R1=R2=R3=Rf/2=R
We know for a Non-inverting Summing Amplifier
Vo = (1+ (Rf/R1)) (( Va+Vb+Vc)/3)
V0= (V1+V2+V3)
OBSERVATIONS:
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CIRCUIT DIAGRAM:
Voltage Follower
Model Graph:
RESULT:
The design and testing of the Inverting, Non-inverting amplifier and Voltage Follower is
done and the input and output waveforms were drawn.
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2. APPLICATIONS OF OP-AMP-II
(Differentiator and Integrator)
AIM:
To design a Differentiator circuit for the given specifications using Op-Amp IC 741
REFERENCE BOOKS:
APPARATUS REQUIRED:
THEORY:
Differentiator
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CIRCUIT DIAGRAM :
(Differentiator)
DESIGN:
Given: fa = ---------------
We know the frequency at which the gain is 0 dB, fa =1 /(2π Rf C1)
Let us assume C1 = 0.1 µF; then
Rf =
Since fb = 10 fa, fb = ---------------
We know that the gain limiting frequency fb = 1 / (2π R1 C1)
Hence R1 =
Also since R1C1 = Rf Cf ;
Cf =
OBSERVATIONS:
Amplitude
Sl. No. Waveforms
in Volt
1 Input Waveform
2 Output Waveform
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CIRCUIT DIAGRAM :
(Integrator)
DESIGN:
Therefore Rf =
We get, R1 =
OBSERVATIONS:
Amplitude
Sl. No. Waveforms Time Period in ms
in Volt
1 Input Waveform
2 Output Waveform
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Pin diagram:
THEORY:
Integrator
A circuit in which the output voltage waveform is the integral of the input voltage
waveform is the integrator. Such a circuit is obtained by using a basic inverting amplifier
configuration if the feedback resistor Rf is replaced by a capacitor Cf . The expression for the
output voltage is given as,
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T ≥Rf Cf
The integrator is most commonly used in analog computers and ADC and signal-
wave shaping circuits.
PROCEDURE:
MODEL GRAPH:
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DISCUSS QUESTIONS:
1. What is integrator?
2. Write the disadvantages of ideal integrator?
3. Write the application ofintegrator?
4. Why compensation resistance is needed inintegrator and how will you findit values?
5. What is differentiator?
6. Write the disadvantages of ideal differentiator.
7. Write the application of differentiator?
8. Why compensation resistance is needed in differentiator and how will you findit
values?
Why integrators are preferred over differentiators in analog comparators?
MODEL GRAPH:
Comparator
OBSERVATIONS:
Amplitude
Sl. No. Waveforms Time Period in ms
in Volt
1 Input Waveform
2 Output Waveform
RESULT:
The design of the Integrator, Differentiator and Voltage Follower circuit was done and
the input and output waveforms were obtained.
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AIM:
To design an astable multivibrator circuit for the given specifications using 555 Timer
IC.
REFERENCE BOOKS:
APPARATUS REQUIRED:
1 CRO 30 MHz 1
2 Dual RPS 0 – 30 V 1
3 Timer IC IC 555 1
4 Bread Board 1
5 Connecting wires and probes As required
THEORY:
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PIN DIAGRAM:
CIRCUIT DIAGRAM:
DESIGN:
Given f= 4 KHz,
Therefore, R2 =
OBSERVATIONS:
Amplitude
Sl. No. Waveforms Time Period in ms
in Volt
1 Output Waveform
2 Capacitor voltage
PROCEDURE:
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DISCUSSION QUESTIONS:
RESULT:
The design of the Astable multivibrator circuit was done and the output voltage and
capacitor voltage waveforms were obtained.
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AIM:
REFERENCE BOOKS:
APPARATUS REQUIRED:
THEORY:
A monostable multivibrator often called a one-shot multivibrator is a pulse
generating circuit in which the duration of the pulse is determined by the RC network
connected externally to the 555 timer. In a stable or stand-by state the output of the circuit
is approximately zero or at logic low level. When an external trigger pulse is applied, the
output is forced to go high (approx. Vcc). The time during which the output remains highis
given by,
tp = 1.1 R1 C
At the end of the timing interval, the output automatically reverts back to its logic
low state. The output stays low until a trigger pulse is applied again. Then the cycle
repeats. Thus the monostable state has only one stable state hence the name monostable.
PROCEDURE:
1. Connections are given as per the circuit diagram.
2. + 5V supply is given to the + Vcc terminal of the timer IC.
3. A negative trigger pulse ofless than (1/3 VCC) i.e Groundto pin 2 ofthe 555 IC
4. At pin 3the output time period is observed with the help of a LED or CRO
5. At pin 6 the capacitor voltage is obtained in the CRO and the V0 and Vc voltage
waveforms are plotted in a graph sheet.
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CIRCUIT DIAGRAM:
DESIGN:
Typical values:
PIN DIAGRAM:
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OBSERVATIONS:
Time Period
Sl. No. Value of R1 Value of C
Theoritical Practicle
MODEL GRAPH:
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DISCUSSION QUESTIONS:
RESULT:
The design of the Monostable multivibrator circuit was done and the input and output waveforms
were obtained.
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AIM:
To verify the truth table of basic digital ICs of AND, OR, NOT, NAND, NOR, EX-OR gates.
REFERENCE BOOKS:
1. Raj Kamal, ‘ Digital systems-Principles and Design’, Pearson education 2nd edition,
2007
2. M. Morris Mano, ‘Digital Design’, Pearson Education, 2006
APPARATUS REQUIRED:
THEORY:
AND gate:
OR gate:
NOT gate:
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NAND gate:
A NAND gate is a complemented AND gate. The output of the NAND gate will
be ‘0’ if all the input signals are ‘1’ and will be ‘1’ if any one of the input signal is ‘0’.
NOR gate:
A NOR gate is a complemented OR gate. The output of the OR gate will be ‘1’
if all the inputs are ‘0’ and will be ‘0’ if any one of the input signal is ‘1’.
EX-OR gate:
A B = ( A . B’ ) + ( A’ . B )
PROCEDURE:
PIN DIAGRAM OF IC
7432 :
PIN DIAGRAM OF IC 7408 :
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CIRCUIT DIAGRAM:
CIRCUIT
DIAGRAM:
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TRUTH TRUTH
TABLE: TABLE:
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RESULT:
The truth tables of all the basic digital ICs were verified.
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AIM:
To design the logic circuit and verify the truth table of the given Boolean
expression, F (A, B, C, D) = Σ (0, 1, 2, 5, 8, 9, 10)
REFERENCE BOOKS:
1. Raj Kamal, ‘ Digital systems-Principles and Design’, Pearson education 2nd edition,
2007
2. M. Morris Mano, ‘Digital Design’, Pearson Education, 2006
APPARATUS REQUIRED:
PROCEDURE:
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CIRCUIT DIAGRAM:
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DESIGN:
TRUTH TABLE:
INPUT OUTPUT
S. No.
A B C D F=D’B’+C’(B’+A’D)
1. 0 0 0 0 1
2. 0 0 0 1 1
3. 0 0 1 0 1
4. 0 0 1 1 0
5. 0 1 0 0 0
6. 0 1 0 1 1
7. 0 1 1 0 0
8. 0 1 1 1 0
9. 1 0 0 0 1
10. 1 0 0 1 1
11. 1 0 1 0 1
12. 1 0 1 1 0
13. 1 1 0 0 0
14. 1 1 0 1 0
15. 1 1 1 0 0
16. 1 1 1 1 0
The output function F has four input variables hence a four variable Karnaugh Map is used to
obtain a simplified expression for the output as shown,
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RESULT:
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AIM:
To design and verify the truth table of the Half Adder & Full Adder circuits.
REFERENCE BOOKS:
1. Raj Kamal, ‘ Digital systems-Principles and Design’, Pearson education 2nd edition,
2007
2. M. Morris Mano, ‘Digital Design’, Pearson Education, 2006
APPARATUS REQUIRED:
FULL ADDER:
A combinational circuit which performs the arithmetic sum of three input bits is called full
adder. The three input bits include two significant bits and a previous carry bit. A full adder
circuit can be implemented with two half adders and one OR gate.
From the truth table the expression for sum and carry bits of the output can be obtained as,
HALF ADDER
TRUTH TABLE:
Input Output
Sl.n
o
A B S C
1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
4. 1 1 0 1
From the truth table the expression for sum and carry bits of the output can be
obtained as, Sum, S = A B
Carry, C = A . B
CIRCUIT DIAGRAM:
FULL ADDER
TRUTH TABLE:
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Using Karnaugh maps the reduced expression for the output bits can be obtained as,
SUM
CARRY
CARRY = AB + AC + BC
CIRCUIT DIAGRAM:
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PROCEDURE:
RESULT:
The design of the half adder and full adder circuits was done and their truth tables were
verified.
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AIM:
To design and verify the truth table of the Half Subtractor & Full Subtractor
circuits.
REFERENCE BOOKS:
APPARATUS REQUIRED:
THEORY:
The arithmetic operation, subtraction of two binary digits has four possible
elementary operations, namely,
0-0=0
0 - 1 = 1 with 1 borrow
1-0=1
1-1=0
In all operations, each subtrahend bit is subtracted from the minuend bit. In case of the
second operation the minuend bit is smaller than the subtrahend bit, hence 1 is borrowed.
HALF SUBTRACTOR:
A combinational circuit which performs the subtraction of two bits is called half
subtractor. The input variables designate the minuend and the subtrahend bit, whereas the
output variables produce the difference and borrow bits.
FULL SUBTRACTOR:
A combinational circuit which performs the subtraction of three input bits is called
full subtractor. The three input bits include two significant bits and a previous borrow bit.
A full subtractor circuit can be implemented with two half subtractors and one OR gate.
From the truth table the expression for difference and borrow bits of the output can be
obtained as,
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HALF SUBTRACTOR
TRUTH TABLE:
Input Output
S.no
A B Diff Borr
1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
4. 1 1 0 0
From the truth table the expression for difference and borrow bits of the output can be
obtained as,
Difference, DIFF = A B
Borrow, BORR = A’. B
CIRCUIT DIAGRAM:
2. FULL SUBTRACTOR
TRUTH TABLE:
Inpu
t Output
S.no
A B C Diff Borr
1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1
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Using Karnaugh maps the reduced expression for the output bits can be
obtained as,
DIFFERENCE
BORROW
CIRCUIT DIAGRAM:
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PROCEDURE:
DISCUSSION QUESTIONS:
RESULT:
The design of the half subtractor and full subtractor circuits was done and their truth
tables were verified.
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7. a. CODE CONVERSION
AIM:
REFERENCE BOOKS:
1. Raj Kamal, ‘ Digital systems-Principles and Design’, Pearson education 2nd edition,
2007.
2. M. Morris Mano, ‘Digital Design’, Pearson Education, 2006
APPARATUS REQUIRED:
THEORY:
The availability of large variety of codes for the same discrete elements of information
results in the use of different codes by different systems. A conversion circuit must be inserted
between the two systems if each uses different codes for same information. Thus, code converter
is a circuit that makes the two systems compatible even though each uses different binary code.
The bit combination assigned to binary code to gray code. Since each code uses four bits
to represent a decimal digit. There are four inputs and four outputs. Gray code is a non-weighted
code.
The input variable are designated as B3, B2, B1, B0 and the output variables are
designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The
Boolean functions are obtained from K-Map for each output variable.
A code converter is a circuit that makes the two systems compatible even though each
uses a different binary code. To convert from binary code to Excess-3 code, the input lines must
supply the bit combination of elements as specified by code and the output lines generate the
corresponding bit combination of code. Each one of the four maps represents one of the four
outputs of the circuit as a function of the four input variables.
A two-level logic diagram may be obtained directly from the Boolean expressions
derived by the maps. These are various other possibilities for a logic diagram that implements
this circuit. Now the OR gate whose output is C+D has been used to implement partially each of
three outputs.
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DESIGN:
TRUTH TABLE:
From the truth table the expression for the output gray bits are,
G3 (B3, B2, B1, B0) = Σ (8, 9, 10, 11, 12, 13, 14, 15)
G2 (B3, B2, B1, B0) = Σ (4, 5, 6, 7, 8, 9, 10, 11)
G1 (B3, B2, B1, B0) = Σ (2, 3, 4, 5, 9, 10, 11, 12, 13)
G0 (B3, B2, B1, B0) = Σ (1, 2, 5, 6, 9, 10, 13. 14)
Hence obtain the reduced SOP expression using Karnaugh maps as follows,
G3 = B3
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CIRCUIT DIAGRAM:
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PROCEDURE:
DISCUSSION QUESTIONS:
RESULT:
The design of the 4-bit Binary to Gray code converter circuit was done and its truth table was
verified.
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AIM:
To implement the odd and even parity checkers using the logic gates and also to generate
the odd parity and even parity numbers using the generators.
REFERENCE BOOKS:
1. Raj Kamal, ‘ Digital systems-Principles and Design’, Pearson education 2nd edition,
2007.
2. M. Morris Mano, ‘Digital Design’, Pearson Education, 2006.
APPARATUS
REQUIRED:
PROCEDURE:
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TRUTH TABLE:
DISCUSSION QUESTIONS:
RESULT:
The odd and even parity checkers are implemented using the logic gates and the odd
parity and even parity numbers are generated using the corresponding generators.
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8. a. MULTIPLEXERAND DEMULTIPLEXER
AIM:
To design and verify the truth table of a 4X1 Multiplexer & 1X4 Demultiplexer.
REFERENCE BOOKS:
1. Raj Kamal, ‘ Digital systems-Principles and Design’, Pearson education 2nd edition,
2007
2. M. Morris Mano, ‘Digital Design’, Pearson Education, 2006
APPARATUS REQUIRED:
THEORY:
Multiplexing means transmitting a large number of information units over a smaller number of
channels or lines. A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single output line. The selection of
particular input line is controlled by a set of selection lines. Normally, there are 2 n input lines
and n selection lines whose bit combinations determines which input is selected.
A multiplexer is called a data selector, since it selects one of many inputs and steers the binary
information to the output line. A Strobe is also provided to allow the designer to disable all
output data until a specified time. Then, by allowing the STROBE to go low, the proper lead
can be selected. This feature is very useful where data might be changing the same time
DATA SELECT leads change. It is a very useful Medium Scale Integration (MSI) function
and has a multitude of applications. It is used for connecting two or more sources to a single
destination among the computer units and itis useful for constructing acommon bus system.
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4 X 1 MULTIPLEXER
LOGIC SYMBOL:
TRUTH TABLE:
CIRCUIT DIAGRAM:
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1X4 DEMULTIPLEXER
Input Output
S.no
S1 S2 Din Y0 Y1 Y2 Y3
1. 0 0 0 0 0 0 0
2. 0 0 1 1 0 0 0
3. 0 1 0 0 0 0 0
4. 0 1 1 0 1 0 0
5. 1 0 0 0 0 0 0
6. 1 0 1 0 0 1 0
7. 1 1 0 0 0 0 0
8. 1 1 1 0 0 0 1
CIRCUIT DIAGRAM:
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DISCUSSION QUESTIONS:
1. What is multiplexer?
2. What are the applications of multiplexer?
3. What is the difference between multiplexer & demultiplexer?
RESULT:
The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their
truth tables were verified.
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AIM:
To study the operation of Encoder and Decoder circuits using logic gates
REFERENCE BOOKS:
APPARATUS REQUIRED:
THEORY:
DECODER
The example decoder circuit would be an AND gate because the output of an AND gate
is "High" (1) only when all its inputs are "High." Such output is called as "active High output".
If instead of AND gate, the NAND gate is connected the output will be "Low" (0) only when all
its inputs are "High". Such output is called as "active low output".
A slightly more complex decoder would be the n-to-2n type binary decoders. These types
of decoders are combinational circuits that convert binary information from 'n' coded inputs to a
maximum of 2n unique outputs. In case the 'n' bit coded information has unused bit
combinations, the decoder may have less than 2n outputs. 2-to-4 decoder, 3-to-8 decoder or 4-to-
16 decoder are other examples.
The input to a decoder is parallel binary number and it is used to detect the presence of a
particular binary number at the input. The output indicates presence or absence of specific
number at the decoder input.
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OBSERVATIONS:
Inputs Outputs
A B Y3 Y2 Y1 Yo
B
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
OBSERVATIONS:
Input Output
D7 D6 D5 D4 D3 D2 D1 D0 A B C
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
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ENCODER
An encoder is a device, circuit, transducer, software program, algorithm or person that
converts information from one format or code to another. The purpose of encoder is
standardization, speed, secrecy, security, or saving space by shrinking size. Encoders are
combinational logic circuits and they are exactly opposite of decoders. They accept one or more
inputs and generate a multibit output code.
Encoders perform exactly reverse operation than decoder. An encoder has M input and N output
lines. Out of M input lines only one is activated at a time and produces equivalent code on
output N lines. If a device output code has fewer bits than the input code has, the device is
usually called an encoder
PROCEDURE:
RESULT:
The design of the Encoder and Decoder circuit was done and the input and output were
obtained
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AIM:
REFERENCE BOOKS:
1. Raj Kamal, ‘ Digital systems-Principles and Design’, Pearson education 2nd edition,
2007
2. M. Morris Mano, ‘Digital Design’, Pearson Education, 2006
APPARATUS REQUIRED:
THEORY:
A Flip Flop is a sequential device that samples its input signals and changes its output
states only at times determined by clocking signal. Flip Flops may vary in the number of inputs
they possess and the manner in which the inputs affect the binary states.
RS FLIP FLOP:
The clocked RS flip flop consists of NAND gates and the output changes its state with
respect to the input on application of clock pulse. When the clock pulse is high the S and R
inputs reach the second level NAND gates in their complementary form. The Flip Flop is reset
when the R input high and S input is low. The Flip Flop is set when the S input is high and R
input is low. When both the inputs are high the output is in an indeterminate state.
D FLIP FLOP:
To eliminate the undesirable condition of indeterminate state in the SR Flip Flop when
both inputs are high at the same time, in the D Flip Flop the inputs are never made equal at the
same time. This is obtained by making the two inputs complement of each other.
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Circuit Diagram:
SR FLIP – FLOP:
S
7400
Q
7400
CLK
7400 Q
7400
R
JK FLIP – FLOP:
J 7411
7400 Q
CLK
7400 Q
7411
K
D FLIP FLOP:
D
7400
Q
7400
CLK
7400 Q
7400
T FLIP FLOP:
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7408 7400
7400
T CLK
7400
7408 7400
RS Flip -Flop
JK Flip -Flop
D Flip -Flop
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T Flip -Flop
JK FLIP FLOP:
The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop. JK inputs
behave like S and R inputs to set and reset the Flip Flop. The output Q is NAND with K input
and the clock pulse, similarly the output Q’ is NAND with J input and the Clock pulse. When
the clock pulse is zero both the AND gates are disabled and the Q and Q’ output retain their
previous values. When the clock pulse is high, the J and K inputs reach the NOR gates. When
both the inputs are high the output toggles continuously. This is called Race around condition
and this must be avoided.
T FLIP FLOP:
This is a modification of JK Flip Flop, obtained by connecting both inputs J and K inputs
together. T Flip Flop is also called Toggle Flip Flop.
RESULT:
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AIM:
To implement and verify the truth table of a serial in serial out and
parallel in parallel out shift
register.
REFERENCE BOOKS:
APPARATUS REQUIRED:
THEORY:
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CIRCUIT DIAGRAM:
Q4
D1
D Q D Q D Q D Q
1 7 1 2 7 2 3 7 3 4 7 4
Clock pulse
D D
D4 740 3 D2 1
4
Load/
shift
74 740
08 7408 8
74
32 7432 7432
O/
P
D Q D Q D Q D 7
1 7 1 2 7 2 3 7 3 4 Q4
cp cp cp cp
1 74 2 74 3 74 4 74
4 4 4 4
Clock pulse
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TRUTH TABLE:
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PROCEDURE:
RESULT:
The truth table of a serial in serial out left shiftregister was hence verified.
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AIM
REFERENCE BOOKS:
APPARATUS REQUIRED:
THERORY
Fo=1.2/4R1 C1
PROCEDURE
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CIRCUIT DIAGRAM:
OBSERVATIONS:
MODEL GRAPH:
Input
Vin
Time (ms)
Output
Vo
Time (ms)
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RESULT
Thus the frequency multiplication using phase locked loop was done and the
output wave forms were drawn.
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CIRCUIT DIAGRAM:
+15V
10 KΏ
8 6
2K
Ώ
4
5
20 3
KΏ
NE566
7 1
0.01µF
INTERNAL DIAGRAM:
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AIM:
To obtain square wave and triangular wave using voltage controlled oscillator
REFERENCE BOOKS:
1. Ramakant A.Gayakward, ‘Op-amps and Linear Integrated Circuits’, IV edition, Pearson
Education, 2003 / PHI. (2000)
2. D.Roy Choudhary, Sheil B.Jani, ‘Linear Integrated Circuits’, II edition, New Age, 2003.
APPARATUS REQUIRED:
1. Digital IC trainer 1
2. VCO NE566 1
4. Resistor 2K, 10K 2
5. Capacitor 0.01µF 1
7. POT 20K 1
9. Connecting wires and probes As required
THEORY:
In most cases, the frequency of an oscillator is determined by the time constant RC.
However, in cases or applications such as FM, tone generators, and frequency-shift keying
(FSK), the frequency is to be controlled by means of an input voltage, called the control voltage.
This can be achieved in a voltage-controlled oscillator (VCO). A VCO is a circuit that provides
an oscillating output signal (typically of square-wave or triangular waveform) whose
frequency can be adjusted over a range by a dc voltage. An example of a VCO is the 566 IC
unit, that provides simultaneously the square-wave and triangular-wave outputs as a function of
input voltage. The frequency of oscillation is set by an external resistor R1 and a capacitor C1
and the voltage Vc applied to the control terminals. Figure shows that the 566 IC unit contains
current sources to charge and discharge an external capacitor Cv at a rate set by an external
resistor R1 and the modulating dc input voltage. A Schmitt trigger circuit is employed to switch
the current sources between charging and discharging the capacitor, and the triangular voltage
produced across the capacitor and square-wave from the Schmitt trigger are provided as outputs
through buffer amplifiers. Both the output waveforms are buffered so that the output impedance
of each is 50 f2. The typical magnitude of the triangular wave and the square wave are
2.4 V peak.to-peak and 5.4 Vpeak.to.peak.
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PROCEDURE:
RESULT:
Thus the voltage controlled oscillator using NE566 was done and the output was verified.
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