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• Buffered Vs Unbuffered
• Basics RC Circuits
• Questions/References/Appendix
Basic block diagram of IO Communication &
Introduction to IOs
Generic Diagram of IO communication (IC to IC
Communication)
Data generator
package
package
Printed Wiring
Buffers Receiver
Board
• Input
• Output (2 states or 3 states)
• Bi – directional
Input Buffer
VCC
To Internal
PAD circuitry
VSS
From Internal
circuitry
PAD
From Internal
circuitry
VSS
• The output buffer passes data from the core to the external world which is usually
another component on the Printed Circuit Board (PCB) through a track.
• It performs level conversion from the core level voltage to the IO level output
voltage (the motherboard voltage level).
• Output buffers can be either 2-state or 3-state depending on the application. For a
3-state buffer, the three states are logic low, logic high and high impedance.
• A 3-state buffer will have an enable signal which facilitates achieving high
impedance (Hi-Z) at the PAD
• ESD diodes associated with the output buffer also help protect ICs from damage
due to ESD events.
Bi-directional Buffer
VCC
From Internal
circuitry
To Internal
circuitry PAD
From Internal
circuitry
VSS
If T >>RC If T = RC If T << RC
RC Charging Table – Low Pass RC
% of maximum
Time Constant RC Value
Voltage Current
PAD
From Internal
circuitry 250u
VSS
Now
• Max. lengths calculated below for which the length considered as lumped
model only. If it crosses the calculated length we must consider it as a
distributed mode.
• With shorter signal lines all line reflections occur during the rise/fall time of
the signal. In this case it is allowed to use the simplified capacitive load line
model.
Signals launch on t - line
RS
RL
VS VL
RL
VL = VS
RL + RS
Transmission Lines - Reflections
Analysis of line reflections
r Reflected
Special Cases to Remember
A: Terminated in Zo
Zs -
Zo Zo r Zo Zo 0
Vs Zo + Zo
B: Short Circuit
Zs -
Zo r 0 Zo -1
Vs 0 + Zo
C: Open Circuit
Zs - Zo
Zo r 1
Vs + Zo
Terminations
Termination definitions
• Now the question is how to reduce the voltage/current reflections
• Line reflections are eliminated by correct line terminations
• Properly terminating the trace will reduce voltage reflections.
• There are two general strategies for transmission line termination:
• Match the load impedance to the line impedance (Far End Termination)
• Match the source impedance to the line impedance (Near End Termination)
• From a systems design perspective, the first strategy is preferred,
since it eliminates any reflections travelling back to the source, thus
resulting in less noise and electromagnetic interference (EMI).
• from a practical standpoint, either of the two techniques can be
used, depending on the system under design.
Termination Techniques
• There are three basic types of terminations:
• Series Termination (Near End)
• Pull-up/Pull-down Termination (Far End)
• Parallel AC Termination (Far End)
• Parallel AC termination is usually not recommended for clock
generators, since it degrades the rise time of the output clock.
• However, parallel AC termination can be used with series
termination to reduce EMI.
• Except for series termination, the termination network should be
attached to the input (load) that is electrically the greatest distance
from the source.
• Component leads should be as short as possible to prevent
reflections due to lead inductance.
All Termination Circuits
Input Buffer/Receiver Design
Definitions
• Good receiver circuits (input buffers) in CMOS chips are required in
any high-speed, board-level design to change the distorted signals
transmitted between chips (because of the imperfections in the
interconnecting signal paths) into well-defined digital signals with
the correct pulse widths and amplitudes.
• Input buffers are circuits that take a chip's input signal, with
imperfections such as slow rise and fall times, and convert it into a
clean digital signal for use on-chip.
• If the buffer doesn't "slice" the data in the correct position, timing
errors can occur.
• If the input signal is sliced too high or too low, the output signal's
width is incorrect.
• In high-speed systems this reduces the timing budget in the system
and can result in errors.
Basic Requirements
• The ‘switching point’ voltage is defined as the voltage at which the input and
the output transitions from logic high to logic low or vice versa
• If the switching point is too high, the output data has good low noise margin
• If the switching point is too low, the output data has high noise margin
• If the buffer doesn’t slice the data at the correct time instants, timing errors
can occur i.e., the bits of data at the output of the buffer gets distorted.
Signal Noise and Removal Possibilities
Hysteresis
This figure reveals the benefit of using a Schmitt trigger, namely, it allows slow moving
inputs to be made into good solid logic high and low values.
Applications of Schmitt Trigger
• SI/PI Analysis
REFERENCES
References
• https://uta-ir.tdl.org/uta-
ir/bitstream/handle/10106/24772/Abraham_uta_2502M_12777.pdf?sequence=1
• http://www.rnbs.hiroshima-
u.ac.jp/RCNS/lecture/pdf/HJM_H20/OHP_CMOS_4(H20-5-2).pdf
• http://download.intel.com/education/highered/signal/ELCT762/Class17_18_IBIS_io_
buffer_class.ppt
Most of the slides deleted, please go through all the references mentioned
• https://www.u-
cursos.cl/usuario/9553d43f5ccbf1cca06cc02562b4005e/mi_blog/r/CMOS_Circuit_D
esign__Layout__and_Simulation__3rd_Edition.pdf
• http://www.ti.com/lit/an/scha004/scha004.pdf
• http://www.oldfriend.url.tw/article/SI_PI_book/Signal%20and%20Power%20Integrit
y%20-%20Simplified_2nd_Eric%20Bogatin_Prentice%20Hall%20PTR_2010.pdf
• https://www.google.co.in/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&
uact=8&ved=0ahUKEwiLjfqX0KjUAhVMvo8KHQ1SBisQFgghMAA&url=http%3A%2F%
2Fdownload.intel.com%2Feducation%2Fhighered%2Fsignal%2FELCT762%2FClass07_
Using_Transmission_lines.ppt&usg=AFQjCNHaQAuOtX5kbH6C0T6qIs6dvyHJig
• http://www.physics.ohio-state.edu/~hughes/cdf_osu/xft/documents/layout.pdf
• http://www.electronics-tutorials.ws/filter/filter_2.html
• http://www.electronics-tutorials.ws/rc/rc_3.html