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1 1

LCFC Confidential
Ju
st
BMWC1&C2 M/B Schematics Document
2 for
NM-A471 REV:0.4 2

LC
Intel Braswell M-Processor with DDRIIIL + NV (N16V-GM) GPU
FC
2015-03-23 PE
3
REV:0.4
De 3

bu
g
4 4

Security Classification
Classification LC Future Center Secret Data Title
Issued Date 2014/09/24 Deciphered Date 2015/03/23 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
BMWC1

www.bios-downloads.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, April 07, 2015 Sheet 1 of 60
A B C D E
A B C D E

NV (N16V-GM)
GB2B-64 Package PCI-Express Memory BUS (DDR3L)
Page 18~28 PCIe Port0 Dual Channel DDR3L-SO-DIMM
2x Gen2 Page 14

VRAM 256/128*16 1.35V DDR3L 1600 MT/s


UP TO 8G
1
DDR3L*4 2GB/1GB 1
Page 19~28

USB 3.0 1x USB Left 3.0 Conn


HDMI
HDMI Conn. USB 2.0 1x USB 3.0 Port0
Page 34
USB 2.0 Port0 Page 41

DP to VGA DPx2 Lane


Braswell-M (4.5W) USB Right 2.0 Conn

Ju
VGA Conn. USB 2.0 1x
Page 36 Page 35 ITE IT6515FN
USB 2.0 Port1 Page 45
eDP Conn
BGA-1170 USB Right 2.0 Conn

st
USB 2.0 1x
Int. Camera
USB 2.0 Port3 25mm*27mm USB2.0 Port4 Page 45
eDP x2 Lane
USB Board

for
Int. MIC Conn.
USB 3.0 1x
Cardreader Realtek SD/MMC Conn.
Page 33
2
GL3213L-OHY05 2

Page 30 USB 3.0 Port1

LC
SATA HDD SATA Gen3 SDIO
Page 42 SATA Port0

USB2.0 1x
SATA ODD SATA Gen1 NGFF Card
WLAN&BT

FC
Page 42 SATA Port1 PCIe 1x
PCIe Port2
Page 40 USB 2.0 Port2

LAN Realtek
RJ45 Conn.
RTL8111H_CG
PCIe 1x USB 2.0 1x Int. Camera
Page 38
USB 2.0 Port3

3
Page 37 PCIe Port3

HD Audio
Page 4~12

LPC BUS
PE
FSPI BUS SPI ROM
8MB Sub-board ( for 14")
POWER BOARD
3

De
Codec SPK Conn.
Conexant_CX20751
Page 43
Page 43 USB Board
TPM
EC ST33ZP24AR28PVSP

bu
ITE IT8886E-LQFP
Page 44
Sub-board ( for 15")
HP&Mic Combo Conn.
POWER BOARD
USB Board
Touch Pad
Page 45
Int.KBD
Page 45
Thermal Sensor
NCT7718W
Page 39
g USB Board

ODD Board
4 4

Security Classification
Classification LC Future Center Secret Data Title
Issued Date 2014/09/24 Deciphered Date 2015/03/23 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 2 of 60
A B C D E

www.bios-downloads.com
www.vinafix.com
A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )

+5VS
SIGNAL
Power Plane +3VS STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+1.5VS
+3VALW_SOC Full ON HIGH HIGH HIGH HIGH ON ON ON ON
B+ +3VALW +1.0VALW +1.35V
+0.68VS S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+3VL +5VALW +1.8VALW
1
CPU_CORE 1
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
State GFX_CORE
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF

S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF

S0 O O O O O

Ju
USB Port Table
S3 O O O O X XHCI Port Port device
BOM Structure Table
S5 S4/AC Only O O O X
st X USB 3.0
0
1
USB Port (Left Side)
USB3.0 Card Reader
BOM Structure
AOAC@
OPT@
BTO Item
AOAC support part
GPU Part

for
S5 S4 O X X X X UMA@ UMA SKU ID part
Battery only 0 USB Port (Left Side) 14@ For 14" part
S5 S4 1 15@ For 15" part
AC & Battery X X X X X USB 2.0 USB Port (Right Side)
100M@ 100M LAN part
2 BT

LC
2 2
don't exist 3 Camera N15SGT@ N15SGT Part
N15VGM@ N15GSM Part
4 USB Port (Right Side)
SIGNAL GIGA@ GIGA LAN Part
STATE SLP_S1# SLP_S3# SLP_S4# +VALW +VALW_PCH +V +VS Clock USB HUB 1
2 GC6@ GPU GC6 Part

FC
Full ON HIGH HIGH HIGH ON ON ON ON ON 3 TS@ Touch Screen part
4 RANKA@ GPU VRAM RANKA PART
S1(Power On Suspend) LOW HIGH HIGH ON ON ON ON LOW
RANKB@ GPU VRAM RANKB PART
S3 (Suspend to RAM) LOW LOW HIGH ON ON ON OFF OFF ME@ Connector
CD@ COST DOWN

PE
S4 (Suspend to Disk) LOW LOW LOW ON ON OFF OFF OFF
@ Not stuff
S5 (Soft OFF) LOW LOW LOW ON ON OFF OFF OFF

PCIE PORT LIST


SMBUS Control Table Port Device Hynix VRAM Part
H4T@

3
SOURCE VGA BATT IT8986E SODIMM
WLAN
WiMAX
Thermal
Sensor
PCH TP
Module charger
1
2
3
4
Discrete GPU
Discrete GPU
WLAN De M4T@
S4T@@
Micron VRAM Part
Samsung VRAM Part 3

bu
EC_SMB_CK1 EC V LAN
EC_SMB_DA1 +3VALW X V +3VALW X X X X X V 5
6
7

g
EC_SMB_CK2 EC V V
X X X V X X X 8
EC_SMB_DA2 +3VS +3VGS +3VS +3VS

PCH_SMB_CLK PCH
PCH_SMB_DATA +3VALW_PCH X X X V V X V X X
+3VS +3VS +3VALW_PCH
DDI PORT LIST
Port Device
DDI0 DP TO VGA
EC SM Bus1 address EC SM Bus2 address PCH SM Bus address DDI1
Device Address eDP
4
Device Device Address DDR DIMMA 1010 000Xb DDI2 HDMI 4

Smart Battery 0001 011X b Thermal Sensor EMC1403-2 1001_100xb(reserve)


Charger need to update VGA 0x9E(base on NV default) Wlan Rsvd
TP need to update

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 3 of 60
A B C D E
5 4 3 2 1

? CHV_MCP_EDS
UC1C DDR3_M0_DQ_63 +1.8VALW
DDI0_RCOMP_P RPC27
EDP_HPD# 3 2
1

VGA_HPD# 4 1
RC1
M44
402_0402_1% RSVD_M44 K44 EDP_HPD DP to VGA _HPD 1K_0404_4P2R_5%
RSVD_K44
K48
2

DDI0_RCOMP_N RSVD_K48
{35} VGA_TX0+ VGA_TX0+ D50 K47
DDI0_TXP_0 V1P0 RSVD_K47 VGA_HPD#
VGA_TX0- C51 EDP_HPD#

MCSI and Camera interface


{35} VGA_TX0- DDI0_TXN_0 V1P0
DDI1_RCOMP_P T44
V1P24 MCSI_1_CLKP
{35} VGA_TX1+ VGA_TX1+ H49 T45
DDI0_TXP_1 V1P0 V1P24 MCSI_1_CLKN
1

{35} VGA_TX1- VGA_TX1- H50


RC2 DDI0_TXN_1 V1P0
D Y47 D
V1P24 MCSI_1_DP_0
402_0402_1% F53
DDI0_TXP_2 V1P0 DDI0 V1P24 MCSI_1_DN_0
Y48
F52 V45

3
V1P0 V1P24 QC4B D
DP TO VGA Converter DDI0_TXN_2 MCSI_1_DP_1

6
V47 QC4A D
V1P24 5
2

DDI1_RCOMP_N G53 MCSI_1_DN_1 V50 2 DP_VGA_HPD {35}


DDI0_TXP_3 V1P0 V1P24 MCSI_1_DP_2 CPU_EDP_HPD {33} G
G52 V48 G
DDI0_TXN_3 V1P0 V1P24 MCSI_1_DN_2 T41
V1P24 MCSI_1_DP_3 S 2N7002KDWH_SOT363-6
VGA_AUX H47 T42 S

4
2N7002KDWH_SOT363-6

2
{35} VGA_AUX V1P0 V1P24

1
DDI0_AUXP MCSI_1_DN_3

1
{35} VGA_AUX# VGA_AUX# H46
DDI0_AUXN V1P0 RC4 0604 RC27
P50
V1P24 MCSI_2_CLKP 4.7K_0402_5%
VGA_HPD# W51 P48 100K_0402_5%
HV_DDI0_HPD V1P8A V1P24 MCSI_2_CLKN

Ju
0604
Y51 P47

1
V1P8 V1P24

2
Y52 HV_DDI0_DDC_SCL MCSI_2_DP_0 P45
HV_DDI0_DDC_SDA V1P8 V1P24 MCSI_2_DN_0 M48
V1P24 MCSI_2_DP_1
V52 M47
PANEL0_BKLTEN V1P8 V1P24 MCSI_2_DN_1
V51
PANEL0_BKLTCTL V1P8
W53 T50

st
PANEL0_VDDEN V1P8 MSCI_3_CLKP
DDI0_RCOMP_P F38 T48
DDI0_RCOMP_N G38 DDI0_PLLOBS_P MSCI_3_CLKN
DDI0_PLLOBS_N P44 1 RC24 2
V1P24 MCSI_COMP PCH_ENBKL
CPU_EDP_TX0+ J51 PCH_ENBKL {33}
{33} CPU_EDP_TX0+ DDI1_TXP_0 V1P0 150_0402_1%
CPU_EDP_TX0- H51 AB41
V1P0
{33} CPU_EDP_TX0-
{33} CPU_EDP_TX1+ CPU_EDP_TX1+ K51 DDI1_TXN_0 GP_CAMERASB00 AB45 PCH_ENBKL can direct connect to EC for costdown

for
CPU_EDP_TX1- K52 DDI1_TXP_1 V1P0 GP_CAMERASB01 AB44
{33} CPU_EDP_TX1- DDI1_TXN_1 GP_CAMERASB02
V1P0 AC53
L53 GP_CAMERASB03 AB51
L51 DDI1_TXP_2 V1P0 DDI1 GP_CAMERASB04 AB52
DDI1_TXN_2 V1P0 GP_CAMERASB05
EDP M52 AA51 +3VS
M51 DDI1_TXP_3 V1P0 GP_CAMERASB06 AB40 +3VALW
DDI1_TXN_3 V1P0 GP_CAMERASB07 Y44 GPIO_CAM_8
CPU_EDP_AUX M42 GP_CAMERASB08 GPIO_CAM_8 {12}
{33} CPU_EDP_AUX DDI1_AUXP
CPU_EDP_AUX# K42 V1P0 Y42

4
3
{33} CPU_EDP_AUX#

LC
C DDI1_AUXN GP_CAMERASB09 GPIO_CAM_9 {12} C
V1P0 Y41 ODD_EN
EDP_HPD# R51 GP_CAMERASB10 V40 ODD_EN {42} RPC26
HV_DDI1_HPD V1P8A GP_CAMERASB11 GPIO_CAM_11 {12} 10K_0404_4P2R_5%
PCH_ENBKL P51
PCH_BKLT_CTRL_Q P52 PANEL1_BKLTEN V1P8

1
2
PCH_LCD_VDDEN_Q R53 PANEL1_BKLTCTL V1P8 M7 PCH_EDP_PWM {33}
PANEL1_VDDEN V1P8 SDMMC1_CLK
DDI1_RCOMP_P F47 V1P8
DDI1_RCOMP_N F49 DDI1_PLLOBS_P P6

FC
DDI1_PLLOBS_N V1P8 SDMMC1_CMD

D2 3
{34} HDMI_TX2+ HDMI_TX2+ F40 M6
DDI2_TXP_0 V1P8 SDMMC1_D0 QC2B
HDMI D2 {34} HDMI_TX2- HDMI_TX2- G40 V1P0 M4
DDI2_TXN_0 V1P8 SDMMC1_D1 5 G2 PJT138K_SOT363-6
V1P0 P9
V1P8 SDMMC1_D2
{34} HDMI_TX1+ HDMI_TX1+ J40 P7
HDMI D1 HDMI_TX1- K40 DDI2_TXP_1 V1P0 SDMMC1
V1P8 SDMMC1_D3_CD_N
T6

4 S2
{34} HDMI_TX1- DDI2_TXN_1 V1P0 V1P8 SMMC1_D4_SD_WE
{34} HDMI_TX0+ HDMI_TX0+ F42 T7

D1 6
DDI2_TXP_2 V1P8 SMMC1_D5
{34} HDMI_TX0- HDMI_TX0- G42 V1P0 DDI2 V1P8
T10
QC2A
HDMI D0 DDI2_TXN_2 V1P0
V1P8
SMMC1_D6 T12
PCH_BKLT_CTRL_Q 2 G1
HDMI_CLK+ D44 SMMC1_D7 T13 PJT138K_SOT363-6

PE
{34} HDMI_CLK+ V1P0 V1P8
{34} HDMI_CLK- HDMI_CLK- F44 DDI2_TXP_3 SMMC1_RCLK P13 1 RC106 2
DDI2_TXN_3 V1P0 V1P8 SDMMC1_RCOMP
HDMI CLK

1 S1
D48
DDI2_AUXP V1P0 100_0402_1%
C49 K10
DDI2_AUXN V1P0 V1P8 SDMMC2_CLK K9
V1P8 SDMMC2_CMD
U51
{34} HDMI_HPD HV_DDI2_HPD V1P8A
M12
V1P8 SDMMC2_D0
T51 M10
{34} DDPB_CLK HV_DDI2_DDC_SCL V1P8 V1P8 SDMMC2_D1
T52 K7
{34} DDPB_DATA HV_DDI2_DDC_SDA V1P8 V1P8 SDMMC2_D2

De
K6
B53 SDMMC2
V1P8 SDMMC2_D3_CD_N
+3VS
A52 RSVD_B53 F2 SD_CLK_PCH +3VALW
3 OF 13 V1P8
E52 RSVD_A52 SDMMC3_CLK D2 SD_CMD_PCH SD_CLK_PCH {30}
RSVD_E52 V1P8 SDMMC3_CMD SD_CMD_PCH {30}
B D52 ? K3 SD_CD#_PCH B
RSVD_D52 V1P8 SDMMC3_CD_N SD_CD#_PCH {30}
B50

4
3
RSVD_B50
B49
RSVD_B49 NC's V1P8 SDMMC3_D0
J1 SD_D0_PCH
SD_D0_PCH {30} RPC25
DDI PORT LIST E53
RSVD_E53 V1P8 SDMMC3_D1
J3 SD_D1_PCH
SD_D1_PCH {30}

bu
C53 H3 SD_D2_PCH 10K_0404_4P2R_5%
RSVD_C53 V1P8 SDMMC3_D2 SD_D2_PCH {30}
A51 G2 SD_D3_PCH @
RSVD_A51 V1P8 SDMMC3_D3 SD_D3_PCH {30}
A49

1
2
RSVD_A49
Port Device G44
RSVD_G44 SDMMC3
V1P8 SDMMC3_1P8_EN
K2 SD_1P8_SEL
SD_1P8_SEL {10}
PCH_ENVDD {33}
L3 SD_PWR_EN#
V1P8 SDMMC3_PWR_EN_N SD_PWR_EN# {30}
P12 1 2
V1P8
DDI0 DP TO VGA
SDMMC3_RCOMP RC107 80.6_0402_1%

D2 3
g
QC1B
DDI1 eDP 5 G2 PJT138K_SOT363-6
+1.8VALW @
DDI2 HDMI BRASWELL_FCBGA151170 REV = 1.2

4 S2
D1 6
10K_0402_5%
ODD_EN RC5 1 2 QC1A
@ PCH_LCD_VDDEN_Q 2 G1 PJT138K_SOT363-6
+1.8VALW @

1 S1
2

SD_1P8_SEL RC36 2 @ 1 10K_0402_1%


RC47
1K_0402_1%
@
1

+1.8VALW VCC_SD3_S3
PCH_LCD_VDDEN_Q RC21 1 2 0_0402_5% PCH_ENVDD
SD_PWR_EN#
2

A A
2

RC41
RC37 10K_0402_1%
10K_0402_1% PCH_LCD_VDDEN_Q VOH min is 1.8-0.45=1.35V,
need level shift
1
1

@
@
Security Classification LC Future Center Secret Data Title
SD_CD#_PCH SD_CMD_PCH
SOC (DDI,EDP)

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 4 of 60
5 4 3 2 1
5 4 3 2 1

DDRA_DQ[63:0] {14}

DDRA_MA[15:0] {14}

DDRA_DQS[7:0] {14}

DDRA_DQS#[7:0] {14}

DDRA_DM[7:0] {14}

?
CHV_MCP_EDS
UC1A DDR3_M0_DQ_63 ?
CHV_MCP_EDS
UC1B DDR3_M0_DQ_63
DDRA_MA15 BD49 BG33 DDRA_DQ55
DDRA_MA14 BD47 DDR3_M0_MA_15 DDR3_M0_DQ_63 BH28 DDRA_DQ54
BD5
DDR3_M1_MA_15 DDR1 DDR3_M1_DQ_63
BG21
DDR3_M0_MA_14 DDR3_M0_DQ_62 BD7 BH26
DDRA_MA13 BF44 BJ29 DDRA_DQ53 DDR3_M1_MA_14 DDR3_M1_DQ_62
DDRA_MA12 BF48 DDR3_M0_MA_13 DDR0 DDR3_M0_DQ_61 BG28 DDRA_DQ52
BF10
DDR3_M1_MA_13 DDR3_M1_DQ_61
BJ25
DDR3_M0_MA_12 DDR3_M0_DQ_60 Group 6 BF6 BG26
DDRA_MA11 BB49 BG32 DDRA_DQ51 DDR3_M1_MA_12 DDR3_M1_DQ_60
D DDR3_M0_MA_11 DDR3_M0_DQ_59 BB5 BG22 D
DDRA_MA10 BJ45 BH34 DDRA_DQ50 DDR3_M1_MA_11 DDR3_M1_DQ_59
DDR3_M0_MA_10 DDR3_M0_DQ_58 BJ9 BH20
DDRA_MA9 BE52 BG29 DDRA_DQ49 DDR3_M1_MA_10 DDR3_M1_DQ_58
DDR3_M0_MA_9 DDR3_M0_DQ_57 BE2 BG25
DDRA_MA8 BD44 BJ33 DDRA_DQ48 DDR3_M1_MA_9 DDR3_M1_DQ_57
DDR3_M0_MA_8 DDR3_M0_DQ_56 BD10 BJ21
DDRA_MA7 BE46 DDR3_M1_MA_8 DDR3_M1_DQ_56
DDR3_M0_MA_7 BE8
DDRA_MA6 BB46 BD28 DDRA_DQ63 DDR3_M1_MA_7
DDR3_M0_MA_6 DDR3_M0_DQ_55 BB8 BD26
DDRA_MA5 BH48 BF30 DDRA_DQ62 DDR3_M1_MA_6 DDR3_M1_DQ_55
DDR3_M0_MA_5 DDR3_M0_DQ_54 BH6 BF24
DDRA_MA4 BD42 BA34 DDRA_DQ61 DDR3_M1_MA_5 DDR3_M1_DQ_54
DDR3_M0_MA_4 DDR3_M0_DQ_53 BD12 BA20
DDRA_MA3 BH47 BD34 DDRA_DQ60 DDR3_M1_MA_4 DDR3_M1_DQ_53
DDR3_M0_MA_3 DDR3_M0_DQ_52 Group 7 BH7 BD20
DDRA_MA2 BJ48 BD30 DDRA_DQ59 DDR3_M1_MA_3 DDR3_M1_DQ_52
DDR3_M0_MA_2 DDR3_M0_DQ_51 BJ6 BD24
DDRA_MA1 BC42 BA32 DDRA_DQ58 DDR3_M1_MA_2 DDR3_M1_DQ_51
DDR3_M0_MA_1 DDR3_M0_DQ_50 BC12 BA22
DDRA_MA0 BB47 BC34 DDRA_DQ57 DDR3_M1_MA_1 DDR3_M1_DQ_50
DDR3_M0_MA_0 DDR3_M0_DQ_49 BB7 BC20
BF34 DDRA_DQ56 DDR3_M1_MA_0 DDR3_M1_DQ_49
DDR3_M0_DQ_48 BF20
BF52 DDR3_M1_DQ_48
BF2

Ju
{14} DDRA_BS2# AY40 DDR3_M0_BS_2 AV32 DDRA_DQ47
{14} DDRA_BS1# AY14 DDR3_M1_BS_2 AV22
BH46 DDR3_M0_BS_1 DDR3_M0_DQ_47 AV34 DDRA_DQ46
{14} DDRA_BS0# BH8 DDR3_M1_BS_1 DDR3_M1_DQ_47 AV20
DDR3_M0_BS_0 DDR3_M0_DQ_46 BD36 DDRA_DQ45 DDR3_M1_BS_0 DDR3_M1_DQ_46 BD18
BG45 DDR3_M0_DQ_45 BF36 DDRA_DQ44
BG9 DDR3_M1_DQ_45 BF18
{14} DDRA_CAS# BA40 DDR3_M0_CAS_N DDR3_M0_DQ_44 AU32 DDRA_DQ43
{14} DDRA_RAS# BH44 DDR3_M0_RAS_N DDR3_M0_DQ_43 AU34 DDRA_DQ42
Group 5 BA14 DDR3_M1_CAS_N DDR3_M1_DQ_44 AU22
BH10 DDR3_M1_RAS_N DDR3_M1_DQ_43 AU20
{14} DDRA_WE# AU38 DDR3_M0_WE_N DDR3_M0_DQ_42 BA36 DDRA_DQ41
AU16 DDR3_M1_WE_N DDR3_M1_DQ_42 BA18
{14} DDRA_CS1# AY38 DDR3_M0_CSB_1 DDR3_M0_DQ_41 BC36 DDRA_DQ40
AY16 DDR3_M1_CSB_1 DDR3_M1_DQ_41 BC18

st
{14} DDRA_CS0# DDR3_M0_CSB_0 DDR3_M0_DQ_40
DDR3_M1_CSB_0 DDR3_M1_DQ_40
BD38 BH38 DDRA_DQ39
{14} DDRA_CLK1 DDR3_M0_CK_1 DDR3_M0_DQ_39 BD16 BH16
BF38 BH36 DDRA_DQ38 DDR3_M1_CK_1 DDR3_M1_DQ_39
{14} DDRA_CLK1# DDR3_M0_CKB_1 DDR3_M0_DQ_38 BF16 BH18
AY42 BJ41 DDRA_DQ37 DDR3_M1_CKB_1 DDR3_M1_DQ_38
{14} DDRA_CKE1 DDR3_M0_CKE_1 DDR3_M0_DQ_37 AY12 BJ13
BH42 DDRA_DQ36 DDR3_M1_CKE_1 DDR3_M1_DQ_37
DDR3_M0_DQ_36 Group 4 BH12
BD40 BJ37 DDRA_DQ35 DDR3_M1_DQ_36
{14} DDRA_CLK0 DDR3_M0_CK_0 DDR3_M0_DQ_35 BD14 BJ17
BF40 BG37 DDRA_DQ34 DDR3_M1_CK_0 DDR3_M1_DQ_35
{14} DDRA_CLK0# DDR3_M0_CKB_0 DDR3_M0_DQ_34 BF14 BG17
BB44 BG43 DDRA_DQ33 DDR3_M1_CKB_0 DDR3_M1_DQ_34
BB10 BG11

for
{14} DDRA_CKE0 DDR3_M0_CKE_0 DDR3_M0_DQ_33 BG42 DDRA_DQ32 DDR3_M1_CKE_0 DDR3_M1_DQ_33
DDR3_M0_DQ_32 BG12
AT30 DDR3_M1_DQ_32
RSVD_AT30 AT24
AU30 BB51 DDRA_DQ31 RSVD_AT24
RSVD_AU30 DDR3_M0_DQ_31 Del CS_2(chip select: 1 per Rank) AU24 BB3
AW53 DDRA_DQ30 Del CKE_2(chip select: 1 per Rank) RSVD_AU24 DDR3_M1_DQ_31
DDR3_M0_DQ_30 AW1
AV36 BC52 DDRA_DQ29 DDR3_M1_DQ_30
{14} DDRA_ODT0 DDR3_M0_ODT_0 DDR3_M0_DQ_29 AV18 BC2
BA38 AW51 DDRA_DQ28 DDR3_M1_ODT_0 DDR3_M1_DQ_29
{14} DDRA_ODT1 DDR3_M0_ODT_1 DDR3_M0_DQ_28 BA16 AW3
AV51 DDRA_DQ27 Group 3 DDR3_M1_ODT_1 DDR3_M1_DQ_28
DDR3_M0_DQ_27 AV3
DDRA_OCAVREF AT28 BC53 DDRA_DQ26 DDR3_M1_DQ_27
DDR3_M0_OCAVREF DDR3_M0_DQ_26 AT26 BC1
DDRA_ODQVREF AU28 AV52 DDRA_DQ25 DDR3_M1_OCAVREF DDR3_M1_DQ_26
DDR3_M0_ODQVREF DDR3_M0_DQ_25 AU26 AV2
BD52 DDRA_DQ24 DDR3_M1_ODQVREF DDR3_M1_DQ_25
DDR3_M0_DQ_24 BD2
C BA42 DDR3_M1_DQ_24 C

LC
{14} DDRA_DRAMRST# DDR3_M0_DRAMRST_N BA12
DDR_PWROK AV28 AV42 DDRA_DQ7 DDR3_M1_DRAMRST_N
DDR3_DRAM_PWROK DDR3_M0_DQ_23 DDR_CORE_PWROKAV26 AV12
AP41 DDRA_DQ6 DDR3_VCCA_PWROK DDR3_M1_DQ_23
DDR3_M0_DQ_22 AP13
M0_RCOMPPD BA28 AV41 DDRA_DQ5 DDR3_M1_DQ_22
DDR3_M0_RCOMPPD DDR3_M0_DQ_21 M1_RCOMPPD BA26 AV13
AT44 DDRA_DQ4 DDR3_M1_RCOMPPD DDR3_M1_DQ_21
DDR3_M0_DQ_20 Group 0 AT10
DDRA_DM6 BH30 AP40 DDRA_DQ3 DDR3_M1_DQ_20
DDR3_M0_DM_7 DDR3_M0_DQ_19 BH24 AP14
DDRA_DM7 BD32 AT38 DDRA_DQ2 DDR3_M1_DM_7 DDR3_M1_DQ_19

1
DDR3_M0_DM_6 DDR3_M0_DQ_18 BD22 AT16
DDRA_DM5 AY36 AP42 DDRA_DQ1 DDR3_M1_DM_6 DDR3_M1_DQ_18
DDR3_M0_DM_5 DDR3_M0_DQ_17 RC35 AY18 AP12
DDRA_DM4 BG41 AT40 DDRA_DQ0 DDR3_M1_DM_5 DDR3_M1_DQ_17
DDR3_M0_DM_4 DDR3_M0_DQ_16 182_0402_1% BG13 AT14
DDRA_DM3 BA53 DDR3_M1_DM_4 DDR3_M1_DQ_16
DDR3_M0_DM_3 @ BA1
1

DDRA_DM0 AP44 AV45 DDRA_DQ23

FC
AP10 DDR3_M1_DM_3 AV9
DDRA_DM2 AT48 DDR3_M0_DM_2 DDR3_M0_DQ_15 AY50 DDRA_DQ22

2
RC34 AT6 DDR3_M1_DM_2 DDR3_M1_DQ_15 AY4
182_0402_1% DDRA_DM1 AP52 DDR3_M0_DM_1 DDR3_M0_DQ_14 AT50 DDRA_DQ21
INTEL PDG 182 ohm AP2 DDR3_M1_DM_1 DDR3_M1_DQ_14 AT4
SD00001KG00 DDR3_M0_DM_0 DDR3_M0_DQ_13 AP47 DDRA_DQ20 INTEL PDG 182 ohm DDR3_M1_DM_0 DDR3_M1_DQ_13 AP7
DDRA_DQS6 BH32 DDR3_M0_DQ_12 AV50 DDRA_DQ19 Group 2 BH22 DDR3_M1_DQ_12 AV4
2

DDRA_DQS#6 BG31 DDR3_M0_DQS_7 DDR3_M0_DQ_11 AY48 DDRA_DQ18


BG23 DDR3_M1_DQS_7 DDR3_M1_DQ_11 AY6
DDRA_DQS7 BC30 DDR3_M0_DQSB_7 DDR3_M0_DQ_10 AT47 DDRA_DQ17
BC24 DDR3_M1_DQSB_7 DDR3_M1_DQ_10 AT7
DDRA_DQS#7 BC32 DDR3_M0_DQS_6 DDR3_M0_DQ_9 AP48 DDRA_DQ16
BC22 DDR3_M1_DQS_6 DDR3_M1_DQ_9 AP6
DDRA_DQS5 AT32 DDR3_M0_DQSB_6 DDR3_M0_DQ_8
AT22 DDR3_M1_DQSB_6 DDR3_M1_DQ_8
DDRA_DQS#5 AT34 DDR3_M0_DQS_5 AP51 DDRA_DQ15
AT20 DDR3_M1_DQS_5 AP3
DDRA_DQS4 BH40 DDR3_M0_DQSB_5 DDR3_M0_DQ_7 AR53 DDRA_DQ14
For dual rank BH14 DDR3_M1_DQSB_5 DDR3_M1_DQ_7 AR1
DDRA_DQS#4 BG39 DDR3_M0_DQS_4 DDR3_M0_DQ_6 AK52 DDRA_DQ13
BG15 DDR3_M1_DQS_4 DDR3_M1_DQ_6 AK2
DDRA_DQS3 AY52 DDR3_M0_DQSB_4 DDR3_M0_DQ_5 AL53 DDRA_DQ12 DDR3_M1_DQSB_4 DDR3_M1_DQ_5

PE
DDR3_M0_DQS_3 DDR3_M0_DQ_4 Group 1 AY2 AL1
DDRA_DQS#3 BA51 AR51 DDRA_DQ11 DDR3_M1_DQS_3 DDR3_M1_DQ_4
DDR3_M0_DQSB_3 DDR3_M0_DQ_3 BA3 AR3
DDRA_DQS0 AT42 AT52 DDRA_DQ10 DDR3_M1_DQSB_3 DDR3_M1_DQ_3
DDR3_M0_DQS_2 DDR3_M0_DQ_2 AT12 AT2
DDRA_DQS#0 AT41 AL51 DDRA_DQ9 DDR3_M1_DQS_2 DDR3_M1_DQ_2
DDR3_M0_DQSB_2 DDR3_M0_DQ_1 AT13 AL3
DDRA_DQS2 AV47 AK51 DDRA_DQ8 DDR3_M1_DQSB_2 DDR3_M1_DQ_1
DDR3_M0_DQS_1 DDR3_M0_DQ_0 AV7 AK3
DDRA_DQS#2 AV48 DDR3_M1_DQS_1 DDR3_M1_DQ_0
DDR3_M0_DQSB_1 AV6
DDRA_DQS1 AM52 DDR3_M1_DQSB_1
DDR3_M0_DQS_0 AM2
DDRA_DQS#1 AM51 DDR3_M1_DQS_0
DDR3_M0_DQSB_0 AM3
1 OF 13 DDR3_M1_DQSB_0 2 OF 13
BRASWELL_FCBGA151170
BRASWELL_FCBGA151170
REV = 1.2 ?
REV = 1.2 ?
VREF is not used for DDR3L

De
+1.35V
+1.35V
1

B B
1

RC9
RC6
4.7K_0402_1%
4.7K_0402_1%

bu
2
2

@
@
DDRA_ODQVREF
DDRA_OCAVREF
1

1
1 RC10
1

g
4.7K_0402_1% CC131
RC7 CC130 +3VALW
4.7K_0402_1% .1U_0402_10V6-K +1.35V
.1U_0402_10V6-K 2
2
2

@
@
@
2

4
3

@
RPC14
10K_0404_4P2R_5%
1
2

DDR_CORE_PWROK
+3VALW +1.35V

1
4
3

CC18
RPC13
3

QC10B D .1U_0402_10V6-K
2
10K_0404_4P2R_5% 5
G
1
2

2N7002KDWH_SOT363-6
S
4
6

QC10A D
DDR_PWROK
{7,44} SYS_PWROK 2
1 G
2N7002KDWH_SOT363-6
1 CC19 S
1

A A
CD@
3

QC5B D CC1 .1U_0402_10V6-K


2
5 .1U_0402_10V6-K
G 2
2N7002KDWH_SOT363-6
S
4
6

QC5A D
2 Title
{55} VDDQ_PGOOD G Security Classification
Security Classification LC Future Center Secret Data
2N7002KDWH_SOT363-6
1 S Issued Date 2014/09/24 Deciphered Date 2015/03/23 SOC (DDI,EDP)
1

www.bios-downloads.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
CC3 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
EMC@ Custom 0.4
2
.1U_0402_10V6-K DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 5 of 60

5 4 3 2 1
5 4 3 2 1

+1.8VALW
RPC1
5 4 WLAN_CLKREQ#_Q
6 3 PCIE_CLKREQ_2#
7 2 GPU_CLKREQ#_Q
8 1 LAN_CLKREQ#_Q +3VS

10K_0804_8P4R_5%

2
? RC11
UC1D CHV_MCP_EDS
DDR3_M0_DQ_63 10K_0402_5%
@

1
OPT@ CC4 1 2 .1U_0402_10V6-K PCIE_CTX_GRX_P0 C24 C31 SATA_PTX_DRX_P0
D {19} PCIE_CTX_C_GRX_P0 PCIE_TXP0 V1P0 V1P8 SATA_TXP0 SATA_PTX_DRX_P0 {42} LAN_CLKREQ#_Q D
OPT@ CC5 1 2 .1U_0402_10V6-K PCIE_CTX_GRX_N0 B24 B30 SATA_PTX_DRX_N0 HDD
{19} PCIE_CTX_C_GRX_N0 PCIE_TXN0 V1P0 V1P8 SATA_TXN0 SATA_PTX_DRX_N0 {42} @
PCIE_CRX_GTX_P0 G20 N28 SATA_PRX_DTX_P0
{19} PCIE_CRX_GTX_P0 PCIE_RXP0 V1P0 V1P8 SATA_RXP0 SATA_PRX_DTX_P0 {42}
dGPU PCIE_CRX_GTX_N0 J20 M28 SATA_PRX_DTX_N0

3
{19} PCIE_CRX_GTX_N0 PCIE_RXN0 V1P0 V1P8 SATA_RXN0 SATA_PRX_DTX_N0 {42} D
C29 SATA_PTX_DRX_P1
V1P8 SATA_TXP1 SATA_PTX_DRX_P1 {42} 5
{19} PCIE_CTX_C_GRX_P1 OPT@ CC7 1 2 .1U_0402_10V6-K PCIE_CTX_GRX_P1 A25 A29 SATA_PTX_DRX_N1 2N7002KDWH_SOT363-6
PCIE_TXP1 V1P0 V1P8 SATA_TXN1 SATA_PTX_DRX_N1 {42} G
{19} PCIE_CTX_C_GRX_N1 OPT@ CC6 1 2 .1U_0402_10V6-K PCIE_CTX_GRX_N1 C25
PCIE_TXN1 V1P0 V1P8 SATA_RXP1
J28 SATA_PRX_DTX_P1
SATA_PRX_DTX_P1 {42} ODD QC22B @
{19} PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P1 D20 SATA K28 SATA_PRX_DTX_N1
PCIE_RXP1 V1P0 V1P8 SATA_RXN1 SATA_PRX_DTX_N1 {42} S

6
PCIE_CRX_GTX_N1 F20

4
{19} PCIE_CRX_GTX_N1 V1P0 D
PCIE_RXN1 AH3 2
CC103 1 V1P8 SATA_LED_N 2N7002KDWH_SOT363-6 LAN_CLKREQ# {37}
2 .1U_0402_10V6-K PCIE_PTX_DRX_P4 B26 AH2 G
{40} PCIE_PTX_C_DRX_P4 PCIE_TXP2 V1P0 V1P8 SATA_GP0

Ju
CC104 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_N4 C26 AG3 QC22A
WLAN {40} PCIE_PTX_C_DRX_N4
PCIE_PRX_DTX_P4 D22 PCIE_TXN2 V1P0
PCIe
V1P8 SATA_GP1 AG1 RC18 1 @ 2 0_0402_5% S
{40} PCIE_PRX_DTX_P4 V1P0 V1P8 SATA0_DEVSLP {42}

1
PCIE_PRX_DTX_N4 F22 PCIE_RXP2 SATA_GP2/SATA_DEVSLP0 AF3
{40} PCIE_PRX_DTX_N4 PCIE_RXN2 V1P0 V1P8
SATA_GP3/SATA_DEVSLP1
CC106 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_P3 A27 N30 SATA_RCOMP_DP
{37} PCIE_PTX_C_DRX_P3 PCIE_TXP3 V1P0 SATA_RCOMP_P
CC1051 2 .1U_0402_10V6-K PCIE_PTX_DRX_N3 C27 M30 SATA_RCOMP_DN
{37} PCIE_PTX_C_DRX_N3 PCIE_TXN3 V1P0 SATA_RCOMP_N
LAN PCIE_PRX_DTX_P3 G24

st
{37} PCIE_PRX_DTX_P3 PCIE_RXP3 V1P0
{37} PCIE_PRX_DTX_N3 PCIE_PRX_DTX_N3 J24 W3 PCH_SPI_CLK_R 10_0402_1%2 1 RC134
PCIE_RXN3 V1P0 V1P8 FST_SPI_CLK EC_SPI_CLK {44}
GPU_CLKREQ#_Q AM10 V4 PCH_SPI_CS0#_R 33_0402_5%2 1 RC135
PCIE_CLKREQ_2# AM12 PCIE_CLKREQ0_N V1P8 V1P8 FST_SPI_CS0_N V6 EC_SPI_CS0# {44}
WLAN_CLKREQ#_Q AK14 PCIE_CLKREQ1_N V1P8 V1P8 FST_SPI_CS1_N V7
LAN_CLKREQ#_Q RC19 1 2 0_0402_5% LAN_CLKREQ#
LAN_CLKREQ#_Q AM14 PCIE_CLKREQ2_N V1P8 V1P8 FST_SPI_CS2_N
PCIE_CLKREQ3_N V1P8

for
V1P8
V2 PCH_SPI_D0_R 10_0402_1%2 1 RC130 LAN_CLKREQ# is OD,Can pull high to 1.8V
A21 FST_SPI_D0 V3 EC_SPI_D0 {44}
CLK_PCIE_GPU
V1P8
PCH_SPI_D1_R 10_0402_1%2 1 RC131
{19} CLK_PCIE_GPU CLK_DIFF_P_0 FST_SPI_D1 EC_SPI_D1 {44}
{19} CLK_PCIE_GPU#
CLK_PCIE_GPU# C21
CLK_DIFF_N_0
FAST
V1P8 SPI FST_SPI_D2
U1 PCH_SPI_D2_R 10_0402_1%2 1 RC132
EC_SPI_D2 {44}
C19 U3 PCH_SPI_D3_R 10_0402_1%2 1 RC133 +3VS
CLK_DIFF_P_1 V1P8 FST_SPI_D3 EC_SPI_D3 {44}
B20
CLK_PCIE_WLAN C18 CLK_DIFF_N_1 AF13 HDA_RST_AUDIO#_R 1 RC39 2 75_0402_1%
{40} CLK_PCIE_WLAN CLK_DIFF_P_2 V1P5 MF_HDA_RST_N HDA_RST_AUDIO# {43}
CLK_PCIE_WLAN# B18 AD6

2
{40} CLK_PCIE_WLAN# CLK_DIFF_N_2 V1P5 MF_HDA_SDI1 RC40
CLK_PCIE_LAN C17 AD9 HDA_BITCLK_AUDIO_R 1 2 75_0402_1%
{37} CLK_PCIE_LAN CLK_DIFF_P_3 V1P5 MF_HDA_CLK HDA_BITCLK_AUDIO {43} RC3
CLK_PCIE_LAN# A17 AD7

LC
C {37} CLK_PCIE_LAN# CLK_DIFF_N_3 V1P5 MF_HDA_SDI0 HDA_SDIN0 {43} 10K_0402_5% C
C16 AF12 HDA_SYNC_AUDIO_R 1 RC42 2 75_0402_1%
RSVD_C16 V1P5 MF_HDA_SYNC HDA_SYNC_AUDIO {43}
B16 AF14 HDA_SDOUT_AUDIO_R 1 RC43 2 75_0402_1%
RSVD_B16 V1P5 MF_HDA_SDO HDA_SDOUT_AUDIO {43}
AB9

1
V1P5 MF_HDA_DOCKEN_N
PCIE_RCOMP_DP D26 AB7 WLAN_CLKREQ#_Q
PCIE_RCOMP_P V1P5 MF_HDA_DOCKRST_N
PCIE_RCOMP_DN F26
PCIE_RCOMP_N H4
V1P8 SPKR PCH_BEEP {43}

3
V14
SPI1_CLK V1P8 AUDIO D
Y13 AK9 5

FC
SPI1_CS0_N V1P8 GP_SSP_2_CLK 2N7002KDWH_SOT363-6
Y12 AK10 G
V13 SPI1_CS1_N SPI
V1P8 GP_SSP_2_FS AK12 QC8B
SPI1_MISO V1P8 GP_SSP_2_TXD
V12 AK13 S

6
V1P8

4
SPI1_MOSI GP_SSP_2_RXD D
2
2N7002KDWH_SOT363-6 WLAN_CLKREQ# {40}
REV = 1.2 G
QC8A
BRASWELL_FCBGA151170 4 OF 13 S

1
SATA_RCOMP_DP PCIE_RCOMP_DP

PE
2
2

RC30 RC38 +3VS


402_0402_1% 402_0402_1%

De
1

2
1

PCIE_RCOMP_DN
SATA_RCOMP_DN RC8
10K_0402_5%
B OPT@ B

1
GPU_CLKREQ#_Q

bu
+3VALW OPT@

3
D
5
RC94 1 2 +VCC_SPI 2N7002KDWH_SOT363-6 G
0_0402_5% QC7B OPT@
S

6
4
D

g
? 2
2N7002KDWH_SOT363-6 GPU_CLKREQ# {19}
G
+VCC_SPI +1.8VALW QC7A
S

1
@ +3VS
RC20 1 2 PCH_SPI_CS0# RC84 1 2 PCH_SPI_CS0#_R
@ 0_0402_5%
100K_0402_5%

2
RC17
+VCC_SPI
UC2 OPT@
PCH_SPI_CS0# 1 8 50mA 10K_0402_5%

1
CS# VCC GPU_CLKREQ#
1
PCH_SPI_D1 2 7 PCH_SPI_D3
DO HOLD# CC8
PCH_SPI_D2 3 6 PCH_SPI_CLK .1U_0402_10V6-K
WP# CLK 2
4 5 PCH_SPI_D0
GND DI

W25Q64FVSSIQ_SO8
A 0605 A

PCH_SPI_CS0#
PCH_SPI_CLK PCH_SPI_CS0# {44}
PCH_SPI_D0 PCH_SPI_CLK {44}
PCH_SPI_D1 PCH_SPI_D0 {44}
PCH_SPI_D2 PCH_SPI_D1 {44} Security Classification LC Future Center Secret Data Title
PCH_SPI_D2 {44}
PCH_SPI_D3
PCH_SPI_D3 {44} Issued Date 2014/09/24 Deciphered Date 2015/03/23 SOC (DDI,EDP)

www.bios-downloads.com
SPI ROM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 6 of 60
5 4 3 2 1
5 4 3 2 1

+1.8VALW
1,Spec. request 19.2MHz, Cp=12pf, RC=200K
32.768K need change to SJ10000IM00, PMC_PLTRST# 2 RC70 1 @
+1.8VALW +1.8VALW +3VALW
as intel EDS New request 10K_0402_5%
PCH_SMB_ALERT# 2 RC120 1 @
10K_0402_5%
+1.8VALW +3VALW +1.8VALW
PMC_RSTBTN# 1 RC73 2 10K_0402_5%

RTC_X2

XTAL19_OUT
XTAL19_IN
VCCRTC

RTC_X1

3
4

3
4
1 RC71 2 100K_0402_5%
SUSWARN# @
RPC22 RPC23
RC92 1 2 10M_0402_5% RC89 1 2 20K_0402_1%
2

2
SRTC_RST#
2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5%
RC96 RC97 RC98 PMC_SUSCLK @ 1 RC83 2 10K_0402_5%
XTAL@

2
0_0402_5% 0_0402_5% 10K_0402_5%
YC1 RC93 1 2 200K_0402_5% RC90 1 2 20K_0402_1%

2
1

2
1
RTC_RST# EC_RSMRST# 2 RC930 1 100K_0402_5%
TPM@

G1
1

1
UC3 1 2 XTAL@ EC_RSMRST# CC132 1 20.01U_0402_25V7K
PCH_SMB_CLK 1 S1 D1 6 PCH_SMB_CLK_Q
1 6 YC2 @

1U_0402_6.3V6K

1U_0402_6.3V6K
VCCA VCCB 32.768KHZ_12.5PF_202740-PG14
2 2 1 1 SUSWARN# 1 RC75 2 100K_0402_5%

1
CC10
D 2 5 XTAL@ 1 4 JCMOS1 D

CC9
GND EO CC11 CC12 OSC1 NC2 SHORT PADS QC20A
SOC_SERIRQ 3 4 15P_0402_50V8J 18P_0402_50V8J 2 3 @ PJT138K_SOT363-6

2
A4 B4 SERIRQ {44,45} 1 1 1 NC1 OSC2 2 2
JCMOS/JCMOS1

G2 5
1 1 XTAL@ XTAL@ 1
Place under Bottom +3VS
CC13
CC15 CC16 RPC29
G2129TL1U_SC70-6 27P_0402_50V8J CC14
.1U_0402_10V6-K
2 TPM@ 2
.1U_0402_10V6-K CRYSTAL 2
XTAL@
19.2MHZ_18PF_7V19200005
2
27P_0402_50V8J
RTCRST#
Space 15Mil
PCH_SMB_DATA 4 S2 D2 3 PCH_SMB_DATA_Q SMB_CLK_S3 4 1
TPM@ XTAL@ SMB_DATA_S3 3 2
TPM@ 1,Space 15MIL XTAL@
2,No trace under crystal @
QC20B 2.2K_0404_4P2R_5%
3,place on oppsosit side of MCP for temp influence RTC RST# PJT138K_SOT363-6
R_CLK@ R_CLK@
RC121 1 2 0_0402_5% RTC_X1 RC122 1 2 0_0402_5% XTAL19_IN +3VS
{17} RTC_CLK {17} 19.2M_CLK
NTPM@
SOC_SERIRQ RC33 1 2 0_0402_5% SERIRQ

PCB_ID0 PCB_ID1 PCB_ID2 PCB_ID3 Description

Ju
SERIRQ level shift need IC, not MOS for frequence 0 Reserve Reserve UMA SKU

5
SYS_PWROK 1 2 CC140 ? 1 Reserve Reserve GPU SKU

G
EMC@ .1U_0402_10V6-K UC1E CHV_MCP_EDS
DDR3_M0_DQ_63 QC6B

0 Reserve Reserve 14’ panel


XTAL19_IN P24 PCH_SMB_CLK_Q 3 4

S
M22 OSCIN C11 SMB_CLK_S3 {14,40}
XTAL19_OUT @

D
st
OSCOUT RSVD_C11 B10 2N7002KDWH_SOT363-6 1 Reserve Reserve 15’ panel
J26 RSVD_B10 F12
?
CHV_MCP_EDS RSVD_J26 RSVD_F12 RC123 1 2 0_0402_5%
UC1G DDR3_M0_DQ_63 N26 F10
RC45 RSVD_N26 RSVD_F10

2
2.49K_0402_1% 2 1 ICLK_ICOMP P20

G
49.9_0402_1% 2 RC44 1 ICLK_RCOMP N20 ICLKICOMP D12 QC6A
1 AF42 M18 P26 ICLKRCOMP iCLK RESERVED RSVD_D12 E8
+1.8VALW
JTAG/ITP

TP13 @ XDP_TCLK RTC_X1


TP14 @ 1 XDP_TDI AD47 TCK V1P8 RTC_X1 K18 RTC_X2 K26 RSVD_P26 RSVD_E8 C7
TDI V1P8 RTC_X2 RSVD_K26 RSVD_C7
TP15 @ 1 XDP_TDO AF40 F16 BVCCRTC_EXTPAD CC17 1 2 .1U_0402_10V6-K M26 D6 PCH_SMB_DATA_Q 6 1

S
TP16 @ 1 XDP_TMS AD48 TDO V1P8 RTC_EXTPAD AH45 RSVD_M26 RSVD_D6 @
SMB_DATA_S3 {14,40}

D
TP17 @ 1 XDP_TRST# AB48 TMS V1P8 RTC
D18 RTC_RST# RSVD_AH45 J12 2N7002KDWH_SOT363-6
TRST_N V1P8 RTC_RST_N RTC_RST# {44} RSVD_J12
G16 A9 F7

PLTFM CLK's
SYS_PWROK

for
V3P3 COREPWROK SYS_PWROK {5,44} MF_PLT_CLK0 RSVD_F7
F18 EC_RSMRST# C9 V1P8 J14
V3P3 RSMRST_N EC_RSMRST# {44} MF_PLT_CLK1 RSVD_J14

2
TP18 @ 1 XDP_PRDY# AD45 J16 SRTC_RST# B8 V1P8 L13

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
TP19 @ 1 XDP_PREQ# AF41 CX_PRDY_N RTC_TEST_N G18 RTC_INTRUDER B7 MF_PLT_CLK2 V1P8 RSVD_L13 RC124 1 2 0_0402_5%

RC59

RC58

RC948

RC949
CX_PREQ_N RSVD_VSS_G18 MF_PLT_CLK3 OPT@ 15@ @ @
M13 B5 V1P8 AK6
RSVD_M13 MF_PLT_CLK4 V1P8 I2C0_SCL
AE3 SUSWARN# B4 V1P8 AH7
V1P8 SUSPWRDNACK SUSWARN# {56} MF_PLT_CLK5 V1P8 I2C0_SDA
RC80 1 2 0_0402_5% PCH_PCI_CLK_RP2 D14 1 @ TP5 V1P8
{44} CLK_PCI_EC MF_LPC_CLKOUT0V3P3 V1P8 SUS_STAT_N

1
RC81 1 2 0_0402_5% R3 C15 PMC_SUSCLK AF6
{45} CLK_PCI_TPM
TPM@ T3 MF_LPC_CLKOUT1V3P3 V1P8 PMU_SUSCLK C12 PM_SLP_S4# TP23 @ 1 AM40
V1P8 I2C1_SCL
AH6
P3 LPC_CLKRUN_N V3P3 V1P8 PMU_SLP_S4_N B14 PM_SLP_S3# AM41 GPIO_DFX0 V1P8 I2C1_SDA

GPIO_DFX
{44,45} LPC_FRAME# LPC_FRAME_N V3P3 V1P8 PMU_SLP_S3_N GPIO_DFX1
PMU

AF2 PMC_RSTBTN# PCB_ID0 AM44 AF9 PCB_ID0


V1P8 PMU_RESETBUTTON_N GPIO_DFX2 V1P8 I2C2_SCL
M3 F14 PMC_PLTRST# PCB_ID1 AM45 Internal 20K(H) AF7 PCB_ID1
LPC

{44,45} LPC_AD0 M2 MF_LPC_AD0 V3P3 V1P8 PMU_PLTRST_N C14 PMC_BATLOW# 1 RC72 2 PCB_ID2 AM47 GPIO_DFX3 I2C V1P8 I2C2_SDA
PCB_ID2
C {44,45} LPC_AD1 MF_LPC_AD1 V3P3 V1P8 PMU_BATLOW_N +1.8VALW GPIO_DFX4 C
N3 C13 PMC_ACIN 20K_0402_1% PCB_ID3 AK48 AE4 PCB_ID3
{44,45} LPC_AD2 N1 MF_LPC_AD2 V3P3 V1P8 PMU_AC_PRESENT
A13 PMC_SLP_S0IX# 1 @ TP4 AM48 GPIO_DFX5 V1P8 I2C3_SCL
AD2
{44,45} LPC_AD3 MF_LPC_AD3 V3P3 V1P8 PMU_SLP_S0IX_N GPIO_DFX6 V1P8 I2C3_SDA

LC
B12 PMU_SLP_LAN# 1 @ TP20 PXS_RST#_SOC AK41 0610
100_0402_1% V1P8 PMU_SLP_LAN_N GPIO_DFX7

2
RC104 1 2 RCOMP_LPC_HVT T4 N16 PMC_PCIE_WAKE# TP22 @ 1 XDP_GPIO_DFX8 AK42 AC1

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
LPC_HVT_RCOMP V1P8 PMU_WAKE_N GPIO_DFX8 V1P8 I2C4_SCL
SOC_SERIRQ T2 M16 PBTN_OUT# AD3

RC64

RC62

RC950

RC951
ILB_SERIRQ V1P8 V1P8 PMU_PWRBTN_N V1P8 I2C4_SDA UMA@ 14@ @ @
P18 PMC_LAN_WAKE# 1 @ TP21 {12} GPIO_SUS_0 AD51
V1P8PMU_WAKE_LAN_N GPIO_SUS0
H5 {12} GPIO_SUS_1 AD52 AB2 PCH_CMOS_ON#_Q
RSVD_H5 GPIO_SUS1 V1P8 I2C5_SCL
H7 AD42 CPU_SVID_CLK AH50 AC3

GPIO_SUS
SVID

RSVD_H7 V1P8 SVID0_CLK CPU_SVID_CLK {58,59} {12} GPIO_SUS_2 GPIO_SUS2 V1P8 I2C5_SDA

1
AD41 CPU_SVID_DAT @ 1 AH48
V1P8 SVID0_DATA CPU_SVID_DAT {58,59} TP24 GPIO_SUS3
+1.8VALW AD40 CPU_SVID_ALRT# {12} GPIO_SUS_4 AH51 AA1
V1P8 SVID0_ALERT_N CPU_SVID_ALERT# {58,59} GPIO_SUS4 V1P8 I2C6_SCL
{12} GPIO_SUS_5 AH52 AB3 SD_WP_PCH
GPIO_SUS5 V1P8 I2C6_SDA SD_WP_PCH {30}
P28 AG51
2

RSVD_P28 {12,44} EC_SCI# GPIO_SUS6


P30 AG32 VCC0_SENSE EC_SMI# AG53 AA3
Reserved

RC48 RSVD_P30 CORE_VCC0_SENSE GPIO_SUS7 V1P8 RSVD_AA3


Voltage sense

AF50 AJ32 VSS0_SENSE {12} GPIO_SUS_9 AF52 Y2


20K_0402_5% RSVD_AF50 CORE_VSS0_SENSE SEC_GPIO_SUS9 V1P8 RSVD_Y2
AF48 AD29 VCC1_SENSE {12} GPIO_SUS_8 AF51
@

FC
AF44 RSVD_AF48 CORE_VCC1_SENSE AF27 VSS1_SENSE PXS_PWREN#_SOCAE51 SEC_GPIO_SUS8 AM6 PCH_SMB_CLK
AF45 RSVD_AF44 CORE_VSS1_SENSE AD24 VCC_AXG_SENSE KBRST# AC51 SEC_GPIO_SUS10 V1P8 MF_SMB_CLK AM7 PCH_SMB_DATA PCB ID
1

H_PROCHOT# AD50 RSVD_AF45 DDI_VGG_SENSE AD22UNCORE_VSS_SENSE


VCC_AXG_SENSE {59}
2 1 GPIO_RCOMP18 AH40 SEC_GPIO_SUS11 SMBUS
V1P8 MF_SMB_DATA AM9 PCH_SMB_ALERT#
{44} H_PROCHOT# PROCHOT_N V1P8 UNCORE_VSS_SENSE_2 UNCORE_VSS_SENSE {59} GPIO0_RCOMP V1P8MF_SMB_ALERT_N
AC27VNN_SENSE VNN_SENSE {56} RC108 100_0402_1% Y3
UNCORE_VSS_SENSE_1 GPIO_ALERT

RPC5
VCC0_SENSE 1 4
CPU_VCC_SENSE {58}
VSS0_SENSE 2 3
CPU_VSS_SENSE {58}
100_0404_4P2R_1%
+CPU_CORE +GFX_CORE RPC6
VCC1_SENSE 1 4 CPU_VCC_SENSE
VSS1_SENSE 2 3 CPU_VSS_SENSE
2 RC12 1 100_0402_1% CPU_VCC_SENSE 2 RC28 1 100_0402_1% VCC_AXG_SENSE 100_0404_4P2R_1%

2 RC13 1 100_0402_1% CPU_VSS_SENSE 2 RC29 1 100_0402_1% UNCORE_VSS_SENSE

PE
CPU_SVID_ALRT# 1 RC66 2 200_0402_1% +1.05VA_SOC_G3

change from 1.05VA for layout

RC65
+1.8VALW +3VALW
RTC_INTRUDER 1 2

10K_0402_5%

2
+1.8VALW +3VS
RC933

De

1
5 OF 13 10K_0402_5%
BRASWELL_FCBGA151170 RC932

2
REV = 1.2 ? 2.2K_0402_5% @

1
G
B RC112 @ B
2

10K_0402_5%

1
RC14 @ PMC_SUSCLK
10K_0402_5% SUSCLK {40}

D
1
7 OF 13 @
+3VALW +3VS CMOS_ON# {33}
BRASWELL_FCBGA151170
1

REV = 1.2 ? QC203


PJA138K_SOT23-3 +1.8VALW
3
4

QC18

bu
RPC17 EC_SMI# EC_SMI# {44} 1

2
10K_0404_4P2R_5% D
PCH_CMOS_ON#_Q 2 RC61

2
2.2K_0402_5%
2
1

G
PLT_RST# {19,37,40,44,45} S
@

1
3 PMC_ACIN
AC_PRESENT {44}

D
PJA138K_SOT23-3
D2 3

+1.8VALW +3VALW
2

2
QC15B
5 G2 PJT138K_SOT363-6 RC105 RC63 QC207

g
100K_0402_5% 10K_0402_5% PJA138K_SOT23-3

1
@ D QC9
4 S2

+3VALW +3VS 2 0605


1

3
4

1
ACIN# {44}
D1 6

G
QC15A RPC28
PMC_PLTRST# 2 G1 PJT138K_SOT363-6 10K_0404_4P2R_5% S 2N7002KW_SOT323-3

3
3
4
@
RPC3
2
1
1 S1

10K_0404_4P2R_5%
OPT@
2
1

PJA138K_SOT23-3
PXS_RST# {19}
QC168

D2 3
S

PMC_PCIE_WAKE#
PCIE_WAKE# {37,40,44}
QC16B +3VS
1
3

5 G2 PJT138K_SOT363-6
G

+1.8VALW
2

4 S2

2
D1 6

OPT@ RC956
QC16A 10K_0402_5%
PXS_RST#_SOC 2 G1 PJT138K_SOT363-6 OPT@

1
PXS_PWREN
PXS_PWREN {21,57}
1 S1

OPT@

QC19
A +1.8VALW 1 A
+1.8VALW D
PXS_PWREN#_SOC 2

1
G D
RC170 1 OPT@2 2 QC210
3
4

S {44} VGA_GATE#
0_0402_5% G 2N7002KW_SOT323-3
RPC2 3
1
3
4

10K_0404_4P2R_5% PJA138K_SOT23-3 CC137 OPT@ S

3
RPC4 @ .1U_0402_10V6-K
OPT@
@
2
1

10K_0404_4P2R_5%
2
2
1

PM_SLP_S3#
PM_SLP_S3# {44}
KBRST#
KBRST# {44} PM_SLP_S4#
PM_SLP_S4# {44}

Security Classification LC Future Center Secret Data Title

PBTN_OUT#
Issued Date 2014/09/24 Deciphered Date 2015/03/23 SOC (DDI,EDP)
PBTN_OUT# {44}

www.bios-downloads.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 7 of 60

5 4 3 2 1
5 4 3 2 1

? +1.8VALW
UC1F CHV_MCP_EDS DDR3_M0_DQ_63 RPC18
USB_OC1# 2 3
D D
B48 USB_OC0# 1 4
V1P8 USB_OTG_ID
USB30_TX_P0 B32 C42 USB20_P0
{41} USB30_TX_P0 USB3_TXP0 V1P05A V1P8 USB_DP0 USB20_P0 {41}
{41} USB30_TX_N0 USB30_TX_N0 C32
USB3_TXN0 V1P05A V1P8 USB_DN0
B42 USB20_N0
USB20_N0 {41}
LEFT USB (3.0) 10K_0404_4P2R_5%
LEFT USB (3.0) {41} USB30_RX_P0 USB30_RX_P0
USB30_RX_N0
F28
D28 USB3_RXP0 V1P05A C43 USB20_P1
{41} USB30_RX_N0 USB3_RXN0 V1P05A V1P8 USB_DP1 USB20_P1 {45}
B44 USB20_N1
USB30_CTX_DRX_P2 A33
V1P8 USB_DN1 USB20_N1 {45} RIGHT USB (2.0)
{30} USB30_CTX_DRX_P2
USB30_CTX_DRX_N2 C33 USB3_TXP1 V1P05A C41 USB20_P3
{30} USB30_CTX_DRX_N2 USB3_TXN1 V1P05A V1P8 USB_DP2 USB20_P3 {40}
Cardreader (3.0) {30} USB30_CRX_DTX_P2 USB30_CRX_DTX_P2 F30
USB3_RXP1 V1P05A V1P8 USB_DN2
A41 USB20_N3 USB20_N3 {40} BT
{30} USB30_CRX_DTX_N2 USB30_CRX_DTX_N2 D30
USB3_RXN1 V1P05A

Ju
C45 USB20_P4
V1P8 USB_DP3 USB20_P4 {33}
C34 A45 USB20_N4
B34 USB3_TXP2 V1P05A V1P8 USB_DN3 USB20_N4 {33} Camera
G32 USB3_TXN2 V1P05A B40 USB20_P2
USB3_RXP2 V1P05A V1P8 USB_DP4 USB20_P2 {45}
RIGHT USB (2.0)

USB3.0

USB2.0
J32 C40 USB20_N2
USB3_RXN2 V1P05A V1P8 USB_DN4 USB20_N2 {45}
C35 P16 USB_OC1#

st
USB3_TXP3 V1P05A V1P8 USB_OC1_N USB_OC1# {45}
A35 P14 USB_OC0# USB_OC0# {41}
G34 USB3_TXN3 V1P05A V1P8 USB_OC0_N
J34 USB3_RXP3 V1P05A B46
USB3_RXN3 V1P05A RSVD_B46 B47 USB_VBUSSNS RC16 1 2 0_0402_5%
USB3_RCOMP_DP D34 USB_VBUSSNS A48 USB_RCOMP RC193 1 2 113_0402_1%
USB3_RCOMP_DN F34 USB3_RCOMP_P USB_RCOMP

for
USB3_RCOMP_N M36
V1P2 USB_HSIC_0_STROBE PDG 112.5 ohm
C37 N36 Demo 113 ohm
RSVD_C37 V1P2 USB_HSIC_0_DATA
A37

HSIC
F36 RSVD_A37 K38 SD00001KH00

RESERVED
RSVD_F36 V1P2 USB_HSIC_1_STROBE
D36 M38
RSVD_D36 V1P2 USB_HSIC_1_DATA
M34 N38
RSVD_M34 V1P2 USB_HSIC_RCOMP
M32
RSVD_M32 AD10 UART0_TXD
V1P8 UART1_TXD
USB3_RCOMP_DP C38 AD12 UART0_RXD

LC
C RSVD_C38 V1P8 UART1_RXD C
B38 AD13

UART
RSVD_B38 V1P8 UART1_CTS_B
2

G36 AD14
RSVD_G36 V1P8 UART1_RTS_B only for Win7 debug port
RC192 J36
RSVD_J36 Y6
402_0402_1% V1P8 UART2_TXD
N34 Y7
RSVD_N34 V1P8 UART2_RXD
P34 V9
V1P8 UART2_CTS_N
1

USB3_RCOMP_DN RSVD_P34 V10


V1P8 UART2_RTS_N

FC
+1.8VALW
+1.8VALW
+3VALW
6 OF 13
BRASWELL_FCBGA151170
REV = 1.2 ?

3
4

3
4
RPC31 RPC32

PE
2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5%

G2 5
@ @

2
1

2
1
UART0_TXD 4 S2 D2 3
UART_TX_DEBUG {40}
@
QC11B

2
PJT138K_SOT363-6

G1
De
UART0_RXD 1 S1 D1 6
UART_RX_DEBUG {40}
@
B B
QC11A
PJT138K_SOT363-6

only for Win7 debug port

bu
g
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/09/24 Deciphered Date 2015/03/23 SOC (DDI,EDP)

www.bios-downloads.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 8 of 60
5 4 3 2 1
5 4 3 2 1

?
UC1H CHV_MCP_EDS DDR3_M0_DQ_63
+VNN_1.05VA_S4
+CPU_CORE
7A EDS AA18
AF36 UNCORE_VNN_S4_1 AA19
AG33 CORE_VCC1_3 UNCORE_VNN_S4_2 AA21
AG35 CORE_VCC1_7 UNCORE_VNN_S4_3 AA22
AG36 CORE_VCC1_8 UNCORE_VNN_S4_4 AA24
AG38 CORE_VCC1_9 UNCORE_VNN_S4_5 AA25
AJ33 CORE_VCC1_10 UNCORE_VNN_S4_6 AC18
AJ36 CORE_VCC1_14 UNCORE_VNN_S4_7 AC19
AJ38 CORE_VCC1_15 UNCORE_VNN_S4_8 AC21
CORE_VCC1_16 UNCORE_VNN_S4_9 AC22
AF30 UNCORE_VNN_S4_10 AC24
AG27 CORE_VCC1_2 UNCORE_VNN_S4_11 AC25
AG29 CORE_VCC1_4 UNCORE_VNN_S4_12 AD25 +1.05VA_SOC_G3
AG30 CORE_VCC1_5 UNCORE_VNN_S4_13 AD27
AJ27 CORE_VCC1_6 UNCORE_VNN_S4_14
D D
AJ29 CORE_VCC1_11 AA30
AJ30 CORE_VCC1_12 RSVD_AA30 V33
AF29 CORE_VCC1_13 VCCSRAMSOCIUN_1P056 AA32
CORE_VCC1_1 VCCSRAMSOCIUN_1P051 AA33
+GFX_CORE VCCSRAMSOCIUN_1P052 AA35
AD16 VCCSRAMSOCIUN_1P053 AA36
AD18 DDI_VGG_1 VCCSRAMSOCIUN_1P054 AC32
AD19 DDI_VGG_2 VCCSRAMSOCIUN_1P055 Y30
AF16 DDI_VGG_3 VCCSRAMSOCIUN_1P057 Y32 +1.05VA_ICLK_S4
AF18 DDI_VGG_4 VCCSRAMSOCIUN_1P058 Y33
AF19 DDI_VGG_5 VCCSRAMSOCIUN_1P059 Y35
AF21 DDI_VGG_6 VCCSRAMSOCIUN_1P0510

Ju
AF22 DDI_VGG_7 V19 +1.05VA_DDR_G3

iCLK
AJ19 DDI_VGG_8 ICLK_GND_OFF_2 V18
AG16 DDI_VGG_15 ICLK_GND_OFF_1
AG18 DDI_VGG_9 AM21
AG19 DDI_VGG_10 DDR_V1P05A_G3_1 AM33
AG21 DDI_VGG_11 DDR_V1P05A_G3_4 AM22

DDR
AG22 DDI_VGG_12 DDR_V1P05A_G3_2 AN22
DDI_VGG_13 DDR_V1P05A_G3_5

st
AG24 AN32
AJ21 DDI_VGG_14 DDR_V1P05A_G3_6 AM32
AJ22 DDI_VGG_16 DDR_V1P05A_G3_3
DDI_VGG_17 +1.05VA_MPHY_G3
+1.15VA_SOC_G3 AJ24 V22

PCIe
AK24 DDI_VGG_18 PCIE_V1P05A_G3_1 V24
DDI_VGG_19 PCIE_V1P05A_G3_2
AK30
AK35 CORE_V1P15_1 U24

SATA
for
AK36 CORE_V1P15_2 SATA_V1P05A_G3_2 U22
+1.15VA_FUSE_G3 AM29 CORE_V1P15_3 SATA_V1P05A_G3_1 +1.05VA_SSIC_G3
CORE_V1P15_4
+1.15VA_DDI_G3 V27

FUSE USB
AK33 USB3_V1P05A_G3_2 U27
AJ35 FUSE_V1P15_2 USB3_V1P05A_G3_1 V29
AM19 FUSE_V1P15_1 USBSSIC_V1P05A_G3
AK21 VCCSRAMGEN_1P152 N18
VCCSRAMGEN_1P151 FUSE3_V1P05A_G5 U19
FUSE_V1P05A_G3

LC
C C
8 OF 13
REV = 1.2
BRASWELL_FCBGA151170

+CPU_CORE

1
6.4 A

CC30
4.7U_0402_6.3V6M
1
CC31
4.7U_0402_6.3V6M
1
CC32
4.7U_0402_6.3V6M
1
CC33
4.7U_0402_6.3V6M
1
CC34
4.7U_0402_6.3V6M
1
CC35
4.7U_0402_6.3V6M
FC
+1.05VA

2
@
PJ1
2

JUMP_43X79
Need short

1
1

1
CC55
+VNN_1.05VA_S4

1U_0402_6.3V6K
1
3.5A
CC56
1U_0402_6.3V6K
1
CC57
1U_0402_6.3V6K
1
CC58
1U_0402_6.3V6K
1
CC59
1U_0402_6.3V6K
1
CC60
22U_0805_6.3V6M
1
CC61
22U_0805_6.3V6M
1
CC62
22U_0805_6.3V6M

PE
2 2 2 2 2 2 ?
CD@ 2 2 2 2 2
CD@ 2 2 2
CD@ @
Note:Place CAP Back of CPU Note:Place CAP Back of CPU

Note:Place CAP Back of CPU Note:Place Close of CPU's Edge


+CPU_CORE

+1.05VA
33P_0402_50V8J

+1.05VA_SOC_G3
CC139

1 +1.05VA

De
1 1 1 1 +1.05VA_ICLK_S4
CC36 CC37
22U_0805_6.3V6M 22U_0805_6.3V6M CC38 CC39 1 RC9238 2 0_0603_5%
RF_NS@

22U_0603_6.3V6-M 22U_0603_6.3V6-M 2 1 RC9241 2 0_0603_5%


2 2 2 2
CD@ CD@ @ @ 1 1 1 1 1
B CC63 CC64 CC65 CC66 CC67 B
Note:Place Close of CPU's Edge 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1
CC68
+1.15VA_SOC 2 2 2 2 2 1U_0402_6.3V6K
+1.15VA_SOC_G3
@ @

bu
2
1 RC9243 2 0_0603_5% Note:Place CAP Back of CPU
Note:Place CAP Back of CPU Note:Place Close of CPU's Edge
+GFX_CORE 1 1 1 1 1 1
CC46 CC47 CC48 CC49 CC50 CC51
+1.05VA
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
11A +1.05VA_DDR_G3 +1.05VA
+1.05VA_MPHY_G3

g
2 2 2 2 2 2
33P_0402_50V8J

CD@ CD@ @ @
CC41

1
1 1 1 1 RC9281 2 0_0603_5%
CC138 CC42 1 RC9240 2 0_0603_5%
CC40 4.7U_0402_6.3V6M 4.7U_0402_6.3V6M
22U_0603_6.3V6-M Note:Place CAP Back of CPU Note:Place Close of CPU's Edge
RF_NS@

2 1 1 1 1
2 2 2 CC69 CC70 1 1 1
CC73 CC74 CC75
1U_0402_6.3V6K 1U_0402_6.3V6K CC71 CC72
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
Note:Place CAP Back of CPU 22U_0603_6.3V6-M 22U_0603_6.3V6-M
2 2 2 2
CD@ 2 2 2
CD@

+GFX_CORE
+1.15VA_SOC
+1.15VA_DDI_G3 Note:Place CAP Back of CPU Note:Place Close of CPU's Edge Note:Place CAP Back of CPU

1 1 1 1 RC9244 2 0_0603_5%

CC141 CC44 CC45 +1.05VA


1 1 1 +1.05VA_SSIC_G3
22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M CC52 CC53 CC54
2 2 2
CD@ 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
1 RC9242 2 0_0603_5%
Note:Place CAP Back of CPU 2 2 2
10uF 0402 change to 4.7uF for cost down CD@ @
Note:Place CAP Back of CPU 1 1 1 1 1
CC76 CC77 CC78 CC79 CC80
A 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K A
Note:Place Close of CPU's Edge
2 2 2 2 2
@ @ @

+1.15VA_FUSE_G3 Note:Place CAP Back of CPU Note:Place Close of CPU's Edge


+1.15VA_SOC

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
1 RC9279 2 0_0603_5%

Issued Date 2014/09/24 Deciphered Date 2015/03/23 SOC (Power)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
BMWC1 0.4

Date: Tuesday, April 07, 2015 Sheet 9 of 60


5 4 3 2 1
5 4 3 2 1

?CHV_MCP_EDS
+1.35V_DDRCLK +1.35V_DDR UC1I DDR3_M0_DQ_63
+1.24VA_DP_G3
+1.35V AN27
DDRSFR_VDDQ_G_S4 DDI_VDDQ_G3_1
V36
AM25 Y36
DDR_VDDQ_G_S4_2 DDI_VDDQ_G3_2 +1.24VA_G3
BE1 T40
BE53 DDR_VDDQ_G_S4_16 MIPI_V1P2A_G3_2 P40
BJ2 DDR_VDDQ_G_S4_19 MIPI_V1P2A_G3_1 +1.24VA_SIO_G3
BJ3 DDR_VDDQ_G_S4_26 Y27
BJ49 DDR_VDDQ_G_S4_27 ICLK_VSFR_G3_2 Y25 +1.24VA_PLL_G3
BJ5 DDR_VDDQ_G_S4_28 ICLK_VSFR_G3_1
BH50 DDR_VDDQ_G_S4_29 P38
BH5 DDR_VDDQ_G_S4_25 CORE_VSFR_G3_5 V30

DDR
BH49 DDR_VDDQ_G_S4_24 CORE_VSFR_G3_6 AC30
BH4 DDR_VDDQ_G_S4_23 CORE_VSFR_G3_AC30
BE3 DDR_VDDQ_G_S4_22 +1.24VA_CPUPLL_G3
BG51 DDR_VDDQ_G_S4_17 AF35
BG3 DDR_VDDQ_G_S4_21 CORE_VSFR_G3_4 AD35
D BJ51 DDR_VDDQ_G_S4_20 CORE_VSFR_G3_2 AD38 D
BJ52 DDR_VDDQ_G_S4_30 CORE_VSFR_G3_3 AC36
AY10 DDR_VDDQ_G_S4_31 CORE_VSFR_G3_1
AY44 DDR_VDDQ_G_S4_14 +1.24VA_G3
DDR_VDDQ_G_S4_15
AV44
DDR_VDDQ_G_S4_13 USBHSIC_V1P2A_G3
M41 +1.24VA_USB_G3 +1.24VA_G3
AV10 U35
DDR_VDDQ_G_S4_10 USB_VDDQ_G3_2 +1.24VA_USB2_G3

USB
BE51 V35
AV38 DDR_VDDQ_G_S4_18 USB_VDDQ_G3_3 H44
AV16 DDR_VDDQ_G_S4_12 USB_VDDQ_G3_1 P41 +1.8VALW_USB
AU36 DDR_VDDQ_G_S4_11 USBSSIC_V1P2A_G3
AU18 DDR_VDDQ_G_S4_9 AA29
AN36 DDR_VDDQ_G_S4_8 USB_V1P8A_G3 +3VALW_USB_G3
AN35 DDR_VDDQ_G_S4_7 C23
AN19 DDR_VDDQ_G_S4_6 USB_V3P3A_G3_2 B22 VCCRTC
AN18 DDR_VDDQ_G_S4_5 USB_V3P3A_G3_1
AM36 DDR_VDDQ_G_S4_4 C5
AM18 DDR_VDDQ_G_S4_3 RTC_V3P3RTC_G5_2 B6 +3VALW_RTC

RTC
DDR_VDDQ_G_S4_1 RTC_V3P3RTC_G5_1 D4
VCC_LPC_G3 VCC_SD3_S3 RTC_V3P3A_G5_1
RTC_V3P3A_G5_2
E3
E1
SDIO_V3P3A_V1P8A_G3_1
+1.8VALW_FUSE
+1.5VS_HDA_S3 E2
SDIO_V3P3A_V1P8A_G3_2 +1.05VA_FUSE_G3
G1 U16
+1.8VALW_GPIO_E_G3

Ju
AH4 SDIO_V3P3A_V1P8A_G3_3 FUSE_V1P8A_G3
+1.8VALW_GPIO_G3 AF4 VCCCFIOAZA_1P802 H10
Y18 VCCCFIOAZA_1P801 FUSE1_V1P05A_G4 G10

FUSE
AD33 GPIO_V1P8A_G3_5 FUSE0_V1P05A_G3 A3
AK18 GPIO_V1P8A_G3_1 RSVD_A3 K20
AF33 GPIO_V1P8A_G3_3 RSVD_K20 M20
AK19 GPIO_V1P8A_G3_2 RSVD_M20
GPIO_V1P8A_G3_4

9 OF 13
BRASWELL_FCBGA151170 REV = 1.2

st
C
+1.35V

2
1.9 A

CC81
2.2U_0402_6.3V6M
1

2
CC82
2.2U_0402_6.3V6M
1

2
CC83
2.2U_0402_6.3V6M
1

2
CC84
330P_0402_50V7K
1

2
CC85
22U_0603_6.3V6-M
@
2
1
CC86
22U_0603_6.3V6-M
2
CC87
1

22U_0603_6.3V6-M
@
2
CC88
22U_0603_6.3V6-M
1

?
+1.24VALW

for 1 RC9248 2 0_0603_5%


+1.24VA_DP_G3

1
CC102
+1.24VALW

1
RC898
2 0_0603_5%
+1.24VA_G3

1
CC133
1
CC134
+1.24VALW

1 RC9249 2 0_0603_5%
+1.24VA_SIO_G3

1
C

LC
Note:Place CAP Back of CPU EMC@ Note:Place Close of CPU's Edge 1U_0402_6.3V6K 1U_0402_6.3V6K CC135
1U_0402_6.3V6K
@ 1U_0402_6.3V6K
2 2
2Note:Place CAP Back of CPU Note:Place CAP Back of CPU
2
Note:Place CAP Back of CPU
+1.35V
+1.35V
+1.35V_DDR
+1.35V_DDRCLK
+1.24VALW +1.24VA_PLL_G3
1 RC9246 2 0_0603_5%
1 RC9247 2 0_0603_5% +1.24VALW +1.24VA_CPUPLL_G3 +1.24VA_G3
1 RC9250 2 0_0603_5%
1 1 RC9251
CC89 1 1 1 2 0_0603_5% CAD NOTE:FOR
CC91

FC
1U_0402_6.3V6K CC90 PINS M41 1
1U_0402_6.3V6K CC92 1 1 CC109
22U_0603_6.3V6-M CC136 CC107
2 2 22U_0603_6.3V6-M 1U_0402_6.3V6K
2 2 1U_0402_6.3V6K 1U_0402_6.3V6K 1
@
Note:Place CAP Back of CPU @ CC108 2
Note:Place CAP Back of CPU 2 2 1U_0402_6.3V6K @
Note:Place CAP Back of CPU 2
Note:Place CAP Back of CPU
Note:Place Close of CPU's Edge Note:Place Close of CPU's Edge

+1.24VALW +1.24VA_USB_G3
+1.24VALW +1.24VA_USB2_G3
1
RC9253
2 0_0603_5% +1.24VA_G3
VCC_SD3_S3 +3VALW_SOC VCC_LPC_G3
1 RC9254 2 0_0402_5%
+1.8VALW +1.5VS +1.5VS_HDA_S3 CAD NOTE:FOR
1 RC928 2 0_0402_5% 1 1 PINS P41

PE
1 RC9283 2 0_0402_5% CC110 CC111
1 RC905 2 0_0402_5% 1U_0402_6.3V6K 1U_0402_6.3V6K 1 1
1 RC9278 2 0_0402_5% CC142 CC112 1
1 1 @
@ 2 2 1U_0402_6.3V6K
1U_0402_6.3V6K CC113
CC93 CC94 +1.8VALW 1 1U_0402_6.3V6K
1U_0402_6.3V6K 1U_0402_6.3V6K 1 CC96 Note:Place CAP Back of CPU 2 2
Note:Place CAP Back of CPU
CC95
@ 1U_0402_6.3V6K @ 2
2 2 1U_0402_6.3V6K
CD@
2 Note:Place CAP Back of CPU
Note:Place CAP Back of CPU 2
B B

+1.8VALW +1.8VALW_USB

1 RC9256 2 0_0603_5%
+3VALW_SOC +3VALW_USB_G3

De
1 1
CC114 CC115
+1.8VALW +1.8VALW_GPIO_G3 +1.8VALW +1.8VALW_GPIO_E_G3 1U_0402_6.3V6K 1U_0402_6.3V6K
1 RC9257 2 0_0603_5%
VCCRTC +3VALW_SOC +3VALW_RTC
2 2
1 RC924 2 0_0603_5% CD@
1 RC925 2 0_0402_5% Note:Place CAP Back of CPU 1 RC9282 2 0_0402_5%
1
1 1 CC116
CC97 CC98 1U_0402_6.3V6K 1
1 1 1 1 CC118
1U_0402_6.3V6K 1U_0402_6.3V6K
CC99 CC100 CC101 2 CC117 .1U_0402_10V6-K
@
2 2 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K .1U_0402_10V6-K
@ 2
2 2 2 2 @
CD@

bu
Note:Place CAP Back of CPU

+1.8VALW +1.8VALW_FUSE
+1.05VA +1.05VA_FUSE_G3
1 RC9258 2 0_0402_5%
1 RC9259 2 0_0402_5%

1
CC119
1U_0402_6.3V6K 1

g
+3VALW +3VALW CC120
+3VALW 2 Note:Place CAP Back of CPU 1U_0402_6.3V6K
2
@
@
2

RW128
10K_0402_5%
2

@
3

S
RW127
1

G
10K_0402_5% SD_1P8_SEL_3.3V_EN 2 1 RW130 CW24 2 QW14
10K_0402_5% LP2301ALT1G_SOT23-3
0.1U_0402_10V7K

@ D
1
1

@ @
D2 3

QW12B 2
A SD_1P8_SEL_1.8V_EN 5 G2 A
PJT138K_SOT363-6
VCC_SD3_S3
4 S2
D1 6

@
QW12A
SD_1P8_SEL 2 G1 PJT138K_SOT363-6
{4} SD_1P8_SEL
1 S1

@
3

S
G
SD_1P8_SEL_1.8V_EN 2 1 RW129 CW23 2 QW2
10K_0402_5% LP2301ALT1G_SOT23-3
0.1U_0402_10V7K

@ D
1
1

Security Classification LC Future Center Secret Data Title


@
2
Issued Date 2014/09/24 Deciphered Date 2015/03/23 SOC (Power2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
+1.8VALW D 0.4
Note:Intel PAG1.2 recommend E1,E2 not empty even unused DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 10 of 60
5 4 3 2 1

www.bios-downloads.com
5 4 3 2 1

? ?
UC1JCHV_MCP_EDS DDR3_M0_DQ_63 CHV_MCP_EDS
UC1K DDR3_M0_DQ_63
Power-VSS Power-VSS

AN3 AF38 AN21 AY9


AN29 VSS_107 VSS_55 AF32 BG30 VSS_103 VSS_166 AY28
AN25 VSS_106 VSS_54 AF25 BG27 VSS_213 VSS_157 AY26
AN24 VSS_105 VSS_53 AF10 BG24 VSS_212 VSS_156 AY24
AN16 VSS_104 VSS_51 AE9 BG20 VSS_211 VSS_155 AY22
AN14 VSS_102 VSS_50 AE8 BG19 VSS_210 VSS_154 AY20
AN12 VSS_101 VSS_49 AE6 BG18 VSS_209 VSS_153 AW35
AN11 VSS_100 VSS_48 AE53 BG16 VSS_208 VSS_151 AW27
AN1 VSS_99 VSS_47 AE50 BG14 VSS_207 VSS_150 AW19
AM50 VSS_98 VSS_46 AE48 BF42 VSS_206 VSS_149 AM13
D
AM42 VSS_97 VSS_45 AE46 BF32 VSS_203 VSS_88 AK29 D
AM4 VSS_96 VSS_44 AE45 BF28 VSS_201 VSS_78 AK22
AM38 VSS_95 VSS_43 AE43 BF27 VSS_200 VSS_75 AV40
AM35 VSS_94 VSS_42 AE42 BF26 VSS_199 VSS_147 AV35
AH44 VSS_93 VSS_41 AE40 BF22 VSS_198 VSS_146 AV30
AM30 VSS_64 VSS_40 AE14 BF12 VSS_197 VSS_145 AV27
AM27 VSS_92 VSS_39 AE12 BE35 VSS_196 VSS_144 AV24
U25 VSS_91 VSS_38 AE11 BE19 VSS_195 VSS_143 AV19
P10 VSS_335 VSS_37 AE1 C20 VSS_194 VSS_142 AV14
AM16 VSS_317 VSS_36 AD44 BD53 VSS_240 VSS_141 AJ18
AD4 VSS_89 VSS_35 AD36 BG7 VSS_193 VSS_69 AU53
AK7 VSS_34 VSS_33 AC29 BD35 VSS_223 VSS_140 AU51
VSS_87 VSS_26 VSS_192 VSS_139

Ju
AK50 AD32 BD27 AU3
AK47 VSS_86 VSS_32 AD30 BD19 VSS_191 VSS_138 AU1
AK45 VSS_85 VSS_31 AD21 BD1 VSS_190 VSS_137 AT9
AK44 VSS_84 VSS_30 AC38 BC44 VSS_189 VSS_136 AT51
AK40 VSS_83 VSS_29 AC35 BC40 VSS_188 VSS_135 AT45
AK4 VSS_82 VSS_28 AC33 BC38 VSS_187 VSS_134 AT36
AK38 VSS_81 VSS_27 AC16 BC28 VSS_186 VSS_133 AT35
AK32 VSS_80 VSS_25 AB6 BC26 VSS_185 VSS_132 AT3

st
AK27 VSS_79 VSS_24 AB50 BC16 VSS_184 VSS_131 AT27
AK25 VSS_77 VSS_23 AB47 BC14 VSS_183 VSS_130 AT19
AM24 VSS_76 VSS_22 AB42 BC10 VSS_182 VSS_129 AT18
AK16 VSS_90 VSS_21 AB4 BB35 VSS_181 VSS_128 AP9
AJ53 VSS_74 VSS_20 AB14 BB27 VSS_178 VSS_127 AP50
AJ51 VSS_73 VSS_19 AB13 BB19 VSS_177 VSS_126 AP45
AJ3 VSS_72 VSS_18 AB12 BA35 VSS_176 VSS_125 AP4
VSS_71 VSS_17 VSS_175 VSS_124

for
AJ25 AB10 BA30 AN9
AJ16 VSS_70 VSS_16 AA53 BA27 VSS_174 VSS_123 AN8
AJ1 VSS_68 VSS_15 AA38 BA24 VSS_173 VSS_122 AN6
AH9 VSS_67 VSS_14 AA27 BA19 VSS_172 VSS_121 AN53
AH47 VSS_66 VSS_13 AA16 B36 VSS_171 VSS_120 AN51
AH42 VSS_65 VSS_12 A47 B28 VSS_169 VSS_119 AN5
AH41 VSS_63 VSS_8 A43 AY7 VSS_168 VSS_118 AN49
AH14 VSS_62 VSS_7 A39 AY51 VSS_165 VSS_117 AN48
AH13 VSS_61 VSS_6 A31 AY47 VSS_164 VSS_116 AN46
AH12 VSS_60 VSS_5 A23 AY34 VSS_163 VSS_115 AN45
AH10 VSS_59 VSS_4 A19 AY32 VSS_161 VSS_114 AN43

LC
C C
AG25 VSS_58 VSS_3 A15 AY30 VSS_160 VSS_113 AN42
AF47 VSS_57 VSS_2 A11 AY3 VSS_159 VSS_112 AN40
VSS_56 VSS_1 AN30 VSS_158 VSS_111 AN38
10 OF 13 AY45 VSS_108 VSS_110
BRASWELL_FCBGA151170 VSS_162
REV = 1.2
? 11 OF 13
?
BRASWELL_FCBGA151170

FC
REV = 1.2

?
UC1LCHV_MCP_EDS DDR3_M0_DQ_63
Power-VSS

AN33 Y24 CHV_MCP_EDS ?


P32 VSS_109 VSS_369 G30 UC1M DDR3_M0_DQ_63
P27 VSS_321 VSS_272 G28 Power-VSS
VSS_320 VSS_271 F1 W1
P22 G26 VSS_NCTF_F1 VSS_362

PE
VSS_319 VSS_270 C1 V44
P19 G22 VSS_NCTF_C1 VSS_361
VSS_318 VSS_269 BH53 V42
AF24 G14 VSS_NCTF_BH53VSS_360
VSS_52 VSS_268 BH52 V41
N53 G12 VSS_NVTF_BH52VSS_359
VSS_316 VSS_267 BH2 V38
N51 F5 VSS_NCTF_BH2 VSS_358
VSS_315 VSS_266 BH1
N32 F35 VSS_NCTF_BH1
VSS_314 VSS_265 BG53 V32
N24 F32 VSS_NCTF_BG53VSS_357
VSS_313 VSS_264 BG1 V21
N22 F27 VSS_NCTF_BG1 VSS_355
VSS_312 VSS_263 B52 V16
M9 F24 VSS_NCTF_B52 VSS_354
VSS_311 VSS_262 B2 U9
F19 VSS_NCTF_B2 VSS_353
VSS_261 U8
K45 E51 VSS_352
VSS_296 VSS_259 A6 U6
M40 E35 VSS_NCTF_A6 VSS_351
VSS_308 VSS_257 A5 U53

De
M35 E19 VSS_NCTF_A5 VSS_350
VSS_307 VSS_256 U5
M27 D42 VSS_349
VSS_306 VSS_255 M24 U49
AW13 D40 VSSA VSS_348
VSS_148 VSS_254 A7 U48
M19 D38 VSS_11 VSS_347
VSS_304 VSS_253 BF50 U46
M14 D32 VSS_204 VSS_346
VSS_303 VSS_252 BF4 U45
B L35 D27 VSS_202 VSS_345 B
VSS_301 VSS_251 BB50 U43
L27 D24 VSS_180 VSS_344
VSS_300 VSS_250 U42
L19 D16 VSS_343
VSS_299 VSS_249 BB4 U40
L1 D10 VSS_179 VSS_342
VSS_298 VSS_248 U38

bu
K50 J42 VSS_341
VSS_297 VSS_284 BG47
T47 C47 VSS_219
VSS_328 VSS_247 Y9 U33
K4 C39 VSS_376 VSS_339
VSS_295 VSS_246 Y50 U32
K36 C36 VSS_375 VSS_338
VSS_294 VSS_245 Y45 U30
K34 C30 VSS_374 VSS_337
VSS_293 VSS_244 Y40 U29
K32 C3 VSS_373 VSS_336
VSS_292 VSS_243 Y4
K30 C28 VSS_372
VSS_291 VSS_242 Y38 U21
K24 C22 VSS_371 VSS_334
VSS_290 VSS_241 Y29 U18

g
K22 AW41 VSS_370 VSS_333
VSS_289 VSS_152 Y22 U36
K16 BJ7 VSS_368 VSS_340
VSS_288 VSS_238 Y21 U14
K14 BJ47 VSS_367 VSS_332
VSS_287 VSS_237 Y19 U12
K12 BJ43 VSS_366 VSS_331
VSS_286 VSS_236 Y16 U11
J53 BJ39 VSS_365 VSS_330
VSS_285 VSS_235 Y14 T9
M45 BJ35 VSS_364 VSS_329
VSS_309 VSS_234 Y10 P42
J38 BJ31 VSS_363 VSS_325
VSS_283 VSS_233 T14
J35 BJ27 VSS_327
VSS_282 VSS_232 P4 R1
J30 BJ23 VSS_324 VSS_326
VSS_281 VSS_231 L41
J27 BJ19 VSS_302
VSS_280 VSS_230 P36 P35
J22 BJ15 VSS_323 VSS_322
J19 VSS_279 VSS_229 BJ11
J18 VSS_278 VSS_228 BG5
H8 VSS_277 VSS_221 BG49
E46 VSS_276 VSS_220 BG40
H35 VSS_258 VSS_218 BG38
H27 VSS_275 VSS_217 BG36 13 OF 13
H19 VSS_274 VSS_216 BG35 BRASWELL_FCBGA151170
M50 VSS_273 VSS_215 BG34 REV = 1.2
V25 VSS_310 VSS_214
VSS_356

12 OF 13
BRASWELL_FCBGA151170
REV = 1.2 ?
A A

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 SOC (VSS)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 11 of 60
5 4 3 2 1
5 4 3 2 1

Hardware STRAPS
(Follow up CRB) +1.8VALW

+1.8VALW

D D

2
RC9263 RC9264 RC9266 RC9265 RC9267
10K_0402_1% 10K_0402_1% 10K_0402_1% 4.7K_0402_5% 1K_0402_1%
@
2

2
@ @ @
RC9273 RC9274 RC9275 RC46 RC9276

1
100K_0402_5% 100K_0402_5% 10K_0402_1% 4.7K_0402_5% 4.7K_0402_5%

@
1

1
GPIO_SUS_9 {7}

Ju
GPIO_SUS_6
EC_SCI# {7,44}
GPIO_SUS_0 {7}
GPIO_CAM_8 {4}
GPIO_SUS_1 {7}
GPIO_CAM_9 {4}

st
GPIO_SUS_2 {7}
GPIO_CAM_11 {4}
GPIO_SUS_4 {7}

C GPIO_SUS_5 {7} C

for
GPIO_SUS_8 {7}

2
2
RC9268 RC9270 RC9271
100K_0402_5% RC9262 100K_0402_5% 10K_0402_1%
2

100K_0402_5%
@

1
RC9277 RC49 RC51
4.7K_0402_5% 10K_0402_1% 10K_0402_1%

1
@ @

LC
1

B
FC B

PE
GPIO_SUS_5
0606

2
RC961
4.7K_0402_1%
1

De
1

D QC214 RC962
2

2 1 2
G PCH_ME_PROTECT {44}
ME2
SHORT PADS 0_0402_5%
1

S 2N7002KW_SOT323-3
3

bu A

g
Security Classification LC Future Center Secret Data Title
Issued Date 2014/09/24 Deciphered Date 2015/03/23 SOC (STRAPS & OTHERS)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 12 of 60
5 4 3 2 1

www.bios-downloads.com
5 4 3 2 1

D D

Ju
st
C
for C

LC
FC
B
PE B

De
bu
g
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/09/24 Deciphered Date 2015/03/23 MCP (OTHER)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 13 of 60
5 4 3 2 1

www.bios-downloads.com
5 4 3 2 1

DDR Mapping table DDR3 SO-DIMM A


DDRA_DQ[0..63] {5}
DDRA_DQ6---DQ0
DDRA_DQ1---DQ1 +1.35V +1.35V
DDRA_DQS[0..7] {5}
DDRA_DQ4---DQ2
DDRA_DQ2---DQ3 DDRA_DQS#[0..7] {5}
DDRA_DQ3---DQ4
DDRA_DQ0---DQ5 3A@1.5V DDRA_MA[0..15] {5}
DDRA_DQ7---DQ6 For RF request
JDDR1
DDRA_DQ5---DQ7 1 2 DDRA_DM[7:0] {5}
DDR_DQ
D 3 VREF_DQ VSS_2 4 DDRA_DQ3 D

CD4

CD5

CD6
VSS_1 DQ4

.1U_0402_10V6-K

22P_0402_50V8-J

22P_0402_50V8-J

22P_0402_50V8-J
DDRA_DQ9----DQ8 DDRA_DQ6 5 6 DDRA_DQ0
DDRA_DQ1 7 DQ0 DQ5 8
DDRA_DQ12---DQ9 1 DQ1 VSS_4 1 1 1
DDRA_DQ11---DQ10 CD3 9 10 DDRA_DQS#0
DDRA_DM0 11 VSS_3 DQS0# 12 DDRA_DQS0
DDRA_DQ14---DQ11 DM0 DQS0
13 14
DDRA_DQ8----DQ12 2 DDRA_DQ4 15 VSS_5 VSS_6 16 DDRA_DQ7 2 2 2
DDRA_DQ13---DQ13 DDRA_DQ2 17 DQ2 DQ6 18 DDRA_DQ5
DDRA_DQ15---DQ14 19 DQ3 DQ7 20
DDRA_DQ10---DQ15 DDRA_DQ9 21 VSS_7 VSS_8 22 DDRA_DQ8 RF@ RF@ RF@
DDRA_DQ12 23 DQ8 DQ12 24 DDRA_DQ13

Ju
25 DQ9 DQ13 26
DDRA_DQ20---DQ16 VSS_9 VSS_10
DDRA_DQ16---DQ17 DDRA_DQS#1 27 28 DDRA_DM1
DDRA_DQS1 29 DQS1# DM1 30
DDRA_DQ17---DQ18
DDRA_DQ23---DQ19 31 DQS1 RESET# 32 DDRA_DRAMRST# {5} OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
DDRA_DQ11 33 VSS_11 VSS_12 34 DDRA_DQ15
DDRA_DQ19---DQ20 DDRA_DQ14 35 DQ10 DQ14 36 DDRA_DQ10
DDRA_DQ21---DQ21

st
37 DQ11 DQ15 38
DDRA_DQ22---DQ22 DDRA_DQ20 39 VSS_13 VSS_14 40 DDRA_DQ19
DDRA_DQ18---DQ23 DQ16 DQ20 Layout Note:
DDRA_DQ16 41 42 DDRA_DQ21
43 DQ17 DQ21 44 Place near DIMM (10uF_0603_6.3V)*8
DDRA_DQS#2 45 VSS_15 VSS_16 46 DDRA_DM2
DDRA_DQ28---DQ24 DQS2# DM2 (0.1uF_402_10V)*4
DDRA_DQ25---DQ25 DDRA_DQS2 47 48
49 DQS2 VSS_18 50 DDRA_DQ22

for
DDRA_DQ29---DQ26 VSS_17 DQ22
DDRA_DQ24---DQ27 DDRA_DQ17 51 52 DDRA_DQ18
DDRA_DQ23 53 DQ18 DQ23 54
DDRA_DQ27---DQ28 55 DQ19 VSS_20 56 DDRA_DQ27
DDRA_DQ30---DQ29 DDRA_DQ28 57 VSS_19 DQ28 58 DDRA_DQ30 +1.35V
DDRA_DQ26---DQ30 DDRA_DQ25 59 DQ24 DQ29 60
DDRA_DQ31---DQ31 61 DQ25 VSS_22 62 DDRA_DQS#3
DDRA_DM3 63 VSS_21 DQS3# 64 DDRA_DQS3
DM3 DQS3

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
DDRA_DQ32---DQ32 65 66 1
VSS_23 VSS_24

LC
C DDRA_DQ29 67 68 DDRA_DQ26 CD7 1 CD8 1 CD9 1 CD10 CD11 CD12 CD13 CD14 CD15 CD16 CD17 CD18 C
DDRA_DQ33---DQ33 DQ26 DQ30 1 1 1 1 1 1 1 1 1
DDRA_DQ24 69 70 DDRA_DQ31 + CD19
DDRA_DQ39---DQ34 DQ27 DQ31
71 72 220U_6.3V_M
DDRA_DQ34---DQ35 VSS_25 VSS_26
DDRA_DQ37---DQ36 2 2 2 2 2 2 2 2 2 2 2 2 2
DDRA_DQ36---DQ37 DDRA_CKE0 73 74 DDRA_CKE1 @
DDRA_DQ38---DQ38 {5} DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 {5}
75 76
DDRA_DQ35---DQ39 77 VDD_1 VDD_2 78 DDRA_MA15 @ @
NC_1 A15

FC
DDRA_BS2# 79 80 DDRA_MA14
{5} DDRA_BS2# BA2 A14
DDRA_DQ40---DQ40 81 82
DDRA_MA12 83 VDD_3 VDD_4 84 DDRA_MA11
DDRA_DQ45---DQ41 A12/BC# A11
DDRA_DQ42---DQ42 DDRA_MA9 85 86 DDRA_MA7
87 A9 A7 88
DDRA_DQ43---DQ43 VDD_5 VDD_6
DDRA_MA8 89 90 DDRA_MA6
DDRA_DQ44---DQ44 DDRA_MA5 91 A8 A6 92 DDRA_MA4
DDRA_DQ41---DQ45 93 A5 A4 94
DDRA_DQ47---DQ46 DDRA_MA3 95 VDD_7 VDD_8 96 DDRA_MA2 +1.35V
DDRA_DQ46---DQ47 DDRA_MA1 97 A3 A2 98 DDRA_MA0 +1.35V

PE
99 A1 A0 100
DDRA_CLK0 101 VDD_9 VDD_10 102 DDRA_CLK1
DDRA_DQ48---DQ48 {5} DDRA_CLK0 CK0 CK1 DDRA_CLK1 {5} RPD2
DDRA_DQ51---DQ49 DDRA_CLK0# 103 104 DDRA_CLK1#

CD75

330P_0402_50V7K

CD76

330P_0402_50V7K

CD73

330P_0402_50V7K

CD74

330P_0402_50V7K

CD71

330P_0402_50V7K

CD72

330P_0402_50V7K
{5} DDRA_CLK0# CK0# CK1# DDRA_CLK1# {5} 1 4 RD6
DDRA_DQ53---DQ50 105 106
VDD_11 VDD_12 2 3 1 2 DDR_CA
DDRA_DQ49---DQ51 DDRA_MA10 107 108 DDRA_BS1# 1 1 1 1 1 1
DDRA_BS0# 109 A10/AP BA1 110 DDRA_RAS# DDRA_BS1# {5}
DDRA_DQ55---DQ52 {5} DDRA_BS0#
111 BA0 RAS# 112 DDRA_RAS# {5} 4.7K_0404_4P2R_1%
0_0402_5%
DDRA_DQ50---DQ53 DDRA_WE# 113 VDD_13 VDD_14 114 DDRA_CS0#
DDRA_DQ52---DQ54 {5} DDRA_WE# WE# S0# DDRA_CS0# {5} 2 2 2 2 2 2
DDRA_CAS# 115 116 DDRA_ODT0
DDRA_DQ54---DQ55 {5} DDRA_CAS# CAS# ODT0 DDRA_ODT0 {5}
117 118

De
DDRA_MA13 119 VDD_15 VDD_16 120 DDRA_ODT1 +1.35V
DDRA_CS1# 121 A13 ODT1 122 DDRA_ODT1 {5} EMC@ EMC@ EMC@ EMC@ EMC@ EMC@
DDRA_DQ60---DQ56 {5} DDRA_CS1# S1# NC_2
DDRA_DQ61---DQ57 123 124
125 VDD_17 VDD_18 126 DDR_CA
B
DDRA_DQ63---DQ58 TEST VREF_CA RPD1 B
DDRA_DQ62---DQ59 127 128
VSS_27 VSS_28 1 4 RD5
.1U_0402_10V6-K

DDRA_DQ32 129 130 DDRA_DQ37


DDRA_DQ56---DQ60 DDRA_DQ33 131 DQ32 DQ36 132 DDRA_DQ36
2 3 1 2 DDR_DQ
DDRA_DQ57---DQ61 DQ33 DQ37 1
CD21

133 134

bu
DDRA_DQ58---DQ62 DDRA_DQS#4 135 VSS_29 VSS_30 136 DDRA_DM4 4.7K_0404_4P2R_1%0_0402_5%
DDRA_DQ59---DQ63 DDRA_DQS4 137 DQS4# DM4 138
139 DQS4 VSS_32 140 DDRA_DQ38 2
DDRA_DQ39 141 VSS_31 DQ38 142 DDRA_DQ35
DDRA_DQ34 143 DQ34 DQ39 144
145 DQ35 VSS_34 146 DDRA_DQ44
VSS_33 DQ44

g
DDRA_DQ40 147 148 DDRA_DQ41
DDRA_DQ45 149 DQ40 DQ45 150
151 DQ41 VSS_35 152 DDRA_DQS#5
DDRA_DM5 153 VSS_36 DQS5# 154 DDRA_DQS5
DM5 DQS5 Layout Note:
155 156
DDRA_DQ42 157 VSS_37 VSS_38 158 DDRA_DQ47 Place near DIMM
DDRA_DQ43 159 DQ42 DQ46 160 DDRA_DQ46
161 DQ43 DQ47 162 +1.35V
DDRA_DQ48 163 VSS_39 VSS_40 164 DDRA_DQ55
DDRA_DQ51 165 DQ48 DQ52 166 DDRA_DQ50 +0.675VS
167 DQ49 DQ53 168
VSS_41 VSS_42

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
DDRA_DQS#6 169 170 DDRA_DM6
DQS6# DM6

CD64

CD65
DDRA_DQS6 171 172 CD68 1 CD69 1 CD66 1 CD67 1
RD10 1 2 0_0402_5% SA0 173 DQS6 VSS_44 174 DDRA_DQ52

CD70
VSS_43 DQ54

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

10U_0603_6.3V6M

10U_0603_6.3V6M

22P_0402_50V8-J
RD11 1 2 0_0402_5% SA1 DDRA_DQ53 175 176 DDRA_DQ54
DDRA_DQ49 177 DQ50 DQ55 178 CD24 1 CD25 CD26
DQ51 VSS_46 2 2 2 2 1 1 1 1 1 1
179 180 DDRA_DQ56 CD23
DDRA_DQ60 181 VSS_45 DQ60 182 DDRA_DQ57 1U_0402_6.3V6K
DDRA_DQ61 183 DQ56 DQ61 184
185 DQ57 VSS_48 186 DDRA_DQS#7 @ @ @ @ 2 2 2 2 2 2 2
DDRA_DM7 187 VSS_47 DQS7# 188 DDRA_DQS7
189 DM7 DQS7 190
A DDRA_DQ63 191 VSS_49 VSS_50 192 DDRA_DQ58 @ @ @ @ RF@ A
DQ58 DQ62 cost down bom to change 0.1uF
DDRA_DQ62 193 194 DDRA_DQ59 For RF request
195 DQ59 DQ63 196
SA0 197 VSS_51 VSS_52 198
199 SA0 EVENT# 200
+3VS SA1 201 VDDSPD SDA 202 SMB_DATA_S3 {7,40}
203 SA1 SCL 204 SMB_CLK_S3 {7,40}
1 1 VTT_1 VTT_2 +0.675VS
Security Classification LC Future Center Secret Data Title
CD27 CD28 205
GND1 GND2
206 0.65A@0.75V
2.2U_0603_6.3V6K .1U_0402_10V6-K 207 208

www.bios-downloads.com
2 2 BOSS1 BOSS2 Issued Date 2014/09/24 Deciphered Date 2015/03/23 DDRIII SO-DIMM A
@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
LCN_DAN06-K4406-0103 Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
ME@ Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 14 of 60
5 4 3 2 1
5 4 3 2 1

Swap Table
Pin
Number Pin Name Net Name
5 DQ0 DDRB_DQ17
7 DQ1 DDRB_DQ23
15 DQ2 DDRB_DQ18
17 DQ3 DDRB_DQ21
4 DQ4 DDRB_DQ16
6 DQ5 DDRB_DQ22
D
16 DQ6 DDRB_DQ19 D
18 DQ7 DDRB_DQ20
10 DQS#0 DDRB_DQS#2
12 DQS0 DDRB_DQS2
21 DQ8 DDRB_DQ3
23 DQ9 DDRB_DQ5
33 DQ10 DDRB_DQ6
35 DQ11 DDRB_DQ1
22 DQ12 DDRB_DQ2

Ju
24 DQ13 DDRB_DQ4
34 DQ14 DDRB_DQ0
36 DQ15 DDRB_DQ7
27 DQS#1 DDRB_DQS#0
29 DQS1 DDRB_DQS0

st
39 DQ16 DDRB_DQ8
41 DQ17 DDRB_DQ10
51 DQ18 DDRB_DQ14
53 DQ19 DDRB_DQ15
40 DQ20 DDRB_DQ13

for
42 DQ21 DDRB_DQ12
50 DQ22 DDRB_DQ9
52 DQ23 DDRB_DQ11
45 DQS#2 DDRB_DQS#1
47 DQS2 DDRB_DQS1
57 DQ24 DDRB_DQ27

LC
C C
59 DQ25 DDRB_DQ26
67 DQ26 DDRB_DQ28
69 DQ27 DDRB_DQ24
56 DQ28 DDRB_DQ31
58 DQ29 DDRB_DQ30
68 DQ30 DDRB_DQ29
70 DQ31 DDRB_DQ25

FC
62 DQS#3 DDRB_DQS#3
64 DQS3 DDRB_DQS3
129 DQ32 DDRB_DQ33
131 DQ33 DDRB_DQ36
141 DQ34 DDRB_DQ39
143 DQ35 DDRB_DQ38
130 DQ36 DDRB_DQ37

PE
132 DQ37 DDRB_DQ32
140 DQ38 DDRB_DQ35
142 DQ39 DDRB_DQ34
135 DQS#4 DDRB_DQS#4
137 DQS4 DDRB_DQS4
147 DQ40 DDRB_DQ40
149 DQ41 DDRB_DQ43
157 DQ42 DDRB_DQ42

De
159 DQ43 DDRB_DQ44
146 DQ44 DDRB_DQ45
148 DQ45 DDRB_DQ41
B B
158 DQ46 DDRB_DQ46
160 DQ47 DDRB_DQ47
152 DQS#5 DDRB_DQS#5

bu
154 DQS5 DDRB_DQS5
163 DQ48 DDRB_DQ52
165 DQ49 DDRB_DQ51
175 DQ50 DDRB_DQ50
177 DQ51 DDRB_DQ48

g
164 DQ52 DDRB_DQ49
166 DQ53 DDRB_DQ53
174 DQ54 DDRB_DQ54
176 DQ55 DDRB_DQ55
169 DQS#6 DDRB_DQS#6
171 DQS6 DDRB_DQS6
181 DQ56 DDRB_DQ62
183 DQ57 DDRB_DQ57
191 DQ58 DDRB_DQ59
193 DQ59 DDRB_DQ63
180 DQ60 DDRB_DQ56
182 DQ61 DDRB_DQ61
192 DQ62 DDRB_DQ58
194 DQ63 DDRB_DQ60
186 DQS#7 DDRB_DQS#7
188 DQS7 DDRB_DQS7
A A

0.65A@0.75V

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 DDRIII SO-DIMM B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 15 of 59
5 4 3 2 1
5 4 3 2 1

D D

Ju
st
C

for C

LC
FC
B
PE B

De
bu
A
g A

Security Classification LC Future Center Secret Data Title


Issued Date 2014/09/24 Deciphered Date 2015/03/23 USB Hub GL850G-OHY31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 16 of 60
5 4 3 2 1

www.bios-downloads.com
5 4 3 2 1

3437:SA000078V00;3436:SA000078X00

RTC_VCC

D D
1

RG11 UG1
330_0402_5% +3VALW
+3VL 15 14 CG3 1 2 GCLK@
GCLK@ V3.3A VOUT
2
VDD 2.2U_0402_6.3V6M
2

10
VRTC
1 9
32.768K RTC_CLK {7}
CG9 11 6 1 RG1 2 0_0402_5% +1.05VA
27M_VIOE CLK_19.2M
22U_0603_6.3V6-M VIOE_27M 19.2M 19.2M_CLK {7}
2 GCLK@ RG101 2 0_0402_5% 19.2M_VIOE
GCLK@ 19.2M_VIOE 8 12 CLK_27M 1 RG4 2 22_0402_5%
VIOE_19.2M 27M 27M_CLK {19}
27M@ 1

Ju
25M_VIOE 3 4 CLK_25M 1 RG3 2 33_0402_5%
VIO_25M 25M 25M_CLK {37}
GCLK@ CG8
GCLK_XTALI 1 .1U_0402_10V6-K
GCLK_XTALO 16 X1 2
X2 GCLK@

GND1
GND2
GND3

GND4
st
C C
@
5
7
13

17
SLG3NB3437VTR_TQFN16_2X3
+3VL
+3VALW

for
RG5 1 2 0_0402_5%
1 +3VG_AON @
RG6 1 2 0_0402_5% 27M_VIOE
CG5
27M@
.1U_0402_10V6-K
2
GCLK@
1
GCLK_XTALI
CG10

LC
YG1
GCLK@ GCLK_XTALO .1U_0402_10V6-K
2
3 2 27M@
OSC2 GND1
4 1
GND2 OSC1
+3VALW
1 1 +3VALW

FC
B 25MHZ_10PF_7V25000014 B
CG1 CG2 RG7 1 2 0_0402_5%
15P_0402_50V8J 15P_0402_50V8J +3VS GCLK@
2 GCLK@ 2 GCLK@
1 RG8 1 2 0_0402_5% 25M_VIOE
@
CG4
.1U_0402_10V6-K
2 1
GCLK@
CG11

PE
.1U_0402_10V6-K
2
GCLK@

EMC_NS@
CLK_25M CG12 1 2 6P_0402_50V8D

EMC_NS@

De
27M_CLK CG13 1 2 6P_0402_50V8D

A A

Security Classification LC Future Center Secret Data Title


CLK_19.2M CG15 1 2 4.7P_0402_50V8-J Issued Date 2014/09/24 Deciphered Date 2015/03/23 Blank

bu
EMC@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
For EMC Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 17 of 60
5 4 3 2 1

www.bios-downloads.com
5 4 3 2 1

N15x GPIO
Performance Mode P0 TDP at Tj = 102 C* (DDR3)
GPIO I/O ACTIVE Function Description
FBVDDQ PCI Express I/O and Other
GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD
GPIO0 OUT - FB Enable for GC6 2.0 (4) (1,5) /MCLK NVVDD (1.35V) (1.35V) (6) (1.05V) (3.3V)
Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W)
D GPIO1 OUT N/A D

N14X
GPIO2 OUT N/A 128bit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
2GB
DDR3
GPIO3 OUT N/A

GPIO4 OUT N/A

GPIO5 OUT N/A GPU power sequencing---3V3_MAIN_EN

GPIO6

GPIO7
IN

OUT
-

N/A

Ju
GPU wake signal for GC6 2.0

st
GPIO8 I/O - System side PCIe reset Monitor

GPIO9 I/O N/A 2.2K Pull-up


N15x Multi-level Straps
GPIO10 OUT N/A

GPIO11

GPIO12

GPIO13
OUT

IN

OUT
-

-
GPU Core VDD PWM control signal

AC Power Detect Input

Phase Shedding for (10K pull High)


Physical
Strapping pin
ROM_SCLK
Power Rail
+3VGS
Logical
Strapping Bit3
SOR3_EXPOSED
Logical
Strapping Bit2
SOR2_EXPOSED
Logical
Strapping Bit1
SOR1_EXPOSED
Logical
Strapping Bit0
SOR0_EXPOSED

LC
C C
GPIO14 IN N/A
ROM_SI +3VGS RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
GPIO15 IN N/A ROM_SO +3VGS DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE
STRAP0 +3VGS Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
GPIO16 N/A
STRAP1 +3VGS

FC
GPIO17 IN N/A STRAP2 +3VGS
Reserved(keep pull-up and pull-down footprint and not stuff by default)
STRAP3 +3VGS
GPIO18 IN N/A
STRAP4 +3VGS
GPIO19 IN N/A

GPIO20 N/A SMBUS_ALT_ADDR

PE
GPIO21 OUT GPU PCIe self-reset control 0 0x9E (Default)

OVERT OUT Active Low Thermal Catastrophic Over Temperature 1 0x9C (Multi-GPU usage)

N15V-GM Power Sequence

+3VG_AON Other Power rail


N15x Binary Straps
De B

bu
+VGA_CORE
+3VG_AON
Physical
tNVVDD >0
Strapping pin Power Rail Strap Mapping
+1.35VGS
Tpower-off <10ms ROM_SCLK +3VGS SMB_ALT_ADDR
tFBVDDQ >0

g
ROM_SI +3VGS SUB_VENDOR
+1.05VS_VGA
ROM_SO +3VGS VGA_DEVICE
tPEX_VDD >0
STRAP0 +3VGS RAM_CFG[0]
1.all GPU power rails should be turned off within 10ms STRAP1 +3VGS RAM_CFG[1]
1. all power rail ramp up time should be larger than 40us 2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
STRAP2 +3VGS RAM_CFG[2]
STRAP3 +3VGS RAM_CFG[3]
STRAP4 +3VGS PCIE_MAX_SPEED
N15S-GT Power Sequence

+3VG_AON

+VGA_CORE
A A

tNVVDD >0
+1.05VS_VGA

+1.35VGS
tPEX_VDD >0
Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
1. all power rail ramp up time should be larger than 40us
Issued Date 2014/09/24 Deciphered Date 2015/03/23 VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 18 of 60
5 4 3 2 1
5 4 3 2 1

RV1 1 2 0_0402_5% FB_GC6_EN_R

RV2 1 2 0_0402_5% GPU_EVENT#

{6} PCIE_CRX_GTX_N[0..1]

{6} PCIE_CRX_GTX_P[0..1]

{6} PCIE_CTX_C_GRX_N[0..1]
UV1A
{6} PCIE_CTX_C_GRX_P[0..1]
Part 1 of 6
PCIE_CTX_C_GRX_P0 AG6 C6 FB_GC6_EN
D PEX_RX0 GPIO0 FB_GC6_EN {23} D
+3VG_AON +3VG_AON PCIE_CTX_C_GRX_N0 AG7 B2
PCIE_CTX_C_GRX_P1 AF7 PEX_RX0_N GPIO1 D6
PCIE_CTX_C_GRX_N1 AE7 PEX_RX1 GPIO2 C7
AE9 PEX_RX1_N GPIO3 F9
3
4

AF9 PEX_RX2 GPIO4 A3 3VGS_PWR_EN


PEX_RX2_N GPIO5 3VGS_PWR_EN {21,57}
RPV5 AG9 A4 GPU_EVENT#_R

5
AG10 PEX_RX3 GPIO6 B6

G
2.2K_0404_4P2R_5%
@ AF10 PEX_RX3_N GPIO7 E9 SYS_PEX_RST_MON#
AE10 NC81 GPIO8 F8 VGA_ALERT#
A6 Symbol update to OVER
2
1

AE12 NC82 GPIO9 C5


VGA_SMB_CK2 4
S
3 AF12 NC83 GPIO10 E7 NVVDD PWM_VID DV1
EC_SMB_CK2 {39,44} NC84 GPIO11 NVVDD PWM_VID {57}

D
AG12 D7 VGA_AC_DET_R 2 1
NC85 GPIO12 VGA_AC_DET {44}
AG13 B4 PSI_VGA_R @

GPIO
QV1B AF13 NC86 GPIO13 B3 RB751V-40_SOD323-2
2N7002KDWH_SOT363-6 AE13 NC87 GPIO14 C3
2 RV6
2

@ AE15 NC88 GPIO15 D5 1 PSI_VGA


G

NC1 GPIO16 PSI_VGA {57}

Ju
RV7 2 OPT@ 1 0_0402_5% AF15 D4 @ 0_0402_5%
AG15 NC2 GPIO17 C2
AG16 NC3 GPIO18 F7
VGA_SMB_DA2 1 6 AF16 NC4 GPIO19 E6
S

EC_SMB_DA2 {39,44} NC5 GPIO20


D

AE16 C4 GPU_PEX_RST_HOLD#
AE18 NC6 GPIO21
QV1A AF18 NC7 A6 OVERT#
2N7002KDWH_SOT363-6 AG18 NC8 OVERT AB6
AG19 NC9 NC33
@

st
RV9 2 OPT@1 0_0402_5% PU AT EC SIDE, +3VS AND 4.7K AF19 NC10
AE19 NC11 PLT_RST_VGA# 1 RV174 2 0_0402_5%
AE21 NC12 AG3

.1U_0402_10V6-K
+3VS AF21 NC13 NC97 AF4 OPT@
NC14 NC98 1
AG21 AF3 CV218

2
AG22 NC15 NC99

G
+3VGARST RV10 2 @ 1 0_0402_5% NC16 @ +3VG_AON +3VG_AON
2

for
+3VG_AON PCIE_CRX_GTX_P0 CV10 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_P0 AC9 AE3

DACs
PCIE_CRX_GTX_N0 CV13 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_N0 AB9 PEX_TX0 NC100 AE4 OVERT# 3 1
PEX_TX0_N NC101 WRST# {44}

D
RV12 1 2 0_0402_5% PCIE_CRX_GTX_P1 CV8 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_P1 AB10
PCIE_CRX_GTX_N1 CV9 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_N1 AC10 PEX_TX1
1 QV23

2
PEX_TX1_N

PCI EXPRESS
AD11

.1U_0402_10V6-K
C 1 C
AC11 PEX_TX2 W5 CV221 2N7002KW_SOT323-3 RV13
1 PEX_TX2_N NC102
AC12 AE2 0.01U_0402_25V7K OPT@ 10K_0402_5% CV12

2
CV11 AB12 PEX_TX3 NC103 AF2 @ 2 @ @

G
.1U_0402_10V6-K AB13 PEX_TX3_N NC104 2

1
2 OPT@ AC13 NC89
AD14 NC90
AC14 NC91 GPU_EVENT#_R 3 1 GPU_EVENT#

LC
5

NC92

D
UV2 AC15
AB15 NC93 QV4
VCC

1 AB16 NC94 B7 VGA_CRT_CLK 2N7002KW_SOT323-3


{7} PXS_RST# IN1 NC95 I2CA_SCL
4 SYS_PEX_RST_MON# AC16 A7 VGA_CRT_DATA @
PLT_RST# 2 OUT AD17 NC96 I2CA_SDA Connect to CPU GPIO
GND

{7,37,40,44,45} PLT_RST# IN2 AC17 NC17 C9 I2CB_SCL 1 2 RV15


AC18 NC18 I2CB_SCL C8 I2CB_SDA @ 0_0402_5%
NC19 I2CB_SDA

I2C
MC74VHC1G08DFT2G_SC70-5 AB18
2
3

OPT@ AB19 NC20 A9 I2CC_SCL


RV14 NC21 I2CC_SCL
AC19 B9 I2CC_SDA

FC
10K_0402_5% NC22 I2CC_SDA
AD20
OPT@ NC23
AC20 D9 VGA_SMB_CK2 +3VG_AON +3VG_AON
AC21 NC24 I2CS_SCL D8 VGA_SMB_DA2 Internal Thermal Sensor
1

AB21 NC25 I2CS_SDA


AD23 NC26 RPV1
AE23 NC27 VGA_CRT_DATA 4 1 3VGS_PWR_EN RV18 2 1
AF24 NC28 60mA VGA_CRT_CLK 3 2 OPT@ 10K_0402_5%
AE24 NC29 L6 +PLLVDD 10K_0404_4P2R_5% OPT@ OVERT# RV20 1 2
1 2 RV16 NC30 CORE_PLLVDD
AG24 M6 RPV2 OPT@ 10K_0402_5%
@ 0_0402_5% NC31 SP_PLLVDD
AG25 I2CB_SCL 4 1 VGA_ALERT# RV23 1 2
NC32 N6
45mA 1 2 RV24 +SP_PLLVDD I2CB_SDA 3 2 OPT@ 10K_0402_5%
VID_PLLVDD OPT@
0_0402_5% 10K_0404_4P2R_5% OPT@ VGA_AC_DET_R RV26 1 2
45mA RPV3 OPT@ 100K_0402_5%

PE
+3VGS +3VG_AON {6} CLK_PCIE_GPU CLK_PCIE_GPU AE8 I2CC_SCL 4 1 PSI_VGA RV29 1 2
CLK_PCIE_GPU# AD8 PEX_REFCLK I2CC_SDA 3 2 OPT@ 10K_0402_5%
{6} CLK_PCIE_GPU# PEX_REFCLK_N
CLK_REQ_GPU# AC6 10K_0404_4P2R_5% OPT@ GPU_PEX_RST_HOLD# RV31 1 2
PEX_CLKREQ_N OPT@ 10K_0402_5%
1 2 RV32 AF22 RV33 1 2

CLK
PEX_TSTCLK_OUT XTALOUT
Differential signal @ 200_0402_1% PEX_TSTCLK_OUT# AE22 PEX_TSTCLK C11 XTAL_IN @ 10K_0402_5%
2

PEX_TSTCLK_N XTAL_IN B10 XTAL_OUT


B
RV180 RV37 XTAL_OUT B
10K_0402_5% 10K_0402_5% PLT_RST_VGA# AC7 A10 XTALSSIN 1 OPT@ 2 RV21 10K_0402_5%
1 2 RV35 AF25 PEX_RST_N XTAL_SSIN C10 XTALOUT 1 OPT@ 2 RV22
DV6
@ @ PEX_TERMP
PEX_TERMP XTAL_OUTBUFF
10K_0402_5% Under GPU(below 150mils)
OPT@ 2.49K_0402_1% 300ohms (ESR=0.2) Bead
1

GPU_PEX_RST_HOLD# 2
1 PLT_RST_VGA# N16V-GM-S-B1_FCBGA595 +SP_PLLVDD 1 2 LV1

De
+1.05VGS
SYS_PEX_RST_MON# 3 OPT@ PBY160808T-301Y-N_2P

10U_0603_6.3V6M

22U_0805_6.3V6M
150mA

0.1U_0402_10V7K

0.1U_0402_10V7K
1 1 1 1
CV15 CV16 CV17 CV18 OPT@
BAT54AWT1G_SOT323-3
@
2 2 2 2
OPT@ OPT@ OPT@ OPT@
1 2 RV39
OPT@ 0_0402_5%

bu
1 2 RV38
change to BAT54A for cost down OPT_XTAL@ 10M_0402_5%
YV1
Under GPU Near GPU 30ohms (ESR=0.05) Bead
+3VG_AON +3VG_AON XTAL_IN 1 4
OSC1 GND2 +PLLVDD 1 2 LV2 +1.05VGS
2 3 1 RV184 2 XTAL_OUT
GND1 OSC2 PBY160808T-300Y-N_2P
1 1

g
470_0402_1%
2

1 1 OPT@
RV40 RV41 OPT_XTAL@ CV21 CV22
10K_0402_5% 10K_0402_5% CV19 27MHZ_10PF_7V27000050 CV20 0.1U_0402_10V7K 22U_0805_6.3V6M
@ @ OPT@ 2 2 OPT@
OPT_XTAL@
2 2
12P_0402_50V8-J 12P_0402_50V8-J
1

OPT_XTAL@ OPT_XTAL@
+3VG_AON +3VG_AON
.1U_0402_10V6-K

.1U_0402_10V6-K

1 1
CV23 CV24
@ @
2

2
2

A 2 RV44 2 RV45 A
G

27M@
10K_0402_5% 10K_0402_5%
{17} 27M_CLK RV183 1 2 0_0402_5% XTAL_IN
@ @
1

{6} GPU_CLKREQ#
1 3 CLK_REQ_GPU# FB_GC6_EN_R 1 3 FB_GC6_EN
D

QV5 QV6
2

2N7002KW_SOT323-3 2N7002KW_SOT323-3
@ RV46 @ RV47
10K_0402_5% 10K_0402_5%
@
Connect to CPU GPIO @ Title
1 2 RV48 1 2 RV49 Security Classification
Classification LC Future Center Secret Data
1

OPT@
0_0402_5% @ 0_0402_5%
Issued Date 2014/09/24 Deciphered Date 2015/03/23 N16X_PCIE/ DAC/ GPIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 19 of 60
5 4 3 2 1

www.bios-downloads.com
5 4 3 2 1

D D

UV1C

Part 3 of 6 F11
AC3 NC50 AD10
AC4 NC105 NC51 AD7
Y4 NC106 NC52
Y3 NC107 V5
B19 Symbol update to FBA_CMD32
AA3 NC108 FERMI_RSVD1 V6
AA2 NC109 FERMI_RSVD2 G1
AB1 NC110 NC56 G2
NC111 NC57

NC
AA1 G3
NC112 NC58

Ju
AA4 G4
AA5 NC113 NC59 G5
NC114 NC60 G6
NC61 G7
AB5 NC62 V1
AB4 NC115 NC63 V2
AB3 NC116 NC64 W1
AB2 NC117 NC65 W2

st
AD3 NC118 NC66 W3
AD2 NC119 NC67 W4
AE1 NC120 NC68
AD1 NC121
AD4 NC122
AD5 NC123
NC124 D11 2 1 RV50
BUFRST_N