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1 1

LCFC Confidential
Ju
st
BMWC1&C2 M/B Schematics Document
2 for
NM-A471 REV:0.4 2

LC
Intel Braswell M-Processor with DDRIIIL + NV (N16V-GM) GPU
FC
2015-03-23 PE
3
REV:0.4
De 3

bu
g
4 4

Security Classification
Classification LC Future Center Secret Data Title
Issued Date 2014/09/24 Deciphered Date 2015/03/23 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
BMWC1

www.bios-downloads.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, April 07, 2015 Sheet 1 of 60
A B C D E
A B C D E

NV (N16V-GM)
GB2B-64 Package PCI-Express Memory BUS (DDR3L)
Page 18~28 PCIe Port0 Dual Channel DDR3L-SO-DIMM
2x Gen2 Page 14

VRAM 256/128*16 1.35V DDR3L 1600 MT/s


UP TO 8G
1
DDR3L*4 2GB/1GB 1
Page 19~28

USB 3.0 1x USB Left 3.0 Conn


HDMI
HDMI Conn. USB 2.0 1x USB 3.0 Port0
Page 34
USB 2.0 Port0 Page 41

DP to VGA DPx2 Lane


Braswell-M (4.5W) USB Right 2.0 Conn

Ju
VGA Conn. USB 2.0 1x
Page 36 Page 35 ITE IT6515FN
USB 2.0 Port1 Page 45
eDP Conn
BGA-1170 USB Right 2.0 Conn

st
USB 2.0 1x
Int. Camera
USB 2.0 Port3 25mm*27mm USB2.0 Port4 Page 45
eDP x2 Lane
USB Board

for
Int. MIC Conn.
USB 3.0 1x
Cardreader Realtek SD/MMC Conn.
Page 33
2
GL3213L-OHY05 2

Page 30 USB 3.0 Port1

LC
SATA HDD SATA Gen3 SDIO
Page 42 SATA Port0

USB2.0 1x
SATA ODD SATA Gen1 NGFF Card
WLAN&BT

FC
Page 42 SATA Port1 PCIe 1x
PCIe Port2
Page 40 USB 2.0 Port2

LAN Realtek
RJ45 Conn.
RTL8111H_CG
PCIe 1x USB 2.0 1x Int. Camera
Page 38
USB 2.0 Port3

3
Page 37 PCIe Port3

HD Audio
Page 4~12

LPC BUS
PE
FSPI BUS SPI ROM
8MB Sub-board ( for 14")
POWER BOARD
3

De
Codec SPK Conn.
Conexant_CX20751
Page 43
Page 43 USB Board
TPM
EC ST33ZP24AR28PVSP

bu
ITE IT8886E-LQFP
Page 44
Sub-board ( for 15")
HP&Mic Combo Conn.
POWER BOARD
USB Board
Touch Pad
Page 45
Int.KBD
Page 45
Thermal Sensor
NCT7718W
Page 39
g USB Board

ODD Board
4 4

Security Classification
Classification LC Future Center Secret Data Title
Issued Date 2014/09/24 Deciphered Date 2015/03/23 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 2 of 60
A B C D E

www.bios-downloads.com
www.vinafix.com
A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )

+5VS
SIGNAL
Power Plane +3VS STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+1.5VS
+3VALW_SOC Full ON HIGH HIGH HIGH HIGH ON ON ON ON
B+ +3VALW +1.0VALW +1.35V
+0.68VS S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+3VL +5VALW +1.8VALW
1
CPU_CORE 1
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
State GFX_CORE
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF

S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF

S0 O O O O O

Ju
USB Port Table
S3 O O O O X XHCI Port Port device
BOM Structure Table
S5 S4/AC Only O O O X
st X USB 3.0
0
1
USB Port (Left Side)
USB3.0 Card Reader
BOM Structure
AOAC@
OPT@
BTO Item
AOAC support part
GPU Part

for
S5 S4 O X X X X UMA@ UMA SKU ID part
Battery only 0 USB Port (Left Side) 14@ For 14" part
S5 S4 1 15@ For 15" part
AC & Battery X X X X X USB 2.0 USB Port (Right Side)
100M@ 100M LAN part
2 BT

LC
2 2
don't exist 3 Camera N15SGT@ N15SGT Part
N15VGM@ N15GSM Part
4 USB Port (Right Side)
SIGNAL GIGA@ GIGA LAN Part
STATE SLP_S1# SLP_S3# SLP_S4# +VALW +VALW_PCH +V +VS Clock USB HUB 1
2 GC6@ GPU GC6 Part

FC
Full ON HIGH HIGH HIGH ON ON ON ON ON 3 TS@ Touch Screen part
4 RANKA@ GPU VRAM RANKA PART
S1(Power On Suspend) LOW HIGH HIGH ON ON ON ON LOW
RANKB@ GPU VRAM RANKB PART
S3 (Suspend to RAM) LOW LOW HIGH ON ON ON OFF OFF ME@ Connector
CD@ COST DOWN

PE
S4 (Suspend to Disk) LOW LOW LOW ON ON OFF OFF OFF
@ Not stuff
S5 (Soft OFF) LOW LOW LOW ON ON OFF OFF OFF

PCIE PORT LIST


SMBUS Control Table Port Device Hynix VRAM Part
H4T@

3
SOURCE VGA BATT IT8986E SODIMM
WLAN
WiMAX
Thermal
Sensor
PCH TP
Module charger
1
2
3
4
Discrete GPU
Discrete GPU
WLAN De M4T@
S4T@@
Micron VRAM Part
Samsung VRAM Part 3

bu
EC_SMB_CK1 EC V LAN
EC_SMB_DA1 +3VALW X V +3VALW X X X X X V 5
6
7

g
EC_SMB_CK2 EC V V
X X X V X X X 8
EC_SMB_DA2 +3VS +3VGS +3VS +3VS

PCH_SMB_CLK PCH
PCH_SMB_DATA +3VALW_PCH X X X V V X V X X
+3VS +3VS +3VALW_PCH
DDI PORT LIST
Port Device
DDI0 DP TO VGA
EC SM Bus1 address EC SM Bus2 address PCH SM Bus address DDI1
Device Address eDP
4
Device Device Address DDR DIMMA 1010 000Xb DDI2 HDMI 4

Smart Battery 0001 011X b Thermal Sensor EMC1403-2 1001_100xb(reserve)


Charger need to update VGA 0x9E(base on NV default) Wlan Rsvd
TP need to update

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 3 of 60
A B C D E
5 4 3 2 1

? CHV_MCP_EDS
UC1C DDR3_M0_DQ_63 +1.8VALW
DDI0_RCOMP_P RPC27
EDP_HPD# 3 2
1

VGA_HPD# 4 1
RC1
M44
402_0402_1% RSVD_M44 K44 EDP_HPD DP to VGA _HPD 1K_0404_4P2R_5%
RSVD_K44
K48
2

DDI0_RCOMP_N RSVD_K48
{35} VGA_TX0+ VGA_TX0+ D50 K47
DDI0_TXP_0 V1P0 RSVD_K47 VGA_HPD#
VGA_TX0- C51 EDP_HPD#

MCSI and Camera interface


{35} VGA_TX0- DDI0_TXN_0 V1P0
DDI1_RCOMP_P T44
V1P24 MCSI_1_CLKP
{35} VGA_TX1+ VGA_TX1+ H49 T45
DDI0_TXP_1 V1P0 V1P24 MCSI_1_CLKN
1

{35} VGA_TX1- VGA_TX1- H50


RC2 DDI0_TXN_1 V1P0
D Y47 D
V1P24 MCSI_1_DP_0
402_0402_1% F53
DDI0_TXP_2 V1P0 DDI0 V1P24 MCSI_1_DN_0
Y48
F52 V45

3
V1P0 V1P24 QC4B D
DP TO VGA Converter DDI0_TXN_2 MCSI_1_DP_1

6
V47 QC4A D
V1P24 5
2

DDI1_RCOMP_N G53 MCSI_1_DN_1 V50 2 DP_VGA_HPD {35}


DDI0_TXP_3 V1P0 V1P24 MCSI_1_DP_2 CPU_EDP_HPD {33} G
G52 V48 G
DDI0_TXN_3 V1P0 V1P24 MCSI_1_DN_2 T41
V1P24 MCSI_1_DP_3 S 2N7002KDWH_SOT363-6
VGA_AUX H47 T42 S

4
2N7002KDWH_SOT363-6

2
{35} VGA_AUX V1P0 V1P24

1
DDI0_AUXP MCSI_1_DN_3

1
{35} VGA_AUX# VGA_AUX# H46
DDI0_AUXN V1P0 RC4 0604 RC27
P50
V1P24 MCSI_2_CLKP 4.7K_0402_5%
VGA_HPD# W51 P48 100K_0402_5%
HV_DDI0_HPD V1P8A V1P24 MCSI_2_CLKN

Ju
0604
Y51 P47

1
V1P8 V1P24

2
Y52 HV_DDI0_DDC_SCL MCSI_2_DP_0 P45
HV_DDI0_DDC_SDA V1P8 V1P24 MCSI_2_DN_0 M48
V1P24 MCSI_2_DP_1
V52 M47
PANEL0_BKLTEN V1P8 V1P24 MCSI_2_DN_1
V51
PANEL0_BKLTCTL V1P8
W53 T50

st
PANEL0_VDDEN V1P8 MSCI_3_CLKP
DDI0_RCOMP_P F38 T48
DDI0_RCOMP_N G38 DDI0_PLLOBS_P MSCI_3_CLKN
DDI0_PLLOBS_N P44 1 RC24 2
V1P24 MCSI_COMP PCH_ENBKL
CPU_EDP_TX0+ J51 PCH_ENBKL {33}
{33} CPU_EDP_TX0+ DDI1_TXP_0 V1P0 150_0402_1%
CPU_EDP_TX0- H51 AB41
V1P0
{33} CPU_EDP_TX0-
{33} CPU_EDP_TX1+ CPU_EDP_TX1+ K51 DDI1_TXN_0 GP_CAMERASB00 AB45 PCH_ENBKL can direct connect to EC for costdown

for
CPU_EDP_TX1- K52 DDI1_TXP_1 V1P0 GP_CAMERASB01 AB44
{33} CPU_EDP_TX1- DDI1_TXN_1 GP_CAMERASB02
V1P0 AC53
L53 GP_CAMERASB03 AB51
L51 DDI1_TXP_2 V1P0 DDI1 GP_CAMERASB04 AB52
DDI1_TXN_2 V1P0 GP_CAMERASB05
EDP M52 AA51 +3VS
M51 DDI1_TXP_3 V1P0 GP_CAMERASB06 AB40 +3VALW
DDI1_TXN_3 V1P0 GP_CAMERASB07 Y44 GPIO_CAM_8
CPU_EDP_AUX M42 GP_CAMERASB08 GPIO_CAM_8 {12}
{33} CPU_EDP_AUX DDI1_AUXP
CPU_EDP_AUX# K42 V1P0 Y42

4
3
{33} CPU_EDP_AUX#

LC
C DDI1_AUXN GP_CAMERASB09 GPIO_CAM_9 {12} C
V1P0 Y41 ODD_EN
EDP_HPD# R51 GP_CAMERASB10 V40 ODD_EN {42} RPC26
HV_DDI1_HPD V1P8A GP_CAMERASB11 GPIO_CAM_11 {12} 10K_0404_4P2R_5%
PCH_ENBKL P51
PCH_BKLT_CTRL_Q P52 PANEL1_BKLTEN V1P8

1
2
PCH_LCD_VDDEN_Q R53 PANEL1_BKLTCTL V1P8 M7 PCH_EDP_PWM {33}
PANEL1_VDDEN V1P8 SDMMC1_CLK
DDI1_RCOMP_P F47 V1P8
DDI1_RCOMP_N F49 DDI1_PLLOBS_P P6

FC
DDI1_PLLOBS_N V1P8 SDMMC1_CMD

D2 3
{34} HDMI_TX2+ HDMI_TX2+ F40 M6
DDI2_TXP_0 V1P8 SDMMC1_D0 QC2B
HDMI D2 {34} HDMI_TX2- HDMI_TX2- G40 V1P0 M4
DDI2_TXN_0 V1P8 SDMMC1_D1 5 G2 PJT138K_SOT363-6
V1P0 P9
V1P8 SDMMC1_D2
{34} HDMI_TX1+ HDMI_TX1+ J40 P7
HDMI D1 HDMI_TX1- K40 DDI2_TXP_1 V1P0 SDMMC1
V1P8 SDMMC1_D3_CD_N
T6

4 S2
{34} HDMI_TX1- DDI2_TXN_1 V1P0 V1P8 SMMC1_D4_SD_WE
{34} HDMI_TX0+ HDMI_TX0+ F42 T7

D1 6
DDI2_TXP_2 V1P8 SMMC1_D5
{34} HDMI_TX0- HDMI_TX0- G42 V1P0 DDI2 V1P8
T10
QC2A
HDMI D0 DDI2_TXN_2 V1P0
V1P8
SMMC1_D6 T12
PCH_BKLT_CTRL_Q 2 G1
HDMI_CLK+ D44 SMMC1_D7 T13 PJT138K_SOT363-6

PE
{34} HDMI_CLK+ V1P0 V1P8
{34} HDMI_CLK- HDMI_CLK- F44 DDI2_TXP_3 SMMC1_RCLK P13 1 RC106 2
DDI2_TXN_3 V1P0 V1P8 SDMMC1_RCOMP
HDMI CLK

1 S1
D48
DDI2_AUXP V1P0 100_0402_1%
C49 K10
DDI2_AUXN V1P0 V1P8 SDMMC2_CLK K9
V1P8 SDMMC2_CMD
U51
{34} HDMI_HPD HV_DDI2_HPD V1P8A
M12
V1P8 SDMMC2_D0
T51 M10
{34} DDPB_CLK HV_DDI2_DDC_SCL V1P8 V1P8 SDMMC2_D1
T52 K7
{34} DDPB_DATA HV_DDI2_DDC_SDA V1P8 V1P8 SDMMC2_D2

De
K6
B53 SDMMC2
V1P8 SDMMC2_D3_CD_N
+3VS
A52 RSVD_B53 F2 SD_CLK_PCH +3VALW
3 OF 13 V1P8
E52 RSVD_A52 SDMMC3_CLK D2 SD_CMD_PCH SD_CLK_PCH {30}
RSVD_E52 V1P8 SDMMC3_CMD SD_CMD_PCH {30}
B D52 ? K3 SD_CD#_PCH B
RSVD_D52 V1P8 SDMMC3_CD_N SD_CD#_PCH {30}
B50

4
3
RSVD_B50
B49
RSVD_B49 NC's V1P8 SDMMC3_D0
J1 SD_D0_PCH
SD_D0_PCH {30} RPC25
DDI PORT LIST E53
RSVD_E53 V1P8 SDMMC3_D1
J3 SD_D1_PCH
SD_D1_PCH {30}

bu
C53 H3 SD_D2_PCH 10K_0404_4P2R_5%
RSVD_C53 V1P8 SDMMC3_D2 SD_D2_PCH {30}
A51 G2 SD_D3_PCH @
RSVD_A51 V1P8 SDMMC3_D3 SD_D3_PCH {30}
A49

1
2
RSVD_A49
Port Device G44
RSVD_G44 SDMMC3
V1P8 SDMMC3_1P8_EN
K2 SD_1P8_SEL
SD_1P8_SEL {10}
PCH_ENVDD {33}
L3 SD_PWR_EN#
V1P8 SDMMC3_PWR_EN_N SD_PWR_EN# {30}
P12 1 2
V1P8
DDI0 DP TO VGA
SDMMC3_RCOMP RC107 80.6_0402_1%

D2 3
g
QC1B
DDI1 eDP 5 G2 PJT138K_SOT363-6
+1.8VALW @
DDI2 HDMI BRASWELL_FCBGA151170 REV = 1.2

4 S2
D1 6
10K_0402_5%
ODD_EN RC5 1 2 QC1A
@ PCH_LCD_VDDEN_Q 2 G1 PJT138K_SOT363-6
+1.8VALW @

1 S1
2

SD_1P8_SEL RC36 2 @ 1 10K_0402_1%


RC47
1K_0402_1%
@
1

+1.8VALW VCC_SD3_S3
PCH_LCD_VDDEN_Q RC21 1 2 0_0402_5% PCH_ENVDD
SD_PWR_EN#
2

A A
2

RC41
RC37 10K_0402_1%
10K_0402_1% PCH_LCD_VDDEN_Q VOH min is 1.8-0.45=1.35V,
need level shift
1
1

@
@
Security Classification LC Future Center Secret Data Title
SD_CD#_PCH SD_CMD_PCH
SOC (DDI,EDP)

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 4 of 60
5 4 3 2 1
5 4 3 2 1

DDRA_DQ[63:0] {14}

DDRA_MA[15:0] {14}

DDRA_DQS[7:0] {14}

DDRA_DQS#[7:0] {14}

DDRA_DM[7:0] {14}

?
CHV_MCP_EDS
UC1A DDR3_M0_DQ_63 ?
CHV_MCP_EDS
UC1B DDR3_M0_DQ_63
DDRA_MA15 BD49 BG33 DDRA_DQ55
DDRA_MA14 BD47 DDR3_M0_MA_15 DDR3_M0_DQ_63 BH28 DDRA_DQ54
BD5
DDR3_M1_MA_15 DDR1 DDR3_M1_DQ_63
BG21
DDR3_M0_MA_14 DDR3_M0_DQ_62 BD7 BH26
DDRA_MA13 BF44 BJ29 DDRA_DQ53 DDR3_M1_MA_14 DDR3_M1_DQ_62
DDRA_MA12 BF48 DDR3_M0_MA_13 DDR0 DDR3_M0_DQ_61 BG28 DDRA_DQ52
BF10
DDR3_M1_MA_13 DDR3_M1_DQ_61
BJ25
DDR3_M0_MA_12 DDR3_M0_DQ_60 Group 6 BF6 BG26
DDRA_MA11 BB49 BG32 DDRA_DQ51 DDR3_M1_MA_12 DDR3_M1_DQ_60
D DDR3_M0_MA_11 DDR3_M0_DQ_59 BB5 BG22 D
DDRA_MA10 BJ45 BH34 DDRA_DQ50 DDR3_M1_MA_11 DDR3_M1_DQ_59
DDR3_M0_MA_10 DDR3_M0_DQ_58 BJ9 BH20
DDRA_MA9 BE52 BG29 DDRA_DQ49 DDR3_M1_MA_10 DDR3_M1_DQ_58
DDR3_M0_MA_9 DDR3_M0_DQ_57 BE2 BG25
DDRA_MA8 BD44 BJ33 DDRA_DQ48 DDR3_M1_MA_9 DDR3_M1_DQ_57
DDR3_M0_MA_8 DDR3_M0_DQ_56 BD10 BJ21
DDRA_MA7 BE46 DDR3_M1_MA_8 DDR3_M1_DQ_56
DDR3_M0_MA_7 BE8
DDRA_MA6 BB46 BD28 DDRA_DQ63 DDR3_M1_MA_7
DDR3_M0_MA_6 DDR3_M0_DQ_55 BB8 BD26
DDRA_MA5 BH48 BF30 DDRA_DQ62 DDR3_M1_MA_6 DDR3_M1_DQ_55
DDR3_M0_MA_5 DDR3_M0_DQ_54 BH6 BF24
DDRA_MA4 BD42 BA34 DDRA_DQ61 DDR3_M1_MA_5 DDR3_M1_DQ_54
DDR3_M0_MA_4 DDR3_M0_DQ_53 BD12 BA20
DDRA_MA3 BH47 BD34 DDRA_DQ60 DDR3_M1_MA_4 DDR3_M1_DQ_53
DDR3_M0_MA_3 DDR3_M0_DQ_52 Group 7 BH7 BD20
DDRA_MA2 BJ48 BD30 DDRA_DQ59 DDR3_M1_MA_3 DDR3_M1_DQ_52
DDR3_M0_MA_2 DDR3_M0_DQ_51 BJ6 BD24
DDRA_MA1 BC42 BA32 DDRA_DQ58 DDR3_M1_MA_2 DDR3_M1_DQ_51
DDR3_M0_MA_1 DDR3_M0_DQ_50 BC12 BA22
DDRA_MA0 BB47 BC34 DDRA_DQ57 DDR3_M1_MA_1 DDR3_M1_DQ_50
DDR3_M0_MA_0 DDR3_M0_DQ_49 BB7 BC20
BF34 DDRA_DQ56 DDR3_M1_MA_0 DDR3_M1_DQ_49
DDR3_M0_DQ_48 BF20
BF52 DDR3_M1_DQ_48
BF2

Ju
{14} DDRA_BS2# AY40 DDR3_M0_BS_2 AV32 DDRA_DQ47
{14} DDRA_BS1# AY14 DDR3_M1_BS_2 AV22
BH46 DDR3_M0_BS_1 DDR3_M0_DQ_47 AV34 DDRA_DQ46
{14} DDRA_BS0# BH8 DDR3_M1_BS_1 DDR3_M1_DQ_47 AV20
DDR3_M0_BS_0 DDR3_M0_DQ_46 BD36 DDRA_DQ45 DDR3_M1_BS_0 DDR3_M1_DQ_46 BD18
BG45 DDR3_M0_DQ_45 BF36 DDRA_DQ44
BG9 DDR3_M1_DQ_45 BF18
{14} DDRA_CAS# BA40 DDR3_M0_CAS_N DDR3_M0_DQ_44 AU32 DDRA_DQ43
{14} DDRA_RAS# BH44 DDR3_M0_RAS_N DDR3_M0_DQ_43 AU34 DDRA_DQ42
Group 5 BA14 DDR3_M1_CAS_N DDR3_M1_DQ_44 AU22
BH10 DDR3_M1_RAS_N DDR3_M1_DQ_43 AU20
{14} DDRA_WE# AU38 DDR3_M0_WE_N DDR3_M0_DQ_42 BA36 DDRA_DQ41
AU16 DDR3_M1_WE_N DDR3_M1_DQ_42 BA18
{14} DDRA_CS1# AY38 DDR3_M0_CSB_1 DDR3_M0_DQ_41 BC36 DDRA_DQ40
AY16 DDR3_M1_CSB_1 DDR3_M1_DQ_41 BC18

st
{14} DDRA_CS0# DDR3_M0_CSB_0 DDR3_M0_DQ_40
DDR3_M1_CSB_0 DDR3_M1_DQ_40
BD38 BH38 DDRA_DQ39
{14} DDRA_CLK1 DDR3_M0_CK_1 DDR3_M0_DQ_39 BD16 BH16
BF38 BH36 DDRA_DQ38 DDR3_M1_CK_1 DDR3_M1_DQ_39
{14} DDRA_CLK1# DDR3_M0_CKB_1 DDR3_M0_DQ_38 BF16 BH18
AY42 BJ41 DDRA_DQ37 DDR3_M1_CKB_1 DDR3_M1_DQ_38
{14} DDRA_CKE1 DDR3_M0_CKE_1 DDR3_M0_DQ_37 AY12 BJ13
BH42 DDRA_DQ36 DDR3_M1_CKE_1 DDR3_M1_DQ_37
DDR3_M0_DQ_36 Group 4 BH12
BD40 BJ37 DDRA_DQ35 DDR3_M1_DQ_36
{14} DDRA_CLK0 DDR3_M0_CK_0 DDR3_M0_DQ_35 BD14 BJ17
BF40 BG37 DDRA_DQ34 DDR3_M1_CK_0 DDR3_M1_DQ_35
{14} DDRA_CLK0# DDR3_M0_CKB_0 DDR3_M0_DQ_34 BF14 BG17
BB44 BG43 DDRA_DQ33 DDR3_M1_CKB_0 DDR3_M1_DQ_34
BB10 BG11

for
{14} DDRA_CKE0 DDR3_M0_CKE_0 DDR3_M0_DQ_33 BG42 DDRA_DQ32 DDR3_M1_CKE_0 DDR3_M1_DQ_33
DDR3_M0_DQ_32 BG12
AT30 DDR3_M1_DQ_32
RSVD_AT30 AT24
AU30 BB51 DDRA_DQ31 RSVD_AT24
RSVD_AU30 DDR3_M0_DQ_31 Del CS_2(chip select: 1 per Rank) AU24 BB3
AW53 DDRA_DQ30 Del CKE_2(chip select: 1 per Rank) RSVD_AU24 DDR3_M1_DQ_31
DDR3_M0_DQ_30 AW1
AV36 BC52 DDRA_DQ29 DDR3_M1_DQ_30
{14} DDRA_ODT0 DDR3_M0_ODT_0 DDR3_M0_DQ_29 AV18 BC2
BA38 AW51 DDRA_DQ28 DDR3_M1_ODT_0 DDR3_M1_DQ_29
{14} DDRA_ODT1 DDR3_M0_ODT_1 DDR3_M0_DQ_28 BA16 AW3
AV51 DDRA_DQ27 Group 3 DDR3_M1_ODT_1 DDR3_M1_DQ_28
DDR3_M0_DQ_27 AV3
DDRA_OCAVREF AT28 BC53 DDRA_DQ26 DDR3_M1_DQ_27
DDR3_M0_OCAVREF DDR3_M0_DQ_26 AT26 BC1
DDRA_ODQVREF AU28 AV52 DDRA_DQ25 DDR3_M1_OCAVREF DDR3_M1_DQ_26
DDR3_M0_ODQVREF DDR3_M0_DQ_25 AU26 AV2
BD52 DDRA_DQ24 DDR3_M1_ODQVREF DDR3_M1_DQ_25
DDR3_M0_DQ_24 BD2
C BA42 DDR3_M1_DQ_24 C

LC
{14} DDRA_DRAMRST# DDR3_M0_DRAMRST_N BA12
DDR_PWROK AV28 AV42 DDRA_DQ7 DDR3_M1_DRAMRST_N
DDR3_DRAM_PWROK DDR3_M0_DQ_23 DDR_CORE_PWROKAV26 AV12
AP41 DDRA_DQ6 DDR3_VCCA_PWROK DDR3_M1_DQ_23
DDR3_M0_DQ_22 AP13
M0_RCOMPPD BA28 AV41 DDRA_DQ5 DDR3_M1_DQ_22
DDR3_M0_RCOMPPD DDR3_M0_DQ_21 M1_RCOMPPD BA26 AV13
AT44 DDRA_DQ4 DDR3_M1_RCOMPPD DDR3_M1_DQ_21
DDR3_M0_DQ_20 Group 0 AT10
DDRA_DM6 BH30 AP40 DDRA_DQ3 DDR3_M1_DQ_20
DDR3_M0_DM_7 DDR3_M0_DQ_19 BH24 AP14
DDRA_DM7 BD32 AT38 DDRA_DQ2 DDR3_M1_DM_7 DDR3_M1_DQ_19

1
DDR3_M0_DM_6 DDR3_M0_DQ_18 BD22 AT16
DDRA_DM5 AY36 AP42 DDRA_DQ1 DDR3_M1_DM_6 DDR3_M1_DQ_18
DDR3_M0_DM_5 DDR3_M0_DQ_17 RC35 AY18 AP12
DDRA_DM4 BG41 AT40 DDRA_DQ0 DDR3_M1_DM_5 DDR3_M1_DQ_17
DDR3_M0_DM_4 DDR3_M0_DQ_16 182_0402_1% BG13 AT14
DDRA_DM3 BA53 DDR3_M1_DM_4 DDR3_M1_DQ_16
DDR3_M0_DM_3 @ BA1
1

DDRA_DM0 AP44 AV45 DDRA_DQ23

FC
AP10 DDR3_M1_DM_3 AV9
DDRA_DM2 AT48 DDR3_M0_DM_2 DDR3_M0_DQ_15 AY50 DDRA_DQ22

2
RC34 AT6 DDR3_M1_DM_2 DDR3_M1_DQ_15 AY4
182_0402_1% DDRA_DM1 AP52 DDR3_M0_DM_1 DDR3_M0_DQ_14 AT50 DDRA_DQ21
INTEL PDG 182 ohm AP2 DDR3_M1_DM_1 DDR3_M1_DQ_14 AT4
SD00001KG00 DDR3_M0_DM_0 DDR3_M0_DQ_13 AP47 DDRA_DQ20 INTEL PDG 182 ohm DDR3_M1_DM_0 DDR3_M1_DQ_13 AP7
DDRA_DQS6 BH32 DDR3_M0_DQ_12 AV50 DDRA_DQ19 Group 2 BH22 DDR3_M1_DQ_12 AV4
2

DDRA_DQS#6 BG31 DDR3_M0_DQS_7 DDR3_M0_DQ_11 AY48 DDRA_DQ18


BG23 DDR3_M1_DQS_7 DDR3_M1_DQ_11 AY6
DDRA_DQS7 BC30 DDR3_M0_DQSB_7 DDR3_M0_DQ_10 AT47 DDRA_DQ17
BC24 DDR3_M1_DQSB_7 DDR3_M1_DQ_10 AT7
DDRA_DQS#7 BC32 DDR3_M0_DQS_6 DDR3_M0_DQ_9 AP48 DDRA_DQ16
BC22 DDR3_M1_DQS_6 DDR3_M1_DQ_9 AP6
DDRA_DQS5 AT32 DDR3_M0_DQSB_6 DDR3_M0_DQ_8
AT22 DDR3_M1_DQSB_6 DDR3_M1_DQ_8
DDRA_DQS#5 AT34 DDR3_M0_DQS_5 AP51 DDRA_DQ15
AT20 DDR3_M1_DQS_5 AP3
DDRA_DQS4 BH40 DDR3_M0_DQSB_5 DDR3_M0_DQ_7 AR53 DDRA_DQ14
For dual rank BH14 DDR3_M1_DQSB_5 DDR3_M1_DQ_7 AR1
DDRA_DQS#4 BG39 DDR3_M0_DQS_4 DDR3_M0_DQ_6 AK52 DDRA_DQ13
BG15 DDR3_M1_DQS_4 DDR3_M1_DQ_6 AK2
DDRA_DQS3 AY52 DDR3_M0_DQSB_4 DDR3_M0_DQ_5 AL53 DDRA_DQ12 DDR3_M1_DQSB_4 DDR3_M1_DQ_5

PE
DDR3_M0_DQS_3 DDR3_M0_DQ_4 Group 1 AY2 AL1
DDRA_DQS#3 BA51 AR51 DDRA_DQ11 DDR3_M1_DQS_3 DDR3_M1_DQ_4
DDR3_M0_DQSB_3 DDR3_M0_DQ_3 BA3 AR3
DDRA_DQS0 AT42 AT52 DDRA_DQ10 DDR3_M1_DQSB_3 DDR3_M1_DQ_3
DDR3_M0_DQS_2 DDR3_M0_DQ_2 AT12 AT2
DDRA_DQS#0 AT41 AL51 DDRA_DQ9 DDR3_M1_DQS_2 DDR3_M1_DQ_2
DDR3_M0_DQSB_2 DDR3_M0_DQ_1 AT13 AL3
DDRA_DQS2 AV47 AK51 DDRA_DQ8 DDR3_M1_DQSB_2 DDR3_M1_DQ_1
DDR3_M0_DQS_1 DDR3_M0_DQ_0 AV7 AK3
DDRA_DQS#2 AV48 DDR3_M1_DQS_1 DDR3_M1_DQ_0
DDR3_M0_DQSB_1 AV6
DDRA_DQS1 AM52 DDR3_M1_DQSB_1
DDR3_M0_DQS_0 AM2
DDRA_DQS#1 AM51 DDR3_M1_DQS_0
DDR3_M0_DQSB_0 AM3
1 OF 13 DDR3_M1_DQSB_0 2 OF 13
BRASWELL_FCBGA151170
BRASWELL_FCBGA151170
REV = 1.2 ?
REV = 1.2 ?
VREF is not used for DDR3L

De
+1.35V
+1.35V
1

B B
1

RC9
RC6
4.7K_0402_1%
4.7K_0402_1%

bu
2
2

@
@
DDRA_ODQVREF
DDRA_OCAVREF
1

1
1 RC10
1

g
4.7K_0402_1% CC131
RC7 CC130 +3VALW
4.7K_0402_1% .1U_0402_10V6-K +1.35V
.1U_0402_10V6-K 2
2
2

@
@
@
2

4
3

@
RPC14
10K_0404_4P2R_5%
1
2

DDR_CORE_PWROK
+3VALW +1.35V

1
4
3

CC18
RPC13
3

QC10B D .1U_0402_10V6-K
2
10K_0404_4P2R_5% 5
G
1
2

2N7002KDWH_SOT363-6
S
4
6

QC10A D
DDR_PWROK
{7,44} SYS_PWROK 2
1 G
2N7002KDWH_SOT363-6
1 CC19 S
1

A A
CD@
3

QC5B D CC1 .1U_0402_10V6-K


2
5 .1U_0402_10V6-K
G 2
2N7002KDWH_SOT363-6
S
4
6

QC5A D
2 Title
{55} VDDQ_PGOOD G Security Classification
Security Classification LC Future Center Secret Data
2N7002KDWH_SOT363-6
1 S Issued Date 2014/09/24 Deciphered Date 2015/03/23 SOC (DDI,EDP)
1

www.bios-downloads.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
CC3 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
EMC@ Custom 0.4
2
.1U_0402_10V6-K DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 5 of 60

5 4 3 2 1
5 4 3 2 1

+1.8VALW
RPC1
5 4 WLAN_CLKREQ#_Q
6 3 PCIE_CLKREQ_2#
7 2 GPU_CLKREQ#_Q
8 1 LAN_CLKREQ#_Q +3VS

10K_0804_8P4R_5%

2
? RC11
UC1D CHV_MCP_EDS
DDR3_M0_DQ_63 10K_0402_5%
@

1
OPT@ CC4 1 2 .1U_0402_10V6-K PCIE_CTX_GRX_P0 C24 C31 SATA_PTX_DRX_P0
D {19} PCIE_CTX_C_GRX_P0 PCIE_TXP0 V1P0 V1P8 SATA_TXP0 SATA_PTX_DRX_P0 {42} LAN_CLKREQ#_Q D
OPT@ CC5 1 2 .1U_0402_10V6-K PCIE_CTX_GRX_N0 B24 B30 SATA_PTX_DRX_N0 HDD
{19} PCIE_CTX_C_GRX_N0 PCIE_TXN0 V1P0 V1P8 SATA_TXN0 SATA_PTX_DRX_N0 {42} @
PCIE_CRX_GTX_P0 G20 N28 SATA_PRX_DTX_P0
{19} PCIE_CRX_GTX_P0 PCIE_RXP0 V1P0 V1P8 SATA_RXP0 SATA_PRX_DTX_P0 {42}
dGPU PCIE_CRX_GTX_N0 J20 M28 SATA_PRX_DTX_N0

3
{19} PCIE_CRX_GTX_N0 PCIE_RXN0 V1P0 V1P8 SATA_RXN0 SATA_PRX_DTX_N0 {42} D
C29 SATA_PTX_DRX_P1
V1P8 SATA_TXP1 SATA_PTX_DRX_P1 {42} 5
{19} PCIE_CTX_C_GRX_P1 OPT@ CC7 1 2 .1U_0402_10V6-K PCIE_CTX_GRX_P1 A25 A29 SATA_PTX_DRX_N1 2N7002KDWH_SOT363-6
PCIE_TXP1 V1P0 V1P8 SATA_TXN1 SATA_PTX_DRX_N1 {42} G
{19} PCIE_CTX_C_GRX_N1 OPT@ CC6 1 2 .1U_0402_10V6-K PCIE_CTX_GRX_N1 C25
PCIE_TXN1 V1P0 V1P8 SATA_RXP1
J28 SATA_PRX_DTX_P1
SATA_PRX_DTX_P1 {42} ODD QC22B @
{19} PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P1 D20 SATA K28 SATA_PRX_DTX_N1
PCIE_RXP1 V1P0 V1P8 SATA_RXN1 SATA_PRX_DTX_N1 {42} S

6
PCIE_CRX_GTX_N1 F20

4
{19} PCIE_CRX_GTX_N1 V1P0 D
PCIE_RXN1 AH3 2
CC103 1 V1P8 SATA_LED_N 2N7002KDWH_SOT363-6 LAN_CLKREQ# {37}
2 .1U_0402_10V6-K PCIE_PTX_DRX_P4 B26 AH2 G
{40} PCIE_PTX_C_DRX_P4 PCIE_TXP2 V1P0 V1P8 SATA_GP0

Ju
CC104 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_N4 C26 AG3 QC22A
WLAN {40} PCIE_PTX_C_DRX_N4
PCIE_PRX_DTX_P4 D22 PCIE_TXN2 V1P0
PCIe
V1P8 SATA_GP1 AG1 RC18 1 @ 2 0_0402_5% S
{40} PCIE_PRX_DTX_P4 V1P0 V1P8 SATA0_DEVSLP {42}

1
PCIE_PRX_DTX_N4 F22 PCIE_RXP2 SATA_GP2/SATA_DEVSLP0 AF3
{40} PCIE_PRX_DTX_N4 PCIE_RXN2 V1P0 V1P8
SATA_GP3/SATA_DEVSLP1
CC106 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_P3 A27 N30 SATA_RCOMP_DP
{37} PCIE_PTX_C_DRX_P3 PCIE_TXP3 V1P0 SATA_RCOMP_P
CC1051 2 .1U_0402_10V6-K PCIE_PTX_DRX_N3 C27 M30 SATA_RCOMP_DN
{37} PCIE_PTX_C_DRX_N3 PCIE_TXN3 V1P0 SATA_RCOMP_N
LAN PCIE_PRX_DTX_P3 G24

st
{37} PCIE_PRX_DTX_P3 PCIE_RXP3 V1P0
{37} PCIE_PRX_DTX_N3 PCIE_PRX_DTX_N3 J24 W3 PCH_SPI_CLK_R 10_0402_1%2 1 RC134
PCIE_RXN3 V1P0 V1P8 FST_SPI_CLK EC_SPI_CLK {44}
GPU_CLKREQ#_Q AM10 V4 PCH_SPI_CS0#_R 33_0402_5%2 1 RC135
PCIE_CLKREQ_2# AM12 PCIE_CLKREQ0_N V1P8 V1P8 FST_SPI_CS0_N V6 EC_SPI_CS0# {44}
WLAN_CLKREQ#_Q AK14 PCIE_CLKREQ1_N V1P8 V1P8 FST_SPI_CS1_N V7
LAN_CLKREQ#_Q RC19 1 2 0_0402_5% LAN_CLKREQ#
LAN_CLKREQ#_Q AM14 PCIE_CLKREQ2_N V1P8 V1P8 FST_SPI_CS2_N
PCIE_CLKREQ3_N V1P8

for
V1P8
V2 PCH_SPI_D0_R 10_0402_1%2 1 RC130 LAN_CLKREQ# is OD,Can pull high to 1.8V
A21 FST_SPI_D0 V3 EC_SPI_D0 {44}
CLK_PCIE_GPU
V1P8
PCH_SPI_D1_R 10_0402_1%2 1 RC131
{19} CLK_PCIE_GPU CLK_DIFF_P_0 FST_SPI_D1 EC_SPI_D1 {44}
{19} CLK_PCIE_GPU#
CLK_PCIE_GPU# C21
CLK_DIFF_N_0
FAST
V1P8 SPI FST_SPI_D2
U1 PCH_SPI_D2_R 10_0402_1%2 1 RC132
EC_SPI_D2 {44}
C19 U3 PCH_SPI_D3_R 10_0402_1%2 1 RC133 +3VS
CLK_DIFF_P_1 V1P8 FST_SPI_D3 EC_SPI_D3 {44}
B20
CLK_PCIE_WLAN C18 CLK_DIFF_N_1 AF13 HDA_RST_AUDIO#_R 1 RC39 2 75_0402_1%
{40} CLK_PCIE_WLAN CLK_DIFF_P_2 V1P5 MF_HDA_RST_N HDA_RST_AUDIO# {43}
CLK_PCIE_WLAN# B18 AD6

2
{40} CLK_PCIE_WLAN# CLK_DIFF_N_2 V1P5 MF_HDA_SDI1 RC40
CLK_PCIE_LAN C17 AD9 HDA_BITCLK_AUDIO_R 1 2 75_0402_1%
{37} CLK_PCIE_LAN CLK_DIFF_P_3 V1P5 MF_HDA_CLK HDA_BITCLK_AUDIO {43} RC3
CLK_PCIE_LAN# A17 AD7

LC
C {37} CLK_PCIE_LAN# CLK_DIFF_N_3 V1P5 MF_HDA_SDI0 HDA_SDIN0 {43} 10K_0402_5% C
C16 AF12 HDA_SYNC_AUDIO_R 1 RC42 2 75_0402_1%
RSVD_C16 V1P5 MF_HDA_SYNC HDA_SYNC_AUDIO {43}
B16 AF14 HDA_SDOUT_AUDIO_R 1 RC43 2 75_0402_1%
RSVD_B16 V1P5 MF_HDA_SDO HDA_SDOUT_AUDIO {43}
AB9

1
V1P5 MF_HDA_DOCKEN_N
PCIE_RCOMP_DP D26 AB7 WLAN_CLKREQ#_Q
PCIE_RCOMP_P V1P5 MF_HDA_DOCKRST_N
PCIE_RCOMP_DN F26
PCIE_RCOMP_N H4
V1P8 SPKR PCH_BEEP {43}

3
V14
SPI1_CLK V1P8 AUDIO D
Y13 AK9 5

FC
SPI1_CS0_N V1P8 GP_SSP_2_CLK 2N7002KDWH_SOT363-6
Y12 AK10 G
V13 SPI1_CS1_N SPI
V1P8 GP_SSP_2_FS AK12 QC8B
SPI1_MISO V1P8 GP_SSP_2_TXD
V12 AK13 S

6
V1P8

4
SPI1_MOSI GP_SSP_2_RXD D
2
2N7002KDWH_SOT363-6 WLAN_CLKREQ# {40}
REV = 1.2 G
QC8A
BRASWELL_FCBGA151170 4 OF 13 S

1
SATA_RCOMP_DP PCIE_RCOMP_DP

PE
2
2

RC30 RC38 +3VS


402_0402_1% 402_0402_1%

De
1

2
1

PCIE_RCOMP_DN
SATA_RCOMP_DN RC8
10K_0402_5%
B OPT@ B

1
GPU_CLKREQ#_Q

bu
+3VALW OPT@

3
D
5
RC94 1 2 +VCC_SPI 2N7002KDWH_SOT363-6 G
0_0402_5% QC7B OPT@
S

6
4
D

g
? 2
2N7002KDWH_SOT363-6 GPU_CLKREQ# {19}
G
+VCC_SPI +1.8VALW QC7A
S

1
@ +3VS
RC20 1 2 PCH_SPI_CS0# RC84 1 2 PCH_SPI_CS0#_R
@ 0_0402_5%
100K_0402_5%

2
RC17
+VCC_SPI
UC2 OPT@
PCH_SPI_CS0# 1 8 50mA 10K_0402_5%

1
CS# VCC GPU_CLKREQ#
1
PCH_SPI_D1 2 7 PCH_SPI_D3
DO HOLD# CC8
PCH_SPI_D2 3 6 PCH_SPI_CLK .1U_0402_10V6-K
WP# CLK 2
4 5 PCH_SPI_D0
GND DI

W25Q64FVSSIQ_SO8
A 0605 A

PCH_SPI_CS0#
PCH_SPI_CLK PCH_SPI_CS0# {44}
PCH_SPI_D0 PCH_SPI_CLK {44}
PCH_SPI_D1 PCH_SPI_D0 {44}
PCH_SPI_D2 PCH_SPI_D1 {44} Security Classification LC Future Center Secret Data Title
PCH_SPI_D2 {44}
PCH_SPI_D3
PCH_SPI_D3 {44} Issued Date 2014/09/24 Deciphered Date 2015/03/23 SOC (DDI,EDP)

www.bios-downloads.com
SPI ROM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 6 of 60
5 4 3 2 1
5 4 3 2 1

+1.8VALW
1,Spec. request 19.2MHz, Cp=12pf, RC=200K
32.768K need change to SJ10000IM00, PMC_PLTRST# 2 RC70 1 @
+1.8VALW +1.8VALW +3VALW
as intel EDS New request 10K_0402_5%
PCH_SMB_ALERT# 2 RC120 1 @
10K_0402_5%
+1.8VALW +3VALW +1.8VALW
PMC_RSTBTN# 1 RC73 2 10K_0402_5%

RTC_X2

XTAL19_OUT
XTAL19_IN
VCCRTC

RTC_X1

3
4

3
4
1 RC71 2 100K_0402_5%
SUSWARN# @
RPC22 RPC23
RC92 1 2 10M_0402_5% RC89 1 2 20K_0402_1%
2

2
SRTC_RST#
2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5%
RC96 RC97 RC98 PMC_SUSCLK @ 1 RC83 2 10K_0402_5%
XTAL@

2
0_0402_5% 0_0402_5% 10K_0402_5%
YC1 RC93 1 2 200K_0402_5% RC90 1 2 20K_0402_1%

2
1

2
1
RTC_RST# EC_RSMRST# 2 RC930 1 100K_0402_5%
TPM@

G1
1

1
UC3 1 2 XTAL@ EC_RSMRST# CC132 1 20.01U_0402_25V7K
PCH_SMB_CLK 1 S1 D1 6 PCH_SMB_CLK_Q
1 6 YC2 @

1U_0402_6.3V6K

1U_0402_6.3V6K
VCCA VCCB 32.768KHZ_12.5PF_202740-PG14
2 2 1 1 SUSWARN# 1 RC75 2 100K_0402_5%

1
CC10
D 2 5 XTAL@ 1 4 JCMOS1 D

CC9
GND EO CC11 CC12 OSC1 NC2 SHORT PADS QC20A
SOC_SERIRQ 3 4 15P_0402_50V8J 18P_0402_50V8J 2 3 @ PJT138K_SOT363-6

2
A4 B4 SERIRQ {44,45} 1 1 1 NC1 OSC2 2 2
JCMOS/JCMOS1

G2 5
1 1 XTAL@ XTAL@ 1
Place under Bottom +3VS
CC13
CC15 CC16 RPC29
G2129TL1U_SC70-6 27P_0402_50V8J CC14
.1U_0402_10V6-K
2 TPM@ 2
.1U_0402_10V6-K CRYSTAL 2
XTAL@
19.2MHZ_18PF_7V19200005
2
27P_0402_50V8J
RTCRST#
Space 15Mil
PCH_SMB_DATA 4 S2 D2 3 PCH_SMB_DATA_Q SMB_CLK_S3 4 1
TPM@ XTAL@ SMB_DATA_S3 3 2
TPM@ 1,Space 15MIL XTAL@
2,No trace under crystal @
QC20B 2.2K_0404_4P2R_5%
3,place on oppsosit side of MCP for temp influence RTC RST# PJT138K_SOT363-6
R_CLK@ R_CLK@
RC121 1 2 0_0402_5% RTC_X1 RC122 1 2 0_0402_5% XTAL19_IN +3VS
{17} RTC_CLK {17} 19.2M_CLK
NTPM@
SOC_SERIRQ RC33 1 2 0_0402_5% SERIRQ

PCB_ID0 PCB_ID1 PCB_ID2 PCB_ID3 Description

Ju
SERIRQ level shift need IC, not MOS for frequence 0 Reserve Reserve UMA SKU

5
SYS_PWROK 1 2 CC140 ? 1 Reserve Reserve GPU SKU

G
EMC@ .1U_0402_10V6-K UC1E CHV_MCP_EDS
DDR3_M0_DQ_63 QC6B

0 Reserve Reserve 14’ panel


XTAL19_IN P24 PCH_SMB_CLK_Q 3 4

S
M22 OSCIN C11 SMB_CLK_S3 {14,40}
XTAL19_OUT @

D
st
OSCOUT RSVD_C11 B10 2N7002KDWH_SOT363-6 1 Reserve Reserve 15’ panel
J26 RSVD_B10 F12
?
CHV_MCP_EDS RSVD_J26 RSVD_F12 RC123 1 2 0_0402_5%
UC1G DDR3_M0_DQ_63 N26 F10
RC45 RSVD_N26 RSVD_F10

2
2.49K_0402_1% 2 1 ICLK_ICOMP P20

G
49.9_0402_1% 2 RC44 1 ICLK_RCOMP N20 ICLKICOMP D12 QC6A
1 AF42 M18 P26 ICLKRCOMP iCLK RESERVED RSVD_D12 E8
+1.8VALW
JTAG/ITP

TP13 @ XDP_TCLK RTC_X1


TP14 @ 1 XDP_TDI AD47 TCK V1P8 RTC_X1 K18 RTC_X2 K26 RSVD_P26 RSVD_E8 C7
TDI V1P8 RTC_X2 RSVD_K26 RSVD_C7
TP15 @ 1 XDP_TDO AF40 F16 BVCCRTC_EXTPAD CC17 1 2 .1U_0402_10V6-K M26 D6 PCH_SMB_DATA_Q 6 1

S
TP16 @ 1 XDP_TMS AD48 TDO V1P8 RTC_EXTPAD AH45 RSVD_M26 RSVD_D6 @
SMB_DATA_S3 {14,40}

D
TP17 @ 1 XDP_TRST# AB48 TMS V1P8 RTC
D18 RTC_RST# RSVD_AH45 J12 2N7002KDWH_SOT363-6
TRST_N V1P8 RTC_RST_N RTC_RST# {44} RSVD_J12
G16 A9 F7

PLTFM CLK's
SYS_PWROK

for
V3P3 COREPWROK SYS_PWROK {5,44} MF_PLT_CLK0 RSVD_F7
F18 EC_RSMRST# C9 V1P8 J14
V3P3 RSMRST_N EC_RSMRST# {44} MF_PLT_CLK1 RSVD_J14

2
TP18 @ 1 XDP_PRDY# AD45 J16 SRTC_RST# B8 V1P8 L13

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
TP19 @ 1 XDP_PREQ# AF41 CX_PRDY_N RTC_TEST_N G18 RTC_INTRUDER B7 MF_PLT_CLK2 V1P8 RSVD_L13 RC124 1 2 0_0402_5%

RC59

RC58

RC948

RC949
CX_PREQ_N RSVD_VSS_G18 MF_PLT_CLK3 OPT@ 15@ @ @
M13 B5 V1P8 AK6
RSVD_M13 MF_PLT_CLK4 V1P8 I2C0_SCL
AE3 SUSWARN# B4 V1P8 AH7
V1P8 SUSPWRDNACK SUSWARN# {56} MF_PLT_CLK5 V1P8 I2C0_SDA
RC80 1 2 0_0402_5% PCH_PCI_CLK_RP2 D14 1 @ TP5 V1P8
{44} CLK_PCI_EC MF_LPC_CLKOUT0V3P3 V1P8 SUS_STAT_N

1
RC81 1 2 0_0402_5% R3 C15 PMC_SUSCLK AF6
{45} CLK_PCI_TPM
TPM@ T3 MF_LPC_CLKOUT1V3P3 V1P8 PMU_SUSCLK C12 PM_SLP_S4# TP23 @ 1 AM40
V1P8 I2C1_SCL
AH6
P3 LPC_CLKRUN_N V3P3 V1P8 PMU_SLP_S4_N B14 PM_SLP_S3# AM41 GPIO_DFX0 V1P8 I2C1_SDA

GPIO_DFX
{44,45} LPC_FRAME# LPC_FRAME_N V3P3 V1P8 PMU_SLP_S3_N GPIO_DFX1
PMU

AF2 PMC_RSTBTN# PCB_ID0 AM44 AF9 PCB_ID0


V1P8 PMU_RESETBUTTON_N GPIO_DFX2 V1P8 I2C2_SCL
M3 F14 PMC_PLTRST# PCB_ID1 AM45 Internal 20K(H) AF7 PCB_ID1
LPC

{44,45} LPC_AD0 M2 MF_LPC_AD0 V3P3 V1P8 PMU_PLTRST_N C14 PMC_BATLOW# 1 RC72 2 PCB_ID2 AM47 GPIO_DFX3 I2C V1P8 I2C2_SDA
PCB_ID2
C {44,45} LPC_AD1 MF_LPC_AD1 V3P3 V1P8 PMU_BATLOW_N +1.8VALW GPIO_DFX4 C
N3 C13 PMC_ACIN 20K_0402_1% PCB_ID3 AK48 AE4 PCB_ID3
{44,45} LPC_AD2 N1 MF_LPC_AD2 V3P3 V1P8 PMU_AC_PRESENT
A13 PMC_SLP_S0IX# 1 @ TP4 AM48 GPIO_DFX5 V1P8 I2C3_SCL
AD2
{44,45} LPC_AD3 MF_LPC_AD3 V3P3 V1P8 PMU_SLP_S0IX_N GPIO_DFX6 V1P8 I2C3_SDA

LC
B12 PMU_SLP_LAN# 1 @ TP20 PXS_RST#_SOC AK41 0610
100_0402_1% V1P8 PMU_SLP_LAN_N GPIO_DFX7

2
RC104 1 2 RCOMP_LPC_HVT T4 N16 PMC_PCIE_WAKE# TP22 @ 1 XDP_GPIO_DFX8 AK42 AC1

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
LPC_HVT_RCOMP V1P8 PMU_WAKE_N GPIO_DFX8 V1P8 I2C4_SCL
SOC_SERIRQ T2 M16 PBTN_OUT# AD3

RC64

RC62

RC950

RC951
ILB_SERIRQ V1P8 V1P8 PMU_PWRBTN_N V1P8 I2C4_SDA UMA@ 14@ @ @
P18 PMC_LAN_WAKE# 1 @ TP21 {12} GPIO_SUS_0 AD51
V1P8PMU_WAKE_LAN_N GPIO_SUS0
H5 {12} GPIO_SUS_1 AD52 AB2 PCH_CMOS_ON#_Q
RSVD_H5 GPIO_SUS1 V1P8 I2C5_SCL
H7 AD42 CPU_SVID_CLK AH50 AC3

GPIO_SUS
SVID

RSVD_H7 V1P8 SVID0_CLK CPU_SVID_CLK {58,59} {12} GPIO_SUS_2 GPIO_SUS2 V1P8 I2C5_SDA

1
AD41 CPU_SVID_DAT @ 1 AH48
V1P8 SVID0_DATA CPU_SVID_DAT {58,59} TP24 GPIO_SUS3
+1.8VALW AD40 CPU_SVID_ALRT# {12} GPIO_SUS_4 AH51 AA1
V1P8 SVID0_ALERT_N CPU_SVID_ALERT# {58,59} GPIO_SUS4 V1P8 I2C6_SCL
{12} GPIO_SUS_5 AH52 AB3 SD_WP_PCH
GPIO_SUS5 V1P8 I2C6_SDA SD_WP_PCH {30}
P28 AG51
2

RSVD_P28 {12,44} EC_SCI# GPIO_SUS6


P30 AG32 VCC0_SENSE EC_SMI# AG53 AA3
Reserved

RC48 RSVD_P30 CORE_VCC0_SENSE GPIO_SUS7 V1P8 RSVD_AA3


Voltage sense

AF50 AJ32 VSS0_SENSE {12} GPIO_SUS_9 AF52 Y2


20K_0402_5% RSVD_AF50 CORE_VSS0_SENSE SEC_GPIO_SUS9 V1P8 RSVD_Y2
AF48 AD29 VCC1_SENSE {12} GPIO_SUS_8 AF51
@

FC
AF44 RSVD_AF48 CORE_VCC1_SENSE AF27 VSS1_SENSE PXS_PWREN#_SOCAE51 SEC_GPIO_SUS8 AM6 PCH_SMB_CLK
AF45 RSVD_AF44 CORE_VSS1_SENSE AD24 VCC_AXG_SENSE KBRST# AC51 SEC_GPIO_SUS10 V1P8 MF_SMB_CLK AM7 PCH_SMB_DATA PCB ID
1

H_PROCHOT# AD50 RSVD_AF45 DDI_VGG_SENSE AD22UNCORE_VSS_SENSE


VCC_AXG_SENSE {59}
2 1 GPIO_RCOMP18 AH40 SEC_GPIO_SUS11 SMBUS
V1P8 MF_SMB_DATA AM9 PCH_SMB_ALERT#
{44} H_PROCHOT# PROCHOT_N V1P8 UNCORE_VSS_SENSE_2 UNCORE_VSS_SENSE {59} GPIO0_RCOMP V1P8MF_SMB_ALERT_N
AC27VNN_SENSE VNN_SENSE {56} RC108 100_0402_1% Y3
UNCORE_VSS_SENSE_1 GPIO_ALERT

RPC5
VCC0_SENSE 1 4
CPU_VCC_SENSE {58}
VSS0_SENSE 2 3
CPU_VSS_SENSE {58}
100_0404_4P2R_1%
+CPU_CORE +GFX_CORE RPC6
VCC1_SENSE 1 4 CPU_VCC_SENSE
VSS1_SENSE 2 3 CPU_VSS_SENSE
2 RC12 1 100_0402_1% CPU_VCC_SENSE 2 RC28 1 100_0402_1% VCC_AXG_SENSE 100_0404_4P2R_1%

2 RC13 1 100_0402_1% CPU_VSS_SENSE 2 RC29 1 100_0402_1% UNCORE_VSS_SENSE

PE
CPU_SVID_ALRT# 1 RC66 2 200_0402_1% +1.05VA_SOC_G3

change from 1.05VA for layout

RC65
+1.8VALW +3VALW
RTC_INTRUDER 1 2

10K_0402_5%

2
+1.8VALW +3VS
RC933

De

1
5 OF 13 10K_0402_5%
BRASWELL_FCBGA151170 RC932

2
REV = 1.2 ? 2.2K_0402_5% @

1
G
B RC112 @ B
2

10K_0402_5%

1
RC14 @ PMC_SUSCLK
10K_0402_5% SUSCLK {40}

D
1
7 OF 13 @
+3VALW +3VS CMOS_ON# {33}
BRASWELL_FCBGA151170
1

REV = 1.2 ? QC203


PJA138K_SOT23-3 +1.8VALW
3
4

QC18

bu
RPC17 EC_SMI# EC_SMI# {44} 1

2
10K_0404_4P2R_5% D
PCH_CMOS_ON#_Q 2 RC61

2
2.2K_0402_5%
2
1

G
PLT_RST# {19,37,40,44,45} S
@

1
3 PMC_ACIN
AC_PRESENT {44}

D
PJA138K_SOT23-3
D2 3

+1.8VALW +3VALW
2

2
QC15B
5 G2 PJT138K_SOT363-6 RC105 RC63 QC207

g
100K_0402_5% 10K_0402_5% PJA138K_SOT23-3

1
@ D QC9
4 S2

+3VALW +3VS 2 0605


1

3
4

1
ACIN# {44}
D1 6

G
QC15A RPC28
PMC_PLTRST# 2 G1 PJT138K_SOT363-6 10K_0404_4P2R_5% S 2N7002KW_SOT323-3

3
3
4
@
RPC3
2
1
1 S1

10K_0404_4P2R_5%
OPT@
2
1

PJA138K_SOT23-3
PXS_RST# {19}
QC168

D2 3
S

PMC_PCIE_WAKE#
PCIE_WAKE# {37,40,44}
QC16B +3VS
1
3

5 G2 PJT138K_SOT363-6
G

+1.8VALW
2

4 S2

2
D1 6

OPT@ RC956
QC16A 10K_0402_5%
PXS_RST#_SOC 2 G1 PJT138K_SOT363-6 OPT@

1
PXS_PWREN
PXS_PWREN {21,57}
1 S1

OPT@

QC19
A +1.8VALW 1 A
+1.8VALW D
PXS_PWREN#_SOC 2

1
G D
RC170 1 OPT@2 2 QC210
3
4

S {44} VGA_GATE#
0_0402_5% G 2N7002KW_SOT323-3
RPC2 3
1
3
4

10K_0404_4P2R_5% PJA138K_SOT23-3 CC137 OPT@ S

3
RPC4 @ .1U_0402_10V6-K
OPT@
@
2
1

10K_0404_4P2R_5%
2
2
1

PM_SLP_S3#
PM_SLP_S3# {44}
KBRST#
KBRST# {44} PM_SLP_S4#
PM_SLP_S4# {44}

Security Classification LC Future Center Secret Data Title

PBTN_OUT#
Issued Date 2014/09/24 Deciphered Date 2015/03/23 SOC (DDI,EDP)
PBTN_OUT# {44}

www.bios-downloads.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 7 of 60

5 4 3 2 1
5 4 3 2 1

? +1.8VALW
UC1F CHV_MCP_EDS DDR3_M0_DQ_63 RPC18
USB_OC1# 2 3
D D
B48 USB_OC0# 1 4
V1P8 USB_OTG_ID
USB30_TX_P0 B32 C42 USB20_P0
{41} USB30_TX_P0 USB3_TXP0 V1P05A V1P8 USB_DP0 USB20_P0 {41}
{41} USB30_TX_N0 USB30_TX_N0 C32
USB3_TXN0 V1P05A V1P8 USB_DN0
B42 USB20_N0
USB20_N0 {41}
LEFT USB (3.0) 10K_0404_4P2R_5%
LEFT USB (3.0) {41} USB30_RX_P0 USB30_RX_P0
USB30_RX_N0
F28
D28 USB3_RXP0 V1P05A C43 USB20_P1
{41} USB30_RX_N0 USB3_RXN0 V1P05A V1P8 USB_DP1 USB20_P1 {45}
B44 USB20_N1
USB30_CTX_DRX_P2 A33
V1P8 USB_DN1 USB20_N1 {45} RIGHT USB (2.0)
{30} USB30_CTX_DRX_P2
USB30_CTX_DRX_N2 C33 USB3_TXP1 V1P05A C41 USB20_P3
{30} USB30_CTX_DRX_N2 USB3_TXN1 V1P05A V1P8 USB_DP2 USB20_P3 {40}
Cardreader (3.0) {30} USB30_CRX_DTX_P2 USB30_CRX_DTX_P2 F30
USB3_RXP1 V1P05A V1P8 USB_DN2
A41 USB20_N3 USB20_N3 {40} BT
{30} USB30_CRX_DTX_N2 USB30_CRX_DTX_N2 D30
USB3_RXN1 V1P05A

Ju
C45 USB20_P4
V1P8 USB_DP3 USB20_P4 {33}
C34 A45 USB20_N4
B34 USB3_TXP2 V1P05A V1P8 USB_DN3 USB20_N4 {33} Camera
G32 USB3_TXN2 V1P05A B40 USB20_P2
USB3_RXP2 V1P05A V1P8 USB_DP4 USB20_P2 {45}
RIGHT USB (2.0)

USB3.0

USB2.0
J32 C40 USB20_N2
USB3_RXN2 V1P05A V1P8 USB_DN4 USB20_N2 {45}
C35 P16 USB_OC1#

st
USB3_TXP3 V1P05A V1P8 USB_OC1_N USB_OC1# {45}
A35 P14 USB_OC0# USB_OC0# {41}
G34 USB3_TXN3 V1P05A V1P8 USB_OC0_N
J34 USB3_RXP3 V1P05A B46
USB3_RXN3 V1P05A RSVD_B46 B47 USB_VBUSSNS RC16 1 2 0_0402_5%
USB3_RCOMP_DP D34 USB_VBUSSNS A48 USB_RCOMP RC193 1 2 113_0402_1%
USB3_RCOMP_DN F34 USB3_RCOMP_P USB_RCOMP

for
USB3_RCOMP_N M36
V1P2 USB_HSIC_0_STROBE PDG 112.5 ohm
C37 N36 Demo 113 ohm
RSVD_C37 V1P2 USB_HSIC_0_DATA
A37

HSIC
F36 RSVD_A37 K38 SD00001KH00

RESERVED
RSVD_F36 V1P2 USB_HSIC_1_STROBE
D36 M38
RSVD_D36 V1P2 USB_HSIC_1_DATA
M34 N38
RSVD_M34 V1P2 USB_HSIC_RCOMP
M32
RSVD_M32 AD10 UART0_TXD
V1P8 UART1_TXD
USB3_RCOMP_DP C38 AD12 UART0_RXD

LC
C RSVD_C38 V1P8 UART1_RXD C
B38 AD13

UART
RSVD_B38 V1P8 UART1_CTS_B
2

G36 AD14
RSVD_G36 V1P8 UART1_RTS_B only for Win7 debug port
RC192 J36
RSVD_J36 Y6
402_0402_1% V1P8 UART2_TXD
N34 Y7
RSVD_N34 V1P8 UART2_RXD
P34 V9
V1P8 UART2_CTS_N
1

USB3_RCOMP_DN RSVD_P34 V10


V1P8 UART2_RTS_N

FC
+1.8VALW
+1.8VALW
+3VALW
6 OF 13
BRASWELL_FCBGA151170
REV = 1.2 ?

3
4

3
4
RPC31 RPC32

PE
2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5%

G2 5
@ @

2
1

2
1
UART0_TXD 4 S2 D2 3
UART_TX_DEBUG {40}
@
QC11B

2
PJT138K_SOT363-6

G1
De
UART0_RXD 1 S1 D1 6
UART_RX_DEBUG {40}
@
B B
QC11A
PJT138K_SOT363-6

only for Win7 debug port

bu
g
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/09/24 Deciphered Date 2015/03/23 SOC (DDI,EDP)

www.bios-downloads.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 8 of 60
5 4 3 2 1
5 4 3 2 1

?
UC1H CHV_MCP_EDS DDR3_M0_DQ_63
+VNN_1.05VA_S4
+CPU_CORE
7A EDS AA18
AF36 UNCORE_VNN_S4_1 AA19
AG33 CORE_VCC1_3 UNCORE_VNN_S4_2 AA21
AG35 CORE_VCC1_7 UNCORE_VNN_S4_3 AA22
AG36 CORE_VCC1_8 UNCORE_VNN_S4_4 AA24
AG38 CORE_VCC1_9 UNCORE_VNN_S4_5 AA25
AJ33 CORE_VCC1_10 UNCORE_VNN_S4_6 AC18
AJ36 CORE_VCC1_14 UNCORE_VNN_S4_7 AC19
AJ38 CORE_VCC1_15 UNCORE_VNN_S4_8 AC21
CORE_VCC1_16 UNCORE_VNN_S4_9 AC22
AF30 UNCORE_VNN_S4_10 AC24
AG27 CORE_VCC1_2 UNCORE_VNN_S4_11 AC25
AG29 CORE_VCC1_4 UNCORE_VNN_S4_12 AD25 +1.05VA_SOC_G3
AG30 CORE_VCC1_5 UNCORE_VNN_S4_13 AD27
AJ27 CORE_VCC1_6 UNCORE_VNN_S4_14
D D
AJ29 CORE_VCC1_11 AA30
AJ30 CORE_VCC1_12 RSVD_AA30 V33
AF29 CORE_VCC1_13 VCCSRAMSOCIUN_1P056 AA32
CORE_VCC1_1 VCCSRAMSOCIUN_1P051 AA33
+GFX_CORE VCCSRAMSOCIUN_1P052 AA35
AD16 VCCSRAMSOCIUN_1P053 AA36
AD18 DDI_VGG_1 VCCSRAMSOCIUN_1P054 AC32
AD19 DDI_VGG_2 VCCSRAMSOCIUN_1P055 Y30
AF16 DDI_VGG_3 VCCSRAMSOCIUN_1P057 Y32 +1.05VA_ICLK_S4
AF18 DDI_VGG_4 VCCSRAMSOCIUN_1P058 Y33
AF19 DDI_VGG_5 VCCSRAMSOCIUN_1P059 Y35
AF21 DDI_VGG_6 VCCSRAMSOCIUN_1P0510

Ju
AF22 DDI_VGG_7 V19 +1.05VA_DDR_G3

iCLK
AJ19 DDI_VGG_8 ICLK_GND_OFF_2 V18
AG16 DDI_VGG_15 ICLK_GND_OFF_1
AG18 DDI_VGG_9 AM21
AG19 DDI_VGG_10 DDR_V1P05A_G3_1 AM33
AG21 DDI_VGG_11 DDR_V1P05A_G3_4 AM22

DDR
AG22 DDI_VGG_12 DDR_V1P05A_G3_2 AN22
DDI_VGG_13 DDR_V1P05A_G3_5

st
AG24 AN32
AJ21 DDI_VGG_14 DDR_V1P05A_G3_6 AM32
AJ22 DDI_VGG_16 DDR_V1P05A_G3_3
DDI_VGG_17 +1.05VA_MPHY_G3
+1.15VA_SOC_G3 AJ24 V22

PCIe
AK24 DDI_VGG_18 PCIE_V1P05A_G3_1 V24
DDI_VGG_19 PCIE_V1P05A_G3_2
AK30
AK35 CORE_V1P15_1 U24

SATA
for
AK36 CORE_V1P15_2 SATA_V1P05A_G3_2 U22
+1.15VA_FUSE_G3 AM29 CORE_V1P15_3 SATA_V1P05A_G3_1 +1.05VA_SSIC_G3
CORE_V1P15_4
+1.15VA_DDI_G3 V27

FUSE USB
AK33 USB3_V1P05A_G3_2 U27
AJ35 FUSE_V1P15_2 USB3_V1P05A_G3_1 V29
AM19 FUSE_V1P15_1 USBSSIC_V1P05A_G3
AK21 VCCSRAMGEN_1P152 N18
VCCSRAMGEN_1P151 FUSE3_V1P05A_G5 U19
FUSE_V1P05A_G3

LC
C C
8 OF 13
REV = 1.2
BRASWELL_FCBGA151170

+CPU_CORE

1
6.4 A

CC30
4.7U_0402_6.3V6M
1
CC31
4.7U_0402_6.3V6M
1
CC32
4.7U_0402_6.3V6M
1
CC33
4.7U_0402_6.3V6M
1
CC34
4.7U_0402_6.3V6M
1
CC35
4.7U_0402_6.3V6M
FC
+1.05VA

2
@
PJ1
2

JUMP_43X79
Need short

1
1

1
CC55
+VNN_1.05VA_S4

1U_0402_6.3V6K
1
3.5A
CC56
1U_0402_6.3V6K
1
CC57
1U_0402_6.3V6K
1
CC58
1U_0402_6.3V6K
1
CC59
1U_0402_6.3V6K
1
CC60
22U_0805_6.3V6M
1
CC61
22U_0805_6.3V6M
1
CC62
22U_0805_6.3V6M

PE
2 2 2 2 2 2 ?
CD@ 2 2 2 2 2
CD@ 2 2 2
CD@ @
Note:Place CAP Back of CPU Note:Place CAP Back of CPU

Note:Place CAP Back of CPU Note:Place Close of CPU's Edge


+CPU_CORE

+1.05VA
33P_0402_50V8J

+1.05VA_SOC_G3
CC139

1 +1.05VA

De
1 1 1 1 +1.05VA_ICLK_S4
CC36 CC37
22U_0805_6.3V6M 22U_0805_6.3V6M CC38 CC39 1 RC9238 2 0_0603_5%
RF_NS@

22U_0603_6.3V6-M 22U_0603_6.3V6-M 2 1 RC9241 2 0_0603_5%


2 2 2 2
CD@ CD@ @ @ 1 1 1 1 1
B CC63 CC64 CC65 CC66 CC67 B
Note:Place Close of CPU's Edge 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1
CC68
+1.15VA_SOC 2 2 2 2 2 1U_0402_6.3V6K
+1.15VA_SOC_G3
@ @

bu
2
1 RC9243 2 0_0603_5% Note:Place CAP Back of CPU
Note:Place CAP Back of CPU Note:Place Close of CPU's Edge
+GFX_CORE 1 1 1 1 1 1
CC46 CC47 CC48 CC49 CC50 CC51
+1.05VA
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
11A +1.05VA_DDR_G3 +1.05VA
+1.05VA_MPHY_G3

g
2 2 2 2 2 2
33P_0402_50V8J

CD@ CD@ @ @
CC41

1
1 1 1 1 RC9281 2 0_0603_5%
CC138 CC42 1 RC9240 2 0_0603_5%
CC40 4.7U_0402_6.3V6M 4.7U_0402_6.3V6M
22U_0603_6.3V6-M Note:Place CAP Back of CPU Note:Place Close of CPU's Edge
RF_NS@

2 1 1 1 1
2 2 2 CC69 CC70 1 1 1
CC73 CC74 CC75
1U_0402_6.3V6K 1U_0402_6.3V6K CC71 CC72
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
Note:Place CAP Back of CPU 22U_0603_6.3V6-M 22U_0603_6.3V6-M
2 2 2 2
CD@ 2 2 2
CD@

+GFX_CORE
+1.15VA_SOC
+1.15VA_DDI_G3 Note:Place CAP Back of CPU Note:Place Close of CPU's Edge Note:Place CAP Back of CPU

1 1 1 1 RC9244 2 0_0603_5%

CC141 CC44 CC45 +1.05VA


1 1 1 +1.05VA_SSIC_G3
22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M CC52 CC53 CC54
2 2 2
CD@ 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
1 RC9242 2 0_0603_5%
Note:Place CAP Back of CPU 2 2 2
10uF 0402 change to 4.7uF for cost down CD@ @
Note:Place CAP Back of CPU 1 1 1 1 1
CC76 CC77 CC78 CC79 CC80
A 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K A
Note:Place Close of CPU's Edge
2 2 2 2 2
@ @ @

+1.15VA_FUSE_G3 Note:Place CAP Back of CPU Note:Place Close of CPU's Edge


+1.15VA_SOC

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
1 RC9279 2 0_0603_5%

Issued Date 2014/09/24 Deciphered Date 2015/03/23 SOC (Power)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
BMWC1 0.4

Date: Tuesday, April 07, 2015 Sheet 9 of 60


5 4 3 2 1
5 4 3 2 1

?CHV_MCP_EDS
+1.35V_DDRCLK +1.35V_DDR UC1I DDR3_M0_DQ_63
+1.24VA_DP_G3
+1.35V AN27
DDRSFR_VDDQ_G_S4 DDI_VDDQ_G3_1
V36
AM25 Y36
DDR_VDDQ_G_S4_2 DDI_VDDQ_G3_2 +1.24VA_G3
BE1 T40
BE53 DDR_VDDQ_G_S4_16 MIPI_V1P2A_G3_2 P40
BJ2 DDR_VDDQ_G_S4_19 MIPI_V1P2A_G3_1 +1.24VA_SIO_G3
BJ3 DDR_VDDQ_G_S4_26 Y27
BJ49 DDR_VDDQ_G_S4_27 ICLK_VSFR_G3_2 Y25 +1.24VA_PLL_G3
BJ5 DDR_VDDQ_G_S4_28 ICLK_VSFR_G3_1
BH50 DDR_VDDQ_G_S4_29 P38
BH5 DDR_VDDQ_G_S4_25 CORE_VSFR_G3_5 V30

DDR
BH49 DDR_VDDQ_G_S4_24 CORE_VSFR_G3_6 AC30
BH4 DDR_VDDQ_G_S4_23 CORE_VSFR_G3_AC30
BE3 DDR_VDDQ_G_S4_22 +1.24VA_CPUPLL_G3
BG51 DDR_VDDQ_G_S4_17 AF35
BG3 DDR_VDDQ_G_S4_21 CORE_VSFR_G3_4 AD35
D BJ51 DDR_VDDQ_G_S4_20 CORE_VSFR_G3_2 AD38 D
BJ52 DDR_VDDQ_G_S4_30 CORE_VSFR_G3_3 AC36
AY10 DDR_VDDQ_G_S4_31 CORE_VSFR_G3_1
AY44 DDR_VDDQ_G_S4_14 +1.24VA_G3
DDR_VDDQ_G_S4_15
AV44
DDR_VDDQ_G_S4_13 USBHSIC_V1P2A_G3
M41 +1.24VA_USB_G3 +1.24VA_G3
AV10 U35
DDR_VDDQ_G_S4_10 USB_VDDQ_G3_2 +1.24VA_USB2_G3

USB
BE51 V35
AV38 DDR_VDDQ_G_S4_18 USB_VDDQ_G3_3 H44
AV16 DDR_VDDQ_G_S4_12 USB_VDDQ_G3_1 P41 +1.8VALW_USB
AU36 DDR_VDDQ_G_S4_11 USBSSIC_V1P2A_G3
AU18 DDR_VDDQ_G_S4_9 AA29
AN36 DDR_VDDQ_G_S4_8 USB_V1P8A_G3 +3VALW_USB_G3
AN35 DDR_VDDQ_G_S4_7 C23
AN19 DDR_VDDQ_G_S4_6 USB_V3P3A_G3_2 B22 VCCRTC
AN18 DDR_VDDQ_G_S4_5 USB_V3P3A_G3_1
AM36 DDR_VDDQ_G_S4_4 C5
AM18 DDR_VDDQ_G_S4_3 RTC_V3P3RTC_G5_2 B6 +3VALW_RTC

RTC
DDR_VDDQ_G_S4_1 RTC_V3P3RTC_G5_1 D4
VCC_LPC_G3 VCC_SD3_S3 RTC_V3P3A_G5_1
RTC_V3P3A_G5_2
E3
E1
SDIO_V3P3A_V1P8A_G3_1
+1.8VALW_FUSE
+1.5VS_HDA_S3 E2
SDIO_V3P3A_V1P8A_G3_2 +1.05VA_FUSE_G3
G1 U16
+1.8VALW_GPIO_E_G3

Ju
AH4 SDIO_V3P3A_V1P8A_G3_3 FUSE_V1P8A_G3
+1.8VALW_GPIO_G3 AF4 VCCCFIOAZA_1P802 H10
Y18 VCCCFIOAZA_1P801 FUSE1_V1P05A_G4 G10

FUSE
AD33 GPIO_V1P8A_G3_5 FUSE0_V1P05A_G3 A3
AK18 GPIO_V1P8A_G3_1 RSVD_A3 K20
AF33 GPIO_V1P8A_G3_3 RSVD_K20 M20
AK19 GPIO_V1P8A_G3_2 RSVD_M20
GPIO_V1P8A_G3_4

9 OF 13
BRASWELL_FCBGA151170 REV = 1.2

st
C
+1.35V

2
1.9 A

CC81
2.2U_0402_6.3V6M
1

2
CC82
2.2U_0402_6.3V6M
1

2
CC83
2.2U_0402_6.3V6M
1

2
CC84
330P_0402_50V7K
1

2
CC85
22U_0603_6.3V6-M
@
2
1
CC86
22U_0603_6.3V6-M
2
CC87
1

22U_0603_6.3V6-M
@
2
CC88
22U_0603_6.3V6-M
1

?
+1.24VALW

for 1 RC9248 2 0_0603_5%


+1.24VA_DP_G3

1
CC102
+1.24VALW

1
RC898
2 0_0603_5%
+1.24VA_G3

1
CC133
1
CC134
+1.24VALW

1 RC9249 2 0_0603_5%
+1.24VA_SIO_G3

1
C

LC
Note:Place CAP Back of CPU EMC@ Note:Place Close of CPU's Edge 1U_0402_6.3V6K 1U_0402_6.3V6K CC135
1U_0402_6.3V6K
@ 1U_0402_6.3V6K
2 2
2Note:Place CAP Back of CPU Note:Place CAP Back of CPU
2
Note:Place CAP Back of CPU
+1.35V
+1.35V
+1.35V_DDR
+1.35V_DDRCLK
+1.24VALW +1.24VA_PLL_G3
1 RC9246 2 0_0603_5%
1 RC9247 2 0_0603_5% +1.24VALW +1.24VA_CPUPLL_G3 +1.24VA_G3
1 RC9250 2 0_0603_5%
1 1 RC9251
CC89 1 1 1 2 0_0603_5% CAD NOTE:FOR
CC91

FC
1U_0402_6.3V6K CC90 PINS M41 1
1U_0402_6.3V6K CC92 1 1 CC109
22U_0603_6.3V6-M CC136 CC107
2 2 22U_0603_6.3V6-M 1U_0402_6.3V6K
2 2 1U_0402_6.3V6K 1U_0402_6.3V6K 1
@
Note:Place CAP Back of CPU @ CC108 2
Note:Place CAP Back of CPU 2 2 1U_0402_6.3V6K @
Note:Place CAP Back of CPU 2
Note:Place CAP Back of CPU
Note:Place Close of CPU's Edge Note:Place Close of CPU's Edge

+1.24VALW +1.24VA_USB_G3
+1.24VALW +1.24VA_USB2_G3
1
RC9253
2 0_0603_5% +1.24VA_G3
VCC_SD3_S3 +3VALW_SOC VCC_LPC_G3
1 RC9254 2 0_0402_5%
+1.8VALW +1.5VS +1.5VS_HDA_S3 CAD NOTE:FOR
1 RC928 2 0_0402_5% 1 1 PINS P41

PE
1 RC9283 2 0_0402_5% CC110 CC111
1 RC905 2 0_0402_5% 1U_0402_6.3V6K 1U_0402_6.3V6K 1 1
1 RC9278 2 0_0402_5% CC142 CC112 1
1 1 @
@ 2 2 1U_0402_6.3V6K
1U_0402_6.3V6K CC113
CC93 CC94 +1.8VALW 1 1U_0402_6.3V6K
1U_0402_6.3V6K 1U_0402_6.3V6K 1 CC96 Note:Place CAP Back of CPU 2 2
Note:Place CAP Back of CPU
CC95
@ 1U_0402_6.3V6K @ 2
2 2 1U_0402_6.3V6K
CD@
2 Note:Place CAP Back of CPU
Note:Place CAP Back of CPU 2
B B

+1.8VALW +1.8VALW_USB

1 RC9256 2 0_0603_5%
+3VALW_SOC +3VALW_USB_G3

De
1 1
CC114 CC115
+1.8VALW +1.8VALW_GPIO_G3 +1.8VALW +1.8VALW_GPIO_E_G3 1U_0402_6.3V6K 1U_0402_6.3V6K
1 RC9257 2 0_0603_5%
VCCRTC +3VALW_SOC +3VALW_RTC
2 2
1 RC924 2 0_0603_5% CD@
1 RC925 2 0_0402_5% Note:Place CAP Back of CPU 1 RC9282 2 0_0402_5%
1
1 1 CC116
CC97 CC98 1U_0402_6.3V6K 1
1 1 1 1 CC118
1U_0402_6.3V6K 1U_0402_6.3V6K
CC99 CC100 CC101 2 CC117 .1U_0402_10V6-K
@
2 2 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K .1U_0402_10V6-K
@ 2
2 2 2 2 @
CD@

bu
Note:Place CAP Back of CPU

+1.8VALW +1.8VALW_FUSE
+1.05VA +1.05VA_FUSE_G3
1 RC9258 2 0_0402_5%
1 RC9259 2 0_0402_5%

1
CC119
1U_0402_6.3V6K 1

g
+3VALW +3VALW CC120
+3VALW 2 Note:Place CAP Back of CPU 1U_0402_6.3V6K
2
@
@
2

RW128
10K_0402_5%
2

@
3

S
RW127
1

G
10K_0402_5% SD_1P8_SEL_3.3V_EN 2 1 RW130 CW24 2 QW14
10K_0402_5% LP2301ALT1G_SOT23-3
0.1U_0402_10V7K

@ D
1
1

@ @
D2 3

QW12B 2
A SD_1P8_SEL_1.8V_EN 5 G2 A
PJT138K_SOT363-6
VCC_SD3_S3
4 S2
D1 6

@
QW12A
SD_1P8_SEL 2 G1 PJT138K_SOT363-6
{4} SD_1P8_SEL
1 S1

@
3

S
G
SD_1P8_SEL_1.8V_EN 2 1 RW129 CW23 2 QW2
10K_0402_5% LP2301ALT1G_SOT23-3
0.1U_0402_10V7K

@ D
1
1

Security Classification LC Future Center Secret Data Title


@
2
Issued Date 2014/09/24 Deciphered Date 2015/03/23 SOC (Power2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
+1.8VALW D 0.4
Note:Intel PAG1.2 recommend E1,E2 not empty even unused DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 10 of 60
5 4 3 2 1

www.bios-downloads.com
5 4 3 2 1

? ?
UC1JCHV_MCP_EDS DDR3_M0_DQ_63 CHV_MCP_EDS
UC1K DDR3_M0_DQ_63
Power-VSS Power-VSS

AN3 AF38 AN21 AY9


AN29 VSS_107 VSS_55 AF32 BG30 VSS_103 VSS_166 AY28
AN25 VSS_106 VSS_54 AF25 BG27 VSS_213 VSS_157 AY26
AN24 VSS_105 VSS_53 AF10 BG24 VSS_212 VSS_156 AY24
AN16 VSS_104 VSS_51 AE9 BG20 VSS_211 VSS_155 AY22
AN14 VSS_102 VSS_50 AE8 BG19 VSS_210 VSS_154 AY20
AN12 VSS_101 VSS_49 AE6 BG18 VSS_209 VSS_153 AW35
AN11 VSS_100 VSS_48 AE53 BG16 VSS_208 VSS_151 AW27
AN1 VSS_99 VSS_47 AE50 BG14 VSS_207 VSS_150 AW19
AM50 VSS_98 VSS_46 AE48 BF42 VSS_206 VSS_149 AM13
D
AM42 VSS_97 VSS_45 AE46 BF32 VSS_203 VSS_88 AK29 D
AM4 VSS_96 VSS_44 AE45 BF28 VSS_201 VSS_78 AK22
AM38 VSS_95 VSS_43 AE43 BF27 VSS_200 VSS_75 AV40
AM35 VSS_94 VSS_42 AE42 BF26 VSS_199 VSS_147 AV35
AH44 VSS_93 VSS_41 AE40 BF22 VSS_198 VSS_146 AV30
AM30 VSS_64 VSS_40 AE14 BF12 VSS_197 VSS_145 AV27
AM27 VSS_92 VSS_39 AE12 BE35 VSS_196 VSS_144 AV24
U25 VSS_91 VSS_38 AE11 BE19 VSS_195 VSS_143 AV19
P10 VSS_335 VSS_37 AE1 C20 VSS_194 VSS_142 AV14
AM16 VSS_317 VSS_36 AD44 BD53 VSS_240 VSS_141 AJ18
AD4 VSS_89 VSS_35 AD36 BG7 VSS_193 VSS_69 AU53
AK7 VSS_34 VSS_33 AC29 BD35 VSS_223 VSS_140 AU51
VSS_87 VSS_26 VSS_192 VSS_139

Ju
AK50 AD32 BD27 AU3
AK47 VSS_86 VSS_32 AD30 BD19 VSS_191 VSS_138 AU1
AK45 VSS_85 VSS_31 AD21 BD1 VSS_190 VSS_137 AT9
AK44 VSS_84 VSS_30 AC38 BC44 VSS_189 VSS_136 AT51
AK40 VSS_83 VSS_29 AC35 BC40 VSS_188 VSS_135 AT45
AK4 VSS_82 VSS_28 AC33 BC38 VSS_187 VSS_134 AT36
AK38 VSS_81 VSS_27 AC16 BC28 VSS_186 VSS_133 AT35
AK32 VSS_80 VSS_25 AB6 BC26 VSS_185 VSS_132 AT3

st
AK27 VSS_79 VSS_24 AB50 BC16 VSS_184 VSS_131 AT27
AK25 VSS_77 VSS_23 AB47 BC14 VSS_183 VSS_130 AT19
AM24 VSS_76 VSS_22 AB42 BC10 VSS_182 VSS_129 AT18
AK16 VSS_90 VSS_21 AB4 BB35 VSS_181 VSS_128 AP9
AJ53 VSS_74 VSS_20 AB14 BB27 VSS_178 VSS_127 AP50
AJ51 VSS_73 VSS_19 AB13 BB19 VSS_177 VSS_126 AP45
AJ3 VSS_72 VSS_18 AB12 BA35 VSS_176 VSS_125 AP4
VSS_71 VSS_17 VSS_175 VSS_124

for
AJ25 AB10 BA30 AN9
AJ16 VSS_70 VSS_16 AA53 BA27 VSS_174 VSS_123 AN8
AJ1 VSS_68 VSS_15 AA38 BA24 VSS_173 VSS_122 AN6
AH9 VSS_67 VSS_14 AA27 BA19 VSS_172 VSS_121 AN53
AH47 VSS_66 VSS_13 AA16 B36 VSS_171 VSS_120 AN51
AH42 VSS_65 VSS_12 A47 B28 VSS_169 VSS_119 AN5
AH41 VSS_63 VSS_8 A43 AY7 VSS_168 VSS_118 AN49
AH14 VSS_62 VSS_7 A39 AY51 VSS_165 VSS_117 AN48
AH13 VSS_61 VSS_6 A31 AY47 VSS_164 VSS_116 AN46
AH12 VSS_60 VSS_5 A23 AY34 VSS_163 VSS_115 AN45
AH10 VSS_59 VSS_4 A19 AY32 VSS_161 VSS_114 AN43

LC
C C
AG25 VSS_58 VSS_3 A15 AY30 VSS_160 VSS_113 AN42
AF47 VSS_57 VSS_2 A11 AY3 VSS_159 VSS_112 AN40
VSS_56 VSS_1 AN30 VSS_158 VSS_111 AN38
10 OF 13 AY45 VSS_108 VSS_110
BRASWELL_FCBGA151170 VSS_162
REV = 1.2
? 11 OF 13
?
BRASWELL_FCBGA151170

FC
REV = 1.2

?
UC1LCHV_MCP_EDS DDR3_M0_DQ_63
Power-VSS

AN33 Y24 CHV_MCP_EDS ?


P32 VSS_109 VSS_369 G30 UC1M DDR3_M0_DQ_63
P27 VSS_321 VSS_272 G28 Power-VSS
VSS_320 VSS_271 F1 W1
P22 G26 VSS_NCTF_F1 VSS_362

PE
VSS_319 VSS_270 C1 V44
P19 G22 VSS_NCTF_C1 VSS_361
VSS_318 VSS_269 BH53 V42
AF24 G14 VSS_NCTF_BH53VSS_360
VSS_52 VSS_268 BH52 V41
N53 G12 VSS_NVTF_BH52VSS_359
VSS_316 VSS_267 BH2 V38
N51 F5 VSS_NCTF_BH2 VSS_358
VSS_315 VSS_266 BH1
N32 F35 VSS_NCTF_BH1
VSS_314 VSS_265 BG53 V32
N24 F32 VSS_NCTF_BG53VSS_357
VSS_313 VSS_264 BG1 V21
N22 F27 VSS_NCTF_BG1 VSS_355
VSS_312 VSS_263 B52 V16
M9 F24 VSS_NCTF_B52 VSS_354
VSS_311 VSS_262 B2 U9
F19 VSS_NCTF_B2 VSS_353
VSS_261 U8
K45 E51 VSS_352
VSS_296 VSS_259 A6 U6
M40 E35 VSS_NCTF_A6 VSS_351
VSS_308 VSS_257 A5 U53

De
M35 E19 VSS_NCTF_A5 VSS_350
VSS_307 VSS_256 U5
M27 D42 VSS_349
VSS_306 VSS_255 M24 U49
AW13 D40 VSSA VSS_348
VSS_148 VSS_254 A7 U48
M19 D38 VSS_11 VSS_347
VSS_304 VSS_253 BF50 U46
M14 D32 VSS_204 VSS_346
VSS_303 VSS_252 BF4 U45
B L35 D27 VSS_202 VSS_345 B
VSS_301 VSS_251 BB50 U43
L27 D24 VSS_180 VSS_344
VSS_300 VSS_250 U42
L19 D16 VSS_343
VSS_299 VSS_249 BB4 U40
L1 D10 VSS_179 VSS_342
VSS_298 VSS_248 U38

bu
K50 J42 VSS_341
VSS_297 VSS_284 BG47
T47 C47 VSS_219
VSS_328 VSS_247 Y9 U33
K4 C39 VSS_376 VSS_339
VSS_295 VSS_246 Y50 U32
K36 C36 VSS_375 VSS_338
VSS_294 VSS_245 Y45 U30
K34 C30 VSS_374 VSS_337
VSS_293 VSS_244 Y40 U29
K32 C3 VSS_373 VSS_336
VSS_292 VSS_243 Y4
K30 C28 VSS_372
VSS_291 VSS_242 Y38 U21
K24 C22 VSS_371 VSS_334
VSS_290 VSS_241 Y29 U18

g
K22 AW41 VSS_370 VSS_333
VSS_289 VSS_152 Y22 U36
K16 BJ7 VSS_368 VSS_340
VSS_288 VSS_238 Y21 U14
K14 BJ47 VSS_367 VSS_332
VSS_287 VSS_237 Y19 U12
K12 BJ43 VSS_366 VSS_331
VSS_286 VSS_236 Y16 U11
J53 BJ39 VSS_365 VSS_330
VSS_285 VSS_235 Y14 T9
M45 BJ35 VSS_364 VSS_329
VSS_309 VSS_234 Y10 P42
J38 BJ31 VSS_363 VSS_325
VSS_283 VSS_233 T14
J35 BJ27 VSS_327
VSS_282 VSS_232 P4 R1
J30 BJ23 VSS_324 VSS_326
VSS_281 VSS_231 L41
J27 BJ19 VSS_302
VSS_280 VSS_230 P36 P35
J22 BJ15 VSS_323 VSS_322
J19 VSS_279 VSS_229 BJ11
J18 VSS_278 VSS_228 BG5
H8 VSS_277 VSS_221 BG49
E46 VSS_276 VSS_220 BG40
H35 VSS_258 VSS_218 BG38
H27 VSS_275 VSS_217 BG36 13 OF 13
H19 VSS_274 VSS_216 BG35 BRASWELL_FCBGA151170
M50 VSS_273 VSS_215 BG34 REV = 1.2
V25 VSS_310 VSS_214
VSS_356

12 OF 13
BRASWELL_FCBGA151170
REV = 1.2 ?
A A

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 SOC (VSS)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 11 of 60
5 4 3 2 1
5 4 3 2 1

Hardware STRAPS
(Follow up CRB) +1.8VALW

+1.8VALW

D D

2
RC9263 RC9264 RC9266 RC9265 RC9267
10K_0402_1% 10K_0402_1% 10K_0402_1% 4.7K_0402_5% 1K_0402_1%
@
2

2
@ @ @
RC9273 RC9274 RC9275 RC46 RC9276

1
100K_0402_5% 100K_0402_5% 10K_0402_1% 4.7K_0402_5% 4.7K_0402_5%

@
1

1
GPIO_SUS_9 {7}

Ju
GPIO_SUS_6
EC_SCI# {7,44}
GPIO_SUS_0 {7}
GPIO_CAM_8 {4}
GPIO_SUS_1 {7}
GPIO_CAM_9 {4}

st
GPIO_SUS_2 {7}
GPIO_CAM_11 {4}
GPIO_SUS_4 {7}

C GPIO_SUS_5 {7} C

for
GPIO_SUS_8 {7}

2
2
RC9268 RC9270 RC9271
100K_0402_5% RC9262 100K_0402_5% 10K_0402_1%
2

100K_0402_5%
@

1
RC9277 RC49 RC51
4.7K_0402_5% 10K_0402_1% 10K_0402_1%

1
@ @

LC
1

B
FC B

PE
GPIO_SUS_5
0606

2
RC961
4.7K_0402_1%
1

De
1

D QC214 RC962
2

2 1 2
G PCH_ME_PROTECT {44}
ME2
SHORT PADS 0_0402_5%
1

S 2N7002KW_SOT323-3
3

bu A

g
Security Classification LC Future Center Secret Data Title
Issued Date 2014/09/24 Deciphered Date 2015/03/23 SOC (STRAPS & OTHERS)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 12 of 60
5 4 3 2 1

www.bios-downloads.com
5 4 3 2 1

D D

Ju
st
C
for C

LC
FC
B
PE B

De
bu
g
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/09/24 Deciphered Date 2015/03/23 MCP (OTHER)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 13 of 60
5 4 3 2 1

www.bios-downloads.com
5 4 3 2 1

DDR Mapping table DDR3 SO-DIMM A


DDRA_DQ[0..63] {5}
DDRA_DQ6---DQ0
DDRA_DQ1---DQ1 +1.35V +1.35V
DDRA_DQS[0..7] {5}
DDRA_DQ4---DQ2
DDRA_DQ2---DQ3 DDRA_DQS#[0..7] {5}
DDRA_DQ3---DQ4
DDRA_DQ0---DQ5 3A@1.5V DDRA_MA[0..15] {5}
DDRA_DQ7---DQ6 For RF request
JDDR1
DDRA_DQ5---DQ7 1 2 DDRA_DM[7:0] {5}
DDR_DQ
D 3 VREF_DQ VSS_2 4 DDRA_DQ3 D

CD4

CD5

CD6
VSS_1 DQ4

.1U_0402_10V6-K

22P_0402_50V8-J

22P_0402_50V8-J

22P_0402_50V8-J
DDRA_DQ9----DQ8 DDRA_DQ6 5 6 DDRA_DQ0
DDRA_DQ1 7 DQ0 DQ5 8
DDRA_DQ12---DQ9 1 DQ1 VSS_4 1 1 1
DDRA_DQ11---DQ10 CD3 9 10 DDRA_DQS#0
DDRA_DM0 11 VSS_3 DQS0# 12 DDRA_DQS0
DDRA_DQ14---DQ11 DM0 DQS0
13 14
DDRA_DQ8----DQ12 2 DDRA_DQ4 15 VSS_5 VSS_6 16 DDRA_DQ7 2 2 2
DDRA_DQ13---DQ13 DDRA_DQ2 17 DQ2 DQ6 18 DDRA_DQ5
DDRA_DQ15---DQ14 19 DQ3 DQ7 20
DDRA_DQ10---DQ15 DDRA_DQ9 21 VSS_7 VSS_8 22 DDRA_DQ8 RF@ RF@ RF@
DDRA_DQ12 23 DQ8 DQ12 24 DDRA_DQ13

Ju
25 DQ9 DQ13 26
DDRA_DQ20---DQ16 VSS_9 VSS_10
DDRA_DQ16---DQ17 DDRA_DQS#1 27 28 DDRA_DM1
DDRA_DQS1 29 DQS1# DM1 30
DDRA_DQ17---DQ18
DDRA_DQ23---DQ19 31 DQS1 RESET# 32 DDRA_DRAMRST# {5} OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
DDRA_DQ11 33 VSS_11 VSS_12 34 DDRA_DQ15
DDRA_DQ19---DQ20 DDRA_DQ14 35 DQ10 DQ14 36 DDRA_DQ10
DDRA_DQ21---DQ21

st
37 DQ11 DQ15 38
DDRA_DQ22---DQ22 DDRA_DQ20 39 VSS_13 VSS_14 40 DDRA_DQ19
DDRA_DQ18---DQ23 DQ16 DQ20 Layout Note:
DDRA_DQ16 41 42 DDRA_DQ21
43 DQ17 DQ21 44 Place near DIMM (10uF_0603_6.3V)*8
DDRA_DQS#2 45 VSS_15 VSS_16 46 DDRA_DM2
DDRA_DQ28---DQ24 DQS2# DM2 (0.1uF_402_10V)*4
DDRA_DQ25---DQ25 DDRA_DQS2 47 48
49 DQS2 VSS_18 50 DDRA_DQ22

for
DDRA_DQ29---DQ26 VSS_17 DQ22
DDRA_DQ24---DQ27 DDRA_DQ17 51 52 DDRA_DQ18
DDRA_DQ23 53 DQ18 DQ23 54
DDRA_DQ27---DQ28 55 DQ19 VSS_20 56 DDRA_DQ27
DDRA_DQ30---DQ29 DDRA_DQ28 57 VSS_19 DQ28 58 DDRA_DQ30 +1.35V
DDRA_DQ26---DQ30 DDRA_DQ25 59 DQ24 DQ29 60
DDRA_DQ31---DQ31 61 DQ25 VSS_22 62 DDRA_DQS#3
DDRA_DM3 63 VSS_21 DQS3# 64 DDRA_DQS3
DM3 DQS3

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
DDRA_DQ32---DQ32 65 66 1
VSS_23 VSS_24

LC
C DDRA_DQ29 67 68 DDRA_DQ26 CD7 1 CD8 1 CD9 1 CD10 CD11 CD12 CD13 CD14 CD15 CD16 CD17 CD18 C
DDRA_DQ33---DQ33 DQ26 DQ30 1 1 1 1 1 1 1 1 1
DDRA_DQ24 69 70 DDRA_DQ31 + CD19
DDRA_DQ39---DQ34 DQ27 DQ31
71 72 220U_6.3V_M
DDRA_DQ34---DQ35 VSS_25 VSS_26
DDRA_DQ37---DQ36 2 2 2 2 2 2 2 2 2 2 2 2 2
DDRA_DQ36---DQ37 DDRA_CKE0 73 74 DDRA_CKE1 @
DDRA_DQ38---DQ38 {5} DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 {5}
75 76
DDRA_DQ35---DQ39 77 VDD_1 VDD_2 78 DDRA_MA15 @ @
NC_1 A15

FC
DDRA_BS2# 79 80 DDRA_MA14
{5} DDRA_BS2# BA2 A14
DDRA_DQ40---DQ40 81 82
DDRA_MA12 83 VDD_3 VDD_4 84 DDRA_MA11
DDRA_DQ45---DQ41 A12/BC# A11
DDRA_DQ42---DQ42 DDRA_MA9 85 86 DDRA_MA7
87 A9 A7 88
DDRA_DQ43---DQ43 VDD_5 VDD_6
DDRA_MA8 89 90 DDRA_MA6
DDRA_DQ44---DQ44 DDRA_MA5 91 A8 A6 92 DDRA_MA4
DDRA_DQ41---DQ45 93 A5 A4 94
DDRA_DQ47---DQ46 DDRA_MA3 95 VDD_7 VDD_8 96 DDRA_MA2 +1.35V
DDRA_DQ46---DQ47 DDRA_MA1 97 A3 A2 98 DDRA_MA0 +1.35V

PE
99 A1 A0 100
DDRA_CLK0 101 VDD_9 VDD_10 102 DDRA_CLK1
DDRA_DQ48---DQ48 {5} DDRA_CLK0 CK0 CK1 DDRA_CLK1 {5} RPD2
DDRA_DQ51---DQ49 DDRA_CLK0# 103 104 DDRA_CLK1#

CD75

330P_0402_50V7K

CD76

330P_0402_50V7K

CD73

330P_0402_50V7K

CD74

330P_0402_50V7K

CD71

330P_0402_50V7K

CD72

330P_0402_50V7K
{5} DDRA_CLK0# CK0# CK1# DDRA_CLK1# {5} 1 4 RD6
DDRA_DQ53---DQ50 105 106
VDD_11 VDD_12 2 3 1 2 DDR_CA
DDRA_DQ49---DQ51 DDRA_MA10 107 108 DDRA_BS1# 1 1 1 1 1 1
DDRA_BS0# 109 A10/AP BA1 110 DDRA_RAS# DDRA_BS1# {5}
DDRA_DQ55---DQ52 {5} DDRA_BS0#
111 BA0 RAS# 112 DDRA_RAS# {5} 4.7K_0404_4P2R_1%
0_0402_5%
DDRA_DQ50---DQ53 DDRA_WE# 113 VDD_13 VDD_14 114 DDRA_CS0#
DDRA_DQ52---DQ54 {5} DDRA_WE# WE# S0# DDRA_CS0# {5} 2 2 2 2 2 2
DDRA_CAS# 115 116 DDRA_ODT0
DDRA_DQ54---DQ55 {5} DDRA_CAS# CAS# ODT0 DDRA_ODT0 {5}
117 118

De
DDRA_MA13 119 VDD_15 VDD_16 120 DDRA_ODT1 +1.35V
DDRA_CS1# 121 A13 ODT1 122 DDRA_ODT1 {5} EMC@ EMC@ EMC@ EMC@ EMC@ EMC@
DDRA_DQ60---DQ56 {5} DDRA_CS1# S1# NC_2
DDRA_DQ61---DQ57 123 124
125 VDD_17 VDD_18 126 DDR_CA
B
DDRA_DQ63---DQ58 TEST VREF_CA RPD1 B
DDRA_DQ62---DQ59 127 128
VSS_27 VSS_28 1 4 RD5
.1U_0402_10V6-K

DDRA_DQ32 129 130 DDRA_DQ37


DDRA_DQ56---DQ60 DDRA_DQ33 131 DQ32 DQ36 132 DDRA_DQ36
2 3 1 2 DDR_DQ
DDRA_DQ57---DQ61 DQ33 DQ37 1
CD21

133 134

bu
DDRA_DQ58---DQ62 DDRA_DQS#4 135 VSS_29 VSS_30 136 DDRA_DM4 4.7K_0404_4P2R_1%0_0402_5%
DDRA_DQ59---DQ63 DDRA_DQS4 137 DQS4# DM4 138
139 DQS4 VSS_32 140 DDRA_DQ38 2
DDRA_DQ39 141 VSS_31 DQ38 142 DDRA_DQ35
DDRA_DQ34 143 DQ34 DQ39 144
145 DQ35 VSS_34 146 DDRA_DQ44
VSS_33 DQ44

g
DDRA_DQ40 147 148 DDRA_DQ41
DDRA_DQ45 149 DQ40 DQ45 150
151 DQ41 VSS_35 152 DDRA_DQS#5
DDRA_DM5 153 VSS_36 DQS5# 154 DDRA_DQS5
DM5 DQS5 Layout Note:
155 156
DDRA_DQ42 157 VSS_37 VSS_38 158 DDRA_DQ47 Place near DIMM
DDRA_DQ43 159 DQ42 DQ46 160 DDRA_DQ46
161 DQ43 DQ47 162 +1.35V
DDRA_DQ48 163 VSS_39 VSS_40 164 DDRA_DQ55
DDRA_DQ51 165 DQ48 DQ52 166 DDRA_DQ50 +0.675VS
167 DQ49 DQ53 168
VSS_41 VSS_42

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
DDRA_DQS#6 169 170 DDRA_DM6
DQS6# DM6

CD64

CD65
DDRA_DQS6 171 172 CD68 1 CD69 1 CD66 1 CD67 1
RD10 1 2 0_0402_5% SA0 173 DQS6 VSS_44 174 DDRA_DQ52

CD70
VSS_43 DQ54

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

10U_0603_6.3V6M

10U_0603_6.3V6M

22P_0402_50V8-J
RD11 1 2 0_0402_5% SA1 DDRA_DQ53 175 176 DDRA_DQ54
DDRA_DQ49 177 DQ50 DQ55 178 CD24 1 CD25 CD26
DQ51 VSS_46 2 2 2 2 1 1 1 1 1 1
179 180 DDRA_DQ56 CD23
DDRA_DQ60 181 VSS_45 DQ60 182 DDRA_DQ57 1U_0402_6.3V6K
DDRA_DQ61 183 DQ56 DQ61 184
185 DQ57 VSS_48 186 DDRA_DQS#7 @ @ @ @ 2 2 2 2 2 2 2
DDRA_DM7 187 VSS_47 DQS7# 188 DDRA_DQS7
189 DM7 DQS7 190
A DDRA_DQ63 191 VSS_49 VSS_50 192 DDRA_DQ58 @ @ @ @ RF@ A
DQ58 DQ62 cost down bom to change 0.1uF
DDRA_DQ62 193 194 DDRA_DQ59 For RF request
195 DQ59 DQ63 196
SA0 197 VSS_51 VSS_52 198
199 SA0 EVENT# 200
+3VS SA1 201 VDDSPD SDA 202 SMB_DATA_S3 {7,40}
203 SA1 SCL 204 SMB_CLK_S3 {7,40}
1 1 VTT_1 VTT_2 +0.675VS
Security Classification LC Future Center Secret Data Title
CD27 CD28 205
GND1 GND2
206 0.65A@0.75V
2.2U_0603_6.3V6K .1U_0402_10V6-K 207 208

www.bios-downloads.com
2 2 BOSS1 BOSS2 Issued Date 2014/09/24 Deciphered Date 2015/03/23 DDRIII SO-DIMM A
@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
LCN_DAN06-K4406-0103 Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
ME@ Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 14 of 60
5 4 3 2 1
5 4 3 2 1

Swap Table
Pin
Number Pin Name Net Name
5 DQ0 DDRB_DQ17
7 DQ1 DDRB_DQ23
15 DQ2 DDRB_DQ18
17 DQ3 DDRB_DQ21
4 DQ4 DDRB_DQ16
6 DQ5 DDRB_DQ22
D
16 DQ6 DDRB_DQ19 D
18 DQ7 DDRB_DQ20
10 DQS#0 DDRB_DQS#2
12 DQS0 DDRB_DQS2
21 DQ8 DDRB_DQ3
23 DQ9 DDRB_DQ5
33 DQ10 DDRB_DQ6
35 DQ11 DDRB_DQ1
22 DQ12 DDRB_DQ2

Ju
24 DQ13 DDRB_DQ4
34 DQ14 DDRB_DQ0
36 DQ15 DDRB_DQ7
27 DQS#1 DDRB_DQS#0
29 DQS1 DDRB_DQS0

st
39 DQ16 DDRB_DQ8
41 DQ17 DDRB_DQ10
51 DQ18 DDRB_DQ14
53 DQ19 DDRB_DQ15
40 DQ20 DDRB_DQ13

for
42 DQ21 DDRB_DQ12
50 DQ22 DDRB_DQ9
52 DQ23 DDRB_DQ11
45 DQS#2 DDRB_DQS#1
47 DQS2 DDRB_DQS1
57 DQ24 DDRB_DQ27

LC
C C
59 DQ25 DDRB_DQ26
67 DQ26 DDRB_DQ28
69 DQ27 DDRB_DQ24
56 DQ28 DDRB_DQ31
58 DQ29 DDRB_DQ30
68 DQ30 DDRB_DQ29
70 DQ31 DDRB_DQ25

FC
62 DQS#3 DDRB_DQS#3
64 DQS3 DDRB_DQS3
129 DQ32 DDRB_DQ33
131 DQ33 DDRB_DQ36
141 DQ34 DDRB_DQ39
143 DQ35 DDRB_DQ38
130 DQ36 DDRB_DQ37

PE
132 DQ37 DDRB_DQ32
140 DQ38 DDRB_DQ35
142 DQ39 DDRB_DQ34
135 DQS#4 DDRB_DQS#4
137 DQS4 DDRB_DQS4
147 DQ40 DDRB_DQ40
149 DQ41 DDRB_DQ43
157 DQ42 DDRB_DQ42

De
159 DQ43 DDRB_DQ44
146 DQ44 DDRB_DQ45
148 DQ45 DDRB_DQ41
B B
158 DQ46 DDRB_DQ46
160 DQ47 DDRB_DQ47
152 DQS#5 DDRB_DQS#5

bu
154 DQS5 DDRB_DQS5
163 DQ48 DDRB_DQ52
165 DQ49 DDRB_DQ51
175 DQ50 DDRB_DQ50
177 DQ51 DDRB_DQ48

g
164 DQ52 DDRB_DQ49
166 DQ53 DDRB_DQ53
174 DQ54 DDRB_DQ54
176 DQ55 DDRB_DQ55
169 DQS#6 DDRB_DQS#6
171 DQS6 DDRB_DQS6
181 DQ56 DDRB_DQ62
183 DQ57 DDRB_DQ57
191 DQ58 DDRB_DQ59
193 DQ59 DDRB_DQ63
180 DQ60 DDRB_DQ56
182 DQ61 DDRB_DQ61
192 DQ62 DDRB_DQ58
194 DQ63 DDRB_DQ60
186 DQS#7 DDRB_DQS#7
188 DQS7 DDRB_DQS7
A A

0.65A@0.75V

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 DDRIII SO-DIMM B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 15 of 59
5 4 3 2 1
5 4 3 2 1

D D

Ju
st
C

for C

LC
FC
B
PE B

De
bu
A
g A

Security Classification LC Future Center Secret Data Title


Issued Date 2014/09/24 Deciphered Date 2015/03/23 USB Hub GL850G-OHY31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 16 of 60
5 4 3 2 1

www.bios-downloads.com
5 4 3 2 1

3437:SA000078V00;3436:SA000078X00

RTC_VCC

D D
1

RG11 UG1
330_0402_5% +3VALW
+3VL 15 14 CG3 1 2 GCLK@
GCLK@ V3.3A VOUT
2
VDD 2.2U_0402_6.3V6M
2

10
VRTC
1 9
32.768K RTC_CLK {7}
CG9 11 6 1 RG1 2 0_0402_5% +1.05VA
27M_VIOE CLK_19.2M
22U_0603_6.3V6-M VIOE_27M 19.2M 19.2M_CLK {7}
2 GCLK@ RG101 2 0_0402_5% 19.2M_VIOE
GCLK@ 19.2M_VIOE 8 12 CLK_27M 1 RG4 2 22_0402_5%
VIOE_19.2M 27M 27M_CLK {19}
27M@ 1

Ju
25M_VIOE 3 4 CLK_25M 1 RG3 2 33_0402_5%
VIO_25M 25M 25M_CLK {37}
GCLK@ CG8
GCLK_XTALI 1 .1U_0402_10V6-K
GCLK_XTALO 16 X1 2
X2 GCLK@

GND1
GND2
GND3

GND4
st
C C
@
5
7
13

17
SLG3NB3437VTR_TQFN16_2X3
+3VL
+3VALW

for
RG5 1 2 0_0402_5%
1 +3VG_AON @
RG6 1 2 0_0402_5% 27M_VIOE
CG5
27M@
.1U_0402_10V6-K
2
GCLK@
1
GCLK_XTALI
CG10

LC
YG1
GCLK@ GCLK_XTALO .1U_0402_10V6-K
2
3 2 27M@
OSC2 GND1
4 1
GND2 OSC1
+3VALW
1 1 +3VALW

FC
B 25MHZ_10PF_7V25000014 B
CG1 CG2 RG7 1 2 0_0402_5%
15P_0402_50V8J 15P_0402_50V8J +3VS GCLK@
2 GCLK@ 2 GCLK@
1 RG8 1 2 0_0402_5% 25M_VIOE
@
CG4
.1U_0402_10V6-K
2 1
GCLK@
CG11

PE
.1U_0402_10V6-K
2
GCLK@

EMC_NS@
CLK_25M CG12 1 2 6P_0402_50V8D

EMC_NS@

De
27M_CLK CG13 1 2 6P_0402_50V8D

A A

Security Classification LC Future Center Secret Data Title


CLK_19.2M CG15 1 2 4.7P_0402_50V8-J Issued Date 2014/09/24 Deciphered Date 2015/03/23 Blank

bu
EMC@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
For EMC Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 17 of 60
5 4 3 2 1

www.bios-downloads.com
5 4 3 2 1

N15x GPIO
Performance Mode P0 TDP at Tj = 102 C* (DDR3)
GPIO I/O ACTIVE Function Description
FBVDDQ PCI Express I/O and Other
GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD
GPIO0 OUT - FB Enable for GC6 2.0 (4) (1,5) /MCLK NVVDD (1.35V) (1.35V) (6) (1.05V) (3.3V)
Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W)
D GPIO1 OUT N/A D

N14X
GPIO2 OUT N/A 128bit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
2GB
DDR3
GPIO3 OUT N/A

GPIO4 OUT N/A

GPIO5 OUT N/A GPU power sequencing---3V3_MAIN_EN

GPIO6

GPIO7
IN

OUT
-

N/A

Ju
GPU wake signal for GC6 2.0

st
GPIO8 I/O - System side PCIe reset Monitor

GPIO9 I/O N/A 2.2K Pull-up


N15x Multi-level Straps
GPIO10 OUT N/A

GPIO11

GPIO12

GPIO13
OUT

IN

OUT
-

-
GPU Core VDD PWM control signal

AC Power Detect Input

Phase Shedding for (10K pull High)


Physical
Strapping pin
ROM_SCLK
Power Rail
+3VGS
Logical
Strapping Bit3
SOR3_EXPOSED
Logical
Strapping Bit2
SOR2_EXPOSED
Logical
Strapping Bit1
SOR1_EXPOSED
Logical
Strapping Bit0
SOR0_EXPOSED

LC
C C
GPIO14 IN N/A
ROM_SI +3VGS RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
GPIO15 IN N/A ROM_SO +3VGS DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE
STRAP0 +3VGS Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
GPIO16 N/A
STRAP1 +3VGS

FC
GPIO17 IN N/A STRAP2 +3VGS
Reserved(keep pull-up and pull-down footprint and not stuff by default)
STRAP3 +3VGS
GPIO18 IN N/A
STRAP4 +3VGS
GPIO19 IN N/A

GPIO20 N/A SMBUS_ALT_ADDR

PE
GPIO21 OUT GPU PCIe self-reset control 0 0x9E (Default)

OVERT OUT Active Low Thermal Catastrophic Over Temperature 1 0x9C (Multi-GPU usage)

N15V-GM Power Sequence

+3VG_AON Other Power rail


N15x Binary Straps
De B

bu
+VGA_CORE
+3VG_AON
Physical
tNVVDD >0
Strapping pin Power Rail Strap Mapping
+1.35VGS
Tpower-off <10ms ROM_SCLK +3VGS SMB_ALT_ADDR
tFBVDDQ >0

g
ROM_SI +3VGS SUB_VENDOR
+1.05VS_VGA
ROM_SO +3VGS VGA_DEVICE
tPEX_VDD >0
STRAP0 +3VGS RAM_CFG[0]
1.all GPU power rails should be turned off within 10ms STRAP1 +3VGS RAM_CFG[1]
1. all power rail ramp up time should be larger than 40us 2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
STRAP2 +3VGS RAM_CFG[2]
STRAP3 +3VGS RAM_CFG[3]
STRAP4 +3VGS PCIE_MAX_SPEED
N15S-GT Power Sequence

+3VG_AON

+VGA_CORE
A A

tNVVDD >0
+1.05VS_VGA

+1.35VGS
tPEX_VDD >0
Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
1. all power rail ramp up time should be larger than 40us
Issued Date 2014/09/24 Deciphered Date 2015/03/23 VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 18 of 60
5 4 3 2 1
5 4 3 2 1

RV1 1 2 0_0402_5% FB_GC6_EN_R

RV2 1 2 0_0402_5% GPU_EVENT#

{6} PCIE_CRX_GTX_N[0..1]

{6} PCIE_CRX_GTX_P[0..1]

{6} PCIE_CTX_C_GRX_N[0..1]
UV1A
{6} PCIE_CTX_C_GRX_P[0..1]
Part 1 of 6
PCIE_CTX_C_GRX_P0 AG6 C6 FB_GC6_EN
D PEX_RX0 GPIO0 FB_GC6_EN {23} D
+3VG_AON +3VG_AON PCIE_CTX_C_GRX_N0 AG7 B2
PCIE_CTX_C_GRX_P1 AF7 PEX_RX0_N GPIO1 D6
PCIE_CTX_C_GRX_N1 AE7 PEX_RX1 GPIO2 C7
AE9 PEX_RX1_N GPIO3 F9
3
4

AF9 PEX_RX2 GPIO4 A3 3VGS_PWR_EN


PEX_RX2_N GPIO5 3VGS_PWR_EN {21,57}
RPV5 AG9 A4 GPU_EVENT#_R

5
AG10 PEX_RX3 GPIO6 B6

G
2.2K_0404_4P2R_5%
@ AF10 PEX_RX3_N GPIO7 E9 SYS_PEX_RST_MON#
AE10 NC81 GPIO8 F8 VGA_ALERT#
A6 Symbol update to OVER
2
1

AE12 NC82 GPIO9 C5


VGA_SMB_CK2 4
S
3 AF12 NC83 GPIO10 E7 NVVDD PWM_VID DV1
EC_SMB_CK2 {39,44} NC84 GPIO11 NVVDD PWM_VID {57}

D
AG12 D7 VGA_AC_DET_R 2 1
NC85 GPIO12 VGA_AC_DET {44}
AG13 B4 PSI_VGA_R @

GPIO
QV1B AF13 NC86 GPIO13 B3 RB751V-40_SOD323-2
2N7002KDWH_SOT363-6 AE13 NC87 GPIO14 C3
2 RV6
2

@ AE15 NC88 GPIO15 D5 1 PSI_VGA


G

NC1 GPIO16 PSI_VGA {57}

Ju
RV7 2 OPT@ 1 0_0402_5% AF15 D4 @ 0_0402_5%
AG15 NC2 GPIO17 C2
AG16 NC3 GPIO18 F7
VGA_SMB_DA2 1 6 AF16 NC4 GPIO19 E6
S

EC_SMB_DA2 {39,44} NC5 GPIO20


D

AE16 C4 GPU_PEX_RST_HOLD#
AE18 NC6 GPIO21
QV1A AF18 NC7 A6 OVERT#
2N7002KDWH_SOT363-6 AG18 NC8 OVERT AB6
AG19 NC9 NC33
@

st
RV9 2 OPT@1 0_0402_5% PU AT EC SIDE, +3VS AND 4.7K AF19 NC10
AE19 NC11 PLT_RST_VGA# 1 RV174 2 0_0402_5%
AE21 NC12 AG3

.1U_0402_10V6-K
+3VS AF21 NC13 NC97 AF4 OPT@
NC14 NC98 1
AG21 AF3 CV218

2
AG22 NC15 NC99

G
+3VGARST RV10 2 @ 1 0_0402_5% NC16 @ +3VG_AON +3VG_AON
2

for
+3VG_AON PCIE_CRX_GTX_P0 CV10 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_P0 AC9 AE3

DACs
PCIE_CRX_GTX_N0 CV13 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_N0 AB9 PEX_TX0 NC100 AE4 OVERT# 3 1
PEX_TX0_N NC101 WRST# {44}

D
RV12 1 2 0_0402_5% PCIE_CRX_GTX_P1 CV8 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_P1 AB10
PCIE_CRX_GTX_N1 CV9 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_N1 AC10 PEX_TX1
1 QV23

2
PEX_TX1_N

PCI EXPRESS
AD11

.1U_0402_10V6-K
C 1 C
AC11 PEX_TX2 W5 CV221 2N7002KW_SOT323-3 RV13
1 PEX_TX2_N NC102
AC12 AE2 0.01U_0402_25V7K OPT@ 10K_0402_5% CV12

2
CV11 AB12 PEX_TX3 NC103 AF2 @ 2 @ @

G
.1U_0402_10V6-K AB13 PEX_TX3_N NC104 2

1
2 OPT@ AC13 NC89
AD14 NC90
AC14 NC91 GPU_EVENT#_R 3 1 GPU_EVENT#

LC
5

NC92

D
UV2 AC15
AB15 NC93 QV4
VCC

1 AB16 NC94 B7 VGA_CRT_CLK 2N7002KW_SOT323-3


{7} PXS_RST# IN1 NC95 I2CA_SCL
4 SYS_PEX_RST_MON# AC16 A7 VGA_CRT_DATA @
PLT_RST# 2 OUT AD17 NC96 I2CA_SDA Connect to CPU GPIO
GND

{7,37,40,44,45} PLT_RST# IN2 AC17 NC17 C9 I2CB_SCL 1 2 RV15


AC18 NC18 I2CB_SCL C8 I2CB_SDA @ 0_0402_5%
NC19 I2CB_SDA

I2C
MC74VHC1G08DFT2G_SC70-5 AB18
2
3

OPT@ AB19 NC20 A9 I2CC_SCL


RV14 NC21 I2CC_SCL
AC19 B9 I2CC_SDA

FC
10K_0402_5% NC22 I2CC_SDA
AD20
OPT@ NC23
AC20 D9 VGA_SMB_CK2 +3VG_AON +3VG_AON
AC21 NC24 I2CS_SCL D8 VGA_SMB_DA2 Internal Thermal Sensor
1

AB21 NC25 I2CS_SDA


AD23 NC26 RPV1
AE23 NC27 VGA_CRT_DATA 4 1 3VGS_PWR_EN RV18 2 1
AF24 NC28 60mA VGA_CRT_CLK 3 2 OPT@ 10K_0402_5%
AE24 NC29 L6 +PLLVDD 10K_0404_4P2R_5% OPT@ OVERT# RV20 1 2
1 2 RV16 NC30 CORE_PLLVDD
AG24 M6 RPV2 OPT@ 10K_0402_5%
@ 0_0402_5% NC31 SP_PLLVDD
AG25 I2CB_SCL 4 1 VGA_ALERT# RV23 1 2
NC32 N6
45mA 1 2 RV24 +SP_PLLVDD I2CB_SDA 3 2 OPT@ 10K_0402_5%
VID_PLLVDD OPT@
0_0402_5% 10K_0404_4P2R_5% OPT@ VGA_AC_DET_R RV26 1 2
45mA RPV3 OPT@ 100K_0402_5%

PE
+3VGS +3VG_AON {6} CLK_PCIE_GPU CLK_PCIE_GPU AE8 I2CC_SCL 4 1 PSI_VGA RV29 1 2
CLK_PCIE_GPU# AD8 PEX_REFCLK I2CC_SDA 3 2 OPT@ 10K_0402_5%
{6} CLK_PCIE_GPU# PEX_REFCLK_N
CLK_REQ_GPU# AC6 10K_0404_4P2R_5% OPT@ GPU_PEX_RST_HOLD# RV31 1 2
PEX_CLKREQ_N OPT@ 10K_0402_5%
1 2 RV32 AF22 RV33 1 2

CLK
PEX_TSTCLK_OUT XTALOUT
Differential signal @ 200_0402_1% PEX_TSTCLK_OUT# AE22 PEX_TSTCLK C11 XTAL_IN @ 10K_0402_5%
2

PEX_TSTCLK_N XTAL_IN B10 XTAL_OUT


B
RV180 RV37 XTAL_OUT B
10K_0402_5% 10K_0402_5% PLT_RST_VGA# AC7 A10 XTALSSIN 1 OPT@ 2 RV21 10K_0402_5%
1 2 RV35 AF25 PEX_RST_N XTAL_SSIN C10 XTALOUT 1 OPT@ 2 RV22
DV6
@ @ PEX_TERMP
PEX_TERMP XTAL_OUTBUFF
10K_0402_5% Under GPU(below 150mils)
OPT@ 2.49K_0402_1% 300ohms (ESR=0.2) Bead
1

GPU_PEX_RST_HOLD# 2
1 PLT_RST_VGA# N16V-GM-S-B1_FCBGA595 +SP_PLLVDD 1 2 LV1

De
+1.05VGS
SYS_PEX_RST_MON# 3 OPT@ PBY160808T-301Y-N_2P

10U_0603_6.3V6M

22U_0805_6.3V6M
150mA

0.1U_0402_10V7K

0.1U_0402_10V7K
1 1 1 1
CV15 CV16 CV17 CV18 OPT@
BAT54AWT1G_SOT323-3
@
2 2 2 2
OPT@ OPT@ OPT@ OPT@
1 2 RV39
OPT@ 0_0402_5%

bu
1 2 RV38
change to BAT54A for cost down OPT_XTAL@ 10M_0402_5%
YV1
Under GPU Near GPU 30ohms (ESR=0.05) Bead
+3VG_AON +3VG_AON XTAL_IN 1 4
OSC1 GND2 +PLLVDD 1 2 LV2 +1.05VGS
2 3 1 RV184 2 XTAL_OUT
GND1 OSC2 PBY160808T-300Y-N_2P
1 1

g
470_0402_1%
2

1 1 OPT@
RV40 RV41 OPT_XTAL@ CV21 CV22
10K_0402_5% 10K_0402_5% CV19 27MHZ_10PF_7V27000050 CV20 0.1U_0402_10V7K 22U_0805_6.3V6M
@ @ OPT@ 2 2 OPT@
OPT_XTAL@
2 2
12P_0402_50V8-J 12P_0402_50V8-J
1

OPT_XTAL@ OPT_XTAL@
+3VG_AON +3VG_AON
.1U_0402_10V6-K

.1U_0402_10V6-K

1 1
CV23 CV24
@ @
2

2
2

A 2 RV44 2 RV45 A
G

27M@
10K_0402_5% 10K_0402_5%
{17} 27M_CLK RV183 1 2 0_0402_5% XTAL_IN
@ @
1

{6} GPU_CLKREQ#
1 3 CLK_REQ_GPU# FB_GC6_EN_R 1 3 FB_GC6_EN
D

QV5 QV6
2

2N7002KW_SOT323-3 2N7002KW_SOT323-3
@ RV46 @ RV47
10K_0402_5% 10K_0402_5%
@
Connect to CPU GPIO @ Title
1 2 RV48 1 2 RV49 Security Classification
Classification LC Future Center Secret Data
1

OPT@
0_0402_5% @ 0_0402_5%
Issued Date 2014/09/24 Deciphered Date 2015/03/23 N16X_PCIE/ DAC/ GPIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 19 of 60
5 4 3 2 1

www.bios-downloads.com
5 4 3 2 1

D D

UV1C

Part 3 of 6 F11
AC3 NC50 AD10
AC4 NC105 NC51 AD7
Y4 NC106 NC52
Y3 NC107 V5
B19 Symbol update to FBA_CMD32
AA3 NC108 FERMI_RSVD1 V6
AA2 NC109 FERMI_RSVD2 G1
AB1 NC110 NC56 G2
NC111 NC57

NC
AA1 G3
NC112 NC58

Ju
AA4 G4
AA5 NC113 NC59 G5
NC114 NC60 G6
NC61 G7
AB5 NC62 V1
AB4 NC115 NC63 V2
AB3 NC116 NC64 W1
AB2 NC117 NC65 W2

st
AD3 NC118 NC66 W3
AD2 NC119 NC67 W4
AE1 NC120 NC68
AD1 NC121
AD4 NC122
AD5 NC123
NC124 D11 2 1 RV50
BUFRST_N

for
@ 10K_0402_5%

LVDS/TMDS
T2
T3 NC125 D10
T1 NC126 PGOOD
R1 NC127 E10
R2 NC128 NC71

GENERAL
R3 NC129 F10
N2 NC130 NC72
N3 NC131 Symbol update to GPIO8
NC132 D1 STRAP0
STRAP0 STRAP0 {28}
D2 STRAP1

LC
C C
V3 STRAP1 E4 STRAP1 {28}
STRAP2
NC133 STRAP2 STRAP2 {28}
V4 E3 STRAP3
NC134 STRAP3 STRAP3 {28}
U3 D3 STRAP4
U4 NC135 STRAP4 C1 STRAP4 {28}
T4 NC136 NC73
T5 NC137
R4 NC138 F6 1 2 RV51
R5 NC139 MULTI_STRAP_REF0_GND F4 OPT@ 40.2K_0402_1%
NC140 MULTI_STRAP_REF1_GNDMLS_REF1 F5

FC
MULTI_STRAP_REF2_GND RV11
2 1 +3VG_AON
N1
NC34 @ 10K_0402_5%
M1
M2 NC35 F12
M3 NC36 THERMDP
K2 NC37 E12
K3 NC38 THERMDN
K1 NC39
J1 NC40
NC41

PE
M4 F2 VCCSENSE_VGA
NC42 VDD_SENSE VCCSENSE_VGA {57}
M5
L3 NC43
L4 NC44 trace width: 16mils
K4 NC45 differential voltage sensing.
NC46 differential signal routing.
K5
J4 NC47 F1 VSSSENSE_VGA
NC48 GND_SENSE VSSSENSE_VGA {57}

J5

De
N4 NC49
N5 NC141
NC142
TEST
P3 AD9 TESTMODE 1 OPT@ 2 RV52
P4 NC143 TESTMODE AE5 @ 1 10K_0402_5%
B NC144 JTAG_TCK TV1 B
AE6 @ 1
JTAG_TDI AF6 1 TV2
@
JTAG_TDO TV3
J2 AD6 @ 1
J3 NC145 JTAG_TMS AG4 1TV4 2 RV53

bu
NC146 JTAG_TRST_N OPT@ 10K_0402_5%

H3
H4 NC147
NC148 SERIAL
D12 @ 1
ROM_CS_N TV5
B12 ROM_SI
ROM_SI A12 ROM_SI {28}
ROM_SO

g
ROM_SO ROM_SO {28}
C12 ROM_SCLK
ROM_SCLK ROM_SCLK {28}

N16V-GM-S-B1_FCBGA595
OPT@

A A

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 N16X_LVDS/ HDMI/ THERM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 20 of 60
5 4 3 2 1
5 4 3 2 1

UV1D
Near GPU
+1.35VGS Near GPU Under GPU(below 150mils)
2000mA +1.05VGS
3.5A Part 4 of 6
B26 AA10 For RF
C25 FBVDDQ_01 PEX_IOVDDQ_1 AA12

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
22U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
0.1U_0402_10V7K

0.1U_0402_10V7K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
E23 FBVDDQ_02 PEX_IOVDDQ_2 AA13 1 CV215

CV33

@ CV34

@ CV35

@ CV36

CV37

@ CV38

CV39

@ CV40

@ CV41

@ CV42
1 1 1 1 1 1 2 2 2 2

1U_0603_25V6M

1U_0603_25V6M
E26 FBVDDQ_03 PEX_IOVDDQ_3 AA16

CV25

CV26

CV27

CV28

CV29

CV30

CV31

CV32
1 2 1 1 1 1 1 1 FBVDDQ_04 PEX_IOVDDQ_4
F14 AA18 22P_0402_50V8-J
F21 FBVDDQ_05 PEX_IOVDDQ_5 AA19
G13 FBVDDQ_06 PEX_IOVDDQ_6 AA20 2 2 2 2 2 2 1 1 1 1 2
2 1 2 2 2 2 2 2 FBVDDQ_07 PEX_IOVDDQ_7 RF_OPT@
G14 AA21 OPT@ OPT@ OPT@
OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ G15 FBVDDQ_08 PEX_IOVDDQ_8 AB22
G16 FBVDDQ_09 PEX_IOVDDQ_9 AC23
D
G18 FBVDDQ_10 PEX_IOVDDQ_10 AD24
Under GPU(below 150mils) +1.05VGS PEX_IOVVDD/Q Decouling D
G19 FBVDDQ_11 PEX_IOVDDQ_11 AE25
G20 FBVDDQ_12 PEX_IOVDDQ_12 AF26 1 1 1 1 MLCC N15V-GM N15S-GT

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
G21 FBVDDQ_13 PEX_IOVDDQ_13 AF27

CV43

@ CV44

@ CV45

@ CV46
L22 FBVDDQ_14 PEX_IOVDDQ_14
Symbol update to FBVDDQ_AON L24 FBVDDQ_19
H24/H26/J21/K21 L26 FBVDDQ_20 AA22 2 2 2 2
Under Near +3VG_AON 1.0uF 4 1
M21 FBVDDQ_21 PEX_IOVDD_1 AB23
N21 FBVDDQ_22 PEX_IOVDD_2 AC24 OPT@
4.7uF 2 1

1U_0402_6.3V6K
.1U_0402_10V6-K

4.7U_0603_6.3V6K
R21 FBVDDQ_23 PEX_IOVDD_3 AD25

CV47

CV48

CV49
1 1 1

POWER
T21 FBVDDQ_24 PEX_IOVDD_4 AE26
V21 FBVDDQ_25 PEX_IOVDD_5 AE27
FBVDDQ_26 PEX_IOVDD_6 10uF 4 1

Ju
W21
FBVDDQ_27 2 2 2
Symbol update to 3V3_AON OPT@ OPT@ OPT@
H24 22uF 4 1
H26 FBVDDQ_AON_1 +3VG_AON
J21 FBVDDQ_AON_2 G10
FBVDDQ_AON_3 3V3_AON_1 Place near balls(Under GPU) Place near GPU
K21 G12
FBVDDQ_AON_4 3V3_AON_2 +3VGS

st
RV54
V7 G8 +VDD33 1 2
NC149 3V3_MAIN_1 G9

.1U_0402_10V6-K

.1U_0402_10V6-K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
3V3_MAIN_2 +1.35VGS

CV50

CV51

CV52

CV53
1 1 1 1 0_0603_5%
W7
AA6 NC150
+1.05VGS NC151 Change RV9 to 0ohm jump
W6 D22 FB_CAL_VDDQ 1 2 RV55
NC152 FB_CAL_VDDQ 2 2 2 2

for
+5VALW Y6 OPT@ 40.2_0402_1%
NC153 OPT@ OPT@ OPT@ OPT@

1
C24 FB_CAL_GND 1 2 RV56
RV181 FB_CAL_GND OPT@ 42.2_0402_1%
2

470_0603_5%
RV182 @ M7 B25 FB_CAL_TERM 1 2 RV57 CALIBRATION PIN DDR3
N7 NC154 FB_CAL_TERM OPT@ 51.1_0402_1%
47K_0402_5%
3 2
@ T6 NC155
D P6 NC156 FB_CAL_x_PD_VDDQ 40.2Ohm
1

5 QV25B NC157
G
Place near balls

LC
C 2N7002KDWH_SOT363-6 FB_CAL_x_PU_GND 42.2Ohm C
6

D @
2 QV25A S T7 +3VG_AON
{56} +1.05VGS_EN
4

G R7 NC158
2N7002KDWH_SOT363-6
U6 NC159 Under GPU(below 150mils) FB_CAL_xTERM_GND 51.1Ohm
S @ NC160
R6 AA8

.1U_0402_10V6-K
1

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
NC161 PEX_PLL_HVDD_1 AA9

CV55

CV56

CV57
PEX_PLL_HVDD_2 1 1 1
AB8
PEX_SVDD_3V3

FC
2 2 2
J7 OPT@ OPT@ OPT@ +1.05VGS
NC76 120mA 120ohm (ESR=0.18) Bead
K7
K6 NC77 AA14 +PEX_PLLVDD 2 @ 1 LV3
H6 NC78 PEX_PLLVDD_1 AA15 HCB1608KF-121T30_0603

1U_0603_25V6M
.1U_0402_10V6-K

4.7U_0805_25V6-K
J6 NC79 PEX_PLLVDD_2

CV58

CV59

CV60
NC80 1 1 1
RV62
1 2 0_0603_5%
2 2 2
OPT@ OPT@ OPT@

PE
N16V-GM-S-B1_FCBGA595
OPT@
Place near balls
+3.3VS TO +3VG_AON

+3VS +3VG_AON

De
+5VALW
S

3 1
1

QV11 OPT@
1

B B
RV63 OPT@
G

1 1 1
2

47K_0402_5% @ LP2301ALT1G_SOT23-3 CV62 RV64 CV63


CV61 0.01U_0402_25V7K 470_0603_5% 10U_0603_6.3V6M +1.35V +1.35VGS
.1U_0402_10V6-K @ @ OPT@ +1.35V TO +1.35VGS AON6414AL_DFN8-5

bu
2

2 2 2
2

PXS_PWREN# 1 2 RV65 1
10K_0402_5% 2
OPT@ 1 5 3
OPT@ CV67 CV68 CV69 CV70

220U_B2_2.5VM_R15M
1

CV64 QV13 D CV65 CV66 1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

.1U_0402_10V6-K
1

1
QV12 D .1U_0402_10V6-K PXS_PWREN# 2 1 1 QV14 OPT@ 1 1 1

4
2 OPT@ 2 G + RV67

g
{7,57} PXS_PWREN G 470_0603_5%
@ S 2N7002KW_SOT323-3 @
3
1

2 2 2 2 2 2

@
S 2N7002KW_SOT323-3

OPT@

OPT@

OPT@

OPT@
3

2
RV66 OPT@
100K_0402_5% +20VSB
2

1
+5VALW D
1 OPT@ 2 RV68 FBVDDQ_PWR_EN# 2 QV15
100K_0402_5% G 2N7002KW_SOT323-3
@

1
+3VG_AON +3VGS S
RV69 1

3
6
D CV71 RV70
+3.3VS TO +3VGS 1 2 FBVDDQ_PWR_EN# 2 QV17A 0.01U_0402_25V7K 124K_0402_1%
G 2N7002KDWH_SOT363-6 OPT@ OPT@
2

2
47K_0402_5% OPT@
RV171 1 2 S

1
0_0603_5% OPT@
OPT@

3
D
+5VALW 5 QV17B
{23} FBVDDQ_PWR_EN
S

3 1 G 2N7002KDWH_SOT363-6
QV16 @
OPT@
1

4
1

RV71 @
G

1 1 1
2

A 47K_0402_5% @ CV73 RV72 CV74 A


CV72 LP2301ALT1G_SOT23-3 0.01U_0402_25V7K 470_0603_5% 10U_0603_6.3V6M
.1U_0402_10V6-K @ @ @
2

2 2 2
2

DGPU_PWR_EN# 1 RV73 2
10K_0402_5%
@ 1
1

QV19 D @
1

2 @ CV75 QV20 D
{19,57} 3VGS_PWR_EN G .1U_0402_10V6-K 2
DGPU_PWR_EN#
2 G
Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
1

S 2N7002KW_SOT323-3
3

@ S 2N7002KW_SOT323-3
Issued Date 2014/09/24 Deciphered Date 2015/03/23 N16X_Power
3

RV74 @
100K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
2

C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 21 of 60
5 4 3 2 1
5 4 3 2 1

D D

UV1E
UV1F
A2 Part 5 of 6 K11 +VGA_CORE +VGA_CORE
A26 GND_001 GND_057 K13 Part 6 of 6
AB11 GND_002 GND_058 K15
GND_003 GND_059

Ju
AB14 K17 K10 V18
AB17 GND_004 GND_060 L10 K12 VDD_001 VDD_041 V16
AB20 GND_005 GND_061 L12 +VGA_CORE K14 VDD_002 VDD_040 V14
AB24 GND_006 GND_062 L14 K16 VDD_003 VDD_039 V12
GND_007 GND_063 Under GPU VDD_004 VDD_038
AC2 L16 K18 V10
AC22 GND_008 GND_064 L18 L11 VDD_005 VDD_037 U17
GND_009 GND_065 VDD_006 VDD_036

POWER
AC26 L2 L13 U15
AC5 GND_010 GND_066 L23 L15 VDD_007 VDD_035 U13

st
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AC8 GND_011 GND_067 L25 L17 VDD_008 VDD_034 U11
AD12 GND_012 GND_068 L5 M10 VDD_009 VDD_033 T18
GND_013 GND_069 1 1 1 1 1 1 1 1 1 1 1 1 1 VDD_010 VDD_032
AD13 M11 M12 T16

CV76

CV77

CV78

CV79

CV80

CV81

CV82

CV83

CV84

CV85

CV86

CV87

CV88
AD15 GND_014 GND_070 M13 M14 VDD_011 VDD_031 T14
AD16 GND_015 GND_071 M15 M16 VDD_012 VDD_030 T12
AD18 GND_016 GND_072 M17 2 2 2 2 2 2 2 2 2 2 2 2 2 M18 VDD_013 VDD_029 T10
AD19 GND_017 GND_073 N10 N11 VDD_014 VDD_028 R17
GND_018 GND_074 VDD_015 VDD_027

for
AD21 N12 OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ @ @ @ N13 R15
AD22 GND_019 GND_075 N14 N15 VDD_016 VDD_026 R13
AE11 GND_020 GND_076 N16 N17 VDD_017 VDD_025 R11
AE14 GND_021 GND_077 N18 P10 VDD_018 VDD_024 P18
AE17 GND_022 GND_078 P11 P12 VDD_019 VDD_023 P16
GND_023 GND_079 For RF VDD_020 VDD_022
AE20 P13 P14

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
AF1 GND_024 GND_080 P15 VDD_021

CV89

CV90

CV91

CV92
GND_025 GND_081 1 1 1 1 1
AF11 P17
GND

AF14 GND_026 GND_082 P2 CV213


AF17 GND_027 GND_083 P23
AF20 GND_028 GND_084 P26 2 2 2 2 2 22P_0402_50V8-J

LC
C C
AF23 GND_029 GND_085 P5 RF_OPT@
OPT@ OPT@ OPT@ OPT@
AF5 GND_030 GND_086 R10
AF8 GND_031 GND_087 R12
AG2 GND_032 GND_088 R14
AG26 GND_033 GND_089 R16 N16V-GM-S-B1_FCBGA595
B1 GND_034 GND_090 R18 OPT@

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
B11 GND_035 GND_091 T11
B14 GND_036 GND_092 T13
GND_037 GND_093 1 1 1 1 1 1 1 1 1 1
B17 T15

CV93

CV94

CV95

CV96

CV97

CV98

CV99

CV100

CV101

CV102
FC
B20 GND_038 GND_094 T17
B23 GND_039 GND_095 U10
B27 GND_040 GND_096 U12 2 2 2 2 2 2 2 2 2 2
B5 GND_041 GND_097 U14
B8 GND_042 GND_098 U16 OPT@ OPT@ OPT@ OPT@ OPT@ @ @ @ @ @
E11 GND_043 GND_099 U18
E14 GND_044 GND_100 U2
E17 GND_045 GND_101 U23
E2 GND_046 GND_102 U26 For RF
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
E20 GND_047 GND_103 U5
E22 GND_048 GND_104 V11
CV103

CV104

CV105
GND_049 GND_105 1 1 1 1

PE
E25 V13
E5 GND_050 GND_106 V15 CV214
E8 GND_051 GND_107 V17 22P_0402_50V8-J
H2 GND_052 GND_108 Y2 2 2 2 2 RF_OPT@
H23 GND_053 GND_109 Y23 OPT@ OPT@ OPT@
H25 GND_054 GND_110 Y26
H5 GND_055 GND_111 Y5
GND_056 GND_112

Near GPU
AA7

De
GND_113 AB7
GND_114

N16V-GM-S-B1_FCBGA595
B B
OPT@

bu
+5VALW
+VGA_CORE

g
1

RV173
2

470_0603_5%
RV172 @
47K_0402_5%
1 2

@
D
1

2 QV22
G
1

D
2 QV21 @ S
{56,57} EN_VGA
3

G 2N7002KW_SOT323-3

@ S
3

2N7002KW_SOT323-3

A A

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 N16X_+VGA CORE, GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 22 of 60
5 4 3 2 1
5 4 3 2 1

FBA_D[0..63]
{24,25} FBA_D[0..63]

{24,25} FBA_DQM[7..0]
{24,25} FBA_DQS[7..0]
{24,25} FBA_DQS#[7..0]
CMD mapping mod Mode D
Rank0
UV1B Address 0..31 32..63
D FBx_CMD0 CS0# D

Part 2 of 6 FBx_CMD1
FBA_D0 E18 C27 FBA_CS0# FBx_CMD2 ODT0
FBA_D00 FBA_CMD00 FBA_CS0# {24}
FBA_D1 F18 C26
FBA_D2 E16 FBA_D01 FBA_CMD01 E24 FBA_ODT0 FBx_CMD3 CKE0
FBA_D02 FBA_CMD02 FBA_ODT0 {24}
FBA_D3 F17 F24 FBA_CKE0
FBA_D4 D20 FBA_D03 FBA_CMD03 D27 FBA_A14
FBA_CKE0 {24} FBx_CMD4 A14 A14
FBA_D04 FBA_CMD04 FBA_A14 {24,25}
FBA_D5 D21 D26 FBA_RST#
FBA_D6 F20 FBA_D05 FBA_CMD05 F25 FBA_A9
FBA_RST# {24,25} FBx_CMD5 RST RST
E21 FBA_D06 FBA_CMD06 F26 FBA_A9 {24,25}
FBA_D7 FBA_A7
FBA_D07 FBA_CMD07 FBA_A7 {24,25} FBx_CMD6 A9 A9

Ju
FBA_D8 E15 F23 FBA_A2
D15 FBA_D08 FBA_CMD08 G22 FBA_A2 {24,25}
FBA_D9 FBA_A0
FBA_D10 F15 FBA_D09 FBA_CMD09 G23 FBA_A4
FBA_A0 {24,25} FBx_CMD7 A7 A7
FBA_D10 FBA_CMD10 FBA_A4 {24,25}
FBA_D11 F13 G24 FBA_A1
FBA_D12 C13 FBA_D11 FBA_CMD11 F27 FBA_BA0
FBA_A1 {24,25} FBx_CMD8 A2 A2
FBA_D12 FBA_CMD12 FBA_BA0 {24,25}
FBA_D13 B13 G25 FBA_WE
FBA_D14 E13 FBA_D13 FBA_CMD13 G27 FBA_WE {24,25} FBx_CMD9 A0 A0
FBA_D15 D13 FBA_D14 FBA_CMD14 G26 FBA_CAS#

st
FBA_D16 B15 FBA_D15 FBA_CMD15 M24 FBA_CS1#
FBA_CAS# {24,25} FBx_CMD10 A4 A4
C16 FBA_D16 FBA_CMD16 M23 FBA_CS1# {25}
FBA_D17
FBA_D18 A13 FBA_D17 FBA_CMD17 K24 FBA_ODT1 FBx_CMD11 A1 A1
A15 FBA_D18 FBA_CMD18 K23 FBA_ODT1 {25}
FBA_D19 FBA_CKE1
FBA_D20 B18 FBA_D19 FBA_CMD19 M27 FBA_A13
FBA_CKE1 {25} FBx_CMD12 BA0 BA0
FBA_D20 FBA_CMD20 FBA_A13 {24,25}
FBA_D21 A18 M26 FBA_A8
FBA_D22 A19 FBA_D21 FBA_CMD21 M25 FBA_A6
FBA_A8 {24,25} FBx_CMD13 WE WE
FBA_D22 FBA_CMD22 FBA_A6 {24,25}

for
FBA_D23 C19 K26 FBA_A11
FBA_D24 B24 FBA_D23 FBA_CMD23 K22 FBA_A5
FBA_A11 {24,25} FBx_CMD14 A15 A15
FBA_D24 FBA_CMD24 FBA_A5 {24,25}
FBA_D25 C23 J23 FBA_A3
FBA_D26 A25 FBA_D25 FBA_CMD25 J25 FBA_BA2
FBA_A3 {24,25} FBx_CMD15 CAS# CAS#
A24 FBA_D26 FBA_CMD26 J24 FBA_BA2 {24,25}
FBA_D27 FBA_BA1
FBA_D28 A21 FBA_D27 FBA_CMD27 K27 FBA_A12
FBA_BA1 {24,25} FBx_CMD16 CS1#
B21 FBA_D28 FBA_CMD28 K25 FBA_A12 {24,25}
FBA_D29 FBA_A10
FBA_D30 C20 FBA_D29 FBA_CMD29 J27 FBA_RAS#
FBA_A10 {24,25} FBx_CMD17
FBA_D30 FBA_CMD30 FBA_RAS# {24,25}
FBA_D31 C21 J26
FBA_D32 R22 FBA_D31 FBA_CMD31 B19 +1.35VGS FBx_CMD18 ODT1
FBA_D33 R24 FBA_D32 FBA_CMD32 Symbol update to FBA_CMD34/35

LC
C C
FBA_D33 FBx_CMD19 CKE1

INTERFACE A
FBA_D34 T22 F22 RV121 2 @ 1 60.4_0402_1%
FBA_D35 R23 FBA_D34 FBA_CMD34 J22 RV122 2 1 60.4_0402_1%
FBA_D36 N25 FBA_D35 FBA_CMD35 @ FBx_CMD20 A13 A13
FBA_D37 N26 FBA_D36 D19 FBA_DQM0

MEMORY
FBA_D38 N23 FBA_D37 FBA_DQM0 D14 FBA_DQM1 FBx_CMD21 A8 A8
FBA_D39 N24 FBA_D38 FBA_DQM1 C17 FBA_DQM2
30ohms (ESR=0.01) Bead FBA_D39 FBA_DQM2 FBx_CMD22 A6 A6
FBA_D40 V23 C22 FBA_DQM3
FBA_D41 V22 FBA_D40 FBA_DQM3 P24 FBA_DQM4
+1.05VGS +FB_PLLAVDD FBA_D42 T23 FBA_D41 FBA_DQM4 W24 FBA_DQM5 FBx_CMD23 A11 A11

FC
FBA_D43 U22 FBA_D42 FBA_DQM5 AA25 FBA_DQM6
200mA FBA_D44 Y24 FBA_D43 FBA_DQM6 U25 FBA_DQM7 FBx_CMD24 A5 A5
1 2 LV4 FBA_D45 AA24 FBA_D44 FBA_DQM7
HCB1608KF-300T60_2P FBA_D46 Y22 FBA_D45 F19 FBA_DQS#0 FBx_CMD25 A3 A3
FBA_D47 AA23 FBA_D46 FBA_DQS_RN0 C14 FBA_DQS#1
OPT@ FBA_D47 FBA_DQS_RN1 FBx_CMD26 BA2 BA2
FBA_D48 AD27 A16 FBA_DQS#2
AB25 FBA_D48 FBA_DQS_RN2 A22
Place close to BGA FBA_D49 FBA_DQS#3
FBA_D50 AD26 FBA_D49 FBA_DQS_RN3 P25 FBA_DQS#4 FBx_CMD27 BA1 BA1
FBA_D51 AC25 FBA_D50 FBA_DQS_RN4 W22 FBA_DQS#5
FBA_D52 AA27 FBA_D51 FBA_DQS_RN5 AB27 FBA_DQS#6 FBx_CMD28 A12 A12
FBA_D52 FBA_DQS_RN6
Place close to BGA Place close to ball FBA_D53 AA26 T27 FBA_DQS#7
FBA_D53 FBA_DQS_RN7 FBx_CMD29 A10 A10

PE
FBA_D54 W26
FBA_D55 Y25 FBA_D54 E19 FBA_DQS0
+FB_PLLAVDD FBA_D55 FBA_DQS_WP0 FBx_CMD30 RAS# RAS#
FBA_D56 R26 C15 FBA_DQS1
22U_0805_6.3V6M

1U_0402_6.3V6K

0.1U_0402_10V7K

FBA_D57 T25 FBA_D56 FBA_DQS_WP1 B16 FBA_DQS2


CV111

CV112

CV113

1 1 1 FBA_D57 FBA_DQS_WP2 FBx_CMD31


FBA_D58 N27 B22 FBA_DQS3
FBA_D59 R27 FBA_D58 FBA_DQS_WP3 R25 FBA_DQS4
FBA_D60 V26 FBA_D59 FBA_DQS_WP4 W23 FBA_DQS5 FBx_CMD32
2 2 2 FBA_D61 V27 FBA_D60 FBA_DQS_WP5 AB26 FBA_DQS6
FBA_D62 W27 FBA_D61 FBA_DQS_WP6 T26 FBA_DQS7 FBx_CMD33
OPT@ OPT@ OPT@ FBA_D63 W25 FBA_D62 FBA_DQS_WP7
FBA_D63 D24 FBA_CLK0 FBx_CMD34 DBG0
FBA_CLK0 FBA_CLK0 {24}
F16 D25 FBA_CLK0#

De
P22 FB_PLLAVDD_1 FBA_CLK0_N FBA_CLK0# {24} FBx_CMD35 DBG1
FB_PLLAVDD_2 N22 FBA_CLK1
FBA_CLK1 FBA_CLK1 {25}
D23 M22 FBA_CLK1#
FB_VREF FBA_CLK1_N FBA_CLK1# {25}
+FB_PLLAVDD
Place close to ball D18
B
1 2 CV115 H22 FBA_WCK01 C18 B

OPT@ 0.1U_0402_10V7K FB_DLLAVDD FBA_WCK01_N D17


FB_GC6_EN RV119 1 @ 2 0_0402_5% FB_CLAMP F3 FBA_WCK23 D16
RV120 1 OPT@ 2 10K_0402_5% FB_CLAMP FBA_WCK23_N T24

bu
FBA_WCK45 U24
FBA_WCK45_N V24
FBA_WCK67 V25
FBA_WCK67_N

N16V-GM-S-B1_FCBGA595

g
OPT@

DV4 @
{19} FB_GC6_EN FB_GC6_ENRV123 1 2 0_0402_5% GC6_EN 2
1
FBVDDQ_PWR_EN {21}
3
1

+3VGS RV124 1 2 BAV70W-7-F_SOT323-3


10K_0402_5% RV125
200K_0402_5%
@ @
1 2 RV126
{56,57} DGPU_PWROK
2

0_0402_5%
A OPT@ A

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 N16X_MEM Interface
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 23 of 60
5 4 3 2 1
5 4 3 2 1

at least 16 mils width(optimal)


20 mils spacing to other signals /planes FBA_D[0..63] {23,25}

D D

+1.35VGS
FBA_DQM[7..0] {23,25}
RPV6 UV6 UV5
FBA_DQS[7..0] {23,25}
1 4
2 3 +FBA_VREFCA0 +FBA_VREFCA0 M8 E3 FBA_D25 +FBA_VREFCA0 M8 E3 FBA_D12
VREFCA DQL0 VREFCA DQL0 FBA_DQS#[7..0] {23,25}
+FBA_VREFDQ0 H1 F7 FBA_D28 +FBA_VREFDQ0 H1 F7 FBA_D11
1.33K_0404_4P2R_1% VREFDQ DQL1 F2 FBA_D27 VREFDQ DQL1 F2 FBA_D15
1 DQL2 DQL2
OPT@ CV116
.01U_0402_16V7-K {23,25} FBA_A0
FBA_A0
FBA_A1
N3
P7 A0 DQL3
F8
H3
FBA_D29
FBA_D26
Group3 FBA_A0
FBA_A1
N3
P7 A0 DQL3
F8
H3
FBA_D8
FBA_D9
Group1 CMD mapping mod Mode D
{23,25} FBA_A1 P3 A1 DQL4 H8 P3 A1 DQL4 H8
OPT@ FBA_A2 FBA_D30 FBA_A2 FBA_D14
{23,25} FBA_A2 A2 DQL5 A2 DQL5 Rank0

Ju
2 FBA_A3 N2 G2 FBA_D24 FBA_A3 N2 G2 FBA_D13
{23,25} FBA_A3 P8 A3 DQL6 H7 P8 A3 DQL6 H7
FBA_A4 FBA_D31 FBA_A4 FBA_D10
{23,25} FBA_A4
FBA_A5 P2 A4 DQL7 FBA_A5 P2 A4 DQL7 Address 0..31 32..63
{23,25} FBA_A5 A5 A5
FBA_A6 R8 FBA_A6 R8
{23,25} FBA_A6
FBA_A7 R2 A6 D7 FBA_D1 FBA_A7 R2 A6 D7 FBA_D17 FBx_CMD0 CS0#
{23,25} FBA_A7 A7 DQU0 A7 DQU0
FBA_A8 T8 C3 FBA_D6 FBA_A8 T8 C3 FBA_D23
{23,25} FBA_A8
FBA_A9 R3 A8 DQU1 C8 FBA_D2 FBA_A9 R3 A8 DQU1 C8 FBA_D18 FBx_CMD1
{23,25} FBA_A9 A9 DQU2 A9 DQU2
FBA_A10 L7 C2 FBA_D5 FBA_A10 L7 C2 FBA_D20

st
{23,25} FBA_A10
FBA_A11 R7 A10/AP DQU3 A7 FBA_D0 Group0 FBA_A11 R7 A10/AP DQU3 A7 FBA_D16 Group2 FBx_CMD2 ODT0
{23,25} FBA_A11 N7 A11 DQU4 A2 N7 A11 DQU4 A2
FBA_A12 FBA_D7 FBA_A12 FBA_D21
{23,25} FBA_A12
FBA_A13 T3 A12/BC DQU5 B8 FBA_D3 FBA_A13 T3 A12/BC DQU5 B8 FBA_D22 FBx_CMD3 CKE0
{23,25} FBA_A13 T7 A13 DQU6 A3 T7 A13 DQU6 A3
FBA_A14 FBA_D4 FBA_A14 FBA_D19
+1.35VGS
{23,25} FBA_A14 A14 DQU7 A14 DQU7 FBx_CMD4 A14 A14
+1.35VGS +1.35VGS
RPV7 FBx_CMD5 RST RST

for
1 4 FBA_BA0 M2 B2 FBA_BA0 M2 B2
2 3 +FBA_VREFDQ0
{23,25} FBA_BA0
FBA_BA1 N8 BA0 VDD_1 D9 FBA_BA1 N8 BA0 VDD_1 D9 FBx_CMD6 A9 A9
{23,25} FBA_BA1 BA1 VDD_2 BA1 VDD_2
FBA_BA2 M3 G7 FBA_BA2 M3 G7
1.33K_0404_4P2R_1% 1
{23,25} FBA_BA2 BA2 VDD_3 K2 BA2 VDD_3 K2 FBx_CMD7 A7 A7
CV216 VDD_4 K8 VDD_4 K8
OPT@ VDD_5 VDD_5 FBx_CMD8 A2 A2
.01U_0402_16V7-K N1 N1
OPT@ FBA_CLK0 J7 VDD_6 N9 FBA_CLK0 J7 VDD_6 N9
2 {23} FBA_CLK0
FBA_CLK0# K7 CK VDD_7 R1 FBA_CLK0# K7 CK VDD_7 R1 FBx_CMD9 A0 A0
{23} FBA_CLK0# CK VDD_8 CK VDD_8
FBA_CKE0 K9 R9 FBA_CKE0 K9 R9
{23} FBA_CKE0 CKE VDD_9 CKE VDD_9 FBx_CMD10 A4 A4

LC
C C
FBA_ODT0 K1 A1 FBA_ODT0 K1 A1 FBx_CMD11 A1 A1
{23} FBA_ODT0 ODT VDDQ_1 ODT VDDQ_1
FBA_CS0# L2 A8 FBA_CS0# L2 A8
{23} FBA_CS0#
FBA_RAS# J3 CS VDDQ_2 C1 FBA_RAS# J3 CS VDDQ_2 C1 FBx_CMD12 BA0 BA0
{23,25} FBA_RAS# K3 RAS VDDQ_3 C9 K3 RAS VDDQ_3 C9
FBA_CAS# FBA_CAS#
{23,25} FBA_CAS#
FBA_WE L3 CAS VDDQ_4 D2 FBA_WE L3 CAS VDDQ_4 D2 FBx_CMD13 WE WE
{23,25} FBA_WE WE VDDQ_5 E9 WE VDDQ_5 E9
VDDQ_6 F1 VDDQ_6 F1 FBx_CMD14 A15 A15
FBA_DQS3 F3 VDDQ_7 H2 FBA_DQS1 F3 VDDQ_7 H2
FBA_CLK0 FBA_DQS0 C7 DQSL VDDQ_8 H9 FBA_DQS2 C7 DQSL VDDQ_8 H9 FBx_CMD15 CAS# CAS#

FC
DQSU VDDQ_9 DQSU VDDQ_9
FBx_CMD16 CS1#
1

FBA_DQM3 E7 A9 FBA_DQM1 E7 A9
RV129 FBA_DQM0 D3 DML VSS_1 B3 FBA_DQM2 D3 DML VSS_1 B3 FBx_CMD17
162_0402_1% DMU VSS_2 E1 DMU VSS_2 E1
OPT@ VSS_3 G8 VSS_3 G8 FBx_CMD18 ODT1
FBA_DQS#3 G3 VSS_4 J2 FBA_DQS#1 G3 VSS_4 J2
FBx_CMD19 CKE1
2

FBA_DQS#0 B7 DQSL VSS_5 J8 FBA_DQS#2 B7 DQSL VSS_5 J8


FBA_CLK0# DQSU VSS_6 M1 DQSU VSS_6 M1
VSS_7 M9 VSS_7 M9 FBx_CMD20 A13 A13
VSS_8 P1 VSS_8 P1
VSS_9 VSS_9 FBx_CMD21 A8 A8

PE
FBA_RST# T2 P9 FBA_RST# T2 P9
{23,25} FBA_RST# RESET VSS_10 RESET VSS_10
T1 T1
1 2 RV130 L8 VSS_11 T9 L8 VSS_11 T9 FBx_CMD22 A6 A6
243_0402_1% ZQ VSS_12 ZQ VSS_12
OPT@ FBx_CMD23 A11 A11

1
J1 B1 J1 B1
NC1 VSSQ_1 NC1 VSSQ_1 FBx_CMD24 A5 A5
1

L1 B9 RV132 L1 B9
RV131 J9 NC2 VSSQ_2 D1 243_0402_1% J9 NC2 VSSQ_2 D1
FBA_ODT0 10K_0402_5% L9 NC3 VSSQ_3 D8 OPT@ L9 NC3 VSSQ_3 D8 FBx_CMD25 A3 A3
OPT@ M7 NC4 VSSQ_4 E2 M7 NC4 VSSQ_4 E2
FBx_CMD26 BA2 BA2

2
NC5 VSSQ_5 E8 NC5 VSSQ_5 E8
2

FBA_CKE0 VSSQ_6 F9 VSSQ_6 F9

De
VSSQ_7 G1 VSSQ_7 G1 FBx_CMD27 BA1 BA1
VSSQ_8 G9 VSSQ_8 G9
VSSQ_9 VSSQ_9 FBx_CMD28 A12 A12
1

RV133 RV134 96-BALL 96-BALL


10K_0402_5% 10K_0402_5% SDRAM DDR3 SDRAM DDR3 FBx_CMD29 A10 A10
B B
OPT@ OPT@ K4W4G1646B-HC11_FBGA96 K4W4G1646B-HC11_FBGA96
@ @
FBx_CMD30 RAS# RAS#
2

FBx_CMD31

bu
FBx_CMD32
FBx_CMD33
FBx_CMD34 DBG0
FBx_CMD35 DBG1

+1.35VGS UV6 SIDE +1.35VGS +1.35VGS UV5 SIDE

g For RF
+1.35VGS
1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M
33P_0402_50V8J

33P_0402_50V8J
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV117

CV118

CV119

CV120

CV121

CV122

CV127

CV129

CV130

CV131

CV132

CV133

CV134

CV139
1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2
For RF
OPT@ OPT@ OPT@ OPT@ CD@ OPT@ @ OPT@ OPT@ CD@ OPT@ OPT@ OPT@ @

A A

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 DDR3 VRAM Rank0_L
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 24 of 60
5 4 3 2 1
5 4 3 2 1

at least 16 mils width(optimal)


20 mils spacing to other signals /planes

FBA_D[0..63] {23,24}

D D
+1.35VGS
FBA_DQM[7..0] {23,24}
RPV8
1 4 UV8 UV7 FBA_DQS[7..0] {23,24}
2 3 +FBA_VREFCA1
1 +FBA_VREFCA1 M8 E3 FBA_D53 +FBA_VREFCA1 M8 E3 FBA_D40 FBA_DQS#[7..0] {23,24}
1.33K_0404_4P2R_1% CV141 +FBA_VREFDQ1 H1 VREFCA DQL0 F7 FBA_D55 +FBA_VREFDQ1 H1 VREFCA DQL0 F7 FBA_D43
.01U_0402_16V7-K VREFDQ DQL1 F2 FBA_D52 VREFDQ DQL1 F2 FBA_D41
OPT@ DQL2 DQL2
OPT@ FBA_A0 N3 F8 FBA_D50 FBA_A0 N3 F8 FBA_D42 Group5
2 {23,24}
{23,24}
FBA_A0
FBA_A1
FBA_A1 P7 A0
A1
DQL3
DQL4
H3 FBA_D48 Group6 FBA_A1 P7 A0
A1
DQL3
DQL4
H3 FBA_D45 CMD mapping mod Mode D
FBA_A2 P3 H8 FBA_D51 FBA_A2 P3 H8 FBA_D47
{23,24} FBA_A2 N2 A2 DQL5 G2 N2 A2 DQL5 G2
{23,24} FBA_A3
FBA_A3
A3 DQL6
FBA_D54 FBA_A3
A3 DQL6
FBA_D44 Rank0

Ju
FBA_A4 P8 H7 FBA_D49 FBA_A4 P8 H7 FBA_D46
{23,24} FBA_A4 P2 A4 DQL7 P2 A4 DQL7
{23,24} FBA_A5
FBA_A5
A5
FBA_A5
A5
Address 0..31 32..63
FBA_A6 R8 FBA_A6 R8
{23,24} FBA_A6 A6 A6
FBA_A7 R2 D7 FBA_D32 FBA_A7 R2 D7 FBA_D57 FBx_CMD0 CS0#
{23,24} FBA_A7 T8 A7 DQU0 C3 T8 A7 DQU0 C3
FBA_A8 FBA_D39 FBA_A8 FBA_D63
{23,24} FBA_A8 A8 DQU1 A8 DQU1
{23,24} FBA_A9
FBA_A9 R3
A9 DQU2
C8 FBA_D33 FBA_A9 R3
A9 DQU2
C8 FBA_D59 FBx_CMD1
FBA_A10 L7 C2 FBA_D36 FBA_A10 L7 C2 FBA_D62
{23,24} FBA_A10 A10/AP DQU3 A10/AP DQU3
FBA_A11 R7 A7 FBA_D35 Group4 FBA_A11 R7 A7 FBA_D56 Group7 FBx_CMD2 ODT0

st
{23,24} FBA_A11 A11 DQU4 A11 DQU4
FBA_A12 N7 A2 FBA_D38 FBA_A12 N7 A2 FBA_D61
{23,24} FBA_A12 T3 A12/BC DQU5 B8 T3 A12/BC DQU5 B8
{23,24} FBA_A13
FBA_A13
A13 DQU6
FBA_D34 FBA_A13
A13 DQU6
FBA_D58 FBx_CMD3 CKE0
+1.35VGS FBA_A14 T7 A3 FBA_D37 FBA_A14 T7 A3 FBA_D60
{23,24} FBA_A14 A14 DQU7 A14 DQU7
FBx_CMD4 A14 A14
RPV9 +1.35VGS +1.35VGS
1 4 FBx_CMD5 RST RST
2 3 +FBA_VREFDQ1 FBA_BA0 M2 B2 FBA_BA0 M2 B2
{23,24} FBA_BA0 BA0 VDD_1 BA0 VDD_1

for
1 {23,24} FBA_BA1
FBA_BA1 N8
BA1 VDD_2
D9 FBA_BA1 N8
BA1 VDD_2
D9 FBx_CMD6 A9 A9
1.33K_0404_4P2R_1% FBA_BA2 M3 G7 FBA_BA2 M3 G7
CV217 {23,24} FBA_BA2 BA2 VDD_3 BA2 VDD_3
OPT@ .01U_0402_16V7-K VDD_4
K2
VDD_4
K2 FBx_CMD7 A7 A7
K8 K8
OPT@ VDD_5 N1 VDD_5 N1
2 VDD_6 VDD_6 FBx_CMD8 A2 A2
FBA_CLK1 J7 N9 FBA_CLK1 J7 N9
{23} FBA_CLK1 K7 CK VDD_7 R1 K7 CK VDD_7 R1
{23} FBA_CLK1#
FBA_CLK1#
CK VDD_8
FBA_CLK1#
CK VDD_8 FBx_CMD9 A0 A0
FBA_CKE1 K9 R9 FBA_CKE1 K9 R9
{23} FBA_CKE1 CKE VDD_9 CKE VDD_9
FBx_CMD10 A4 A4
FBA_ODT1 K1 A1 FBA_ODT1 K1 A1 FBx_CMD11 A1 A1

LC
C C
{23} FBA_ODT1 L2 ODT VDDQ_1 A8 L2 ODT VDDQ_1 A8
FBA_CS1# FBA_CS1#
{23} FBA_CS1# CS VDDQ_2 CS VDDQ_2
{23,24} FBA_RAS#
FBA_RAS# J3
RAS VDDQ_3
C1 FBA_RAS# J3
RAS VDDQ_3
C1 FBx_CMD12 BA0 BA0
FBA_CAS# K3 C9 FBA_CAS# K3 C9
{23,24} FBA_CAS# L3 CAS VDDQ_4 D2 L3 CAS VDDQ_4 D2
{23,24} FBA_WE
FBA_WE
WE VDDQ_5
FBA_WE
WE VDDQ_5 FBx_CMD13 WE WE
FBA_CLK1 E9 E9
VDDQ_6 F1 VDDQ_6 F1
VDDQ_7 VDDQ_7 FBx_CMD14 A15 A15
FBA_DQS6 F3 H2 FBA_DQS5 F3 H2
1

C7 DQSL VDDQ_8 H9 C7 DQSL VDDQ_8 H9


FBA_DQS4
DQSU VDDQ_9
FBA_DQS7
DQSU VDDQ_9 FBx_CMD15 CAS# CAS#
RV137

FC
162_0402_1% FBx_CMD16 CS1#
FBA_DQM6 E7 A9 FBA_DQM5 E7 A9
DML VSS_1 DML VSS_1
OPT@ FBA_DQM4 D3 B3 FBA_DQM7 D3 B3 FBx_CMD17
2

DMU VSS_2 E1 DMU VSS_2 E1


VSS_3 G8 VSS_3 G8
FBA_CLK1#
VSS_4 VSS_4 FBx_CMD18 ODT1
FBA_DQS#6 G3 J2 FBA_DQS#5 G3 J2
B7 DQSL VSS_5 J8 B7 DQSL VSS_5 J8
FBA_DQS#4
DQSU VSS_6
FBA_DQS#7
DQSU VSS_6 FBx_CMD19 CKE1
M1 M1
VSS_7 M9 VSS_7 M9
VSS_8 VSS_8 FBx_CMD20 A13 A13
P1 P1
VSS_9 VSS_9
{23,24} FBA_RST#
FBA_RST# T2
RESET VSS_10
P9 FBA_RST# T2
RESET VSS_10
P9 FBx_CMD21 A8 A8

PE
T1 T1
VSS_11 VSS_11
L8
ZQ VSS_12
T9 L8
ZQ VSS_12
T9 FBx_CMD22 A6 A6
FBA_CKE1
FBx_CMD23 A11 A11

1
J1 B1 J1 B1
1

L1 NC1 VSSQ_1 B9 L1 NC1 VSSQ_1 B9


FBA_ODT1
NC2 VSSQ_2
RV141
NC2 VSSQ_2 FBx_CMD24 A5 A5
RV140 J9 D1 243_0402_1% J9 D1
L9 NC3 VSSQ_3 D8 L9 NC3 VSSQ_3 D8
243_0402_1%
NC4 VSSQ_4
OPT@
NC4 VSSQ_4 FBx_CMD25 A3 A3
OPT@ M7 E2 M7 E2

2
NC5 VSSQ_5 NC5 VSSQ_5
1

E8 E8 FBx_CMD26 BA2 BA2


2

RV138 RV139 VSSQ_6 F9 VSSQ_6 F9


VSSQ_7 VSSQ_7
10K_0402_5% 10K_0402_5% G1 G1 FBx_CMD27 BA1 BA1

De
OPT@ OPT@ VSSQ_8 G9 VSSQ_8 G9
VSSQ_9 VSSQ_9
FBx_CMD28 A12 A12
2

96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD29 A10 A10
K4W4G1646B-HC11_FBGA96 K4W4G1646B-HC11_FBGA96
B B
@ @ FBx_CMD30 RAS# RAS#
FBx_CMD31

bu
FBx_CMD32
FBx_CMD33
FBx_CMD34 DBG0
FBx_CMD35 DBG1

+1.35VGS UV8 SIDE


For RF
+1.35VGS +1.35VGS UV7 SIDE

g For RF
+1.35VGS
1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M
33P_0402_50V8J

33P_0402_50V8J
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV142

CV143

CV144

CV145

CV146

CV147

CV152

CV154

CV155

CV156

CV157

CV158

CV159

CV164
1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2

OPT@ OPT@ CD@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ CD@
@ @

A A

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 DDR3 VRAM Rank0_H
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 25 of 60
5 4 3 2 1
5 4 3 2 1

D D

Ju
st
for
LC
C C

FC
PE
B

De B

bu
g
A A

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 DDR3 VRAM Rank1_L
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 26 of 60
5 4 3 2 1
5 4 3 2 1

D D

Ju
st
for
LC
C C

FC
PE
B

De B

bu
g
A A

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 DDR3 VRAM Rank1_H
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 27 of 60
5 4 3 2 1
5 4 3 2 1

+3VG_AON Physical Logical Logical Logical Logical


Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
D D
ROM_SCLK +3VGS SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
ROM_SI +3VGS RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VGS DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE

2
RV146 RV147 RV148 RV149 RV150 STRAP0 +3VGS Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
45.3K_0402_1% 45.3K_0402_1% 10K_0402_1% 4.99K_0402_1% 45.3K_0402_1%
OPT@ @ OPT@ @ @ STRAP1 +3VGS

1
STRAP2 +3VGS
{20} STRAP0 STRAP0 Reserved(keep pull-up and pull-down footprint and not stuff by default)

Ju
{20} STRAP1 STRAP1 STRAP3 +3VGS
{20} STRAP2 STRAP2
{20} STRAP3 STRAP3 STRAP4 +3VGS
{20} STRAP4 STRAP4

DEVID_SEL
2

2
Pull-up to

st
RV151 RV152 RV153 RV154 RV155 Resistor Values +3VGS Pull-down to Gnd
45.3K_0402_1% 45.3K_0402_1% 15K_0402_1% 4.99K_0402_1% 45.3K_0402_1% 0 (Default)
@ OPT@ @ OPT@ OPT@ 4.99K 1000 0000
SD03449918J
1

1
10K 1001 0001 1
15K 1010 0010

for
20K 1011 0011 PCIE_CFG
24.9K 1100 0100
SD03424928J 0 (Default)
30.1K 1101 0101
SD03430128J
34.8K 1110 0110 1
SD03434828J
+3VGS 45.3K 1111 0111
SD03445328J

LC
C C

SMBUS_ALT_ADDR
0 0x9E (Default)
2

2 Physical
RV156 RV157 RV158
Strapping pin Power Rail Strap Mapping
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 1 0x9C (Multi-GPU usage)
@ OPT@ OPT@ ROM_SCLK +3VGS SMB_ALT_ADDR

FC
1

ROM_SI +3VGS SUB_VENDOR


ROM_SO +3VGS VGA_DEVICE VGA_DEVICE
{20} ROM_SI ROM_SI
{20} ROM_SO ROM_SO STRAP0 +3VGS RAM_CFG[0] 0 3D Device (Class Code 302h)
{20} ROM_SCLK ROM_SCLK
STRAP1 +3VGS RAM_CFG[1]
1 VGA Device (Default)
2

STRAP2 +3VGS RAM_CFG[2]


RV159 RV160 RV161
X76 10K_0402_1% 10K_0402_1% 10K_0402_1% STRAP3 +3VGS RAM_CFG[3]

PE
@ @ @
STRAP4 +3VGS PCIE_MAX_SPEED
1

X76

B
GPU FB Memory (DDR3L)

Hynix
900MHz
H5TC4G63AFR-11C
256M x 16 0xE
ROM_SI
0xE
PU 34.8K
0xD
ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

De B

bu
MT41J256M16HA-093G:E
Micron PU 30.1K
N16V-GM 900MHz 256M x 16 0xD
H5TC2G63FFR-11C 0xB
Hynix PU 4.99K PU 4.99K PU 45.3K PD 45.3K PU 10K PD 4.99K PD 45.3K
128M x 16 0xB PU 20K
900MHz

g
MT41J128M16JT-093G 0x8
Micron
900MHz 128M x 16 0x8 PU 4.99K
K4W2G1646Q-BC1A 0x7
Samsung
900MHz 128M x 16 0x7 PD 45.3K

VRAM X76 VRAM P/N

X7606012101 SA00005SH40
Samsung

X7606012001 SA00005M120
Micron

A A

Hynix X7606012002 SA00005VS00

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 N16X_MISC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 28 of 60
5 4 3 2 1
5 4 3 2 1

D D

Ju
C

st C

for
LC
B
FC B

PE
De
A

bu A

g
Security Classification LC Future Center Secret Data Title
Issued Date 2014/09/24 Deciphered Date 2015/03/23 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 29 of 59
5 4 3 2 1

www.bios-downloads.com
5 4 3 2 1

.1U_0402_10V6-K CW25 1 2USB30_CTX_C_DRX_N2 1 RW1 @ 2 0_0402_5% USB30_CTX_R_DRX_N2 DVDD12


{8} USB30_CTX_DRX_N2
.1U_0402_10V6-K CW26 1 2USB30_CTX_C_DRX_P2 1 RW2 @ 2 0_0402_5% USB30_CTX_R_DRX_P2
{8} USB30_CTX_DRX_P2 UW1
DVDD12 CARD_3V3 +3VS
{8} USB30_CRX_DTX_N2 USB30_CRX_DTX_N2 RW3 1 @ 2 0_0402_5% USB30_CRX_R_DTX_N2
12 23

.1U_0402_10V6-K

.1U_0402_10V6-K
{8} USB30_CRX_DTX_P2 USB30_CRX_DTX_P2 RW4 1 @ 2 0_0402_5% USB30_CRX_R_DTX_P2 +3VS DVDD12 PMOS VHUSI
1 1
13

4.7U_0603_6.3V6K
V33IN 24 RSTZ CW13 CW14
1

100P_0402_50V8J
RSTZ

47P_0402_50V8J
.1U_0402_10V6-K CW12
D USB30_CRX_R_DTX_N2 CW1 1 2 USB30_CRX_C_DTX_N2 1 +3VS CW19 2 2 D
RW5 TXN 22 1
CW20

1
DP 1 2 DM DVDD33 2
USB30_CRX_R_DTX_P2 CW2 1 2 USB30_CRX_C_DTX_P2 2
0_0402_5% TXP EMC@
USB30_CTX_R_DRX_N2 .1U_0402_10V6-K 4 21 VHUSI 2 1

2
2
RXN VUHSI 1U_0402_6.3V6K CW11 Close to Pin3 and Pin28
USB30_CTX_R_DRX_P2 5 Close to Pin22
LW1 RXP 20 EMC@
SD_D2_R
USB30_CTX_C_DRX_N21 2 USB30_CTX_R_DRX_N2 SD_D2 Close to Pin21
1 2 CR_XTALI 6
X1 19 SD_D3_R
CR_XTALO 7 SD_D3
USB30_CTX_C_DRX_P24 3 USB30_CTX_R_DRX_P2 X2
4 3 18 SD_CMD_R
EMC@ SD_CMD
EXC24CH900U_4P 3 17
LW2 DVDD12 AVDD12_1 GND_1 CARD_3V3
@

Ju
USB30_CRX_DTX_N2 1 2 USB30_CRX_R_DTX_N2 28 16 SD_CLK_R
1 2 AVDD12_2 SD_CLK RSTZ 1 2
RW16
DP 26 15 SD_D0_R 100K_0402_5%

4.7U_0603_6.3V6K

.1U_0402_10V6-K
USB30_CRX_DTX_P2 4 3 USB30_CRX_R_DTX_P2 DP SD_D0
4 3 1
EMC@ DM 27 10 SD_WP CW15 1
EXC24CH900U_4P +3VS DM SD_WP
AVDD33 25 11 SD_CD# CW16

st
C AVDD33_1 SD_CDZ 2 C
FOR EMI 2 RW12
1 RTERM 8 14 SD_D1_R
2
RTERM SD_D1
680_0402_1%
FOR EMI AVDD33 9 29
SD_D0_R RW6 2 EMC@ 1 33_0402_5% SD_D0 AVDD33_2 GND_2
SD_D0_PCH RW37 2 @ 1 10_0402_1% CW3 1 2 4.7P_0402_50V8-J

for
{4} SD_D0_PCH
EMC@ GL3213L-OHY05_QFN28_4X4
SD_D1_R RW7 2 EMC@ 1 33_0402_5% SD_D1
CR_XTALI
SD_D1_PCH RW38 2 @ 1 10_0402_1% CW4 1 2 4.7P_0402_50V8-J
{4} SD_D1_PCH
EMC@ @ 2
SD_D2_R RW8 2 EMC@ 1 33_0402_5% SD_D2 RW13 1 1M_0402_5% CR_XTALO
SD_D2_PCH RW39 2 @ 1 10_0402_1% CW5 1 2 4.7P_0402_50V8-J
{4} SD_D2_PCH
@
EMC@ YW1
SD_D3_R RW9 2 EMC@ 1 33_0402_5% SD_D3
SD_D3_PCH RW40 2 @ 1 10_0402_1% CW6 1 2 4.7P_0402_50V8-J

LC

2
{4} SD_D3_PCH 3 2
EMC@ OSC2 GND1 RW14
SD_CMD_R RW10 1 EMC@ 2 22_0402_5% SD_CMD CARD_3V3
4 1 0_0402_5%
SD_CMD_PCHRW41 2 @ 1 10_0402_1% CW7 1 2 4.7P_0402_50V8-J GND2 OSC1
{4} SD_CMD_PCH
EMC@ 1 1
SD_CLK_R RW11 1 EMC@ 2 22_0402_5% SD_CLK

1
CW9 25MHZ_10PF_7V25000014 CW10 JREAD1
CW8 1 2 4.7P_0402_50V8-J
10P_0402_50V8J 10P_0402_50V8J 4
@ VDD
EMC@ @

.1U_0402_10V6-K
FC
B SD_CLK_PCHRW42 1 @ 2 0_0402_5% SD_CLK B

1
{4} SD_CLK_PCH 2 2 SD_D0 7
1

10K_0402_5%
CW221
2 4.7P_0402_50V8-J
8 DAT0
SD_D1
Close to UW1 Placement
@
RW17 CW17 SD_D2 9 DAT1
SD_D3 1 DAT2
SD_CD#_PCHRW43 1 @ 2 0_0402_5% SD_CD# 2 CD/DAT3
{4} SD_CD#_PCH
RW44 1 @ 2 0_0402_5% SD_WP FOR ESD Close to Connector

2
{7} SD_WP_PCH SD_CD# 11
SD_WP 10 C/D
W/P
CARD_3V3 Close to Connector SD_CMD 2
5 CMD

PE
SD_CLK
CLK

AZ5425-01F_DFN1006P2E2
3 12

1
+3VS CARD_3V3 VSS1 GND_1
UW2 2 6 13
DW1 VSS2 GND_2

1
5 1 EMC_NS@
IN OUT CW18 DEREN_404232501111RHF_NR
1 4.7P_0402_50V8-J
CW21 2 1 ME@
1U_0402_6.3V6K GND EMC@

2
@ 4 3
2 {4} SD_PWR_EN# EN FLG

De
SD / MMC

2
@
AP22802BW5-7_SOT25-5 Close to Connector
A A

Low Active 2A
Security Classification LC Future Center Secret Data Title
Issued Date 2014/09/24 Deciphered Date 2015/03/23 Cardreader

bu
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 30 of 59
5 4 3 2 1

www.bios-downloads.com
5 4 3 2 1

D D

Ju
st
C C

for
LC
FC
B B

PE
A

Security Classification
Issued Date 2014/09/24 De
LC Future Center Secret Data
Deciphered Date 2015/03/23
Title

Blank
A

bu
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 31 of 59
5 4 3 2 1

www.bios-downloads.com
5 4 3 2 1

D D

Ju
st
C C

for
LC
FC
B B

PE
A

Security Classification
Issued Date 2014/09/24 De
LC Future Center Secret Data
Deciphered Date 2015/03/23
Title

Blank
A

bu
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 32 of 59
5 4 3 2 1

www.bios-downloads.com
5 4 3 2 1

LCD POWER CIRCUIT CMOS Camera


W=60mils

+3VS +3VS Need short +3VS_CMOS_R


+LCDVDD_CON J1 @
1 2
U5 1 2
W=60mils JUMP_43X39
5 1
IN OUT +3VS_CMOS

33P_0402_50V8J
.1U_0402_10V6-K
C121

C122

C123
4.7U_0603_6.3V6K
C1 1 2
GND LP2301ALT1G_SOT23-3
1U_0402_6.3V6K 1 1 1
PCH_ENVDD 4 3 W=40 mils R3 W=40mils
EN FLG

D
Q7 3 1 1 2
2

.01U_0402_16V7-K
0_0603_5%

EMC_NS@
D 2 2 2 D

C6
AP22802AW5-7_SOT25-5 @ 1 1
C3 C4

G
1 1

2
C5 .1U_0402_10V6-K 10U_0603_6.3V6M
@ .1U_0402_10V6-K @
@ 2 2
2 @
PCH_ENVDD @2
{4} PCH_ENVDD
For RF R5 1 @ 2
1

{7} CMOS_ON#
100K_0402_5%
R1
100K_0402_5% 1 1
C9 C10

Ju
0.01U_0402_25V7K For EMI .1U_0402_10V6-K
EMC_NS@ Close to R5 @
2

2 2

+3VS

+3VS

st EMI request

2
R8 R9
2

100K_0402_1% 100K_0402_1% DMIC_CLK DISPOFF# INVT_PWM

470P_0402_50V7K
R10

for

470P_0402_50V7K
100P_0402_50V8J
C11

C12

C13
PCH_ENBKL R11 1 @ 2 4.7K_0402_5% @ @

1
0_0402_5% @ 1 1 1
1

EDP_AUX
R12 1 2 0_0402_5% DISPOFF# B+ +LEDVDD EDP_AUX#
{44} BKOFF# EMC@ 2 2 2
EMC_NS@
2A 80 mil 2A 80 mil EMC_NS@

2
R14 1 2 0_0402_5% ENBKL 2 R17 1
{4} PCH_ENBKL ENBKL {44}

4.7U_0805_25V6-K

0.1U_0402_25V6
0_0805_5% C14 R13 R15
1

LC
C 1 1 100K_0402_1% 100K_0402_1% C
R16
100K_0402_5% AO3401A_SOT23-3 C15 @ @

1
2 2

D
Q33 3 1 @
2

JEDP1
+LEDVDD 1
2 1
@

G
2

2
3

FC
+3VS 4 3
B+ R179 1 @ 2 LEDVDD_EN#
100K_0402_5% CPU_EDP_TX0+ C19 1 2 .1U_0402_10V6-K EDP_TX0+ 5 4
C23 0.1u for G HSW panel blink issue {4} CPU_EDP_TX0+
CPU_EDP_TX0- C16 1 2 .1U_0402_10V6-K EDP_TX0- 6 5
{4} CPU_EDP_TX0- 6
2

1
7
R18 CPU_EDP_TX1+ C17 1 2 .1U_0402_10V6-K EDP_TX1+ 8 7
R180 {4} CPU_EDP_TX1+
1K_0402_5% CPU_EDP_TX1- C18 1 2 .1U_0402_10V6-K EDP_TX1- 9 8
100K_0402_5% {4} CPU_EDP_TX1-
@ @ 10 9
CPU_EDP_AUX C20 1 2 .1U_0402_10V6-K EDP_AUX 11 10
{4} CPU_EDP_AUX
1

Q34 11

2
CPU_EDP_AUX# C21 1 2 .1U_0402_10V6-K EDP_AUX# 12
1 {4} CPU_EDP_AUX# 12
R19 1 2 0_0402_5% INVT_PWM 13
{4} PCH_EDP_PWM D 13

PE
DISPOFF# 14
PCH_ENVDD R181 1 @ 2 2 15 14
0_0402_5% 15
1

G INVT_PWM 16
R20 1 S 17 16
100K_0402_5% C132 @ +3VS 18 17
.1U_0402_10V6-K 3 18
PJA138K_SOT23-3 19
@ {4} CPU_EDP_HPD 19
2 R21 1 @ 2 20
2

0_0402_5% 21 20
1 +LCDVDD_CON 21
W=60mils 22
C22 23 22
Reserve for power consumption test 680P_0402_50V7K
+3VS
24 23

De
2 {43} DMIC_DATA 24
@ {43} DMIC_CLK 25
26 25 31
27 26 G1 32
R182 1 2 0_0402_5% HUSB20_P1_R 28 27 G2 33
{8} USB20_P4 28 G3
{8} USB20_N4 R183 1 2 0_0402_5% HUSB20_N1_R 29 34
B 30 29 G4 35 B
+3VS_CMOS 30 G5
2
W=40mils ACES_50406-03071-001

bu
C24 ME@
0.047U_0402_16V7K
1
EMC_NS@

EMI request

L12
g For EMI
EMC_NS@
USB20_P4 4 3 HUSB20_P1_R
4 3

USB20_N4 1 2 HUSB20_N1_R
1 2
EXC24CH900U_4P

A A

Security Classification
Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 eDP/ CMOS/Touch screen
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 33 of 60

5 4 3 2 1
5 4 3 2 1

+5VALW
+5VS_HDMI
D8
L2 EMC@ EMC@ BAT54AW_SOT323-3

1
HDMI_CLK-_C 1 2 HDMI_CLK-_CON 1 2
1 2 RP11

2
C26 3.3P_0402_50V8-C
EMC@ RC25 RC26 HDMICLK_R 4 1
HDMI_CLK+_C 4 3 HDMI_CLK+_CON 1 2 0_0402_5% 0_0402_5% HDMIDAT_R 3 2
4 3 C27 3.3P_0402_50V8-C
+1.8VALW @
EXC24CH900U_4P +1.8VALW 2.2K_0404_4P2R_5%

2
1

1
L3 EMC@ EMC@ +5VS_HDMI
D HDMI_TX0-_C 1 2 HDMI_TX0-_CON 1 2 @ D
1 2 C28 3.3P_0402_50V8-C
EMC@ RP9

3
4
HDMI_TX0+_C 4 3 HDMI_TX0+_CON 1 2 2.2K_0404_4P2R_5%
4 3

3
4
C29 3.3P_0402_50V8-C
RP10
EXC24CH900U_4P

G2 5
2.2K_0404_4P2R_5%
L4 EMC@ EMC@

2
1
HDMI_TX1-_C 1 2 HDMI_TX1-_CON 1 2

2
1
1 2 C30 3.3P_0402_50V8-C 4 S2 D2 3 HDMICLK_R_Q

5
{4} DDPB_CLK

G
EMC@

Ju
HDMI_TX1+_C 4 3 HDMI_TX1+_CON 1 2 Q3402B
4 3 C31 3.3P_0402_50V8-C
Q3401B

2
EXC24CH900U_4P HDMICLK_R_Q 3 4 HDMICLK_R
PJT138K_SOT363-6

S
G1
@

D
L5 EMC@ EMC@
HDMI_TX2-_C 1 2 HDMI_TX2-_CON 1 2 HDMIDAT_R_Q 2N7002KDWH_SOT363-6
{4} DDPB_DATA 1 S1 D1 6

st
1 2 C32 3.3P_0402_50V8-C RC54 1 2 0_0402_5%
EMC@

2
G
HDMI_TX2+_C 4 3 HDMI_TX2+_CON 1 2
4 3 Q3401A Q3402A
C33 3.3P_0402_50V8-C
EXC24CH900U_4P PJT138K_SOT363-6
HDMIDAT_R_Q 6 1 HDMIDAT_R

S
for
@

D
2N7002KDWH_SOT363-6
For EMC

RC55 1 2 0_0402_5%

+1.8VALW

LC
C C
RP12
HDMI_CLK-_C
HDMI_CLK+_C
1
2
4
3
R4602 change from 10K to 1K,
619_0404_4P2R_1% as Vienna +5VS
+5VS +5VS_HDMI_F +5VS_HDMI
RP13

2
HDMI_TX0-_C 1 4 D5 @

2
HDMI_TX0+_C 2 3 R3405 D4 2 F1
619_0404_4P2R_1% 1K_0402_1% 1 1 2

FC
3
RP14
HDMI_TX1-_C 1 4 EMC_NS@ RB491D_SOT23-3 0.5A_8V_KMC3S050RY

1
HDMI_TX1+_C 2 3
619_0404_4P2R_1% BAT54S-7-F_SOT23-3

1
{4} HDMI_HPD
RP15 D4 LP2301ALT1G_SOT23-3
HDMI_TX2-_C 1 4 1
1 3 Q32 C34

S
HDMI_TX2+_C 2 3

1
619_0404_4P2R_1% D .1U_0402_10V6-K
Q12 2
G 2
2N7002KW_SOT323-3

PE

G
2
1

D Q13

2
2 S

3
+3VS {46} SUSP
G 2N7002KW_SOT323-3 R41
100K_0402_5%
S JHDMI1
3

HDMI_DET 19

1
18 HP_DET
R42 1 @ 2 +5V
17
HDMIDAT_R 16 DDC/CEC_GND
100K_0402_5% SDA
HDMICLK_R 15

De
14 SCL
13 Reserved
HDMI_CLK- C35 2 1 .1U_0402_10V6-K HDMI_CLK-_C R43 2 @ 1 0_0402_5% HDMI_CLK-_CON 12 CEC 20
{4} HDMI_CLK- CK- GND1
11 21
B
HDMI_CLK+ C36 2 1 .1U_0402_10V6-K HDMI_CLK+_C R44 2 @ 1 0_0402_5% HDMI_CLK+_CON 10 CK_shield GND2 B
{4} HDMI_CLK+ CK+
HDMI_TX0- C37 2 1 .1U_0402_10V6-K HDMI_TX0-_C R45 2 @ 1 0_0402_5% HDMI_TX0-_CON 9 22
{4} HDMI_TX0- D0- GND3
8 23
2 1 .1U_0402_10V6-K HDMI_TX0+_C R46 2 D0_shield GND4

bu
HDMI_TX0+ C38 @ 1 0_0402_5% HDMI_TX0+_CON 7
{4} HDMI_TX0+ D0+
HDMI_TX1- C39 2 1 .1U_0402_10V6-K HDMI_TX1-_C R47 2 @ 1 0_0402_5% HDMI_TX1-_CON 6
{4} HDMI_TX1- D1-
5
HDMI_TX1+ C40 2 1 .1U_0402_10V6-K HDMI_TX1+_C R48 2 @ 1 0_0402_5% HDMI_TX1+_CON 4 D1_shield
{4} HDMI_TX1+ D1+
HDMI_TX2- C41 2 1 .1U_0402_10V6-K HDMI_TX2-_C R49 2 @ 1 0_0402_5% HDMI_TX2-_CON 3
{4} HDMI_TX2- D2-
2
HDMI_TX2+ C42 2 1 .1U_0402_10V6-K HDMI_TX2+_C R50 2 @ 1 0_0402_5% HDMI_TX2+_CON 1 D2_shield
{4} HDMI_TX2+ D2+

g
FOX_QJ111A1-RC0AH1-8H
ME@

D3
HDMI_DET 1 1 10 9 HDMI_DET
Close to JHDMI1 2 2
HDMIDAT_R 9 8 HDMIDAT_R
D6 D7 4 4
HDMICLK_R 7 7 HDMICLK_R
HDMI_CLK+_CON 1 1 10 9 HDMI_CLK+_CON HDMI_TX1-_CON 1 1 10 9 HDMI_TX1-_CON
+5VS_HDMI 5 5 6 6 +5VS_HDMI
HDMI_CLK-_CON 2 2 9 8 HDMI_CLK-_CON HDMI_TX1+_CON 2 2 9 8 HDMI_TX1+_CON
3 3
HDMI_TX0+_CON 4 4 7 7 HDMI_TX0+_CON HDMI_TX2-_CON 4 4 7 7 HDMI_TX2-_CON
8
HDMI_TX0-_CON 5 5 6 6 HDMI_TX0-_CON HDMI_TX2+_CON 5 5 6 6 HDMI_TX2+_CON
A A
3 3 3 3 AZ1045-04F_DFN2510P10E-10-9
8 8 EMC_NS@

For EMC
AZ1045-04F_DFN2510P10E-10-9 For EMC AZ1045-04F_DFN2510P10E-10-9
EMC_NS@ EMC_NS@ Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 HDMI_CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 34 of 60
5 4 3 2 1
5 4 3 2 1

+3VS +DP_3V3

+IVDDO +RX_AVCC
RVG16 1 2 0_0603_5%

1 LVG2 1 2

.1U_0402_10V6-K
BLM15PD600SN1D_2P
CVG8 +DP_3V3 +DP_3V3 +IVDDO +RX_IVDD
1 1

CVG15
10U_0805_10V6K
D 2 CVG10 D

10U_0603_6.3V6M
2 2

10
40

29
30

32

11
20
37
39
UVG1 +DDCP

IVDDO
OVDD_1
OVDD_2

IVDD33_1
IVDD33_2

IVDD_1
IVDD_2
IVDD_3
IVDD_4
DP_VGA_HPD 33
{4} DP_VGA_HPD HPD
38 +IVDDO +RX_IVDD

Ju
CVG3 1 2 .1U_0402_10V6-K DRX0P 22 MCUVDDH
{4} VGA_TX0+ RX0P
CVG2 1 2 .1U_0402_10V6-K DRX0N 23
{4} VGA_TX0- RX0N RVG19 1 2 0_0603_5%

.1U_0402_10V6-K
CVG4 1 2 .1U_0402_10V6-K DRX1P 25
{4} VGA_TX1+ RX1P
CVG5 1 2 .1U_0402_10V6-K DRX1N 26 1
{4} VGA_TX1- RX1N

CVG16
st
24 @1 TVG1
URDBG
12 2
ISPSCL 13
CVG6 1 2 .1U_0402_10V6-K AUXP 19 ISPSDA
{4} VGA_AUX RXAUXP
CVG7 1 2 .1U_0402_10V6-K AUXN 18 17
{4} VGA_AUX# RXAUXN VGADDCCLK 16 CRT_DDC_CLK {36}

for
+DP_3V3 VGADDCSDA CRT_DDC_DAT {36}
15 1 VGA_VS
14 DCAUXP VSYNC 2 VGA_HS VGA_VS {36}
DCAUXN HSYNC VGA_HS {36}
+IVDDO +DAC_VDDC

+RX_AVCC +DAC_VDDC
LVG4 1 2

4.7U_0805_25V6-K
LC
C C

.1U_0402_10V6-K
21 6 BLM15PD600SN1D_2P CVG11
27 AVCC_1 VDDC
AVCC_2 1 1

CVG17
IT6515FN 2 2
9 CRT_R
IORP CRT_R {36}

FC
8 CRT_G
IOGP CRT_G {36}

7 CRT_B
IOBP CRT_B {36}
34
NC_2
3 RVG3 1 2 200_0402_1%
28 RSET
+DAC_VDDC RVG3 closed to pin3

PE
ASPVCC
5
VDDA
+DDCP
RPVG1 4
3 2 36 NC_1
4 1 35 PCSDA
PCSCL
+DP_3V3 +5VS_HDMI_F
2.2K_0404_4P2R_5%

PWD
De
GND
RVG1 1 2 0_0402_5% +DDCP
IT6515FN-BX-0050_QFN40_5X5 CRT_R

31

41
B B

RVG2 1 2 0_0402_5%
1
CRT_G
@

TVG2
@

bu CRT_B

1
RVG25 RVG26 RVG27

g
+DP_3V3 75_0402_1% 75_0402_1% 75_0402_1%

2
2
1

RPVG2 CLOSE TO UVG1


2.2K_0404_4P2R_5%
CD@
3
4

CRT_DDC_CLK

CRT_DDC_DAT

A A

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 DP to CRT Convert(IT6515FN)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 35 of 59
5 4 3 2 1
5 4 3 2 1

+DP_3V3 +5VS_HDMI_F

CRT Connector

2
1
G
+CRT_VCC_CON +5VS_HDMI
QVG1B RPVG3
2.2K_0404_4P2R_5% +5VS
+CRT_VCC RVG39 1 2 0_0603_5%
CRT_DDC_CLK 4 3 CRT_DDC_CLK_R

3
4
{35} CRT_DDC_CLK DVG1

D
CD@ CRT_DDC_CLK_R @ 2 FVG1
2N7002KDWH_SOT363-6 1 1 2 @ +CRT_VCC_CON

2
G
CRT_DDC_DAT_R 3 1
D QVG1A D
PMEG2010ET_SOT23-3 0.5A_8V_KMC3S050RY

1
CVG34
.1U_0402_10V6-K DVG2
W=40mils

1
CRT_DDC_DAT 1 6 CRT_DDC_DAT_R 2

S
{35} CRT_DDC_DAT 1 1 AZ5425-01F_DFN1006P2E2

D
CD@
CD@
2N7002KDWH_SOT363-6 CVG43 CVG44
100P_0402_50V8J 68P_0402_50V8J EMC_NS@
CRT_DDC_CLK RVG5 1 2 0_0402_5% CRT_DDC_CLK_R 2 2
@ @

2
CRT_DDC_DAT RVG4 1 2 0_0402_5% CRT_DDC_DAT_R

2
JCRT1
6

Ju
11
LVG6 1 2 EMC@ CRT_R_CON 1
{35} CRT_R 7
BLM15BA220SN1D_2P For EMC
CRT_DDC_DAT_R 12
LVG7 1 2 EMC@ CRT_G_CON 2
{35} CRT_G 8
BLM15BA220SN1D_2P

st
HSYNC_CON 13
LVG8 1 2 EMC@ CRT_B_CON 3
{35} CRT_B 9
BLM15BA220SN1D_2P

15P_0402_50V8J

15P_0402_50V8J

15P_0402_50V8J

15P_0402_50V8J

15P_0402_50V8J

15P_0402_50V8J
CVG35

CVG36

CVG37

CVG38

CVG39

CVG40
VSYNC_CON 14
1 1 1 1 1 1 4
10 G 16
CRT_DDC_CLK_R 15 17

for
G
5
2 2 2 2 2 2
1
CVG41 SUYIN_070546HR015M25KZR
EMC@ EMC@ EMC@ EMC@ EMC@ EMC@
100P_0402_50V8J ME@
@
2

LC
C C

FC
PE
VGA_HS RVG32 1 2 33_0402_5% HSYNC_CON
{35} VGA_HS

1
CVG42
10P_0402_50V8J
2

De B

{35} VGA_VS
VGA_VS RVG33 1 2 33_0402_5%
bu
VSYNC_CON

g
1
CVG45
10P_0402_50V8J
2

DVG3 DVG4
CRT_B_CON 1 1 10 9 CRT_B_CON VSYNC_CON 1 1 10 9 VSYNC_CON

CRT_G_CON 2 2 9 8 CRT_G_CON HSYNC_CON 2 2 9 8 HSYNC_CON

CRT_R_CON 4 4 7 7 CRT_R_CON CRT_DDC_CLK_R 4 4 7 7 CRT_DDC_CLK_R

5 5 6 6 CRT_DDC_DAT_R 5 5 6 6 CRT_DDC_DAT_R

3 3 3 3
A A
8 8

AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
EMC_NS@ EMC_NS@
For EMC
Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 CRT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 36 of 59
5 4 3 2 1
5 4 3 2 1

+3VALW TO +3VALW_LAN
+3VALW_LAN rising time (10%~90%):
+3VALW +3VALW_LAN
0.5ms<spec<100ms +3VALW_LAN +LAN_VDDREG
Need short
RL1 @
JL1 1 2 @ width : 40 mils 1 2
1 2
JUMP_43X79 0_0603_5%
D D
1 1
+3VALW LP2301ALT1G_SOT23-3 CL1 CL2

.1U_0402_10V6-K

.1U_0402_10V6-K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1 1 1 1 4.7U_0603_6.3V6K .1U_0402_10V6-K

D
Q14 3 1 @ CL4 CL5 CL6 CL7

.1U_0402_10V6-K

.01U_0402_16V7-K
1
2 2
@
RL2 1 1
100K_0402_5% CL8 CL9 @ 2 @ 2 2 2 CD@

G
2
@
2

2 2
RL3 1 @ 2 @ @
{44} LAN_PWR_ON#

Ju
47K_0402_5%
Close to Pin11 Close to Pin32 Close to Pin11 Close to Pin32
+3VALW_LAN +3VS

+3VALW_LAN

st

2
RL4

G
manual change the Codec PN to RTL8111H-CG QFN
2
10K_0402_5% @ QL1
RL5
10K_0402_5% UL1

1
@ LAN_CLKREQ#_R 1 3 @

for
LAN_CLKREQ# {6}

S
1

2N7002KW_SOT323-3
RL7 1 @ 2 0_0402_5% PCIE_WAKE#_R
{7,40,44} PCIE_WAKE#
{40,44} LAN_WAKE# RL6 1 2 0_0402_5%
33 RL18 1 2 0_0402_5%
C +3VALW_LAN 32 GND 16 CLK_PCIE_LAN# C
1 2 RSET 31 AVDD33_2 REFCLK_N 15 CLK_PCIE_LAN CLK_PCIE_LAN# {6}
RL8
30 RSET REFCLK_P 14 CLK_PCIE_LAN {6}
2.49K_0402_1% +LAN_VDD10 PCIE_PTX_C_DRX_N3
29 AVDD10 HSIN 13 PCIE_PTX_C_DRX_N3 {6}
LAN_XTALO PCIE_PTX_C_DRX_P3

LC
CKXTAL2 HSIP PCIE_PTX_C_DRX_P3 {6}
LAN_XTALI 28 12 LAN_CLKREQ#_R
+3VS TL3 @ 1 27 CKXTAL1 CLKREQB 11 +3VALW_LAN
@ LED0 AVDD33_1
LAN_PWR_ON# RL121 2 LAN_DISABLE# 26 10 LAN_MDI3-
LED1/GPIO MDIN3 LAN_MDI3- {38}
0_0402_5% TL4 @ 1 25 9 LAN_MDI3+
LED2 MDIP3 LAN_MDI3+ {38}
1

+LAN_REGOUT 24 8 +LAN_VDD10
RL9 +LAN_VDDREG 23 REGOUT AVDD10_2 7 LAN_MDI2-
22 VDDREG MDIN2 6 LAN_MDI2- {38}
1K_0402_1% +LAN_VDD10 LAN_MDI2+
DVDD10 MDIP2 LAN_MDI2+ {38}

FC
PCIE_WAKE#_R 21 5 LAN_MDI1-
LANWAKEB MDIN1 LAN_MDI1- {38}
ISOLATE# 20 4 LAN_MDI1+
2

19 ISOLATEB MDIP1 3 LAN_MDI1+ {38}


PLT_RST# +LAN_VDD10
{7,19,40,44,45} PLT_RST# PERSTB AVDD10_1
{6} PCIE_PRX_DTX_N3 CL10 1 2 .1U_0402_10V6-K PCIE_PRX_C_DTX_N3 18 2 LAN_MDI0-
HSON MDIN0 LAN_MDI0- {38}
ISOLATE# RL10 1 @ 2 LAN_PWR_ON#
{6} PCIE_PRX_DTX_P3 CL11 1 2 .1U_0402_10V6-K PCIE_PRX_C_DTX_P3 17 1 LAN_MDI0+
HSOP MDIP0 LAN_MDI0+ {38}
0_0402_5% CL10 close to Pin18
1

RL11 CL11 close to Pin17


15K_0402_5%

PE
@
2

RTL8111H-CG QFN 32P

B B

YL1
LAN_XTALI

LAN_XTALO
For RTL8111H (LDO mode)
De
+LAN_VDD10

bu
1 4
OSC1 GND2 +LAN_REGOUT RL20 1 2 0_0805_5%
2 3
GND1 OSC2 @
LL1 1 2 1 1 1 1 1 1 1 1
1 XTAL@ 1 2.2UH_NLC252018T-2R2J-N_5%
CL15 CL16 CL17 CL18 CL19 CL20 CL21 CL22

g
CL12 25MHZ_10PF_7V25000014 CL13 4.7U_0603_6.3V6K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K 1U_0402_6.3V6K .1U_0402_10V6-K
XTAL@ XTAL@ 2 2 2 2 2 2 2 @ 2 @
12P_0402_50V8-J 12P_0402_50V8-J @ @
2 2

Close to Pin3, 8, 22, 30 Close to Pin22(Reserved)


Layout Note: LL1 must be
R_CLK@ within 200mil to Pin24,
{17} 25M_CLK RL19 1 2 0_0402_5% LAN_XTALI CL15,CL16 must be within
200mil to LL1
+LAN_REGOUT: Width =60mil
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/09/24 Deciphered Date 2015/03/23 LAN_RTL8111GUL/RTL8106EUL


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 37 of 60
5 4 3 2 1

www.bios-downloads.com
5 4 3 2 1

DL1/DL2
1'S PN:SC400007R00
TL1
24 1 MCT
D MCT1 TCT1 D
LAN_MDI0- 23 2 LAN_MDO0-
{37} LAN_MDI0- MX1+ TD1+
DL1 EMC_NS@
LAN_MDI2+ 1 10 LAN_MDI2+ LAN_MDI0+ 22 3 LAN_MDO0+
Tx1+In Tx1+Out {37} LAN_MDI0+ MX1- TD1-

1
LAN_MDI2- 2 9 LAN_MDI2-
Tx1-In Tx1-Out 21 4 MCT RL17
3 8 MCT2 TCT2 20_0603_5%
GND1 GND2

1
LAN_MDI1- 20 5 LAN_MDO1-
{37} LAN_MDI1- MX2+ TD2+
LAN_MDI3- 4 7 LAN_MDI3- DL3

1
2
LAN_MDI3+ 5 Tx2+In Tx2+Out 6 LAN_MDI3+ LAN_MDI1+ 19 6 LAN_MDO1+ PDT5061_DO-214AA

Ju
Tx2-In Tx2-Out {37} LAN_MDI1+ MX2- TD2- EMC@

2
11 18 7 MCT
GND3 12 MCT3 TCT3

2
GND4 13 LAN_MDI2+ 17 8 LAN_MDO2+
GND5 {37} LAN_MDI2+ MX3+ TD3+ EMC@

st
LAN_MDI2- 16 9 LAN_MDO2-
{37} LAN_MDI2- MX3- TD3-
RCLAMP3374N.TCT_SLP3020N10-10
15 10 MCT
MCT4 TCT4
1 1
Place Close to TL1 LAN_MDI3+ 14 11 LAN_MDO3+
{37} LAN_MDI3+ MX4+ TD4+

68P_0402_50V8J
DL2 EMC_NS@ CL32 CL25

for
LAN_MDI1- 1 10 LAN_MDI1- 1 LAN_MDI3- 13 12 LAN_MDO3- 0.022U_0603_50V7K 1000P_1206_2KV7-K
Tx1+In Tx1+Out {37} LAN_MDI3- MX4- TD4- 2 2

CL24
LAN_MDI1+ 2 9 LAN_MDI1+ EMC@ EMC_NS@
Tx1-In Tx1-Out
C C
3 8 BOTHHAND GST5009 LF LAN
GND1 GND2 2
LAN_MDI0+ 4 7 LAN_MDI0+
LAN_MDI0- 5 Tx2+In Tx2+Out 6 LAN_MDI0- EMC@

LC
Tx2-In Tx2-Out
11
GND3 12 CHASSIS1_GND
GND4 13
GND5

FC
RCLAMP3374N.TCT_SLP3020N10-10

Place Close to TL2

JRJ1 ME@
12
GND_4

PE
11
GND_3
10
LAN_MDO0+ 1 GND_2
PR1+ 9
B B
LAN_MDO0- 2 GND_1
PR1-
LAN_MDO1+ 3

De
CL27 1 @ 2 0_0402_5% PR2+ CHASSIS1_GND
LAN_MDO2+ 4
CL28 1 @ 2 0_0402_5% PR3+
LAN_MDO2- 5
CL29 1 @ 2 0_0402_5% PR3-
LAN_MDO1- 6
PR2-

bu
LAN_MDO3+ 7
PR4+
CHASSIS1_GND LAN_MDO3- 8
Reserve for EMI go rural solution PR4-

g
SANTA_130460-3

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2014/09/24 Deciphered Date 2015/03/23 LAN_Transformer
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 38 of 60
5 4 3 2 1

www.bios-downloads.com
5 4 3 2 1

Near GPU&VRAM REMOTE+


Near CPU core
Close to U3901 1

1
C46 C
REMOTE+ 100P_0402_50V8J 2 Q16
1 @ B MMBT3904WH_SOT323-3
C44 2 E TM_SENSOR@

3
2200P_0402_50V7K REMOTE-
TM_SENSOR@
2 REMOTE-
REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-: +3VALW Baytrail SOC use thermal sensor to read the thermal,
D
Trace width/space:10/10 mil Baytrail don't has PECI signal D
Trace length:<8"

1
SMSC thermal sensor R98
13.7K_0402_1%
+3VALW
Near CPU
placed near DIMM OPT@

2
NTC_V1

1
+3VS

Ju
R95

1
U3901 13.7K_0402_1%
1 8 EC_SMB_CK2 PH2
VDD SCL EC_SMB_CK2 {19,44}
100K_0402_1%_NCP15WF104F03RC
REMOTE+ 2 7 EC_SMB_DA2 OPT@

2
1 D+ SDA EC_SMB_DA2 {19,44} NTC_V2

2
C47 REMOTE- 3 6

1
st
.1U_0402_10V6-K D- ALERT#
PH1

2
@ 2 R51 2 @ 1 4 5
+3VS T_CRIT# GND 100K_0402_1%_NCP15WF104F03RC
10K_0402_5% R99 R100
NCT7718W_MSOP8 0_0402_5% 0_0402_5%
OPT@

2
TM_SENSOR@ @

for

2
Address 1001_100xb
R96 R97
EC_AGND 0_0402_5% 0_0402_5%
+5VLP +5VLP @
+5VLP

1
LC
C C
HW thermal sensor

2
EC_AGND
C140 R93 R94
1

0.1U_0402_25V6 21.5K_0402_1% 21.5K_0402_1%


@ @
@
2

1
@

FC
U3902
1 8 TMSNS1 R91 1 @ 2 0_0402_5% NTC_V1
VCC TMSNS1 NTC_V1 {44}
2 7 PHYST1 R89 1 @ 2 10K_0402_5%
GND RHYST1
3 6 TMSNS2 R92 1 @ 2 0_0402_5% NTC_V2
{54} EC_ON_R OT1 TMSNS2 NTC_V2 {44}
4 5 PHYST2 R90 1 @ 2 10K_0402_5%
OT2 RHYST2

PE
G718TM1U_SOT23-8

over temperature threshold:


RSET=3*RTMH
92+/-30C
Hysteresis temperature threshold.
RHYST=(RSET*RTML)/(3*RTML-RSET)

B
56+/-30C

De B

FAN Conn
bu
+5VS
@ JFAN1
g
R52 1 2 0_0603_5% +5VS_FAN 1
2 1
{44} EC_FAN_SPEED 2
1 1 3
C3901 4 3
{44} EC_FAN_ANTI 4
C49 .1U_0402_10V6-K {44} EC_FAN_PWM 5
10U_0805_10V6K @ 6 5
2 2 7 GND1
@ GND2

A
ACES_50273-0050N-001 A
ME@

JFAN1 Pin defin need check other G Title


Security Classification LC Future Center Secret Data
Issued Date 2014/09/24 Deciphered Date 2015/03/23 Thermal sensor/FAN CONN

www.bios-downloads.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 39 of 60

5 4 3 2 1
A B C D E

Mini-Express Card(WLAN/WiMAX) +3VS_WLAN

JWLAN1
+3VS Need short +3VS_WLAN
J2 @ 1 2
1 2 3 GND1 3.3VAUX1 4
1 2 {8} USB20_P3 5 USB_D+ 3.3VAUX2 6 1 @ T2
{8} USB20_N3 USB_D- LED#1
JUMP_43X79 7 8
9 GND2 PCM_CLK 10
11 SDIO_CLK PCM_SYNC 12
+3VALW LP2301ALT1G_SOT23-3 13 SDIO_CMD PCM_IN 14
15 SDIO_DAT0 PCM_OUT 16 1 @ T3
SDIO_DAT1 LED#2

D
Q17 3 1 AOAC@ 17 18
1 SDIO_DAT2 GND11 1

.01U_0402_16V7-K
19 20
21 SDIO_DAT3 UART_WAKE 22 @
1 1 1 UART_RX_DEBUG_R R256 1 2 0_0402_5%
SDIO_WAKE UART_RX UART_RX_DEBUG {8}
C51 C52 C53 23

G
2
.1U_0402_10V6-K @ .1U_0402_10V6-K SDIO_RESET
@ AOAC@
2 2 2
R54 1 AOAC@ 2 KEY E
{44} AOAC_ON# 25 PIN24~PIN31 NC PIN 24
1
100K_0402_5% C54 27 26
.1U_0402_10V6-K 29 28
AOAC@ 31 30
2

Ju
33 32 UART_TX_DEBUG_R R257 1 @ 2 0_0402_5%
35 GND3 UART_TX 34 UART_TX_DEBUG {8}
{6} PCIE_PTX_C_DRX_P4 PETP0 UART_CTS
37 36
{6} PCIE_PTX_C_DRX_N4 PETN0 UART_RTS
39 38 EC_TX_RSVD R62 1 @ 2 0_0402_5% EC_TX_R
41 GND4 RSRVD10 40 EC_RX_RSVD R63 1 @ 2 0_0402_5% BT_OFF#
{6} PCIE_PRX_DTX_P4 PERP0 RSRVD11
43 42
{6} PCIE_PRX_DTX_N4 45 PERN0 RSRVD9 44
47 GND5 COEX3 46

st
{6} CLK_PCIE_WLAN REFCLKP0 COEX2
49 48
{6} CLK_PCIE_WLAN# 51 REFCLKN0 COEX1 50 SUSCLK
GND6 SUSCLK SUSCLK {7}
WLAN_CLKREQ_Q# 53 52 PLT_RST#
55 CLKEQ0# PERSTO# 54 1 2 1K_0402_1% PLT_RST# {7,19,37,44,45}
BT_OFF# R53
{7,37,44} PCIE_WAKE# PEWAKE0# RSRVD/W_DISABLE#2 PCH_BT_OFF# {44}
57 56 PCH_WLAN_OFF#
GND7 W_DISABLE#1 PCH_WLAN_OFF# {44}
R57 1 @ 2 0_0402_5%
{37,44} LAN_WAKE#

for
59 58 SMB_DATA_S3_R R58 1 @ 2 0_0402_5%
+3VS 61 RSRVD/PETP1 I2C_DATA 60 1 2 0_0402_5% SMB_DATA_S3 {7,14}
SMB_CLK_S3_R R59 @
+3VS_WLAN RSRVD/PETN1 I2C_CLK SMB_CLK_S3 {7,14}
63 62 1 @ T4
65 GND8 ALERT 64 EC_TX_R EC_TX_R R184 1 2 100_0402_1%
67 RSRVD/PERP1 RSRVD6 66 EC_TX {44}
RERVD/PERN1 RSRVD7
2

69 68 +3VS_WLAN BT_OFF# R185 1 2 100_0402_1%


EC_RX {44}
2

R60 71 GND9 RSRVD8 70


G

Q18 73 RSRVD1 RSRVD12 72


10K_0402_5%

1
75 RSRVD2 3.3VAUX3 74
GND10 3.3VAUX4 R186
1

AOAC@ 3 1 WLAN_CLKREQ_Q# 77 76 100K_0402_5%

LC
2 {6} WLAN_CLKREQ# 2
GND15 GND14
S

2N7002KW_SOT323-3

2
LCN_DAN05-67406-0102
ME@
R61 1 2 0_0402_5%

If support AOAC, NC R61;

FC
if not support AOAC, stuff R61.

PE
3

De 3

bu
g
4 4

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 NGFF WLAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 40 of 60
A B C D E
A B C D E

LEFT SIDE USB3.0 PORT X1 C55 1 2 @

+
+USB_VCCA 220U_6.3V_M

+5VALW +USB_VCCA C56 1 2


U2 22U_0603_6.3V6-M
5 1
1 IN OUT C57 1 2 1
1 @ 470P_0402_50V7K
C58 2
1U_0402_6.3V6K GND 1 2 C25
@ 22U_0805_6.3V6M
{44,45} USB_ON# 4 3 USB_OC0#
2 EN FLG USB_OC0# {8} JUSB1 ME@
USB30_TX_P0 C59 1 2 .1U_0402_10V6-K USB30_TX_C_P0 R4614 1 @ 2 0_0402_5% USB30_TX_R_P0 9
{8} USB30_TX_P0
1 1 StdA_SSTX+
AP22802BW5-7_SOT25-5 C61 VBUS
USB30_TX_N0 C60 1 2 .1U_0402_10V6-K USB30_TX_C_N0 R4612 1 @ 2 0_0402_5% USB30_TX_R_N0 8
1000P_0402_50V7K {8} USB30_TX_N0
USB20_P0 R4615 1 @ 2 0_0402_5% USB20_P0_R 3 StdA_SSTX-
Low Active 2A EMC_NS@ {8} USB20_P0
7 D+

Ju
2
USB20_N0 R4613 1 @ 2 0_0402_5% USB20_N0_R 2 GND_DRAIN 10
{8} USB20_N0
USB30_RX_P0 R4611 1 @ 2 0_0402_5% USB30_RX_R_P0 6 D- GND_1 11
{8} USB30_RX_P0
4 StdA_SSRX+ GND_2 12
USB30_RX_N0 R4610 1 @ 2 0_0402_5% USB30_RX_R_N0 5 GND_5 GND_3 13
{8} USB30_RX_N0 StdA_SSRX- GND_4

st
SUYIN_020053GR009M2736L

USB20_P0_R

for
D22 EMC_NS@ +USB_VCCA
L16 EMC@ USB30_RX_R_N0 9 10 1 1USB30_RX_R_N0 USB20_N0_R
USB30_RX_N0 2 1 USB30_RX_R_N0

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2
2 1 USB30_RX_R_P0 8 2 USB30_RX_R_P0
9 2

1
D9 D10 D11
USB30_RX_P0 3 4 USB30_RX_R_P0 USB30_TX_R_N0 7 7 4 4 USB30_TX_R_N0

1
3 4
EXC24CH900U_4P USB30_TX_R_P0 6 5 USB30_TX_R_P0

LC
2 6 5 2

3 3
L15 EMC@

2
USB30_TX_C_N0 2 1 USB30_TX_R_N0 8
2 1 EMC_NS@ EMC_NS@ EMC_NS@

2
AZ1045-04F_DFN2510P10E-10-9
USB30_TX_C_P0 3 4 USB30_TX_R_P0

FC
3 4
EXC24CH900U_4P

L8 EMC@
USB20_P0 1 2 USB20_P0_R
1 2

PE
USB20_N0 4 3 USB20_N0_R
4 3
EXC24CH900U_4P

3
For EMC
De 3

bu
g
4 4
For EMC

Security Classification
Classification LC Future Center Secret Data Title

Issued Date 2014/09/24 Deciphered Date 2015/03/23 USB2.0/USB3.0 PORT (LEFT)

www.bios-downloads.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 41 of 60

A B C D E
A B C D E F G H

SATA HDD Conn.


FOR 14"
JHDD1 ME@

1
SATA ODD Conn.
SATA_PTX_DRX_P0 C66 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P0 2 GND_1
{6} SATA_PTX_DRX_P0 A+
{6} SATA_PTX_DRX_N0 SATA_PTX_DRX_N0 C67 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N0 3
4 A-
1 SATA_PRX_DTX_N0 C68 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N0 5 GND_2 1
{6} SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C69 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P0 6 B- JODD1
{6} SATA_PRX_DTX_P0 7 B+ 1
GND_3 SATA_PTX_DRX_P1 14@ C70 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P1_14 2 GND_1
{6} SATA_PTX_DRX_P1 RX+
{6} SATA_PTX_DRX_N1 SATA_PTX_DRX_N1 14@ C71 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N1_14 3
8 4 RX-
9 V33_1 SATA_PRX_DTX_N1 14@ C72 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N1_14 5 GND_2
SATA0_DEVSLP 10 V33_2 {6} SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 14@ C73 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P1_14 6 TX-
{6} SATA0_DEVSLP +5VS V33_3 {6} SATA_PRX_DTX_P1 TX+
11 7
Need short +5VS_HDD 12 GND_4 GND_3
J3 @ 13 GND_5 ODD_DETECT# 8

Ju
1 2 14 GND_6 9 DP
1 2 15 V5_1 +5V_ODD 10 +5V_1
JUMP_43X79 16 V5_2 ODD_DA#_R 11 +5V_2 14
17 V5_3 12 MD GND1 15
18 GND_7 13 GND_4 GND2
19 DAS/DSS 26 GND_5

st
+5VS_HDD 20 GND_8 GND_12 25 SUYIN_127382FB013S255ZL
21 V12_1 GND_11 24 ME@
22 V12_2 GND_10 23
V12_3 GND_9
1 1 1 1 1
C74 C75 C77 C78 LCN_ASF98-2231S10-0002

for
1000P_0402_50V7K .1U_0402_10V6-K C76 10U_0805_10V6K 10U_0805_10V6K
1U_0402_6.3V6K @
2 2 2 2 2
@ @
CD@ FOR 15"
2 2

For EMC SATA ODD FFC Conn

LC SATA_PTX_DRX_P1 15@ C79 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P1_15 1


JODD2

FC
SATA_PTX_DRX_N1 15@ C80 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N1_15 2 1
3 2
SATA_PRX_DTX_N1 15@ C81 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N1_15 4 3
SATA_PRX_DTX_P1 15@ C82 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P1_15 5 4
6 5
ODD_DETECT# 7 6
8 7
+5V_ODD 9 8
9

2
ODD_DA#_R 10

PE
R88 10
Need Short 0_0402_5% 11
@ 12 GND_1
J4 GND_2

1
1 2 ACES_51524-01001-003
1 2 ME@
JUMP_43X79

+5VALW +5VS +5V_ODD

De
LP2301ALT1G_SOT23-3
3 3

3
S

1 Q19
.1U_0402_10V6-K

.01U_0402_16V7-K
1

+3VS
C83

C84

10U_0805_10V6K

.1U_0402_10V6-K
1 1
R75 R76
G

1 1
2

10K_0402_5% 10K_0402_5%
@

bu
@

1
@2 @2
2

1
2 2
C86

R77
@
C85

ODD_EN# 1 2 R78 @ R79 10K_0402_5%


100K_0402_5% 1 470_0603_5% @
@ C87 @

2
.01U_0402_16V7-K

g
2

R86 1 @ 2 0_0402_5% ODD_DA#_R


2 {44} ODD_DA_EC#
1 @
D Q20 1
2 PJA138K_SOT23-3 D Q21
{4} ODD_EN
G ODD_EN# 2 PJA138K_SOT23-3
S G
2

S @
R81 3
@ 3
100K_0402_5%
1

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2014/09/24 Deciphered Date 2015/03/23 HDD/ODD CONN


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 42 of 60

www.bios-downloads.com
A B C D E F G H
5 4 3 2 1

+1.5VS
+3VS
@ RA8 1 2 0_0402_5% RA1 1 @ 2 0_0402_5%
RA2 1 2 0_0603_5% +3.3VD +3VS +3VL

RA11 1 2 0_0402_5% DVDD_IO RA43 1 2 0_0603_5% AVDD_HP RA4 1 @ 2 0_0402_5%

.1U_0402_10V6-K
@
+5VS RA6 1 @ 2 0_0402_5%
2
@ CA1
RA7 1 2 0_0603_5% +5VA
RA9 1 @ 2 0_0402_5%
D @ 1 D
RA10 1 2 0_0603_5% +5VD
Same as Vienna RA12 1 @ 2 0_0402_5%

Close to Pin7
+3VS RA13 1 @ 2 0_0402_5%

2
RA14 GND GNDA
10K_0402_5%

{44} BEEP#
0606

2 RA288 1
10K_0402_5%

1
1
CA2
2

Ju
PC_BEEP
.1U_0402_10V6-K
Close to Pin3

4.7U_0603_6.3V6K
st
1

.1U_0402_10V6-K
RA289 1
C CA16 close to Pin18
2 2 QA1 2 1 CA17 close to Pin2
{6} PCH_BEEP
4.7K_0402_1%
B MMBT3904WH_SOT323-3 Close to Pin27
E
manual change the Codec PN to CX11802-33Z
3

CA4
1 2

CA3

1U_0402_6.3V6K
.1U_0402_10V6-K
0608

for

CA7

CA8
2 1

.1U_0402_10V6-K

2.2U_0603_6.3V6K
UA1
2 1

CA5

CA6
HDA_RST_AUDIO# 9 3 FILT_1.8V
+3.3VD

{6} HDA_RST_AUDIO# RESET# FILT_1.8V 7 DVDD_IO 1 2


VDD_IO 2 CD@
HDA_BITCLK_AUDIO 5 VDDO_3.3 18 +3.3VD 1 2
{6} HDA_BITCLK_AUDIO BIT_CLK DVDD_3.3
2

LC
C HDA_SYNC_AUDIO 8 27 AVDD_3.3 C
RA15 {6} HDA_SYNC_AUDIO SYNC AVDD_3.3 29 VREF_1.65V
RA16 VREF_1.65V
5.11K_0402_1% 75_0402_1% 1 2 SDATA_IN 6 28 +5VA
{6} HDA_SDIN0 SDATA_IN AVDD_5V

.1U_0402_10V6-K

1U_0402_6.3V6K
HDA_SDOUT_AUDIO 4 MICBIASB
{6} HDA_SDOUT_AUDIO SDATA_OUT

CA9

CA10
CX20751-11Z 2 1
1

PC_BEEP 10 12 SPK_L+
RA17 1 2 JSENSE SPKR_MUTE# 39 PC_BEEP LEFT+ 14 SPK_L-
{45} PLUG_IN SPKR_MUTE# LEFT- DA2
39.2K_0402_1%
BAT54AW_SOT323-3

1
FC
JSENSE 38 17 SPK_R+ 1 2
JSENSE RIGHT+

1
RA36 1 2 37 15 SPK_R- +5VA AVDD_HP

4LINE_B_R

LINE_B_L
GPIO1/PORTC_R_MIC RIGHT-

.1U_0402_10V6-K

.1U_0402_10V6-K
20K_0402_1% RA42 RA41

CA11

CA12
36 35 0_0402_5% 0_0402_5% 2 2
33_0402_5% 1 RA18 2 40 MUSIC_REQ/GPIO0/PORTC_L_MIC MICBIASC 34
{33} DMIC_CLK
DMIC_CLK_R
DMIC_CLK/MUSIC_REQ/GPIO0 MICBIASB
MICBIASB Close to Pin29
0_0402_5% 1 RA19 2 DMIC_DATA_R 1

2
{33} DMIC_DATA DMIC_DAT/GPIO1

3
33 LINE_B_R @
.1U_0402_10V6-K PORTB_R_LINE 32 LINE_B_L RPA2 1 1
+5VD 1 2 11 PORTB_L_LINE
CLASS-D_REF 100_0404_4P2R_1%
CA13 30 PORTD_A_MIC

PE
PORTD_A_MIC

3K_0402_1%

3K_0402_1%
13 31 PORTD_B_MIC

1
2
LPWR_5.0 PORTD_B_MIC

1
+5VD DMIC_DATA_R 16
RPWR_5.0
100P_0402_50V8J

100P_0402_50V8J

RA37

RA38
25 RING2_CONN Close to Pin28 Close to Pin24
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

HGNDA 1 1
DMIC_CLK_R CA14 1 2 1U_0402_6.3V6K 19 26 RING3_CONN CA35 CA36
FLY_P HGNDB
CA18

CA19
.1U_0402_10V6-K

.1U_0402_10V6-K

20 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K
FLY_N 24 AVDD_HP
1 1 2 2

2
CA17 1 2 2.2U_0603_6.3V6K 21 AVDD_HP 2 2 RPA3
AVEE 23 HPOUT_R 1 4
1 1 PORTA_R HP_OUTR {45}
CA15

CA16

41 22 HPOUT_L 2 3
2 2 1 1 GND PORTA_L HP_OUTL {45}

De
CA51 CA52 82.5_0404_4P2R_1%
EMC_NS@ 2 2 Reserve DA2 to prevent RPA1
EMC_NS@ CX11802-33Z QFN LOW POWER CODEC cross-talk between PORTD_A_MIC 2 3 CA20 1 2 2.2U_0603_6.3V6K
1 4 RING3_CONN {45}
PORTD_B_MIC CA21 1 2 2.2U_0603_6.3V6K
B HPOUT_R/L, if stuff DA2, RING2_CONN {45} B
RA37/RA38 need change to 100_0404_4P2R_1%
3K.
Close to Pin11,13,16

+1.5VS
For EMI

+3VS

bu
g
HDA_RST_AUDIO#
2

HDA_SYNC_AUDIO
RA825 RA826
10K_0402_5% 10K_0402_5% HDA_SDOUT_AUDIO JSPK1
15_0402_5% 1 2
EMC_NS@ RA25 SPK_R+ RA26 1 2 EMC@ BLM18PG221SN1D_2P SPK_R+_CONN 1
EMC@ 2 1
2

RA27 1 HDA_BITCLK_AUDIO 15_0402_5% 1 2


EMC_NS@ RA29 SPK_R- RA31 1 2 EMC@ BLM18PG221SN1D_2P SPK_R-_CONN 2
1

2
G

22_0402_5% 15_0402_5% 1 2
EMC_NS@ RA32 SPK_L+ RA30 1 2 EMC@ BLM18PG221SN1D_2P SPK_L+_CONN 3
@ @ 1 2 1 2 4 3
HDA_SDIN0 15_0402_5% EMC_NS@ RA33 SPK_L- RA34 EMC@ BLM18PG221SN1D_2P SPK_L-_CONN
4
3

HDA_RST_AUDIO# PCH_HDA_RST#_Q
100P_0402_50V8J

CA22

CA23

CA24

CA25

CA26

5
S

GND1

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
22P_0402_50V8-J

22P_0402_50V8-J

10P_0402_50V8J

33P_0402_50V8J

6
GND2
220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K
CA27

CA28

CA29

CA30

CA31

CA32

CA33

CA34
QA198 1 1 1 2 1
2 2 2 2 1 1 1 1 ACES_88231-04001
PJA138K_SOT23-3 ME@
+3.3VD

@
0610 2 2 2 1 2

EMC@

EMC@

EMC@

EMC@
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

1 1 1 1 2 2 2 2
EMC_NS@

EMC_NS@

EMC@
EMC@

RA24 1 @ 2
1

0_0402_5%
A RA28 A
47K_0402_5%
RB751V-40_SOD323-2 For EMI
PCH_HDA_RST#_Q DA3 1 2 @
2

SPKR_MUTE#
RB751V-40_SOD323-2
EC_MUTE# DA4 1 2 @ Title
{44} EC_MUTE# Security Classification LC Future Center Secret Data

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 Codec_CX20751
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
RA35 1 2 Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
0_0402_5% Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 43 of 60
5 4 3 2 1
5 4 3 2 1

For ESD RE1 1 2 0_0603_5% +3VL


PLT_RST#

1 RE3 1 2 0_0603_5%
+3VALW
CE1 Same as SOC LPC power @
+3VL_EC_R
EMC@ 220P_0402_50V7K +3VL_EC +3VL_EC
2
+3VALW RE4 1 2 0_0402_5%
LE1 1 2 0_0402_5%
+3VALW_R All capacitors close to EC +3VL_EC
+3VALW RE16 1 TPM@ 2 0_0402_5% 1 1
+1.8VALW RE6 1 2 0_0402_5%
CE4

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
+3VL_EC_R 1 1 1 1 1 1 .1U_0402_10V6-K CE5

1
RE17 1 2 0_0402_5% VFSPI @ CE6 CE7 CE8 CE9 CE10 CE11 1000P_0402_50V7K
+1.8VALW Close EC LE2 1 2 0_0402_5% 2 EC_AGND 2 RE5
D D
NTPM@ @ 10K_0402_5%
CE3 2 2 2 2 2 2
1 2 VCOREVCC EC_AGND

2
VFSPI CD@
CLK_PCI CE23 1 2 10P_0402_50V8J .1U_0402_10V6-K BEAD change to 0ohm LAN_WAKE# LAN_WAKE# {37,40}
EMC@

114
121
127

106
minimum trace width 12 mil

12

11

26
50
92

74
Change RE6 to 0ohm jump UE1
+3VS

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VCC

AVCC

VFHSPI/VFSPI/VHSPI
VSTBY(PLL)
VCORE
EC_FAN_SPEED RE10 1 2 10K_0402_5%

Ju
EC_FAN_PWM RE11 1 @ 2 10K_0402_5%

{19} WRST# +1.8VALW


4 V1P8 24
+3VL_EC {7} KBRST# KBRST#/GPB6 PWM0/GPA0 PWR_LED# {45} ENBKL RE9 1 @ 2 100K_0402_5%
5 25
{7,45} SERIRQ 6 SERIRQ/GPM6 PWM1/GPA1 28 BATT_CHG_LED# {45}
LPC_FRAME#
{7,45} LPC_FRAME# LFRAME#/GPM5 PWM2/GPA2 BATT_LOW_LED# {45}

st
7 29 0_0402_5% 2 1 RE54
{7,45} LPC_AD3 LAD3/GPM3 PWM3/GPA3 5PFAN@ EC_FAN_ANTI {39}
DE1 1 2 @
{7,45} LPC_AD2
8
9 LAD2/GPM2 PWM PWM4/GPA4
30
31
VGA_GATE#
VGA_GATE# {7} 5 Pin Fan Conn +5VS +3VS
EC_FAN_PWM
{7,45} LPC_AD1 LAD1/GPM1 PWM5/GPA5 EC_FAN_PWM {39}
10 32

2
RB751V-40_SOD323-2 {7,45} LPC_AD0 1 2 0_0402_5% 13 LAD0/GPM0 LPC PWM6/SSCK/GPA6 34 BEEP# {43}
RE53 CLK_PCI
{7} CLK_PCI_EC LPCCLK/GPM4 PWM7/RIG1#/GPA7 VR_+1.15VS_PWREN {46} RE52 RE51
RE8 1 2 100K_0402_5% WRST# 14 120 LAN_WAKE#
15 WRST# TMRI0/GPC4 124 SUSP# 0_0402_5% 0_0402_5%
{7} EC_SMI# ECSMI#/GPD4 V1P8 TMRI1/GPC6 SUSP# {46,55,56} @
PLT_RST# 22

for
1 {7,19,37,40,45} PLT_RST# LPCRST#/GPD2 V1P8
23 66

1
CE12 {7,12} EC_SCI# ECSCI#/GPD3 V1P8 ADC0/GPI0 NTC_V1 {39}
126 67 RPE3
1U_0402_6.3V6K {52,56} PCH_PWR_EN GA20/GPB5 V1P8 ADC1/GPI1 NTC_V2 {39}
68 BATT_TEMP
2 ADC2/GPI2 BATT_TEMP {52,53} TP_CLK 2 3
IT8886HE/AX ADC ADC3/GPI3
ADC4/GPI4
69
70
71
RSMRST_P {56}
VR_CPU_PWROK {58,59}
TP_DATA 1 4

{45} KSI[0..7]
KSI[0..7] LQFP-128L ADC5/DCD1#/GPI5
ADC6/DSR1#/GPI6
72
73
ADP_I {53}
EC_3VSPWREN {46} 2.2K_0404_4P2R_5%

58 ADC7/CTS1#/GPI7 ADAPTER_ID {51,53}


KSO[0..17] KSI0
KSI0/STB# +5VALW
{45} KSO[0..17] KSI1 59 78
PCH_WLAN_OFF# {40}

LC
C
KSI2 60 KSI1/AFD# DAC2/TACH0B/GPJ2 79 C
61 KSI2/INIT# DAC3/TACH1B/GPJ3 80 MAINPWON {54}
KSI3 DAC H_PROCHOT#_EC
KSI3/SLIN# DAC4/DCD0#/GPJ4 USB_ON# RE15 1 2 100K_0402_5%
+3VL_EC KSI4 62 81
KSI5 63 KSI4 DAC5/RIG0#/GPJ5 PCH_BT_OFF# {40} Change RE14 to 0ohm jump
KSI5 +3VL_EC
KSI6 64 85 EC_RTCRST#_ON
RPE1 KSI7 65 KSI6 PS2CLK0/TMB0/CEC/GPF0 86
EC_SMB_CK1 PAD 1 @ KSI7 PS2DAT0/TMB1/GPF1 PBTN_OUT# {7}
IT2 KSO0 36 PS2 89 TP_CLK
1 4 EC_SMB_CK1 EC_SMB_DA1 PAD 1 @ KSO0/PD0 V1P8 PS2CLK2/GPF4 TP_CLK {45}
IT3 KSO1 37 90 TP_DATA
2 3 EC_SMB_DA1 PAD 1 @ 38 KSO1/PD1 Int. K/B V1P8 PS2DAT2/GPF5 TP_DATA {45}
IT4 KSO2 RSMRST_P RE20 1 2 100K_0402_5%
PAD 1 @ KSO2/PD2 Matrix

FC
IT5 KSO3 39
2.2K_0404_4P2R_5% PAD 1 @ KSO3/PD3
IT6 KSO4 40 96
KSO5 41 KSO4/PD4 HSCE#/GPH3/ID3 97 EC_SPI_CS0# {6}
KSO6 42 KSO5/PD5 HSCK/GPH4/ID4 98 EC_SPI_CLK {6}
KSO6/PD6 EXTERNAL SERIAL FLASH HMISO/GPH5/ID5 EC_SPI_D1 {6} +3VL_EC
+3VS KSO7 43 99
KSI7 PAD 1 @ KSO7/PD7 FDIO3/DSR0#/GPG6 PCH_SPI_D3 {6} SUSP# RE18 1 @ 2 100K_0402_5%
IT7 KSO8 44
KSI6 PAD 1 @ KSO8/ACK#
IT8 KSO9 45 101
RPE2 WRST# PAD 1 @ KSO9/BUSY FSCE# PCH_SPI_CS0# {6} SUSP# RE19 1 2 100K_0402_5%
IT9 KSO10 46 102
1 4 EC_SMB_CK2 KSO10/PE FMOSI PCH_SPI_D0 {6}
KSO11 51 SPI Flash ROM 103
2 3 EC_SMB_DA2 KSO11/ERR# FMISO PCH_SPI_D1 {6} SYSON RE21 1 2 100K_0402_5%
KSO12 52 105
For factory EC flash KSO13 53 KSO12/SLCT FSCK PCH_SPI_CLK {6}
KSO13 EC_3VSPWREN RE23 1 2 100K_0402_5%
2.2K_0404_4P2R_5% KSO14 54

PE
KSO15 55 KSO14
KSO15 SYS_PWROK RE12 1 2 100K_0402_5%
KSO16 56 17 EC_TX
KSO16/SMOSI/GPC3 V1P8 TXD/SOUT0/LPCPD#/GPE6 16 EC_TX {40}
to thermal sensor KSO17 57
KSO17/SMISO/GPC5
UART RXD/SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7
EC_RX
EC_RX {40}
V1P8

EC_SMB_CK1 115 82
{52,53} EC_SMB_CK1 SMCLK1/GPC1 V1P8 EGAD/GPE1 SYS_PWROK {5,7}
to charge ,battery {52,53} EC_SMB_DA1
EC_SMB_DA1 116
SMDAT1/GPC2 V1P8 EGCS#/GPE2
83
EC_MUTE# {43}
ENBKL change from GPJ5 117 84
{33} ENBKL SMCLK2/PECI/GPF6 V1P8 EGCLK/GPE3 ADAPTER_ID_ON# {53}
118 V1P8
{37} LAN_PWR_ON# SMDAT2/PECIRQT#/GPF7
EC_SMB_CK2 87 77 GPG2
{19,39} EC_SMB_CK2
EC_SMB_DA2 88 SMCLK0/GPF2 V1P8 SM Bus SSCE0#/GPG2 110 ON/OFF RTC_RST# {7}
change from GPJ2 {19,39} EC_SMB_DA2 SMDAT0/GPF3 V1P8 PWRSW/GPB3 ON/OFF {45}

De
95 GPIO

1
{6} EC_SPI_D3 HDIO3/GPJ1 V1P8 QE3 D
94
{6} EC_SPI_D2 TACH2/HDIO2/GPJ0 V1P8 EC_RTCRST#_ON 2
BKOFF# 113 107
{33} BKOFF#
123 CRX0/GPC0
V1P8
GPE4/BTN# 119
NOVO# {45} change from GPJ0 for cost down G
{40} AOAC_ON# CTX0/TMA0/GPB2 CRX1/SIN1/SMCLK3/GPH1/ID1 PCH_ME_PROTECT {12}

1
0_0402_5% 2N7002KW_SOT323-3 S
RE27 1 2 0_0402_5% 112

3
B +3VL B
VSTBY0 RE50 @
VGA_AC_DET 2 @ 1 RE30 100
{19} VGA_AC_DET {6} PCH_SPI_D2 FDIO2/DTR1#/SBUSY/GPG1/ID7 100K_0402_5%
125 76
{42} ODD_DA_EC# SSCE1#/GPG0 CLKRUN#/GPH0/ID0 EC_RSMRST# {7} @
SYSON 122 WAKE UP 48 EC_ON_GPIO RE57 2 1 0_0402_5%
{55} SYSON CTX1/SOUT1/SMDAT3/GPH2/ID2 TACH1A/TMA1/GPD7 EC_ON {54}

bu
21 V1P8 47 EC_FAN_SPEED

2
{7} PM_SLP_S4# RI2#/GPD1 V1P8 TACH0A/GPD6 EC_FAN_SPEED {39}
18 19
{7} PM_SLP_S3# RI1#/GPD0 V1P8 V1P8 L80HLAT/BAO/GPE0 CAPS_LED# {45}
20
V1P8 L80LLAT/GPE7 NUM_LED# {45}
USB_ON# 33 108 ACIN#
{41,45} USB_ON# GINT/CTS0#/GPD5 AC_IN#/GPB0
35 109 LID_SW#
{53} ACOFF 93 RTS1#/GPE5 LID_SW#/GPB1 111 LID_SW# {45}
V1P8 RE58 2 1 0_0402_5% EC_ON
{6} EC_SPI_D0 HMOSI/GPH6/ID6 XLP_OUT/GPB4 @
+3VL
0_0402_5% 2 1 RE29 2 GPIO
{7,37,40} PCIE_WAKE# GPJ7 SYSON

g
3
{58,59} EC_VR_ON GPH7
change from GPE4 {7} AC_PRESENT
128
GPJ6
AVSS
VSS1
VSS2
VSS3
VSS4

VSS5

RE35 1 @ 2 10K_0402_5% ON/OFF EMC Request 1


VGA_AC_DET RE33 1 2 0_0402_5%
RE36 1 @ 2 10K_0402_5% BKOFF#
IT8886HE-AX_LQFP128_14X14 Change RE30 to 0ohm jump CE13
1
27
49
91

75

104

@ .1U_0402_10V6-K
RE34 1 2 0_0402_5% H_PROCHOT# {7} EMC_NS@ 2
RE38 1 2 10K_0402_5% LID_SW# {53,58,59} VR_HOT#

1
QE1 D 1
H_PROCHOT#_EC 2 CE14
RE40 1 2 10K_0402_5% BKOFF#
G 47P_0402_50V8J +3VL +3VL_EC
EC_AGND @
2N7002KW_SOT323-3 S 2

1
1
RE65
10K_0402_5%
RE42
100K_0402_5%
+3VS

2
2
1 2 100P_0402_50V8J 1 RE66 2
BATT_TEMP @ CE16 ACIN# EC_ON_GPIO
{7} ACIN#
0_0402_5%
CE21 .1U_0402_10V6-K

CE19 .1U_0402_10V6-K
+3VL_EC NOVO# ACIN# @ CE17 1 2 100P_0402_50V8J

1
1 1 D QE2
A +3VL ON/OFF @ CE18 1 2 1U_0402_6.3V6K 2 A
ACIN {53}
.01U_0402_16V7-K

LID_SW# G
RE44 2 1 10K_0402_5%
C48

GPG2
2 2 2N7002KW_SOT323-3 S
@ 1

3
GPG2 RE46 2 1 10K_0402_5% 1 1 @
ACIN change to hign active to cost QE2
CE20 CE22
.1U_0402_10V6-K .1U_0402_10V6-K
when mirror, GPG2 pull high @ 2
2 2
when no mirror, GPG2 pull low @

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 EC ITE8586LQFP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 44 of 60
5 4 3 2 1
5 4 3 2 1

ON/OFF switch NOVO# R4621 1


0_0402_5%
2 NOVO_BTN#

+3VL +3VALW
K/B Connector +3VS 14" 15"
KB_1 KSI1_14 KSO0_15

2
KSI[0..7] KB_2 KSI7_14 KSI2_15
R82 R83
KSI[0..7] {44}
14" 15"

1
100K_0402_5% 100K_0402_5% KSO[0..17] KB_3 KSI6_14 KSI3_15
KSO[0..17] {44}
@ JKB2 R84 R87
300_0402_5% 300_0402_5% KB_4 KSO9_14 KSO5_15

1
D15 27 15@ JKB1
NOVO# 2 GND1 28 NUM_LED# 30 31
{44} NOVO# {44} NUM_LED# KB_5 KSI4_14 KSO1_15

2
CAPS_LED# 26 GND2 PWR_NUM_LED 29 30 GND1 32
1 {44} CAPS_LED# 25 26 28 29 GND2
NOVO_BTN# PWR_CAPS_LED CAPS_LED# KB_6 KSI5_14 KSI0_15
@ KSO15 24 25 PWR_CAPS_LED 27 28
ON/OFF R85 1 2 0_0402_5% 3 @ KSO10 23 24 KSO17 26 27
23 26
KB_7 KSO0_14 KSO2_15
D KSO11 22 KSO16 25 D
BAT54CW_SOT323-3 KSO14 21 22 KSO15 24 25
21 24 KB_8 KSI2_14 KSO4_15
KSO13 20 KSO10 23
KSO12 19 20 KSO11 22 23
19 22 KB_9 KSI3_14 KSO7_15
KSO3 18 KSO14 21
+3VALW +3VL KSO6 17 18 KSO13 20 21
17 20 KB_10 KSO5_14 KSO8_15
KSO8 16 KSO12 19
KSO7 15 16 KSO3 18 19
15 18 KB_11 KSO1_14 KSO6_15

2
KSO4 14 KSO6 17
R111 R114 KSO2 13 14 KSO8 16 17
13 16
KB_12 KSI0_14 KSO3_15
100K_0402_5% 100K_0402_5% KSI0 12 KSO7 15
@ KSO1 11 12 KSO4 14 15
11 14 KB_13 KSO2_14 KSO12_15
KSO5 10 KSO2 13

1
@ KSI3 9 10 KSI0 12 13
9 12 KB_14 KSO4_14 KSO13_15
ON/OFFBTN# R119 1 2 0_0402_5% ON/OFF KSI2 8 KSO1 11
ON/OFF {44} 7 8 10 11
KSO0 KSO5 KB_15 KSO7_14 KSO14_15
KSI5 6 7 KSI3 9 10
J5 1 2 KSI4 5 6 KSI2 8 9
5 8
KB_16 KSO8_14 KSO11_14
KSO9 4 KSO0 7
SHORT PADS KSI6 3 4 KSI5 6 7
3 6
KB_17 KSO6_14 KSO10_15
KSI7 2 CAPS_LED# NUM_LED# KSI4 5
2 5

Ju
J6 1 2 KSI1 1 KSO9 4 KB_18 KSO3_14 KSO15_15
1 KSI6 3 4

AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2
3

1
SHORT PADS ACES_88514-02601-071 KSI7 2 KB_19 KSO12_14 KSO16_15
D20 D21 KSI1 1 2
ME@

1
1
KB_20 KSO13_14 KSO17_15
ACES_50504-3041-001
ME@ KB_21 KSO14_14 KB_LED_PWR_15
TP/B Connector

2
15@ KB_22 KSO11_14 CAPS_LED#_15
EMC@

2
st
KB_23 KSO10_14 VDD_15
KB_24 KSO15_14 NUM_LED#_15

+5VS TP_PWR TP_DATA


TP_CLK
PWR/B Connector Right Side USB2.0 Port X 2 (USB/B)

for
C R160 1 @ 2 C
USB I/O Connector

2
+3VS 0_0402_5%
JTP1 DT1
R141 1 2 1
0_0402_5% TP_CLK 2 1
{44} TP_CLK 2
TP_DATA 3
{44} TP_DATA 3
.1U_0402_10V6-K

4 +USB_VCCB
1 4
EMC_NS@
1 EMC_NS@
1 TP_P5 5
5
100P_0402_50V8J

100P_0402_50V8J

TP_P6 6 7 JUSB3
6 GND1 8 18 20
2 GND2 17 18 G2 19
C114

2 2 +5VALW +USB_VCCB 17 G1
ACES_50503-0060N-001 16
C115

C116

U3
ME@ EMC_NS@ AZC199-02S.R7G_SOT23-3 +3VL R30 1 2 0_0402_5% USB20_P2_CONN 15 16
5 1 {8} USB20_P2

1
1 2 0_0402_5% 14 15
For EMC IN OUT R31 USB20_N2_CONN

LC
{8} USB20_N2 14
JPWRB1 1 13
C119 2 13
1 1U_0402_6.3V6K GND R32 1 2 0_0402_5% USB20_P1_CONN 12
1 {8} USB20_P1 12
NOVO_BTN# 2 R33 1 2 0_0402_5% USB20_N1_CONN 11
2 {41,44} USB_ON# 4 3 USB_OC1# {8} USB20_N1 11
ON/OFFBTN# 3 2 EN FLG USB_OC1# {8} 10
3 10
TP_LEFT Button TP_LEFT Button LID_SW# 4
4 1
9
9
TP_P5 TP_P5 5 {43} HP_OUTR HP_OUTR 8
5 AP22802BW5-7_SOT25-5 C120 8
6 7 HP_OUTL 7

AZ5215-01F_DFN1006P2E2
6 GND1 1000P_0402_50V7K {43} HP_OUTL 7

1
8 6
GND2 Low Active 2.5A EMC_NS@ RING3_CONN 5 6
D17 2

1
{43} RING3_CONN 5
1

5
AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2
ACES_50503-0060N-001 4
SW1 SW2 ME@ RING2_CONN 3 4
A

A
A1

GND1

A1

GND1
EVQPLHA15_4P

EVQPLHA15_4P
{43} RING2_CONN 3
1

1
DT2 DT3 PLUG_IN 2

FC
{43} PLUG_IN 2

2
1
For 14" For 15"
1

1
EMC_NS@ 1

2
GND2

GND2

ACES_50505-0184N-P01
LID_SW# {44}
ME@
1 VDD 1 VDD
B1

B1
B

B
2

2
14@ 15@
EMC_NS@ EMC_NS@
3

2
L14 EMC_NS@
2 CLK 2 CLK For EMC USB20_P2 1 2 USB20_P2_CONN
1 2

TP_RIGHT Button TP_P6


TP_RIGHT Button TP_P6
USB20_N2 4 3 USB20_N2_CONN
3 DAT 3 DAT NOVO_BTN# ON/OFFBTN#
4
EXC24CH900U_4P
3

AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2
PE
1

1
B B
AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2

4 GND 4 GND SW3 SW4 D18 D19


A

A
A1

GND1

A1

GND1

1
EVQPLHA15_4P

EVQPLHA15_4P

L17 EMC_NS@
1

DT4 DT5 1 2
USB20_P1 USB20_P1_CONN
1 2
1

5 TP-L 5 TP-L
GND2

GND2

2
USB20_N1 4 3 USB20_N1_CONN
EMC@ 4 3
B1

B1

EMC@

2
B

B
2

14@ 15@
EXC24CH900U_4P
EMC_NS@ EMC_NS@
6 TP-R 6 TP-R
3

Change to same as ACLUA For 14" For 15"

LED {44} PWR_LED# PWR_LED# LED1 1 2 R142 1 2 1.5K_0402_5% +5VALW


+3VS
+3VS_TPM

De
1

D16 LTW-C193TS5
AZ5425-01F_DFN1006P2E2
1

20mA
1 2
1 R112 TPM@ 0_0603_5%
1 +3VS_TPM

bu
2

C138
10U_0603_6.3V6M C139
EMC_NS@
2

2 .1U_0402_10V6-K
TPM@ 2 UTPM1 TPM@
TPM@ 1 24
2 NC_1 VPS_1 10
BATT_LOW_LED# LED2 1 2 R143 1 2 470_0402_5%
{44} BATT_LOW_LED# +3VALW 3 NC_2 VPS_2
7 NC_3 28 R113 1 TPM@ 2 10K_0402_5%
TPM
1

D23 LTST-C193KFKT-LC PP LPCPD# 27


AZ5425-01F_DFN1006P2E2 SERIRQ SERIRQ {7,44}
1

6 26
9 NC_4 LAD0 23 LPC_AD0 {7,44}

g
VNC_1 LAD1 22 LPC_AD1 {7,44}
4 LFRAME# 20 LPC_FRAME# {7,44}
11 GND_1 LAD2 17 LPC_AD2 {7,44}
2

A 18 GND_2 LAD3 LPC_AD3 {7,44} A


EMC_NS@ GND_3 25
2

5 NC_11 21 R115 2 TPM@ 1 20_0402_1%


+3VS_TPM NC_5 LCLK CLK_PCI_TPM {7}
8 19 +3VS_TPM
12 VNC_2 NC_10 15 R116 1 2 TPM@
{44} BATT_CHG_LED# BATT_CHG_LED# LED3 1 2 R144 1 2 1.5K_0402_5% +5VALW NC_6 NC_9
13 0_0402_5%
14 NC_7 16
LTW-C193TS5 NC_8 LRESET# PLT_RST# {7,19,37,40,44}
1

D24
AZ5425-01F_DFN1006P2E2 ST33ZP24AR28PVSP_TSSOP28
1

Security Classification LC Future Center Secret Data Title


2

EMC_NS@ Issued Date 2014/09/24 Deciphered Date 2015/03/23 KBD/PWR/IO/LED/TP Conn.


2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
check LED location and BOM structure when placement and Load BOM, PWR LED and BATT LED have the same location on 14"/15" 02/26
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 45 of 60
5 4 3 2 1

www.bios-downloads.com
A B C D E

+5VALW to +5VS +5VALW


TPS22966 +5VALW +5VLP

+3VALW to +3VS Enable:


VIH=1.2V~5.5V

1
1 VIL=0~0.5V
Need Short R4605 @ R4604
C4913 +5VS 100K_0402_5% 100K_0402_5%
CD@ 1U_0402_6.3V6K U4 J11 @
2 1 14 1 2

2
2 VIN1_1 VOUT1_2 13 1 2 1
VIN1_2 VOUT1_1 C4915 @
JUMP_43X118 .1U_0402_10V6-K +3VS_PWREN#
SUSP# R263 1 2 0_0402_5% 3 12 5VS_CT1
EN1 SS1 CD@
2
4 11
BIAS GND

1
D Q4612
R264 1 2 0_0402_5% +3VS_PWREN# 5 10 3VS_CT2 +3VS 2
EN2 SS2 EC_3VSPWREN {44}
+3VALW J12 @ G
0.01U_0402_25V7K
C4916 @

1 6 9 1 2
7 VIN2_1 VOUT2_2 8 1 2 S 2N7002KW_SOT323-3
1

3
VIN2_2 VOUT2_1 JUMP_43X118 C215
1 @
15 .1U_0402_10V6-K
2 C4914 GPAD Need Short CD@
CD@ APL3523AQBI-TRG_TDFN14_2X3 2
1U_0402_6.3V6K
2
5VS_CT1 3VS_CT2

1 1
C4917 C4918
2200P_0402_50V7K 2200P_0402_50V7K
1 0113: TPS22966 slow rate control pin 2 2 1

CT1/CT2 reserve 1000P cap for output rise


time control

AON7408L +5VLP +5VALW


VDS=30V VGS=20V, ID=20A,
Rds=18mohm @ VGS=10V
VGS(th)=3V Max +1.15VA
NeedJ9 short +1.15VA_SOC

1
@ +0.675VS
1 2 R162 R163
1 2 100K_0402_5% 100K_0402_5%
+5VALW +5VLP @

1
JUMP_43X79

2
+20VSB Q30 R159
1
AON7408L_DFN8-5 SUSP 47_0603_5%

Ju
{34} SUSP
1

C216 @
R894 @ R895 1 .1U_0402_10V6-K

2
2
100K_0402_5% 100K_0402_5% 0601 ADD 2 2
5 3 @
R898

1
100K_0402_5% Q4610 D D Q4611
2

2 2 SUSP
@ {44,55,56} SUSP#
+1.15VS_PWREN# @ G G
1

4
0601 ADD @ +1.15VS_PWREN 2 1 S 2N7002KW_SOT323-3 S
2N7002KW_SOT323-3

3
Q170B R266 0_0402_5%
3

D 2N7002KDWH_SOT363-6 @
@ 1

C444
1000P_0402_50V7K
5
VR_+1.15VS_PWREN {44}
6

2
G D Q170A

st
+1.15VS_PWREN# 2 R899 @
S G 2N7002KDWH_SOT363-6 330K_0402_5% 2
4

@
S
1

1
@ @

2
for 2

LC
FC
PE
3

De 3

bu
g
Security Classification
Classification LC Future Center Secret Data Title

Issued Date 2014/09/24 Deciphered Date 2015/03/23 DC V TO VS INTERFACE


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 46 of 60

4 4

www.bios-downloads.com B C D E
5 4 3 2 1

B2 A2
D
+3VLP PCH_PWR_EN# 1 D

V
PU704,+3VALW_SOC

V
AC A1
MODE VIN 3
RSMRST_P

V V
A2 A4 B5

V
PU401 2 +3VALW_SOC

V
PU301

V
B+
+3VALW
BATT V V

Ju
BATT
MODE

V V V
B1
4
PCH_RSMRST#
EC

st
EC_ON
5 PBTN_OUT#
SOC

for
A3 B4 other Device
PM_SLP_S3#
PM_SLP_S4# 6

V
PLTRST# 13

V
11
DDR_CORE_PWROK

V V
LC
C C

B3 12
SYS_PWROK

V
ON/OFF V
NOVO

FC PXS_PWREN

Vb
(DIS)
+VGA_CORE

V
9 VR_REDY SYSON 7 +1.35V
PU910
PU501

V
8
PE PXS_PWREN

Va (DIS)
DGPU_PWROK

V
PU907 VR_ON U4 +1.35VGS

V
V

+5VS QV14

V
PU903

De
+CPU_CORE
+GFX_CORE
B U4 B

V
+3VS +1.05VGS

V
SUSP# 10 PU603

V
bu
GPU
PU704

V
+1.5VS
+3VG_AON

V
QV11

A A

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 Power sequence Block
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 47 of 60
5 4 3 2 1
5 4 3 2 1

D D

Ju
st
C

for C

LC
FC
B
PE B

De
bu
A
g A

Security Classification LC Future Center Secret Data Title


Issued Date 2014/09/24 Deciphered Date 2015/03/23 Virtual symbol
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 48 of 60
5 4 3 2 1

www.bios-downloads.com
5 4 3 2 1

H27 H28
HOLEA HOLEA

NH3 NH4 NH5


H10
HOLEA HOLEA HOLEA
HOLEA

1
PAD_C8P0 PAD_C8P0

1
D 1 D

pad_o2p8x2p5d2p8x2p5n pad_o2p8x2p5d2p8x2p5n PAD_C2P5D2P5N


PAD_OT6P0X5P5D3P3X2P8

H1 H3 H4 H5 H6 H24 H25 H26

Ju
HOLEA HOLEA HOLEA HOLEA HOLEA H7 H8 H9 HOLEA HOLEA HOLEA
HOLEA HOLEA HOLEA
1

1
1

1
PAD_CT8P0D2P8
Pad_ct8p0b9p0d2p8

st
Pad_ct8p0b9p0d2p8
PAD_SHAPET9P0X8P0B9P0D2P8
PAD_ShapeT9P0X8P0B9P0d2P8
PAD_C5P0D4P0 PAD_C5P0D4P0 PAD_C5P0D4P0
PAD_C5P0D3P3
PAD_CT5P0D3P3 PAD_CB8P0D2P5

H13 H14 H15


for H17 H20 H22 H23 H21
C

LC
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

1
FC
CHASSIS1_GND
PAD_C8P0D7P0 PAD_CT6P0B8P0D2P3 PAD_RT8P0X11P0D2P8 PAD_CB8P0D2P5 PAD_C5P5D3P3 PAD_C5P0D3P3 PAD_C5P0D3P3
PAD_C8P0D2P5

GP1
PAD_RT2P65X2P2
GP2
PAD_RT2P65X2P2
GP3
PAD_RT2P65X2P2
GP4
PAD_RT2P65X2P2
GP5
PAD_RT2P65X2P2
GP6
PAD_RT2P65X2P2
GP7
PAD_RT2P65X2P2
GP8
PAD_RT2P65X2P2

PE +1.35V

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
330P_0402_50V7K

330P_0402_50V7K

330P_0402_50V7K

330P_0402_50V7K

330P_0402_50V7K
@ @ @ @ @ @ @ @
1 1 1 1 1 1 1 1
1

1
B B

C4901

C4903

C4904

C4905

C4907

C4908
C4902

C4906
1

1
2 2 2 2 2 2 2 2

GP9 GP10
GP11 GP12
GP14 GP13
EMC@
EMC_NS@

De EMC@ EMC@ EMC@


EMC_NS@
EMC@
EMC_NS@

bu
PAD_RT2P21X2P99 PAD_RT2P21X2P99 PAD_RT2P21X2P99 PAD_RT2P21X2P99
@ @ PAD_RT2P45X2P5 PAD_RT2P45X2P5 @ @
1

@ @
FFC CONN GROUND PAD
1

1
1

1
1

A
PCB Fedical Mark PAD
For EMC
g A

FD1 FD2 FD3 FD4 FD5 FD6


Security Classification LC Future Center Secret Data Title
Issued Date 2014/09/24 Deciphered Date 2015/03/23 Hole
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 49 of 60
5 4 3 2 1

www.bios-downloads.com
5 4 3 2 1

+5VLP/ 100mA
B+
Silergy +1.05VALW / 4.4A

SYX198C CONVERTOR
+5VALW/5A
Adaptor Converter +1.8VA / 3A
D
EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD D

PAGE 54
RICHTEK +1.5VS / 500mA
+3VLP/ 100mA
Silergy RT5041A LDO
+1.24VALW / 500mA
SY8286B MOIC
Converter +3VALW/ 4A

FOR SYSTEM FOR SYSTEM +1.15VALW / 700mA


EC_ON EN PGOOD ALW_PWRGD
PAGE 54
POWER
+3.3VALW_SOC / 375mA

Ju
TI POWER SWITCH
+1.35V/10A
TPS51716RUKR_ EN_1.05VA EN1 +1.8VALW / 500mA
SYSON S5 WQFN20_3X3
SUSP# S3 +0.675VS/2A
EN_1.5VS EN2
TI Switch Mode

st
FOR DDR PGOOD PG for all MOIC power rail
PGOOD PAGE 56
BQ24780RUYR PAGE 55
Battery Charger
Switch Mode
PAGE 53 Onsemi Silergy
SY8032ABC_

for
NCP81201MNTXG CPU Core/6.4A
QFN28_4X4 SOT23-6 +1.05VGS/2A
C Switch Mode Switch Mode C

VR_ON FOR VDDR


SMBus EN FOR CPU Core PGOOD VGATE NVDD_PWR_EN EN PGOOD
PAGE 58 PGOOD_NB

LC
Onsemi
Battery NCP81201MNTXG GFX Core/11A
Li-ion QFN28_4X4
Switch Mode
VR_ON
4S1P/41WH EN FOR CPU Core PGOOD VGATE
PAGE 59 PGOOD_NB

NVDD_PWR_EN
VIDs
EN
Richtek
RT8812AGQW_
WQFN20_3X3
Switch Mode
FOR GPU VDDC
+VGA_CORE/30A FC
PE
PGOOD VGA_PWRGD
PAGE 57

B B

De
bu
A
g A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/09/24 Deciphered Date 2015/03/23 Power Diagram


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 50 of 59
5 4 3 2 1

www.bios-downloads.com
5 4 3 2 1

VCCRTC

VIN
RTC_VCC
JDCIN1 PF101 PJ101 JRTC1
1 APDIN 1 2 APDIN1 2 1 SUYIN_060003HA002M213ZL
1 2 2 1 PD101
2 3 7A_24VDC_429007.WRML @ JUMP_43X118 3
3 +3VL

470P_0402_50V7K

470P_0402_50V7K

+
4

-
4

1000P_0402_50V7K

1000P_0402_50V7K
5 1

1
5 ADAPTER_ID {44,53} PR101

EMC@
EMC_NS@

EMC_NS@
1

1
EMC@
PC101

PC102

PC103

PC104
D ACES_50299-00501-003 1 2 2 D
ME@

1U_0402_10V6K
2

2
1K_0603_5% BAT54CW_SOT323-3
2

PC2
change to 1K SD01310018J

RTC_VCC 20MIL @
1
+3VALW 20MIL
VCCRTC 20MIL
BAT_D 20MIL

Ju
st
for
LC
C C

FC
PE
B

De B

bu
g
A A

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 DCIN / RTC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 51 of 59
5 4 3 2 1
5 4 3 2 1

PL201 EMC@
HCB2012KF-121T50_0805
VMB2 1 2
JBATT1 VMB change bom structure to fix EMI fail issue
PF201 PL202 EMC@
1 8A_24V_F1206HI8000V024T HCB2012KF-121T50_0805
1 2 1 2 1 2
9 2 3 EC_SMCA PR202 1 2 100_0402_1% @ BATT+
GND1 3 EC_SMB_CK1 {44,53}
10 4 EC_SMDA 1 2 PJ202
GND2 4 EC_SMB_DA1 {44,53}
5 PR201 100_0402_1% 2 1
5 6 2 1
6

1
7
7 8 PC201 JUMP_43X79 PC202
8 1000P_0402_50V7K 0.01U_0402_25V7K

2
D EMC@ EMC@ PR225 D
SUYIN_125022HB008M202ZL 1 2
0_0603_5%
+VSBP
PD203 PQ210
AZC199-02S.R7G_SOT23-3 @ TP0610K-T1-E3_SOT23-3 @
EMC_NS@ PJ201
JUMP_43X39
3 1 1 2
B+

1
change BATT connector type to SMD 1 2 +20VSB

0.22U_0603_25V7K
@

Ju

1
100K_0402_1%

2
PR228

PC207
PC208 @
0.1U_0402_25V6

1
2

2
PR208 @

st
1 2 PR232
+3VALW
100K_0402_1% 1
VSBP_2 2 VSBP_3

22K_0402_1%
PR213
BATT_TEMP_IN 1 2
10K_0402_5%
BATT_TEMP {44,53} A/D @

for
1

@ PR234

1
PD204 0_0402_5% PQ204 D
1

EMC_NS@ 1 2 VSBP_1 2
{54} ALW_PWRGD G

1
2

S 2N7002KW_SOT323-3 @

3
PR237 PC210
2

AZ5215-01F_DFN1006P2E2 1 2 1U_0402_6.3V6K

2
{44,56} PCH_PWR_EN

LC
C 1K_0402_1% @ C

FC
PE
B

De B

bu
g
A A

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 BATTERY CONN/OTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 52 of 59
5 4 3 2 1
5 4 3 2 1

PL306 EMC@
HCB2012KF-121T50_0805
1 2
fix EMI fail issue
PL305 EMC@
HCB2012KF-121T50_0805
PQ301 PQ302 1 2
VIN AON6414AL_DFN8-5 P2 AON7408L_DFN8-5 P3
@ PR301
1 1 PJ301 0.01_1206_1%
2 2 JUMP_43X118
5 3 3 5 1 2 1 4
1 2 B+
2 3

10U_0805_25V6K

10U_0805_25V6K
4

EMC_NS@
1

2
D D

PC303

PC304

EMC_NS@
1

1
PC302
PC301 PR302 0.022U_0402_25V7K

1
4.7_0603_5%

2
470P_0402_50V7K

5
PC305

2
0.1U_0402_25V7-K PQ303
AON7408L_DFN8-5
2 1
@
PQ313 BQ24780_BATDRV 4

1U_0603_25V6K

1
2N7002KW_SOT323-3

1
Ju
3 1

PC307
S

D
PC306

499K_0402_1%
2

1
0.1U_0402_25V7-K

3
2
1
2
PR304 @ PR305 @

PR303
1M_0402_5% 1M_0402_5% PC308

G
2 1 2 1 0.01U_0603_50V7K
VIN B+

1
2
delete PD301

st PC309

3
@ 100P_0402_50V8J
PD302 1 2
B+
BAT54CW_SOT323-3

for

10U_0805_25V6K

10U_0805_25V6K
2200P_0402_50V7K
PR309

1
2N7002KW_SOT323-3
1

1
0_0402_5% D

PC311

PC313

PC314
VIN
1

ACN
ACP
1 2 2

EMC@
4.02K_0603_1%

{44} ACOFF
G PR311 PQ311
PQ315

432K_0603_1%

2
2
4.02K_0603_1%
PR310

@
2

5
S PR314

PR313
BQ24780_VDD
3

1
@ PR315 10_1206_5%
2

AON7408L_DFN8-5
PR312 64.9K_0603_1% PC315 PC316

ACN
ACP
10K_0402_1% 1 2 1U_0603_25V6K 2.2U_0603_10V7K

LC
C C

1
2 1 BQ24780_VCC 28 24 1 2
1

2
VCC REGN 4
@
1 2 BQ24780_ACDET6 PR316 PC318
ACDET 2.2_0603_5% 0.047U_0603_25V7-K
PC317 0.1U_0402_25V7-KBQ24780_CMSRC 25 BST_CHG1 2 2 1
BTST PR317
PL302

3
2
1
BQ24780_ACDRV BQ24780RUYR_QFN24_4X4 0.01_1206_1%
3 26 DH_CHG 1UH_PCMB053T-1R0MS_7A_20%
CMSRC HIDRV
PR338 20K_0402_1% @ 1 2 CHG 1 4 BATT+

FC
2 1 4
ACDRV PQ312 2 3

1
BQ24780_VDD PR318 1 2100K_0402_5% @ 27 LX_CHG
PHASE PR321

AON7408L_DFN8-5
PR319 1 2 0_0402_5% 5
BQ24780_ACOK 2.2_0805_5%
{44} ACIN ACOK EMC_NS@
PR320 1 2 0_0402_5% 11
BQ24780_SDA

10U_0805_25V6K
1 2
{44,52} EC_SMB_DA1 SDA PU301 23 DL_CHG 4

10U_0805_25V6K
LODRV

2
PR322 1 2 0_0402_5% 12
BQ24780_SCL 22 PC321

PC319
{44,52} EC_SMB_CK1 SCL GND 1200P_0402_50V7-K

PC320
2
PE
EMC_NS@

0.1U_0402_25V7-K
3
2
1

1
PR323 1 2 0_0402_5% BQ24780_IADP 7 29
{44} ADP_I IADP PAD

1
BQ24780_IDCHG 8 18 BQ24780_BATDRV

PC322

0.1U_0402_25V7-K
IDCHG BATDRV

PC323
BQ24780_PMON 9 PR339 10_0603_5%

2
PMON 17 BQ24780_BATSRC 2 1
BATSRC
@ @ 20 BQ24780_SRP 2 1 SRP
1 2BQ24780_PROC#
10 SRP
{44,58,59} VR_HOT#
100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

1
PROCHOT# PR328
2

PR327 13 10_0603_5% PC327


PC324

PC325

PC326

De
0_0402_5% CMPIN 1U_0603_25V6K

BATPRES#

2
TB_STAT#
14
1

CMPOUT 19 BQ24780_SRN 2 1 SRN


21 SRN
ILIM PR329
1

B B
10_0603_5%
PR330

16

15
0_0402_5%

bu
PR331 PR332
2

+3VALW VIN 316K_0402_1% 14.7K_0402_1%


1 2 1 2
+3VALW BATT_TEMP {44,52}
@
1
1

PR333
1

PC328 100K_0402_1%

g
1

PR334 0.1U_0402_25V6
2

750_0603_1% PR335 @
2

1M_0402_5%
2

@
2

D PQ310A
PR336 2 ADAPTER_ID_ON#_G
0_0402_5% G

S 2N7002KDWH_SOT363-6
1

ADAPTER_ID {44,51}
1

D
680P_0402_50V7K

5 ADAPTER_ID_ON# {44}
1

PR337 G
1M_0402_5%
1
0.1U_0402_25V6

S PQ310B
PC329

4
1

2N7002KDWH_SOT363-6
PC330

A PD304 A
AZ5123-01F.R7G_DFN1006P2X2 @ @
2

@ EMC@
2

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 CHARGER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 53 of 59
5 4 3 2 1
5 4 3 2 1

B+
@
PJ401
2 1
1.5A +3VIN
2 1

1M_0402_5%
0.1U_0402_25V6
1

1
D D
PC403

PR401
10U_0805_25V6K
JUMP_43X79 +3VBS 1 2

PC401

PC402
2

2
0.1U_0603_25V7-M

1
@ 21 +3VALW

IN5

IN3

IN2

IN1

BS
EMC_NS@ GND4
+3VLX 6 20 @
LX LX3 PL401 PJ402
5A
7 19 +3VLX 1 2 +3VALW_P 2 1
GND1 LX2 2.2UH_PCMB063T-2R2MS_8A_20% 2 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
8 18
100mA +3VLP
GND2 GND3

1
Ju
JUMP_43X79
+3V_PWRGD 9 17 PR403

PC404

PC405

PC406

PC407
PG LDO 4.7_0805_5%

2
10 16 EMC_NS@

1
NC1 NC3

OUT

NC2

1 2
EN2

EN1
PC409

FF
4.7U_0603_6.3V6K

2
SY8286BRAC_QFN20_3X3 PC410

st

+3VIN 11

12

13

14

15
PTP401 680P_0402_50V7K
PU401

2
PAD EMC_NS@

+3VALW_P
PR402 PR414
1 2 EC_ON_R 1 2

+3VFB
{44} EC_ON 0_0402_5% 0_0402_5%

{44}
{39}

MAINPWON
EC_ON_R

2
PR417
1
0_0402_5%
1
2
@

0.1U_0402_25V6
PC408

1
2
@

1M_0402_5%
PR404
for 1
PC411

0.01U_0402_25V7K
2 1

1K_0402_1%
PR405
2
2

LC
C C
PR429
330_0603_5%
@
+3VL
1

+3VLP
1

PQ405 D @
1

2 PJ404
PR427 G PC425 2 1
100K_0402_5% 2.2U_0603_10V7K 2 1

FC
2

@ S @
3

2N7002KW_SOT323-3 JUMP_43X39
2

@
+3VALW

2
PR406
100K_0402_5%

PE
PR407 @

1
+3V_PWRGD 1 2
ALW_PWRGD {52}
B+ PU402
0_0402_5% @
@
PJ405 PR408
2 1
2.5A +5V_VIN 8 2 +5V_PWRGD 1 2
2 1 IN PG
10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
1

SYX198CQNC_QFN10_3X3

PC415 0_0402_5% @ +5VALW


PC413

PC414

JUMP_43X79 9 6 +5VBS 1 2
PC412

GND BS 3.3UH_PCMB063T-3R3MS_6.5A_20%
5A
2

PC416 0.1U_0603_25V7-M PL402 PJ406

De
1 2+5VVCC 5 10 +5VLX 1 2 +5VALW_P 2 1
VCC LX 2 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1
PR409 EMC_NS@ 1U_0603_25V6M PR413

1
EC_ON_R 1 2 +5VALW_EN 1 4 +5VALW_OUT1 2+5VALW_P PR410 JUMP_43X79
0_0402_5% EN OUT 0_0402_5% 4.7_0805_5%

PC417

PC418

PC419

PC420
B B
EMC_NS@ @
100mA

2
+5VFB 3 7
+5VLP

2
FB LDO
1M_0402_5%

bu
4.7U_0603_6.3V6K
1

1
1

PC423
PR411

PC422

@ PC421 680P_0402_50V7K
2

2
0.1U_0402_25V6 EMC_NS@
2

PC424
1 2

6800P_0402_25V7-K
1
PR412

1K_0402_1%
2

g
A A

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 PWR_3VALW/5VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 54 of 59
5 4 3 2 1
A B C D

1
PC502 @
0.1U_0402_10V7K

2
PR504 0_0402_5%
+3VALW 1 2 SUSP# {44,46,56}
1.35V_GND

169K_0402_1%
1
1 1
1.35V_GND 1.35V_GND PR501 0_0402_5% @
2A

PR505
2 1 PJ501

S3_1.35V
+1.35V_B+ 2 1

10K_0402_5%
110K_0402_1%

SYSON {44}
2 1 B+
1

PR503
0.1U_0402_10V7K

10U_0805_25V6K

10U_0805_25V6K
1
PR506

2 1 @

EMC_NS@
OPT@
DIS ------10A

0.1U_0402_25V6
DDR_TRIP 2

1
PC503

PC504

PC505
PR513 PC501 JUMP_43X79

S5_1.35V
12K_0402_1%
UMA-----6A

1
UMA@ PR515
DDR_TRIP
2

2
{5} VDDQ_PGOOD 1 2

2
PTP402

Ju
1M_0402_5% PAD

5
10U_0805_6.3V6M

20

19

18

17

16
PU501
1

@
PC513

PGOOD

MODE

TRIP

S3

S5

1
@ 21 PR507 PC506
PAD 0_0603_5% 0.1U_0603_25V7-M PQ501 @
2

1 15 1
BST_1.35V 2 2 1 4 PJ502

st
VTTSNS VBST AON7408L_DFN8-5 2 1
PJ508 2 1
+1.35V 2
2 1
12A 2
VLDOIN DRVH
14 UG_1.35V JUMP_43X118
PL501
2A

3
2
1
0.68UH_PCMC063T-R68MN_15.5A_20% PJ503
22U_0805_6.3V6M

22U_0805_6.3V6M

+0.675VSP JUMP_43X79 3 13 LX_1.35V 1 2 +1.35V_L 2 1

for
VTT SW 2 1
+1.35V
1

1
PC507

PC508

TPS51716RUKR_WQFN20_3X3

2
JUMP_43X118

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
PTP403 1
4 12 @

0.1U_0402_25V6
2

VTTGND V5IN
+5VALW

1
PAD 4.7_0805_5% + PC509

1
PR509

PC517

PC516

PC518

PC519

PC514
@ AON7506_DFN 330U_2.5V_M

VDDQSNS
5 11 PC510 EMC_NS@ OPT@

2
VTTREF DRVL 1U_0603_25V6M 2

2
REFIN
1

PGND
VREF
PQ502
GND
+VTT_REFP

LC
2
PC511 2

1U_0402_6.3V6K LG_1.35V 4 UMA@ UMA@ UMA@ UMA@


2

EMC_NS@
6

DDR_REFIN 8

10

1
PC512
DDR_VREF 680P_0402_50V7K
1.35V_GND EMC_NS@

3
2
1

2
2

2
30K_0402_1%

PR511

FC
PC1265 1.35V_GND
1

0.1U_0402_25V6
1

1.35V_GND
93.1K_0402_1%

PJ504
1

PR512

2 1
+0.675VSP 2 1 +0.675VS

PE
PC515
0.01U_0402_25V7K
2

JUMP_43X79
2

1.35V_GND 1.35V_GND

3
1

JUMPER
PJ4
2

De 3

bu
@
1.35V_GND

g
4 4

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 1.35VS/+0.675VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 55 of 59
A B C D
5 4 3 2 1

+3VALW

1
PU704 @ +5VALW
PC190 PJ14
10U_0603_6.3V6M 17 20 IN_1P05A 2 1
2 +3VALW_SOC IN_3P3A IN_1P05A_0 2 1

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
1

1
21

PC1308

PC1309
EMC_NS@
18 IN_1P05A_1 JUMP_43X39

PC92
O_3P3A

2
1
D D
+1.8VA PC191 PL8
10U_0603_6.3V6M +1.05VA

2
0.47UH_PCMC063T-R47MN_17.5A_20% PJ20
22 1 2 +1.05VS_P 2 1
LX_1P05A_0 2 1

2
14
1

1
SWIN_1P8A 23 PR9463

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
0.01U_0402_25V7K
PC194 +1.8VALW LX_1P05A_1 PR9466 JUMP_43X79
4.7_0603_5%

1
10U_0603_6.3V6M 16 0_0402_5%

PC812
2

SWO_1P8A EMC_NS@

PC800

PC801

PC802

PC807

PC815
PC1305
1 1
1

2
PC195 19 +1.05VS_SENSE PC1316
10U_0603_6.3V6M O_1P05A 680P_0402_50V7K

2
EMC_NS@

2
PR9467 @
9 2 1 EMC_NS@
IN_1P5S PR704 VNN_SENSE {7}
+1.5VS @ 0_0402_5%
1

PJ407 26 2 1
PC192 2 1 +1.5VS_P 10 EN_1P05A PCH_PWR_EN {44,52}
2 1 O_1P5S

1
10U_0603_6.3V6M
2

0_0402_5%
1
PC1313
JUMP_43X39 PC193 0.01U_0402_25V7K

2
Ju
4.7U_0603_6.3V6K @ +5VALW
2

PJ15
1 IN_1P8 2 1
7 IN_1P8_0 2 1

0.1U_0402_25V6

10U_0805_25V6K

10U_0805_25V6K
1

1
+1.24VALW @ IN_1P24A 2

PC808

PC809
PJ408 RT5041ABGQW_WQFN28_4X4 IN_1P8_1 JUMP_43X39

PC91
EMC_NS@
1

2 1 +1.24VA_P 5

2
PC1306 2 1 O_1P24A
1

10U_0603_6.3V6M
2

JUMP_43X39 PC1307
22U_0805_6.3V6M PL10 PJ21 +1.8VA
2

st
27 LX_1P8 1 2 +1.8VALW_P 2 1
LX_1P8_0 2 1

2
1UH_PH041H-1R0MS_3.8A_20%
8 28

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

0.01U_0402_25V7K
+1.15VA @ IN_1P15A LX_1P8_1 PR9462 JUMP_43X79
10U_0603_6.3V6M

1
PJ409
10U_0603_6.3V6M

2 1 6 4.7_0603_5%
@ +1.15VA_P
PC197

PC196

PC803

PC804

PC805

PC806

PC811
1
2 1 O_1P15A
2

2
EMC_NS@
1

3 +1.8VALW_P

1
JUMP_43X39 PC198 O_1P8 PC1315
22U_0805_6.3V6M 680P_0402_50V7K
2

EMC_NS@

2
PC1312

for
1 2 0_0402_5% EMC_NS@
5041_VCC 2 1 25
0.01U_0402_25V7K @ PR708 SLP_S0iX_B +5VALW
PR9452
{44,46,55} SUSP# 2 1 4 11 5041_VCC 1 2
C PR706 0_0402_5% SLP_S3_B VCC 0_0603_5% C
PR705 0_0402_5% @
2 1 24 12

1
{7} SUSWARN# SUSPWRDNACK GND
PR707
PGND_EX

PC1304
PR9456 2 1 13 15 0.01U_0402_25V7K

2
1 2 {44} RSMRST_P RSMRST PGND

10K_0402_5% 0_0402_5%
29

LC
FC
B
+3VALW

PE B
1

PR616
100K_0402_5% +1.05VGS_L

De
@
2A
2

+1.05VGS_PWRGD
PU603
PJ605 PL602 PJ606
+3VALW 2
2 1
1 1A 1.05VMP_VIN 4
IN LX
3 1.05VMP_LX 1 2 2
2 1
1 +1.05VGS
1UH_PH041H-1R0MS_3.8A_20%
JUMP_43X79 5 2 JUMP_43X79
22U_0805_6.3V6M

22U_0805_6.3V6M

PG GND
1

4.7_1206_5%

OPT@
6 1
PC613

PC614

PR611

@ FB EN @
2

SY8032ABC_SOT23-6
68P_0402_50V8J

OPT@ PR612
22U_0805_6.3V6M

22U_0805_6.3V6M
2

75K_0402_1%
@ OPT@
PC615

PC616

PC617

bu
1

OPT@ OPT@
2

PC618
PD701 680P_0402_50V7K
2

1 2 @ @
OPT@
OPT@ OPT@

1 2 1.05VGS_EN 1.05VMP_FB
{23,57} DGPU_PWROK
PR172 4.7K_0402_5%
1

@
1

PR614 PC619 PR615

g
1M_0402_5% .1U_0402_10V6-K 100K_0402_1%
PR715 OPT@ OPT@
2

2 1
2

{22,57} EN_VGA 0_0402_5%


OPT@
OPT@

{21} +1.05VGS_EN

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/09/24 Deciphered Date 2015/03/23 PWR-SYSTEM POWER


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 56 of 59
5 4 3 2 1

www.bios-downloads.com
5 4 3 2 1

D D

+VGA_B+

+3VGS PJ710
2 1
2 1 B+
pr9446 OPT@

OPT@ 2 PR9442 JUMP_43X79

10U_0805_25V6K

10U_0805_25V6K
2 1 10K_0402_5% @

Ju
{7,21} PXS_PWREN
PR9446 @ PD705

1
PC1295

PC1298
0.1U_0402_25V6
AON6414AL_DFN8-5
0_0402_5% RB751V-40_SOD323-2
1

1
NVVDD PWM_VID
OPT@

PC1255
2 1 1 2 EN_VGA EN_VGA {22,56}
{19,21} 3VGS_PWR_EN

2
PR9445 @

2
1

PQ991
0_0402_5% PC1303
PR9443 PR9444 .1U_0402_10V6-K 4
100K_0402_5% 1 2 OPT@

2
st
@ OPT@
10K_0402_1% PR9429 PC1300 EMC_OPT@ OPT@ OPT@
2

0_0603_5% 0.22U_0603_16V7K

3
2
1
2
2 1BOOT1_2_VGA 1 2 OPT@
PR9430 OPT@ OPT@
NVVDD PWM_VID 0_0402_5% PL705
{19} NVVDD PWM_VID +VGA_CORE
0.24UH_PCME063T-R24MS1R145_35A_20%
PSI_VGA reserve OPT@ 1 2

BOOT1_VGA
{19} PSI_VGA

for

5
10P_0402_50V8J
VSSSENSE_VGA PQ992 OPT@
{20} VSSSENSE_VGA

2
AON6554_DFN
PC1261
VCCSENSE_VGA
{20} VCCSENSE_VGA @

2
GPU_VID 4.7_0805_5%

330U_D2_2V_Y

330U_D2_2V_Y
1 1
C DGPU_PWROK LGATE1_VGA 4 PR9435 C
{23,56} DGPU_PWROK

OPT@ PC1293

OPT@ PC1297
PC1258 + +

1
1 2 @

1
2 2

PSI_VGA
2700P_0402_50V7-K OPT@ UGATE1_VGA PR9438 OPT@

3
2
1
LC

EN_VGA
13K_0402_1%
PR9460 PR9461
VREF_VGA 1 2 1 2 OPT@

1
PHASE1_VGA
20K_0402_1% OPT@ 20K_0402_1% OPT@ PC1296
680P_0402_50V7K

REFADJ

2
5

1
PR9464 @
0_0402_5% PR9458 PR9459

UGATE1

BOOT1
VID

PSI

EN
OPT@ 2 1 1 2 1 2
PC1301

FC
18K_0402_1% OPT@ 2K_0402_1% OPT@ 6 20 4.7U_0603_6.3V6K
PR9447 REFADJ PHASE1
PC1259
2 1 1 2 REFIN 7 19 1 2OPT@
PC1257 REFIN LGATE1
2700P_0402_50V7-K @ +VGA_B+ 1 2 VREF_VGA8 18 PVCC_VGA 1 2
100_0402_5% VREF PVCC +5VS
OPT@ 0.1U_0603_25V7K OPT@ PR9418 0_0603_5%
OPT@ PR9465 2
PR9449 0.1U_0402_25V6 PC1314 1 OPT@ OPT@1 2 9 17
OPT@
0_0402_5% 2 1 2.2_0603_5% PR9457 330K_0402_5% TON LGATE2
VSSSENSE_VGA OPT@ 2 1 VSS_SEN 10 16 +VGA_B+
RGND PHASE2

UGATE2
PGOOD

BOOT2
VSNS
GND
1

PC1269

SS
PE
1000P_0402_50V7K PU910

10U_0805_25V6K

10U_0805_25V6K
PR9420 @
2

21

11

12

13

14

15

0.1U_0402_25V6
AON6414AL_DFN8-5
0_0402_5% RT8812AGQW_WQFN20_3X3

1
PC1275

PC1276
VCCSENSE_VGA OPT@ 2 1 VCC_SEN

1000P_0402_25V7-K

PC1273
BOOT2_VGA

2
1

OPT@ PQ993
PC1256
UGATE2_VGA 4
PR9448

2
1 2 DGPU_PWROK
+VGA_CORE
OPT@ PR9425
B B
10K_0402_5% PR9424 PC1278

3
2
1
100_0402_5% 2 1 +3VS 0_0603_5% 0.22U_0603_16V7K EMC_OPT@ OPT@ OPT@

De
OPT@ @ 2 1OPT@ BOOT2_2_VGA 1 2
SS time down OPT@ PL706 +VGA_CORE
0.24UH_PCME063T-R24MS1R145_35A_20%
PR9468 PHASE2_VGA 1 2
10K_0402_5% OPT@

5
2 1 +3VGS PQ994
OPT@

1
AON6554_DFN
PR9453
4.7_0805_5%

330U_D2_2V_Y

330U_D2_2V_Y
bu
1 1
fix PGOOD leakage issue LGATE2_VGA 4 @

OPT@

@
PC1280

PC1281
+ +

2
OPT@ 2 2

3
2
1
g

1
PC1302
680P_0402_50V7K

2
@
Change PC1280 from reserve to mount
Change PC1281 from mount to reserve

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1

1
PC1287

PC1288

PC1289

PC1290

PC1291

PC1292
A A

2
OPT@ OPT@ @ @ OPT@ OPT@

Security Classification
Security Classification LC Future Center Secret Data Title
Issued Date 2014/09/24 Deciphered Date 2015/03/23 PWR-VGA_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 57 of 59
5 4 3 2 1

www.bios-downloads.com
5 4 3 2 1

B+ CORE_VIN
PJ_43x79_6
PJ901
3A

CORE_GND CORE_GND

470P_0402_50V7K
19.6K_0402_1%
1
D D

1
PR778

PC1091

220K_0402_5%_TSM0B224J4702RE
2
PR779

2
1 2
{59} VR_IMVP_IMON
for CPU TDC from 6.4A change to 7.7A 110K_0402_1%

220P_0402_50V7K

330P_0402_50V7K
PR785: 21K→24.3K/0402/1%

1
75K_0402_1%

2
PR783: 7.68K→9.31K/0402/1% PR780

PR781

PH705

PC1092

PC1093
2 1
PR778: 20.5K→19.6K/0402/1% +5VALW 0_0402_5%

1
@

2
PR782
1 2 CPU_PH

69.8K_0603_1%

2 PR784 1+CPU_CORE
1 CSCOMP

CPU_CSREF
CORE_VIN

Ju
CORE_GND

10_0402_1%
9.31K_0402_1%

CSCOMP
PR786

PR783

2
CSSUM
2 @ 1
CORE_GND
0_0402_5% PR785 PC1097

2
24.3K_0402_1% 1000P_0402_50V7K CORE_VIN

1
PC935 PC936 PC937

2
1
CPU_CSREF

10U_0805_25V6K

10U_0805_25V6K
st
PR787 PC1099 PC1100 PC1101 CORE_GND

0.1U_0402_25V6
49.9_0402_1% 330P_0402_50V7K 10P_0402_50V8J CORE_GND 2.2U_0603_6.3V6K

2
1 2 1 2 1 2

2
1 PR788 2
+5VALW

1
PR790 0_0603_5%

5
PR791 PC1102 PR792
1K_0402_1% 2200P_0402_50V7K 4.02K_0402_1% 20K_0402_5% PR793

21
20
19
18
17
16
15
1 2 1 2 1 2 0_0402_5%
1 2

IOUT

CSREF
ILIM

CSSUM

PVCC
CSCOMP

IMAX
CORE_GND

2
PR794 PQ903
@ 0_0402_5% PC1103 CPU_HG 4 EMC_NS@
1 2 22 14 0.01U_0402_25V7K AON7408L_DFN8-5 +CPU_CORE

for
23 ROSC VBOOT/ADDR 13 TSENSE 1 2
PR795
24 COMP
FB
TSENSE
LG
12 CPU_LG
CORE_GND
PL902
6.4A
25 11

3
2
1
1 2 26 DIFFOUT PGND 10 CPU_PH CPU_PH 1 2
{7} CPU_VSS_SENSE VSN SW
0_0402_5% 27 9 CPU_HG PC1110
VSP HG

5
VR_HOT#
C 28 8 1 2 1 2 AON7506_DFN 0.22UH_PCMB063T-R22MS_23A_20% C

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
VR_RDY
ENABLE
2

1
VCC BST

ALERT#
PC1111 @ PC1112

VRMP

1
SCLK
1 2 29

SDIO
PR797 0.22U_0603_25V7K PR9454

PC944

PC945

PC946

PC947

PC948

PC952
1000P_0402_50V7K GND 2.2_0603_5% PQ904 4.7_0805_5%
1

560P_0402_50V7-K PU907 @

2
CPU_LG 4
1
2
3
4
5
6
7

1 2
{7} CPU_VCC_SENSE 1 PR798 2 NCP81201MNTXG_QFN28_4X4
PR799 CORE_GND
0_0402_5% 1 2 PC1310
+5VALW PR800 680P_0402_50V7K

3
2
1

2
LC
2.2_0603_5% 1 2 @
CORE_VIN
1

PC1114 @ @
1U_0603_25V6M 1 1K_0402_1%
2

PC1115
0.01U_0402_25V7K
2

PR801 CORE_GND
2 1 +3VALW
{44,59} EC_VR_ON
0_0402_5%
2

1
CORE_GND
1M_0402_5%

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
PC1116
PR815

1
+1.8VALW .1U_0402_10V6-K PR802 + PC908

PC996

PC967

PC966

PC972
2

@ 10K_0402_5% 220U_D2_2.5VY_R6M
PR804

FC
1

2
2

CORE_GND 0_0402_5% 2 3
PR803 1 2
VR_CPU_PWROK {44,59}
1

69.8_0402_1% CORE_GND
PR9450
fixed CORE abnormal start up 200_0402_1%

100K_0402_1%_TSM0B104F4251RZ
1

PR805
{44,53,59} VR_HOT# PR810 0_0402_5% TSENSE 2 1
2

2 1
{7,59} CPU_SVID_DAT
0_0402_5%
2 1
{7,59} CPU_SVID_ALERT#
PR811 0_0402_5%

1
PR806

PH706
{7,59} CPU_SVID_CLK 13K_0402_1%
1

CORE_GND
1

PR807 2

2
200_0402_1% PR808 PR809

PE
1

301_0402_1% 200_0402_1% PC1117


+1.05VA .1U_0402_10V6-K
2

CORE_GND
2

PJ711
1 2

B JUMPER B

CORE_GND

De
bu
A
g A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/09/24 Deciphered Date 2015/03/23 PWR_CPU_CORE/GFX_CORE


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 58 of 59
5 4 3 2 1

www.bios-downloads.com
5 4 3 2 1

GFX_CORE_GND GFX_CORE_GND

B+ GFX_VIN
PJ_43x79_6

470P_0402_50V7K
PJ902

1
3A

1
PR777

PC767

220K_0402_5%_TSM0B224J4702RE
20.5K_0402_1%
PR758 1

68U_25V_M
2
1 2 +

PC905
{58} VR_IMVP_IMON
110K_0402_1%

220P_0402_50V7K

330P_0402_50V7K
1

1
2

75K_0402_1%

2
D D
PR776

PR824

PH708

PC790

PC793
2 1
+5VALW 0_0402_5% @
GFX_VIN

1
@

2
PR822
1 2 GFX_PH GFX_VIN

1
69.8K_0603_1% PC957 PC956 PC955

1 GFX_CSCOMP

2 PR765 1+GFX_CORE

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
2

2
Ju

GFX_CSREF
fixed OCP GFX_CORE_GND

GFX_CSCOMP

10_0402_1%
13.3K_0402_1%

GFX_CSSUM
PR763

5
PR767

2
2 @ 1

st
GFX_CORE_GND
0_0402_5% PR773 PC771 EMC_NS@

2
35.7K_0402_1% 1000P_0402_50V7K

1
PQ905
GFX_HG 4

2
GFX_CSREF

1
PR771 PC770 PC768 PC799 GFX_CORE_GND AON7408L_DFN8-5
49.9_0402_1% 330P_0402_50V7K 10P_0402_50V8J GFX_CORE_GND 2.2U_0603_6.3V6K +GFX_CORE
1 2 1 2 1 2
PL903 11A

2
for
1 PR769 2
+5VALW

3
2
1
1
0_0603_5% GFX_PH 1 2
PR766 PC750 PR823 PR747

1
1K_0402_1% 2200P_0402_50V7K 4.02K_0402_1% PR820 AON7506_DFN 0.22UH_PCMB063T-R22MS_23A_20%

21
20
19
18
17
16
15
20K_0402_5%

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 2 1 2 1 2 48.7K_0402_1% PR9455

1
1 2 4.7_0805_5%

PC953

PC963

PC975

PC976

PC977

PC989
PVCC
IOUT

CSREF
CSCOMP

IMAX
ILIM

CSSUM
GFX_CORE_GND

2
PR825 PQ906 @
@ 0_0402_5% PC788

1 2

2
1 2 22 14 0.01U_0402_25V7K GFX_LG 4
23 ROSC VBOOT/ADDR 13 1
GFX_TSENSE 2
COMP TSENSE GFX_CORE_GND
24 12 GFX_LG PC1311

LC
C C
25 FB LG 11 680P_0402_50V7K

2
1 2 26 DIFFOUT PGND 10 GFX_PH @
{7} UNCORE_VSS_SENSE

3
2
1
PR826 27 VSN SW 9 GFX_HG PC756
0_0402_5% 28 VSP HG 8 1 2 1 2 @

VR_HOT#
VCC BST
2

VR_RDY
ENABLE

ALERT#
PC1113 PC769

VRMP
1 2 @ 29

SCLK
PR774 0.22U_0603_25V7K

SDIO
1000P_0402_50V7K GND 2.2_0603_5%
1

560P_0402_50V7-K PU903

FC
1
2
3
4
5
6
7
{7} VCC_AXG_SENSE 1 PR817 2 NCP81201MNTXG_QFN28_4X4
PR772 GFX_CORE_GND
0_0402_5%
+5VALW 1 2 17A
PR813
2.2_0603_5% 1 2
GFX_VIN
1

PC759 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
220U_D2_2.5VY_R6M
1U_0603_25V6M 1K_0402_1%
1

1
+

PC909

PC994

PC993

PC988

PC981

PC979

PC982

PC990

PC983

PC985
2

PC763
0.01U_0402_25V7K
2

2
PR770 GFX_CORE_GND 2 3

PE
2 1 +3VALW
{44,58} EC_VR_ON
0_0402_5%
1

GFX_CORE_GND
PC798
+1.8VALW .1U_0402_10V6-K PR821
2

@ 10K_0402_5% @
@ PR789
2
2

GFX_CORE_GND 0_0402_5%
PR775 1 2
69.8_0402_1% VR_CPU_PWROK {44,58}
@
1

100K_0402_1%_TSM0B104F4251RZ
De
1

PR9451 PR816
{44,53,58} VR_HOT# PR812 0_0402_5% 200_0402_1% 2
GFX_TSENSE 1
2 1
{7,58} CPU_SVID_DAT
0_0402_5%
2

2 1
B {7,58} CPU_SVID_ALERT# B
PR814 0_0402_5%

1
PR818

PH707
{7,58} CPU_SVID_CLK 13K_0402_1%

bu
1

GFX_CORE_GND
1

PR819
2

2
200_0402_1% PR768 PR796
1

301_0402_1% 200_0402_1% PC797


+1.05VA .1U_0402_10V6-K
2

GFX_CORE_GND
2

g
PJ708
1 2

JUMPER

GFX_CORE_GND

A A

Security Classification LC Future Center Secret Data Title

www.bios-downloads.com
Issued Date 2014/09/24 Deciphered Date 2015/03/23 PWR_GFX Core
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWC1
Date: Tuesday, April 07, 2015 Sheet 59 of 59
5 4 3 2 1

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