Вы находитесь на странице: 1из 10

Name: Vishakh V Bharadwaj

Roll number: 2018HT80504

Subject: CAD for IC Design - MELZG641

Question 1: Write all the parameters that you know when you do timing
analysis like slack, WNS (Worst negative Slack), TNS (Total Negative
Slack), what is CDC (Clock Domain Crossings)?

The parameters considered while doing timing analysis are:

1) Setup time:
• Setup time is the minimum amount of time the data signal should be
held steady before the clock edge so that the data is
processed/sampled by the clock successfully. This applies to
synchronous circuits such as the flip-flop.
• The time when input data is available and stable before the clock
pulse is applied is called Setup time.

2) Hold time:

• Hold time is the minimum amount of time the data signal should be
held steady after the clock event so that the data is reliably sampled.
This applies to synchronous circuits such as the flip-flop.
• The time after clock pulse where data input is held stable is called
hold time.

3) Slack:

• It is difference between the desired arrival times and the actual arrival
time for a signal.
• Slack time determines if the design is working at the desired
• Positive Slack indicates that the design is meeting the timing and
still it can be improved.
• Zero slack means that the design is critically working at the desired
• Negative slack means, design has not achieved the specified
timings at the specified frequency.
• Slack must be positive always and negative slack indicates a violation
in timing.

WNS (Worst negative Slack):

This points to the path having maximum negative slack.

TNS (Total Negative Slack):

This gives the sum of all negative slacks in the design.

4) Clock jitter:

• Clock jitter is the amount of cycle-to-cycle variation that can occur in

a clock’s period. Because clocks are generated by real physical
devices such as phase-locked loops, there is some uncertainty, and a
perfect waveform with an exact period of x nanoseconds cannot be

5) Clock Skew:

• It is the difference in arrival times of the capture edge at two adjacent

Flip-flop pairs.

Positive skew:

o If capture clock comes late than launch clock, then it is called

positive skew.
Negative skew:

o If capture clock comes early than launch clock it is called

negative skew.


• Clock domain crossing or simply clock crossing, is the traversal of a

signal in a synchronous digital circuit from one clock domain into
• Alternatively, it can also be said that clock domain crossing occurs
whenever data is transferred from a flop driven by one clock to a flop
driven by another clock.

Considering the above diagram, there are 2 flipflops FA and FB, which are
driven by 2 different clocks C1 and C2. The signal ‘A’ launched by the C1
clock domain and needs to be captured properly by the C2 clock domain.
Depending on the relationship between the two clocks, there could be
different types of problems in transferring data from the source clock to the
destination clock.
Question 2: Setup violations and hold violations (how to do worst case
analysis) for it. arrival time, trace back method, required time, critical path

Setup time violation:

• This is a kind of timing error/violation in which the signal arrives too
late and misses the time when it should advance

Hold time violation:

• This kind of timing violation occurs when an input signal changes too
soon just after a clock’s active transition (can be either during positive
edge triggered clock or negative edge triggered clock)

Required time:

• The time within which data is required to arrive at some internal node
of the design. Designers specify this value by setting constraints.

Arrival Time:

• The time in which data arrives at the internal node. It includes all the
net and logic delays in between the reference input point and the
destination node.

Setup Slack: Required time - Arrival time

Hold slack: Arrival time - Required time

Setup Slack:

• Amount of margin by which setup requirements are met.

• It is time required for data to be available at input of device before
clock edge captures the data in device.
• To meet the setup requirements the following equation must be

Setup slack check = Required time > Arrival time

Tcap + T-Tsetup - Tuncertainity > Tcomb + Tcq + Tlaunch +
(uncertainty includes skew, jitter and slack margin)

Hold Slack:

• Amount of margin by which hold time requirements are met.

• It is time required for data to be available at input of the device after
clock edge captures the data in device.

Hold slack check = Required time < Arrival time

Tcap + Thold < Tcomb + Tcq + Tlaunch + Twire

The Negative value of Hold Slack means signal value propagates from one
register to next, too fast that it overrides the old value before that can be
detected by the corresponding active clock edge.

Critical path:
• This is a path between an input and output with maximum delay
• The critical path can be found using technique called traceback

Question 3: Give main difference between static and dynamic timing
analysis, how is interface timing analysis critical, what is statistical timing
analysis, how glitches and clock skews affect timings?


Checks only the static delay Verifies functionality of the design
requirement of the circuit without by applying test vectors
any input or output vectors
Can only be used to analyze Can be used to analyze
synchronous designs synchronous and asynchronous
Focus is on the timing of the design Focus is on both the functionality
and timing of the design

Probability that false path is also Does not catch false paths as path
considered during this kind of is considered based in input test
analysis vectors
Faster compared to dynamic timing Slower compared to static timing
analysis analysis

Brief about interface timing analysis:

Many of the common problems in chip designing are related to interface
timing between different components of the design. These can arise
because of many factors including incomplete simulation models, lack of
test cases to properly verify interface timing, requirements for
synchronization, incorrect interface specifications, and lack of designer
understanding of a component supplied as a 'black box'. There are
specialized CAD tools designed explicitly to analyze interface timing, just
as there are specific CAD tools to verify that an implementation of an
interface conforms to the functional specification.

Statistical timing analysis:
In recent years, the increased variation in semiconductor devices and
interconnect has introduced several issues that cannot be handled by
traditional (deterministic) STA.
This has led to considerable research into statistical static timing
analysis, which replaces the normal deterministic timing of gates and
interconnects with probability distributions and gives a distribution of
possible circuit outcomes rather than a single outcome.

Effect of glitches in timing analysis:

A glitch is any unwanted clock pulse that may cause the sequential
cells to consider it as an actual clock pulse.
A single glitch in clock path can cause the chip to be metastable and even

Consider the above D Flipflop which has inputs D and clock CLK. Output is
If there is some glitch in the clock (denoted by highlighted circle), the
flipflop will treat it as a real clock edge and latch the data to the output.

However, if the pulse is too small, the data may not propagate properly to
output, and the flop may go metastable.

Clock Skew:

• It is the difference in arrival times of the capture edge at two adjacent

Flip-flop pairs.

Positive skew:

o If capture clock comes late than launch clock, then it is called

positive skew.
Negative skew:

o If capture clock comes early than launch clock it is called –ve


Question 4: Add 5-6 summary bullets on layout synthesis from paper

given to you.

Paper: Benchmarks for layout synthesis

• In the past, benchmarks were used mainly to evaluate the

performance of algorithms for problems on placement and routing for
a specific layout style, logic synthesis and test generation for
combinational and sequential circuits.
• The goal of the benchmark sessions later was to contribute further
towards developing an industry-standard set of benchmarks for
various aspects of automatic IC design.
• The benchmark data representation to contain enough information to
drive several different styles of design (like standard cell and gate
array design styles)

• Certain objectives in consideration for benchmarking are:
o Addressing layout designs for increased speed, minimized
clock skew
o Increased importance of performance parameters in IC design
o Transistor resizing, pin swapping, buffer insertion
o Clock signal distribution

• Testability is another main concern of IC designer – usage of scan

chain technique for the final layout quality

• Representing benchmark data:

o Should enable all types of layout systems (like usage of over-
the-cell routings, usage of feed-through cells for ease in

• 1990 MCNC layout benchmark set covered the following areas:

➢ Standard cell layouts
➢ Gate array layouts
➢ Macro block layouts
➢ Mixed macro blocks
➢ Flexibility benchmarks
➢ Floor planning
➢ Compaction

• Compatibility levels and objectives:

o Level 1 – to produce smallest area rectangle of any aspect
ratio, place the cells and route all nets
o Level 2a – Level 1 combined with power and ground nets
having proper widths to satisfy electromigration and voltage
drop constraints
o Level 2b – Level 1 combined with designating critical nets and
timing related constraints
o Level 3 – Objectives of level 2a and 2b fulfilled simultaneously

Benchmark results:

Standard cell benchmarks – 8 benchmarks which included results

for fract, primary1, struct, industry1, primary2, biomed, industry2 and
industry 3 with all having their own specifications

Gate array benchmarks – 4 of the standard cell benchmarks of

standard cells were applicable here – primary1, primary2, industry2
and industry3

Block placement benchmarks – 5 benchmarks (xerox, ami33, apte,

ami49 and hp)

Block/cell benchmarks – 3 benchmarks in this area – g2, a3 and t1

Floor planning benchmarks – 2 benchmarks (xerox and FAN)

10 | P a g e