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FPGA Selection

For conversion of analog signal from the detector we have selected LTC2387-18 Analog to Digital
converter (ADC) figure 1. This ADC is a 18 bit with 15 Mega samples per second IC using successive
approximation register for conversion

Figure 1. LTC2387-18 []

Before storing converted data to the system, there a step of digital data processing at very higher rate for
every Helicity window. For this purpose, ADC must be interfaced with efficient FPGA (Field
Programmable Gate Array) having enough internal memory for processing the digital data and
transmission of processed data on to ethernet port. Number of interfacing channels depends on the FPGA
selection. Interfacing on ADC with FPGA requires 8- 10 pins. Pin number, name and purpose of each
required pin of an ADC is shown in table 1.
Table 1: ADC Pin discerption for interfacing []

S.No Pin_Name Pin_No._ADC Mode Purpose
1 CLk+ 23 Input LVDS Clock Input. This is an externally applied clock
2 CLK- 24 Input that serially shifts out the conversion result, Coming
from FPGA or external source
3 Two_lanes 25 output Digital input that enables two-lane output mode. When
TWOLANES is high (two-lane output mode), the ADC
outputs two bits at a time on DA–/DA+ and DB–/DB+.
When TWOLANES is low (one-lane output mode), the
ADC outputs one bit at a time on DA–/DA+, and DB–
/DB+ are disabled. Logic levels are determined by
4 DB- 15 output Serial LVDS Data Outputs
5 DB+ 16 output
6 DA– 17 output Serial LVDS Data Outputs
7 DA+ 18 output
8 DCO– 19 output Echoed data clock. LVDS Clock Input. This is an
externally applied clock that serially shifts out the
9 DCO+ 20 output conversion result.
10 CNV+ 27 Input Conversion Start LVDS Input. A rising edge on CNV+
puts the internal sample-and-hold into the hold mode
and starts a conversion cycle. CNV+ can also be driven
with a 2.5V CMOS signal if CNV– is tied to GND.

We are going to use ADC in two lane mode.

The FPGA that we have selected for capturing and processing digital data purpose, belongs to Xilinx
Zynq series that is C7Z020-1CLG400C, based upon its customizable, optimizable and flexible
Architecture. This FPGA is a complete SoC (System on Chip) including dual core ARM Cortex-A9
processor (PS), integrated with 28nm programmable logic in a single device []. This PS includes on chip
memory 256KB RAM, externals memory interface tri speed Ethernet MAC peripheral with IEEE std
802.3. To enhance the efficiency PS consist of 512 KB 8-way level 2 cache.
Zynq XC7Z020-1CLG400C consists of total 400 pins out which 125 are available for General Purpose
Input Output []. Programmable logic (PL) sections of the FPGA also satisfies our on chip memory
requirement. On Chip memory also called BRAM (Block RAM). This FPGA has 140 block of BRAM
each of 36 Kb in size with 106,400 flip-flops.
Both PS and PL communicate with ARM AMB AXI bus that provides High-Bandwidth connectivity
with PS and between and PL. Other important features of this FPGA are shown below in the table 2.
Table 2. Feature of FPGA []
Zynq-XC7Z020-1CLG400C Programmable SoCs
Programmable Logic 85K
Look-Up Tables (LUTs) 53,200
DSP Slices 220
(18x25 MACCs)
Maximum Frequency 667 MHz (-1); 766 MHz (-2); 866
MHz (-3)
DMA Channels 8 (4 dedicated to Programmable
Processing System to 2x AXI 32b Master 2x AXI 32-bit
Programmable Logic Slave
Interface Ports 4x AXI 64-bit/32-bit Memory
(Primary Interfaces & AXI 64-bit ACP
Interrupts Only) 16 Interrupts

While dealing with data from ADC and transfer of the processed data there are two main issues that have
to take care.
1. On chip memory BRAM
2. Ethernet protocols
Dealing with our first concern, BRAM of this FPGA is dual port 36Kb with 140 blocks. Possible
Configuration of each port is shown in table 2. In case of Dual port BRAM can be divided into two
independent 18 Kb blocks and this configuration is also applicable in case of dual port arrangement.
Table 2: FPGA BRAM configuration
Block Configuration Block/word ADC word Memory buffer Remaining Block
32768 32768X1 18 7*32768 229376 14
16384 16384X2 9 15*16384 245760 5
8192 8192X4 5 27*8192 221184 5
4096 4096X8 3 45*4096 184320 5
4096 4096X9 2 67*4096 274432 6
2048 2048X16 2 67*2048 137216 6
2048 2048X18 1 140*2048 286720 0
1024 1024X32 1 140*1024 286720 0
1024 1024X36 1 140*1024 286720 0
512 512X64 1 140*512 286720 0
512 512X72 1 140*512 286720 0

Based on this configuration the best configuration that we can use is 4096X9 that uses 134
blocks and 6 blocks with higher efficiency.
To implement the transfer of the processed data over ethernet from FPGA we have to implement
User datagram protocol on the FPGA. As Xilinx Zynq series is complete SoC having on chip
option to configure the Ethernet MAC peripheral. For this purpose, we have worked on the Evaluation
board Zybo-Z7 figure3, by Digilent Technologies consist of our candidate FPGA. We have implemented
a firm ware using Low weight IP (LWIP) application open source TC/IP networking stack.

Figure 3: Zybo Z7 Evaluation Board

Xilinx provides LwIP customized application programming interface (API) with the Software
development kit (SDK). Using these API, we have written a simple firm ware, with the help of
which our FPGA is able to send the data on ethernet. That transferred is capture using wireshark
application for windows operating system. Figure 4, shows the Register Transfer Logic (RTL) for
this application.

Figure 4: RTL for LwIP-UDP implementation

During this experiment of developing the firm ware for transfer of data on ethernet, we configured
Ethernet ENET-0 port of Zynq Processing System (PS). After setting all configurations and
successfully synthesizing our deign, we programmed Zynq-PS section with Xilinx Device drivers
API to communicate with Programmable Logic (PL) section of Zynq. Figure 5, shows the section
of firmware for setting up successful connection of Xilinx FPGA with system and getting
successful ping from the device.

Figure 5: Ethernet firmware for User Datagram Protocol.

After the successful testing the Zynq FPGA on zybo board now we are planning develop our
board. This board is supposed to include 8 ADCs.