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energies
Article
PLL-Less Three-Phase Four-Wire SAPF with STF-dq0
Technique for Harmonics Mitigation under Distorted
Supply Voltage and Unbalanced Load Conditions
Yap Hoon 1,2, * ID
and Mohd Amran Mohd Radzi 1,2 ID
1 Department of Electrical and Electronic Engineering, Faculty of Engineering, Universiti Putra Malaysia,
Serdang 43400, Selangor, Malaysia; amranmr@upm.edu.my
2 Centre for Advanced Power and Energy Research (CAPER), Faculty of Engineering,
Universiti Putra Malaysia, Serdang 43400, Selangor, Malaysia
* Correspondence: davidhoon0304@hotmail.com; Tel.: +603-8946-6322

Received: 29 June 2018; Accepted: 20 July 2018; Published: 17 August 2018
Abstract: This paper presents a non-iterative technique that generates reference current to manage
operation of a three-phase four-wire shunt active power filter which employs a three-leg split
capacitor voltage source inverter (VSI) topology. The proposed technique integrates together a
self-tuning-filter (STF) and direct-quadrature-zero (dq0) principle (referred here as STF-dq0), allowing
the controlled shunt active power filter (SAPF) to perform effectively under distorted source voltages
and unbalanced load conditions. Unlike the previous technique developed based on the standard dq0
principle, the proposed technique does not require any service from a phase-locked loop (PLL) where
two STFs are applied to separate harmonic and fundamental elements for the purpose of generating
synchronization phases and reference current, respectively. Simulation work which includes
connection of the SAPF circuits, design of control techniques and all the necessary assessments
are conducted in MATLAB-Simulink platform. Performance achieved by the SAPF while utilizing the
proposed technique is thoroughly investigated and benchmarked with that demonstrated by the SAPF
while using the standard dq0 technique, to evaluate the inherent advantages. Exhaustive simulation
results are provided and thoroughly discussed to support design concept, effectiveness, and benefits
of the proposed technique.
Keywords: dq0 principle; harmonics filtering; voltage source inverter; neutral current; reference
current generation; synchronization phase; unbalanced load
1. Introduction
Ensuring good quality of power supply is often a challenging task due to ever-increasing usage of
power electronics products. These products, which are more commonly known as nonlinear loads,
draw non-sinusoidal currents and reactive power from the connected power system, and cause high
harmonic distortion (indicated by total harmonic distortion (THD) values) in the source current and
deteriorate overall power system efficiency (indicated by power factor). Moreover, in three-phase
four-wire system, connection of single-phase loads and unequal loads distribution across the three
phases causes excessive neutral currents. These power quality issues can partially be solved by
applying passive filter. The viable solution is by using active power filter (APF) connected in parallel to
the polluted power system. APFs that are applied in this manner are called the shunt-typed. The good
thing about shunt active power filters (SAPFs) is that they are able to deal with unbalanced issues in
the source current along with mitigating harmonic current and compensating reactive power.
For application in three-phase four-wire system, SAPFs are available in two basic topologies. First,
three-leg split capacitor topology where the middle-point of its dc-link is connected to the neutral
Energies 2018, 11, 2143; doi:10.3390/en11082143 www.mdpi.com/journal/energies

Energies 2018, 11, 2143 2 of 27
wire of the power system [1]. Second, four-leg topology which is a more complex topology due to
higher number of semiconductor switches employed and an additional control input [2]. In this work,
the split capacitor topology is preferred for its less complicated structure. Its connection path to the
neutral wire allows the excessive neutral currents to flow towards the two dc-link capacitors where
they will be absorbed and eventually be removed from the neutral wire [3]. Nevertheless, this is
only possible when the controller is designed with such ability. However, as a result of using the two
dc-link capacitors, the controller design is undoubtedly becoming more challenging as the controller
needs to cope with voltage imbalance problem now. Overall, other than the common mitigation
issues encountered in a typical three-phase three-wire system, the SAPF is demanded to cope with
additional issues of neutral current and dc-link voltage unbalance when it is applied in a three-phase
four-wire system.
Regardless of the type of applications an SAPF is designated for, its performance is all dependent
on the capability of its closed-loop control system. The most important part of the control system is the
part responsible for generating reference current. By having an accurate reference current, the SAPF
should be able to perform effectively. Note that the process of generating reference current always
comes together with the process of extracting harmonic current and synchronization phases from
the power line. Although many techniques have been developed for this particular purpose [4,5],
two techniques are reported to be extensively applied in three-phase four-wire system, namely
direct-quadrature-zero dq0 principle [1,6,7] and instantaneous power pq0 theory [2,7,8]. Nevertheless,
dq0 principle is preferred in this work for its reduced control complexity.
According to dq0 principle, ability to extract fundamental element from the load current and
synchronization phases from the source voltage is the key factor that determines quality of the
generated reference current. In dq0-frames, the load current comprises of fundamental (appear as dc
signal) and harmonic (appear as ripples) elements. A high ripple level tends to degrade capability of
the technique and quality of the generated reference current. However, high-pass filter (HPF) which
is commonly applied to isolate the fundamental and harmonic elements may not be effective even
though a good agreement between filter’s order and its cutoff frequency has been met. Moreover,
many issues exist in matching the filter’s order and cutoff frequency as it is performed in iterative
manner. In other words, there is a need to test various combinations of the filter’s order and cutting
frequency to find out the best combination. As a result, large amount of time will be spent just for the
tuning purposes, and thus not worthwhile to be implemented.
Another inherent weakness of the standard dq0 technique is that it requires the service of an
additional phase-locked loop (PLL) circuit to perform dq0-frames transformation and subsequently
synchronize reference current with that of the operating power system. The additional PLL circuit not
only complicates its control structure, but also fails to perform satisfactorily especially when the source
voltage is subjected to distortion [9,10]. An alternative to solve phase tracking error of a standard PLL
is by improving its tracking capability, and this has led to the development of self-tuning-filter (STF)
PLL [10] and decoupled double PLL [9]. However, the incorporation of STF and decoupling network
in PLL structure further increases complexity of an already complex PLL structure.
In this study, a technique to generate reference current (named as STF-dq0) for a three-phase
four-wire SAPF without needing any service from a PLL is proposed. The proposed technique is
developed and evaluated in MATLAB-Simulink platform (R2012a, The MathWorks, Inc., Natick, MA,
USA). To confirm theoretical development of the proposed technique, it is thoroughly tested and
evaluated under various scenarios of source voltages (including distorted and unbalanced conditions)
and unbalanced loads. Moreover, to show benefits of the proposed technique, the standard dq0
technique is implemented too, and both techniques are evaluated in a comparative manner under
similar test scenarios. The next section presents power circuit arrangement of SAPF and control
techniques applied in this work. In Section 3, working principle of the standard dq0 technique is
described. Next, with reference to the standard dq0 technique, the proposed STF-dq0 technique is
presented in Section 4, focusing on the implemented enhancements. All simulation findings are
Energies 2018, 11, 2143 3 of 27
Energies 2018, 11, x FOR PEER REVIEW 3 of 29
presented
techniqueand thoroughly
is presented indiscussed
Section 4,in Sectionon
focusing 5. Finally, a brief conclusion
the implemented is provided
enhancements. to highlight
All simulation
findings are presented
contributions and thoroughly discussed in Section 5. Finally, a brief conclusion is provided
of this work.
to highlight contributions of this work.
2. Three-Phase Three-Leg Four-Wire Shunt Active Power Filter: Arrangement of Power Circuits
and Control Strategies
2. Three-Phase Three-Leg Four-Wire Shunt Active Power Filter: Arrangement of Power Circuits
andFigure
Control
1 Strategies
shows power circuit arrangement and control structure of a three-phase three-leg
four-wire SAPF.
Figure A standard
1 shows powertwo-level inverter with
circuit arrangement twocontrol
and split dc-link capacitors
structure (serving as
of a three-phase the SAPF)
three-leg
is four-wire
connectedSAPF.to theAoperating power system
standard two-level inverterat with
pointtwoof common coupling
split dc-link (PCC)
capacitors between
(serving as thethe power
SAPF)
is connected
supply to the operating
and nonlinear loads. Notepower system
that there at
is point of common
an output coupling (PCC)
filter interfacing betweenbetween the power
the SAPF and the
supply and
connected nonlinear
power system.loads. Notepurpose
Its main that thereisistoan output filter
minimize interfacing
switching between
ripples the SAPF
generated by SAPFand sothethat
mitigating opposition current (referred here as injection current iinj ) can effectively be injectedsointo
connected power system. Its main purpose is to minimize switching ripples generated by SAPF
anythat mitigating
polluted poweropposition
system current
to cancel (referred here ascurrent.
out harmonic current 𝑖𝑖𝑛𝑗 ) can
injectionFurthermore, the effectively
middle-point be injected
of the two
into any
dc-link pollutedispower
capacitors system
connected to to
thecancel
returnout harmonic
neutral wirecurrent. Furthermore,
N to minimize neutral thecurrent.
middle-point of
In addition,
the two dc-link capacitors is connected to the return neutral wire 𝑁 to minimize
while performing mitigation function, a certain amount of current (referred here as dc-link charging neutral current. In
addition,
current idc ) while
is alsoperforming
drawn by the mitigation
SAPF tofunction,
regulateavoltage
certain amount
across itsofdc-link
currentcapacitors.
(referred here
In aasthree-phase
dc-link
charging current 𝑖𝑑𝑐 ) is also drawn by the SAPF to regulate voltage across its dc-link capacitors. In a
four-wire power system, the connected nonlinear loads can be of single-phase balanced/unbalanced
three-phase four-wire power system, the connected nonlinear loads can be of single-phase
and three-phase balanced loads. When the SAPF is installed and functioning properly, harmonic
balanced/unbalanced and three-phase balanced loads. When the SAPF is installed and functioning
current and excessive neutral current in the polluted power system will slowly be removed and
properly, harmonic current and excessive neutral current in the polluted power system will slowly
eventually the source current will be balanced and regain its sinusoidal appearance with fundamental
be removed and eventually the source current will be balanced and regain its sinusoidal appearance
frequency, and neutral current will be maintained at zero.
with fundamental frequency, and neutral current will be maintained at zero.
Ideal / Non-ideal Source Load Line

Source Voltage Current Current Inductance
vS (t) iS (t) iL (t) Ll
PCC
Balanced /
Unbalanced
Single-phase
Nonlinear Loads
Standard Injection
Inverter (APF) Current Balanced
Dc-link i inj (t)
Three-phase
Vdc1 +_ Cdc1 Lfa Dc-link
Nonlinear Loads
N
Charging
Vdc2 +_ Lfb i dc (t) Current
Cdc2
Lfc
Output Filter
(a)
Injection Current ( iinj )
Source Hysteresis
voltage ( vS ) Current Control
Synchronizer
Sin & Cos
Current Pulses for
Load current ( iL ) i inj, ref _ Error upper switches
Reference Current Generation
with dq0 Principle + i error
HBC Pulses for
Upper capacitor
Idc Ibalance lower switches
voltage (Vdc1 ) NOT
Split-Capacitor
Lower capacitor Dc-link Capacitor Voltage
voltage (Vdc2 ) Voltage Regulation Balancing
Control
(b)
Figure 1. Three-phase three-leg four-wire shunt active power filter (SAPF) with two split dc-link
Figure 1. Three-phase three-leg four-wire shunt active power filter (SAPF) with two split dc-link
capacitors: (a) power circuit arrangement, and (b) overall control structure.
capacitors: (a) power circuit arrangement, and (b) overall control structure.
Energies 2018, 11, 2143 4 of 27
To effectively manage operation of SAPF in a three-phase four-wire system, its control system
needs to perform few control procedures which include extraction of synchronization phases
(sin & cos) from source voltage vS , extraction of harmonic current from load current i L , estimation of
Idc (magnitude of the dc-link charging current idc ) and Ibalance (balancing current) from split dc-link
capacitor voltages (Vdc1 and Vdc2 ), derivation of reference current iinj, re f by using all the signals
obtained in the previous procedures, and generation of switching pulses based on the generated
reference current iinj, re f . It is important to note that operation of a typical SAPF is fully based on
characteristic of the generated reference current. In this work, other than mitigation of harmonic
current, the SAPF is also needed to regulate its dc-link voltage and ensure voltage balance across
its split dc-link capacitors. Hence, the generated reference current must contain details on system’s
harmonics, compatible phases to ensure synchronized operation, amount of dc-link charging current
to maintain constant dc-link voltage and balancing current to manage voltage balance of the two split
dc-link capacitors.
This manuscript emphasizes on the control procedure of generating reference current where it is
performed according to dq0 principle. Further details are presented in Sections 3 and 4. Meanwhile,
to regulate dc-link voltage and maintain voltage balance of the split dc-link capacitor, the conventional
proportional-integral (PI) technique is adopted due to its straightforward feature [1,11]. Lastly,
to generate switching pulses, a standard hysteresis band current control (HBC) technique is applied as
it offers the benefits of structure simplicity and quick current controllability [1,2,6].
3. Working Principle of the Standard dq0 Technique

Figure 2 shows control structure of a standard dq0 technique which is commonly applied for
the purpose of generating reference current. According to dq0 principle, extraction of harmonic
current from load current is performed on dq0-frames where the load current i Labc (in abc-domain) is
first transformed into αβ0-domain by using Clarke-matrix expressed as Equation (1) and then into
dq0-frames by using Park-matrix expressed as Equation (2).
− 12 − 12
 
1
2 √ √
abc

Tαβ0 = 3 3 (1)
 0
2 − 2

3 
1 1 1
2 2 2
" #
αβ sin(ωt) cos(ωt)
Tdq = (2)
− cos(ωt) sin(ωt)
Note that sin(ωt) and cos(ωt) denote synchronization reference phases which are particularly
delivered by a PLL.
Let the three-phase load current expressed in matrix form be i Labc = [i La i Lb i Lc ]T . Hence, by using
Equation (1), the corresponding representation in αβ0-domain can be expressed as:
h iT h iT
abc
i Lα i Lβ i L0 = Tαβ0 i La i Lb i Lc . (3)
Subsequently, load current i Lαβ in αβ-domain is further transformed into dq-frames according to
Equation (4). Note that 0-domain of αβ0-domain is not required in the transformation process, and it is
directly applied as 0-frame of dq0-frames. In other words, 0-domain is equivalent to 0-frame.
h iT h iT
αβ
i Ld i Lq = Tdq i Lα i Lβ (4)
Energies 2018, 11, 2143 5 of 27
vS abc Sin_Cos
PLL
iL α Direct (d) i Ld (ac) dq / αβ

iL abc abc Quadrature (q) HPF + Transform αβ0 i inj(abc), ref
Tαβ0 Calculation _ T abc
iLβ dq
αβ Tαβ (7)
(3) Tdq i Lq
(4) (6)
iL0
+
_
Vdc, ref
Vdc1 I dc
+ PI 1
+ _
+
_ Ibalance
PI 2
+
Vdc2
Figure
Figure2.2.Block
Blockdiagram
diagramshowing
showingcontrol
controlstructure
structure of
of standard
standard dq0
dq0 technique
technique [1].
[1].
𝛼𝛽
[𝑖𝐿𝑑
In dq-frames, as a consequence of harmonic 𝑻𝑑𝑞 [𝑖𝐿𝛼 𝑖𝐿𝛽 ]Tthe load current signal contains both
𝑖𝐿𝑞 ]T =contamination, (4)
fundamental (stationary dc) and harmonic (oscillating ac) elements. Hence, the following relationship
In formed:
can be dq-frames, as a consequence of harmonic contamination, the load current signal contains
" # " #
both fundamental (stationary dc) and i Ld harmonic i Ld((oscillating
dc) + i Ld( ac) ac) elements. Hence, the following
relationship can be formed: = (5)
i i Lq +i Lq(dc) Lq( ac)
𝑖𝐿𝑑 𝑖𝐿𝑑(𝑑𝑐) + 𝑖𝐿𝑑(𝑎𝑐)
where i Ld (dc) and i Ld (ac) , respectively,[ denote ] = [ the dc and ac elements ] of the load current in d-frame. (5)
𝑖𝐿𝑞 𝑖𝐿𝑞(𝑑𝑐) + 𝑖𝐿𝑞(𝑎𝑐)
The same representation applies to the elements of load current in q-frame. Note that the stationary dc
element𝑖𝐿𝑑of(𝑑𝑐)
where and 𝑖𝐿𝑑
d-frame (𝑎𝑐) , respectively,
represents the magnitude denoteofthe dc and ac elements
fundamental load currentof thewhereas
load current in d-frame.
the oscillating ac
element
The samerepresents
representation the magnitude
applies to of theharmonic
elementscurrent. On the in
of load current other hand,Note
q-frame. q-frame
thatcontains phase
the stationary
information
dc element ofofd-frame
the loadrepresents
current. Not the to forget, 0-frame
magnitude of dq0-frames
of fundamental loadwhich
current is directly
whereastaken from that
the oscillating
of αβ0-domain
ac is needed
element represents theto magnitude
maintain dc-link voltage balance.
of harmonic current.InOn other
thewords,
other thehand,ac element d-frame
q-frameofcontains
load current
phase i Ld(ac) ,ofq-frame
information the load load currentNot
current. i Lq to
and 0-frame
forget, load current
0-frame i L0 are three
of dq0-frames whichdistinct unwanted
is directly taken
parts that
from of load
of currents
αβ0-domain that represent
is neededharmonic, to maintain reactive
dc-link andvoltage
unbalanced balance.currents, respectively.
In other words, the ac
element of d-frame
Hence, in orderload currentthose
to remove 𝑖𝐿𝑑(𝑎𝑐) , q-frame signals,
unwanted load current 𝑖𝐿𝑞 and
to maintain 0-framedc-link
constant voltage𝑖𝐿0
load current andare to
maintain voltage balance across the two split dc-link capacitors,
three distinct unwanted parts of load currents that represent harmonic, reactive and unbalanced the reference current i inj( abc), re f is
derived by
currents, considering all those factors according to the following approach:
respectively.
Hence, in order to remove h those unwanted iT signals,
h to maintain constant iT dc-link voltage and to
dq
maintain voltage balance across i Lα, re fthei Lβ,re
twof split=dc-link
Tαβ capacitors,
i Ld(ac) − Idcthe reference
i Lq current 𝑖𝑖𝑛𝑗(𝑎𝑏𝑐),𝑟𝑒𝑓 (6) is
derived by considering all those factors according to the following approach:
h iT h iT
𝑑𝑞
iinja,re f iinjb,re [𝑖𝐿𝛼,𝑟𝑒𝑓
f i 𝑖𝐿𝛽,𝑟𝑒𝑓
injc,re f ] T= Tαβ0
= 𝑻 𝛼𝛽
abc [(𝑖i 𝐿𝑑(𝑎𝑐)
Lα,re f − i 𝐼 )
Lβ,re 𝑖 (
𝑑𝑐 f 𝐿𝑞 L0 i] T −I
balance ) (6)
(7)
dq αβ0
𝛼𝛽0
[𝑖𝑖𝑛𝑗𝑎,𝑟𝑒𝑓 𝑖𝑖𝑛𝑗𝑏,𝑟𝑒𝑓
where inverse Park-matrix Tαβ and 𝑖inverse
𝑖𝑛𝑗𝑐,𝑟𝑒𝑓 ] = 𝑻 [𝑖𝐿𝛼,𝑟𝑒𝑓Tabc𝑖𝐿𝛽,𝑟𝑒𝑓
TClarke-matrix are given
𝑎𝑏𝑐
(𝑖𝐿0as
− follows:
𝐼𝑏𝑎𝑙𝑎𝑛𝑐𝑒 )]T (7)
𝑑𝑞 𝛼𝛽0 #
where inverse Park-matrix 𝑻𝛼𝛽 and inversesin (ωt) − cos(𝑻ωt
Clarke-matrix ) are given as follows:
"
dq 𝑎𝑏𝑐
Tαβ = (8)
𝑑𝑞 𝑠𝑖𝑛(𝜔𝑡)
cos (ωt) −𝑐𝑜𝑠(𝜔𝑡)
sin(ωt)
𝑻𝛼𝛽 = [ ] (8)
𝑐𝑜𝑠(𝜔𝑡) 𝑠𝑖𝑛(𝜔𝑡)
Energies 2018, 11, 2143 6 of 27
 
1 0 1
√
αβ0 3
 1 
 −2
Tabc =  2
√
.
1  (9)
3
− 12 − 2 1
Meanwhile, Idc symbolizes the amount of dc-link charging current idc needed to maintain constant
dc-link voltage at desired level (denoted as Vdc, re f ) and compensate losses associated with switching
operation of SAPF, and Ibalance symbolizes the amount of balancing current needed to maintain the
voltage balance.
The oscillating ac element of d-frame load current i Ld(ac) applied in Equation (6) can be obtained by
filtering directly the d-frame load current with a high-pass filter (HPF) [1,6,12]. It is worth noting that
in some dq0 techniques, the oscillating ac element is also obtained indirectly by using low-pass filter
(LPF) associated with a simple calculation, in which the LPF is first applied to obtain the stationary
dc element i Ld(dc) and is then subtracted from the actual d-frame load current i Ld [13–15]. Next, Idc
is estimated by minimizing the error e1 (t) resulted between reference dc-link voltage Vdc, re f and the
total instantaneous dc-link voltage (Vdc (t) = Vdc1 (t) + Vdc2 (t)) with a PI controller. Mathematically,
the approach can be expressed as:
Z t
Idc = k p1 e1 (t) + k i1 e1 (t)dt (10)
0
e1 (t) = Vdc, re f − (Vdc1 (t) + Vdc2 (t)) (11)
where k p1 and k i1 are the two constant values that respectively symbolize proportional and integral
gains of PI1 (first PI) controller. In this work, the values are set to be 0.3 and 2, respectively. Similarly,
a PI controller is applied to estimate Ibalance by minimizing the error e2 (t) resulted between the two
split dc-link capacitors. Mathematically, the approach can be expressed as:
Z t
Ibalance = k p2 e2 (t) + k i2 e2 (t)dt (12)
0
e2 (t) = Vdc2 (t) − Vdc1 (t) (13)
where k p2 and k i2 are the two constant values that respectively symbolize proportional and integral
gains of PI2 (second PI) controller. The values are set to be 0.02 and 0.1, respectively.
4. Working Principle the Proposed STF-dq0 Technique

Figure 3 presents a block diagram that illustrates control structure and particulars of the proposed
STF-dq0 technique. Basically, the proposed STF-dq0 technique generates reference current in a
similar manner to that of a standard dq0 technique where both techniques perform according to the
consecutive transformation sequences of “abc-αβ0-dq0-αβ0-abc”. However, in the proposed technique,
two modifications are made to further enhance capability of SAPF in performing its intended functions.
First, the conventional PLL circuit is removed and replaced with a straightforward synchronization
technique. Second, instead of applying HPF to perform direct extraction of harmonic element on
dq0-frames, a self-tuning-filter (STF) is employed to extract the harmonic element indirectly on
αβ0-domain (an earlier transformation stage before entering the dq0-frames).
Energies 2018, 11, 2143 7 of 27
vSα vSα (dc)

vS abc abc
T αβ First Sin_Cos Sin_Cos
vSβ STF vSβ (dc) Generation
(14) (17) (18)
Direct (d)
+ iL α (ac) Quadrature (q) i Ld (ac)
iL α iL α (dc) Calculation +
_ _
iL abc abc Second
Tαβ0 STF
iLβ (dc) dq / αβ
(3)
(20) _ iL (ac) i inj(abc), ref
β αβ i Lq Transform αβ0
iLβ Tdq T abc
dq
+ Tαβ (7)
(22) & (23)
(6)
iL0
+
Vdc, ref _
I dc
Vdc1 +
+ _ PI 1
+
_ Ibalance
PI 2
+
Vdc2
Figure 3. Block diagram showing control structure of the proposed self-tuning-filter (STF)-dq0
Figure 3. Block diagram showing control structure of the proposed self-tuning-filter (STF)-dq0 technique.
technique.
In
In the
the proposed
proposed STF-dq0
STF-dq0 technique,
technique, the the process
process of of extracting
extracting synchronization
synchronization phases
phases from
from the
the
source voltage is rather straightforward
source voltage is rather straightforward and non-iterative. Let the three-phase source voltage
and non-iterative. Let the three-phase source voltage expressed
in matrix form = [vSabe
be vSabc form vSb𝑣vSc ]T , =and[𝑣 by using TClarke-transform matrix (considers only two
expressed in matrix 𝑆𝑎𝑏𝑐 𝑆𝑎 𝑣𝑆𝑏 𝑣𝑆𝑐 ] , and by using Clarke-transform matrix
phases
(considers only two phases αβ-domain), the(insource
αβ-domain), the source voltage signals abc-domain)
voltagecansignals
be transformed into αβ-domain
(in abc-domain) can be
according to:
transformed into αβ-domainhaccording to: iT h iT
abc
vSα 𝑣 vSβ 𝑣 = T v v
𝑣 Sa 𝑣𝑆𝑏 v (14)
[ 𝑆𝛼 T
𝑆𝛽 ] = αβ 𝑻𝑎𝑏𝑐
𝛼𝛽 [ 𝑆𝑎
Sb 𝑣 Sc
𝑆𝑐 ]
T
(14)
where
where
− 12 − 12
" #
abc 2 1
√ 1 Tαβ
√1 . = (15)
0 1 2−3 − −23 3
2 2 2
𝑻𝑎𝑏𝑐
𝛼𝛽 = [ ]. (15)
3 the√voltage√signals
In αβ-domain, under influence of distortions, 3 3 can respectively be decomposed
0 −
into fundamental and harmonic elements. Hence, the 2following
2 relationship can be formed:
In αβ-domain, under influence
" of
# distortions,
" the voltage
# signals can respectively be
v Sα vSα(dc) + vSα(ac)
decomposed into fundamental and harmonic
= elements. Hence, the following relationship can(16)
be
formed: vSβ vSβ(dc) + vSβ(ac)
𝑣𝑆𝛼
where vSα(dc) and vSα(ac) denote the fundamental 𝑣𝑆𝛼(𝑑𝑐) + 𝑣harmonic
𝑆𝛼(𝑎𝑐)
[𝑣 ] = [𝑣(dc) and + 𝑣to𝑆𝛽(𝑎𝑐) ] (ac) elements of source voltage(16)
in
𝑆𝛽
α-domain, respectively. The same representation 𝑆𝛽(𝑑𝑐) applies element of source voltages in β-domain.
To
where 𝑣𝑆𝛼(𝑑𝑐)
generate and 𝑣𝑆𝛼(𝑎𝑐) denote
synchronization phases,the
thefundamental
dc elements in both
(dc) and harmonicare(ac)
αβ-domain required. A self-tuning
elements of source
filtering approach [16] is applied to extract the dc elements. The applied STF is capable of
voltage in α-domain, respectively. The same representation applies to element of source voltages in suppressing
all the harmonic
β-domain. elements
To generate existed in the phases,
synchronization distortedthevoltage signalsin
dc elements and thus
both improving
αβ-domain quality
are of the
required. A
extracted synchronization phases. As revealed in [16–18], the transfer function (after performing
self-tuning filtering approach [16] is applied to extract the dc elements. The applied STF is capable
Laplace transformation)
of suppressing all the ofharmonic
a typical STF can beexisted
elements expressed in as follow:
the distorted voltage signals and thus
improving quality" of the extracted
# "synchronization phases. # As revealed
" in [16–18],
# the transfer
vSα(dc) (s) K 1 vSα (s) − vSα(dc) (s) 2π f c1 − vSβ(dc) (s)
function (after performing Laplace= transformation) of a typical + STF can be expressed as follow: (17)
vSβ(dc) (s) s vSβ (s) − vSβ(dc) (s) s vSα(dc) (s)
𝑣𝑆𝛼(𝑑𝑐) (𝑠) 𝐾1 𝑣𝑆𝛼 (𝑠) − 𝑣𝑆𝛼(𝑑𝑐) (𝑠) 2𝜋𝑓𝑐1 −𝑣𝑆𝛽(𝑑𝑐) (𝑠)
[ ]= [ ]+ [ ] (17)
𝑣𝑆𝛽(𝑑𝑐) (𝑠) 𝑠 𝑣𝑆𝛽 (𝑠) − 𝑣𝑆𝛽(𝑑𝑐) (𝑠) 𝑠 𝑣𝑆𝛼(𝑑𝑐) (𝑠)
Energies 2018, 11, 2143 8 of 27
where K1 is a constant gain parameter and f c1 is the cutoff frequency of STF1 (first STF). In this
work, the values are set to be 20 and 50 Hz, respectively. With availability of vSα(dc) and vSβ(dc) ,
the synchronization phases, sin(ωt) and cos(ωt) can be obtained according to following approach:
" # " #
sin(ωt) 1 vSα(dc)
= q . (18)
cos(ωt) vSα(dc) 2 + vSβ(dc) 2 vSβ(dc)
By using Equation (18), the service from conventional PLL can be neglected and the synchronization
phases can now effectively be generated regardless of any distortions in the source voltage.
On the other hand, for harmonic extraction, a STF is also employed to perform indirect extraction
of harmonic elements from the load current on αβ-domain. By using Equation (3), the three-phase load
current in abc-domain is first transformed into αβ-domain. Focusing only on αβ-domain (0-domain
does not involve in harmonic extraction), due to harmonic contamination, the load current signals
i Lαβ can respectively be decomposed into fundamental and harmonic elements. Hence, the following
relationship can be formed: " # " #
i Lα i Lα(dc) + i Lα(ac)
= (19)
i Lβ i Lβ(dc) + i Lβ(ac)
where i Lα(dc) and i Lα(ac) denote the fundamental (dc) and harmonic (ac) elements of load current in
α-domain, respectively. The same representation applies to elements of load current in β-domain.
The transfer function (after performing Laplace transformation) of STF applied to extract the dc
elements (i Lα(dc) and i Lβ(dc) ) of load current in αβ-domain is given as follows:
" # " # " #
i Lα(dc) (s) K i Lα (s) − i Lα(dc) (s) 2π f c2 −i Lβ(dc) (s)
= 2 + . (20)
i Lβ(dc) (s) s i Lβ (s) − i Lβ(dc) (s) s i Lα(dc) (s)
where K2 is a constant gain parameter and f c2 is the cutoff frequency of STF2 (second STF). In this
work, the values are set to be 20 and 50 Hz, respectively. With availability of dc elements (i Lα(dc) and
i Lβ(dc) ), the ac elements (i Lα(ac) and i Lβ(ac) ) can be obtained by using simple calculation expressed as:
" # " #
i Lα(ac) i Lα − i Lα(dc)
= . (21)
i Lβ(ac) i Lβ − i Lβ(dc)
From Equation (21), it can be seen that according to this STF approach, the ac elements are
obtained by subtracting the dc elements (extracted in advance using the STF) from the actual load
current signal in αβ-domain i Lαβ . Therefore, in this manner, the harmonic or ac elements are said to be
extracted indirectly.
Next, the ac elements obtained from Equation (21) and synchronization phases obtained from
Equation (18) are applied to perform transformation of αβ-domain into d-frame (contains only ac
elements) according to the following approach:
i Ld(ac) = i Lα(ac) sin(ωt) + i Lβ(ac) cos(ωt) (22)
and meanwhile, the original load current signal in αβ-domain i Lαβ and the similar synchronization
phases are applied to perform transformation of αβ-domain into q-frame according to the
following approach:
i Lq = −i Lα cos(ωt) + i Lβ sin(ωt). (23)
Note that 0-domain of αβ0-domain does not need to be transformed, and it is directly applied as
0-frame of dq0-frames. Finally, together with Idc (obtained from Equation (10)) and Ibalance (obtain from
Equation (12)), Equations (6) and (7) are applied to generate the reference current iinj(abc), re f .
Energies 2018, 11, 2143 9 of 27
5. Results and Discussion

Simulation work which includes connection of SAPF circuits, design of its control system,
and performance assessment of the proposed STF-dq0 technique is performed in MATLAB-Simulink
platform (R2012a). Figure 4 shows the simulation model developed for this work. It is constructed
using simple Simulink-blocks, and is executed in discrete environment. A standard two-level inverter
with split dc-link capacitors of 3300 µF (each) is employed as the SAPF. Its output is connected to a
simple 5 mH L-typed filter to minimize switching ripples. The line inductance is set to be 1 mH. For this
work, the reference dc-link voltage is set to be 880 V (440 V for each split capacitor). The procedures
applied for designing and determining parameter specifications of the SAPF are reported in [19–21].
Meanwhile, for the sources of harmonics, two types of nonlinear loads are considered. The first
nonlinear load comprises of three single-phase nonlinear loads distributed unequally (in unbalanced
manner) across the three phases of the connected power system (referred here as Load 1). The second
nonlinear load comprises of three unbalanced single-phase nonlinear loads connected in parallel with
a balanced three-phase nonlinear load (referred here as Load 2). Particulars of Loads 1 and 2 are
summarized in Table 1.
Table 1. Nonlinear load configuration for simulation work.
Nonlinear Load Load Descriptions

Uncontrolled single-phase rectifier feeding a parallel
Phase a
connected 80 Ω resistor and 1500 µF capacitor
Load 1: Unbalanced Uncontrolled single-phase rectifier feeding a series
Phase b
single-phase load connected 20 Ω resistor and 50 mH inductor
Uncontrolled single-phase rectifier feeding a parallel
Phase c
connected 60 Ω resistor and 1000 µF capacitor
Uncontrolled single-phase rectifier feeding a series
Phase a
connected 30 Ω resistor and 30 mH inductor
Load 2: Unbalanced single-phase Uncontrolled single-phase rectifier feeding a parallel
Phase b
load and balanced three-phase connected 80 Ω resistor and 1500 µF capacitor
load connected in parallel
Uncontrolled single-phase rectifier feeding a series
(refer Figure 4a) Phase c
Uncontrolled three-phase rectifier feeding a series
Analysis is performed in a comparative manner, i.e., by benchmarking performance demonstrated

by SAPF while applying the proposed STF-dq0 technique, with the one using the standard dq0 technique.
Steady-state simulation studies are conducted, considering four scenarios of source voltages, i.e., in
scenario A, a sinusoidal-balanced source voltage, in scenario B, non-sinusoidal-balanced source voltage,
in scenario C, sinusoidal-unbalanced source voltage, and in scenario D, non-sinusoidal-unbalanced
source voltage. For these four scenarios, particulars of the source voltages applied are given as follows:
Energies 2018,
Energies 11, 11,
2018, 2143x FOR PEER REVIEW 10 10
of of
29 27
powergui
Balanced Load
Voltage Supply Load Current Line Inductance Unbalanced Load

Measurement
Neutral Current
Measurement
Switching
Pulses
From
Control
System
Output Filter SAPF
(a)
Synchronizer
Dc-link Capacitor Reference Current Hysteresis Switching

Voltage Regulation Generation Current Pulses
(PI Technique) (𝑑𝑞0 Technique) Control To
SAPF
Split Capacitor Voltage

Balancing
(PI Technique)
(b)
Figure 4. Simulation model of three-phase three-leg four-wire SAPF developed in
Figure 4. Simulation model of three-phase three-leg four-wire SAPF developed in MATLAB-Simulink
MATLAB-Simulink platform: (a) power circuit arrangement, and (b) control system.
platform: (a) power circuit arrangement, and (b) control system.
Energies 2018, 11, 2143 11 of 27
Scenario A: Sinusoidal-balanced source voltage:
(THDa = THDb = THDc = 0.00%)
vSa = 326 sin(ωt) (24)

◦

vSb = 326 sin ωt + 240 (25)
◦

vSc = 326 sin ωt + 120 . (26)
Scenario B: Non-sinusoidal-balanced source voltage:
vSa = 326 sin(ωt) + 50 sin(3ωt) + 40 sin(5ωt) + 20 sin(7ωt) + 10 sin(9ωt) (27)

◦ ◦ ◦
vSb = 326 sin ωt + 240 + 50 sin 3 ωt + 240 + 40 sin 5 ωt + 240
◦ ◦
(28)
+20 sin 7 ωt + 240 + 10 sin 9 ωt + 240
◦ ◦ ◦
vSc = 326 sin ωt + 120 + 50 sin 3 ωt + 120 + 40 sin 5 ωt + 120
◦ ◦
(29)
+20 sin 7 ωt + 120 + 10 sin 9 ωt + 120 .
Scenario C: Sinusoidal-unbalanced source voltage:
vSa = 326 sin(ωt) (30)

◦

vSb = 246 sin ωt + 240 (31)
◦

vSc = 286 sin ωt + 120 . (32)
Scenario D: Non-sinusoidal-unbalanced source voltage
(THDa = 16.80%, THDb = 15.74%and THDc = 6.99%)
vSa = 326 sin(ωt) + 40 sin(3ωt) + 30 sin(5ωt) + 20 sin(7ωt) + 10 sin(9ωt) (33)

◦ ◦ ◦
vSb = 246 sin ωt + 240 + 30 sin 3 ωt + 240 + 20 sin 5 ωt + 240
◦ ◦
(34)
+10 sin 7 ωt + 240 + 10 sin 9 ωt + 240
◦ ◦ ◦
vSc = 286 sin ωt + 120 + 10 sin 3 ωt + 120 + 10 sin 5 ωt + 120
◦ ◦
(35)
+10 sin 7 ωt + 120 + 10 sin 9 ωt + 120 .
5.1. Sinusoidal-Balanced Source Voltage (Scenario A)

In Scenario A, an ideal situation of sinusoidal-balanced source voltage is considered. All the
simulation waveforms obtained under this scenario are shown in Figures 5–9. Meanwhile, Table 2
summarizes the findings in comparative manner. Referring to Figure 5, it can clearly be observed that
both the proposed STF-dq0 and standard dq0 techniques are able to accurately detect synchronization
phase value ωt (appear in the form of sawtooth wave-shape) from a sinusoidal-balanced source
voltage. Next, from Figure 6, both techniques are revealed to have effectively directed their respective
SAPF in mitigating harmonic currents generated by Loads 1, where the source currents are found
to have regained sinusoidal shape with THD values (as tabulated in Table 2) well-maintained below
the 5% harmonic limit set by IEEE standard 519 [22]. Note that no significant differences can be
Energies 2018, 11, 2143 12 of 27
observed between the THD values resulted by the proposed STF-dq0 and standard dq0 techniques.
In addition, it also can be seen that high neutral currents caused by connection of single-phase loads has
effectively been reduced by both SAPFs, proving the ability of both techniques in removing excessive
neutral currents.
Furthermore, as indicated in Table 2, large phase differences that resulted between the source
current and voltage have been minimized by both SAPFs. In other words, it proves that both techniques
are able to effectively synchronize operation of SAPF with the operating power system. This is basically
due to the accurate synchronization phase value ωt detected by both techniques (as indicated in
Figure 5). As a result, the source current seems to work in phase with the source voltage and thus it
leads to2018,
Energies almost
11, x unity power
FOR PEER factor of 0.999. Similar findings can be observed for Load 2, as indicated
REVIEW 12 of 29
in Figure 8 and Table 2. Therefore, as an overall, both techniques show almost similar performances
currents
when causedunder
operating by connection of single-phase
sinusoidal-balanced source loads has scenario.
voltage effectively been reduced by both SAPFs,
proving the ability of both techniques in removing excessive neutral currents.
Furthermore,
Table as indicated
2. Comparative in of
analysis Table 2, large phase
the proposed differences
STF-dq0 that resulted
and the standard between under
dq0 techniques the source
current and A.
Scenario voltage have been minimized by both SAPFs. In other words, it proves that both
techniques are able to effectively synchronize operation of SAPF with the operating power system.
This is basically due to the accurate synchronization Load 1 phase value 𝜔𝑡 detected Loadby2 both techniques
Performance Parameter
(as indicated in Figure 5). As aPhase result,a the Phase
sourceb current
Phaseseems
c to work
Phase a inPhasephaseb withPhase the source
c
voltage and thus it leads to almost unity power factor of 0.999. Similar
Before connecting SAPF findings can be observed for
Load 2, THDas indicated
value (%)
in Figure 8 and
118.27
Table 2. Therefore,
25.99
as
114.73
an overall,
13.46
both techniques
45.53
show
14.73
almost
similarPhase
performances
difference (when
◦) operating
9.80 under 15.60sinusoidal-balanced
7.50 source
8.50 voltage scenario. 10.90
6.80
Other thanfactor
Power effective harmonic mitigation,
0.636 ability to0.651
0.932 regulate dc-link
0.980 voltage is also an0.971
0.903 important
feature of SAPF, thus must thoroughly beconnecting
After assessed. Figures
SAPF with 7 and 9 provideSTF-dq0
the proposed the related results. From
technique
the findings, while
THD value (%) applying the proposed
2.97 STF-dq0
2.81 technique,
2.81 the SAPF
0.98 is found 0.96 to have effectively
1.03
regulated and maintained
Phase difference ( ) ◦ its dc-link
0.70 voltage at
0.30 the desired
0.40 level of 880
0.00 V, for both
0.20 Loads 1 and 2.
0.20
Similarly,Power
it is also clear from the0.999
factor findings that0.999voltages0.999
across the0.999
two split dc-link
0.999 capacitors 0.999 (𝑉𝑑𝑐1
and 𝑉𝑑𝑐2 ) are evenly regulated at half theconnecting
After value of SAPF
overallwith dc-link voltage
the standard dq0 𝑉technique
𝑑𝑐 , i.e., 440 V. This
implies THDthat value
the two(%) PI techniques
2.93 applied respectively
2.78 2.92 for regulating
1.02 the dc-link
0.97 voltage
1.01 and
ensuringPhasevoltage balance
difference ◦
( ) of the 0.80
two split dc-link
0.10 capacitors
0.60 have0.00
performed 0.10effectively and are
0.20
compatible Power
withfactor 0.999 technique.
the proposed STF-dq0 0.999 0.999 0.999 0.999 0.999
Synchronization phase value 𝜔𝑡 detected by the proposed STF-dq0 (red)
Synchronization phase value 𝜔𝑡 detected by the standard 𝑑𝑞0 (red)
Time (s)
Figure 5.
Figure 5. Simulation
Simulation result
result showing
showing the
the detected
detected synchronization
synchronization reference
reference phase
phase value 𝜔𝑡 under
value ωt under
Scenario A.
Scenario A.
Scenario A.
Performance Load 1 Load 2

Parameter Phase 𝒂 Phase 𝒃 Phase 𝒄 Phase 𝒂 Phase 𝒃 Phase 𝒄
Before connecting SAPF
Energies
THD 11, 2143
2018,value (%) 118.27 25.99 114.73 13.46 45.53 13 of 27
14.73
Phase difference (°) 9.80 15.60 7.50 8.50 6.80 10.90
Powerthan
Other factor 0.636 mitigation,
effective harmonic 0.932 ability0.651 0.980 voltage
to regulate dc-link 0.903 0.971
is also an important
After connecting SAPF with the proposed STF-dq0 technique
feature of SAPF, thus must thoroughly be assessed. Figures 7 and 9 provide the related results. From the
THD while
findings, value (%)applying the 2.97 2.81
proposed STF-dq0 2.81
technique, 0.98 is found
the SAPF 0.96 1.03
to have effectively
regulated and maintained its dc-link voltage at the desired level of 880 V, for both Loads 0.20
Phase difference (°) 0.70 0.30 0.40 0.00 0.20 1 and 2.
Power
Similarly, it isfactor
also clear from0.999
the findings0.999
that voltages0.999 0.999
across the two split dc-link 0.999 0.999 and
capacitors (V dc1
Vdc2 ) are evenly regulated at half the After connecting
value of overallSAPF with
dc-link the standard
voltage Vdc , i.e.,dq0
440technique
V. This implies that
THD
the two PIvalue (%) applied
techniques 2.93respectively
2.78for regulating
2.92 the dc-link
1.02voltage and 0.97ensuring1.01
voltage
Phase difference (°) 0.80 0.10 0.60 0.00 0.10
balance of the two split dc-link capacitors have performed effectively and are compatible with the 0.20
Power
proposed factortechnique.0.999
STF-dq0 0.999 0.999 0.999 0.999 0.999
Source Voltage (V) Source Voltage (V)
Load Current (A) Load Current (A)
Injection Current (A) Injection Current (A)
Source Current (A) Source Current (A)
Neutral Current before Mitigation (A) Neutral Current before Mitigation (A)
Neutral Current after Mitigation (A) Neutral Current after Mitigation (A)
Time (s) Time (s)

(a) (b)
Figure 6.6.Simulation
Figure Simulationresults
resultsobtained
obtained under
under Scenario
Scenario A forA Load
for Load 1, which
1, which includeinclude three-phase
three-phase source
source voltage 𝑣𝑆𝑎𝑏𝑐 , load current 𝑖𝐿𝑎𝑏𝑐 , injection current 𝑖𝑖𝑛𝑗𝑎𝑏𝑐 , source current 𝑖𝑆𝑎𝑏𝑐 , and neutral
voltage vSabc , load current i Labc , injection current iinjabc , source current iSabc , and neutral current before
current
and afterbefore and after
mitigation, mitigation,by
demonstrated demonstrated by SAPFthe
SAPF while applying while applying the
(a) proposed (a) proposed
STF-dq0 STF-dq0
and (b) standard
and (b) standard
dq0 techniques. dq0 techniques.
Energies 2018, 11, 2143 14 of 27

Total Dc-link Voltage (V)
Split Dc-link Capacitor Voltage (V)
Time (s)
Figure 7. Simulation result obtained under Scenario Time (s)
A for Load 1, showing the total dc-link voltage
Figure 7.
𝑉𝑑𝑐FigureSimulation result obtained under Scenario A forand
Load 1, ,showing the totalbydc-link voltage
, and 7.voltages across
Simulation resultsplit dc-link
obtained under Scenario 𝑉
capacitors for Load𝑉𝑑𝑐2
A𝑑𝑐1 demonstrated
1, showing SAPF
the total dc-link while
voltage
Vdcapplying
, and voltages
𝑉𝑑𝑐 , and across
thevoltages
proposed split dc-link
STF-dq0
across capacitors
splittechnique. Vdc1 and V dc2 , demonstrated by SAPF while
dc-link capacitors 𝑉𝑑𝑐1 and 𝑉𝑑𝑐2 , demonstrated by SAPF while applying
the proposed
applying STF-dq0 technique.
the proposed STF-dq0 technique.



Source
SourceCurrent
Current(A)
(A) SourceCurrent
Source Current (A)
(A)
Neutral
Neutral Currentbefore
Current beforeMitigation
Mitigation (A)
(A) Neutral
NeutralCurrent
Currentbefore
beforeMitigation
Mitigation(A)(A)
Time (s) Time (s)

Time(a)(s) Time
(b) (s)
(a) (b)
Figure 8. Simulation results obtained under Scenario A for Load 2, which include three-phase
Figure
source8. voltage results
Simulation
𝑣𝑆𝑎𝑏𝑐 obtained
,results
load under
obtained
current Scenario
𝑖𝐿𝑎𝑏𝑐under A for
Scenario
, injection A 𝑖Load
current 2, which
for Load include
2, which three-phase
include source
three-phase
𝑖𝑛𝑗𝑎𝑏𝑐 , source current 𝑖𝑆𝑎𝑏𝑐 , and neutral
source
voltage vSabc , load 𝑣current
voltage 𝑆𝑎𝑏𝑐 , load current
i Labc 𝑖𝐿𝑎𝑏𝑐current
, injection , injection current
iinjabc 𝑖𝑖𝑛𝑗𝑎𝑏𝑐
, source , source
current iSabc ,current 𝑖𝑆𝑎𝑏𝑐 , current
and neutral and neutral
before
and after mitigation, demonstrated by SAPF while applying the (a) proposed STF-dq0 and (b) standard
dq0 techniques.
Energies2018,
Energies 2018,11,
11,x xFOR
FORPEER
PEERREVIEW
REVIEW 1515ofof2929
currentbefore
current beforeand
andafter
aftermitigation,
mitigation,demonstrated
demonstratedby
bySAPF
SAPFwhile
whileapplying
applyingthe
the(a)
(a)proposed
proposedSTF-dq0
STF-dq0
Energies 2018, 11, 2143 15 of 27
and (b) standard dq0 techniques.
TotalDc-link
Total Dc-linkVoltage
Voltage(V)
(V)
SplitDc-link
Split Dc-linkCapacitor
CapacitorVoltage
Voltage(V)
(V)
Time(s)
Time (s)
Figure9.9.Simulation
Figure Simulationresult
resultobtained
obtainedunder
underScenario
ScenarioAAfor forLoad
Load2,2,showing
showingthe
thetotal
totaldc-link
dc-linkvoltage
voltage
Figure 9. Simulation result obtained under Scenario A for Load 2, showing the total dc-link voltage
𝑉
𝑉dc , and voltages
𝑑𝑐 andvoltages across split dc-link capacitors 𝑉
𝑉𝑑𝑐1
𝑑𝑐1 and 𝑉
𝑉𝑑𝑐2
𝑑𝑐2 , demonstrated by SAPF while
V 𝑑𝑐, ,and voltages across
across splitsplit dc-link
dc-link capacitors
capacitors Vdc1 and and
Vdc2 , demonstrated
, demonstrated by SAPFby SAPF
while while
applying
applying
applying the proposed
the STF-dq0 STF-dq0
proposedtechnique. technique.
STF-dq0 technique.
the proposed
5.2.Non-Sinusoidal-Balanced
5.2. Non-Sinusoidal-BalancedSource SourceVoltage
Voltage(Scenario
(ScenarioB)B)
5.2. Non-Sinusoidal-Balanced Source Voltage (Scenario B)
InInScenario
In
ScenarioB,B,aanon-sinusoidal-balanced
Scenario non-sinusoidal-balanced(harmonic
B, a non-sinusoidal-balanced (harmonic
(harmonicdistorted)
distorted)source
sourcevoltage
distorted) source
voltageisisconsidered.
considered.All
voltage is considered.
All
All the
the simulation
the simulation waveforms
waveforms obtained
obtained under this scenario are shown in Figures 10–14. Meanwhile,
simulation waveforms obtained underunder this scenario
this scenario are shown
are shown in Figures
in Figures 10–14. Meanwhile,
10–14. Meanwhile, Table 3
Table33summarizes
Table summarizesthe thefindings
findingsinincomparative
comparativemanner.manner.Referring
ReferringtotoFigure
Figure10,
10,ititcan
canclearly
clearlybebe
summarizes the findings in comparative manner. Referring to Figure 10, it can clearly be observed
observedthat
observed thatthe
theproposed
proposedSTF-dq0
STF-dq0technique
techniqueeffectively
effectivelydetects
detectssynchronization
synchronizationphase phasevalue
value 𝜔𝑡𝜔𝑡
that the proposed STF-dq0 technique effectively detects synchronization phase value ωt (appear in the
(appear
(appear in the form
in the form of sawtooth
of sawtoothfrom wave-shape)
wave-shape) from a non-sinusoidal-balanced
from a non-sinusoidal-balanced source
source voltage,
voltage, where
where
form of sawtooth wave-shape) a non-sinusoidal-balanced source voltage, where the detected
thedetected
the detectedphasephasevalue
valueisisfound
foundtotoaccurately
accuratelymatchmatchthethedesired
desiredphase
phasevalue.
value.InIncontrast,
contrast,for
forthe
the
phase value is found to accurately match the desired phase value. In contrast, for the standard dq0
standard 𝑑𝑞0
standard 𝑑𝑞0 technique,
technique, discrepancies
discrepancies existed betweenbetween the detected
detected and desired
desired phase value,value,
technique, discrepancies existed betweenexisted
the detected and the desired phaseand value, wherephase the resulted
where the
where thewaveform resulted
resulted of sawtooth
sawtooth waveform
waveform of the detected phase value is observed to be oscillating
sawtooth the detected phase of the isdetected
value observed phase
to bevalue is observed
oscillating along the to desired
be oscillating
phase
along the
along the desired
desired phase
phase value.
value. This
This implies
implies thatthat the
the standard 𝑑𝑞0 technique
standard 𝑑𝑞0 technique cannot
cannot workwork asas
value. This implies that the standard dq0 technique cannot work as desired when the source voltage
desiredwhen
desired whenthethesource
sourcevoltage
voltagesuffers
suffersfrom
fromdistortion.
distortion.
suffers from distortion.
Synchronizationphase
Synchronization phasevalue 𝜔𝑡detected
value𝜔𝑡 detectedby
bythe
theproposed
proposedSTF-dq0
STF-dq0(red)
(red)
Synchronizationphase
Synchronization phasevalue 𝜔𝑡detected
value𝜔𝑡 detectedby
bythe
thestandard 𝑑𝑞0(red)
standard𝑑𝑞0 (red)
Time(s)
Time (s)
Figure 10. Simulation result showing the detected synchronization reference phase value ωt under
Scenario B.
Energies 2018, 11, 2143 16 of 27

Table 3. Comparative analysis of the proposed STF-dq0 and the standard dq0 techniques under
B. 10. Simulation result showing the detected synchronization reference phase value 𝜔𝑡 under
Figure
Scenario
Scenario B.
Load 1 Load 2
Table 3.Parameter
Performance Comparative analysis of the proposed STF-dq0 and the standard dq0 techniques under
Scenario B. Phase a Phase b Phase c Phase a Phase b Phase c
THD value (%)
Parameter 𝒂
Phase 123.98 Phase 𝒃35.29 Phase 120.11
𝒄 𝒂
Phase 15.63 𝒃
Phase 46.21 𝒄
Phase 20.71
Phase difference (◦ ) 10.10 10.40 Before connecting
8.20 SAPF11.10 12.10 11.80
Power factor
THD value (%) 123.980.618 35.29 0.927 120.110.633 15.630.969 46.210.887 20.710.958
Phase difference (°) 10.10 10.40 8.20 11.10 12.10
After connecting SAPF with the proposed STF-dq0 technique 11.80
Power factor 0.618 0.927 0.633 0.969 0.887 0.958
THD value (%) 2.91 2.90SAPF with
After connecting 2.73
the proposed0.92 0.95
STF-dq0 technique 0.98
Phase difference ◦
THD value (%)( ) 2.91 0.80 2.90 0.20 2.73 0.30 0.92 0.10 0.95 0.20 0.98 0.20
Power
Phase factor (°)
difference 0.80 0.999 0.20 0.999 0.30 0.999 0.10 0.999 0.200.999 0.20 0.999
Power factor 0.999 0.999connecting
After 0.999
SAPF with0.999
the standard 0.999 0.999
dq0 technique
After connecting SAPF with the standard dq0 technique
THD value (%) 8.56 8.08 7.41 6.75 6.92 7.33
THD value (%) 8.56 8.08 7.41 6.75 6.92 7.33
Phase difference (◦ ) 0.80 0.10 0.50 0.10 0.20 0.10
Power factor 0.996 0.997 0.997 0.997 0.997 0.997
Power factor 0.996 0.997 0.997 0.997 0.997 0.997
Time (s) Time (s)

(a) (b)
Figure 11. Simulation results obtained under Scenario B for Load 1, which include three-phase
Figure 11. Simulation results obtained under Scenario B for Load 1, which include three-phase source
dq0 techniques.
current before and after mitigation, demonstrated by SAPF while applying the (a) proposed STF-dq0 17 of 27
Energies 2018, 11, 2143
Time (s)
Figure
Figure 12.12. Simulation
Simulation resultobtained
result obtainedunder
underScenario
Scenario BB for
for Load
Load 1,
1, showing
showingthe
thetotal
totaldc-link
dc-linkvoltage
voltage
𝑉 𝑑𝑐 , and voltages across split dc-link capacitors 𝑉 𝑑𝑐1 and 𝑉𝑑𝑐2 , demonstrated
Vdc , and voltages across split dc-link capacitors Vdc1 and Vdc2 , demonstrated by SAPF whileby SAPFapplying
while
applying the proposed STF-dq0 technique.
the proposed
Energies 2018, 11,STF-dq0 technique.
x FOR PEER REVIEW 18 of 29
Time (s) Time (s)

(a) (b)
source results
voltage 𝑣𝑆𝑎𝑏𝑐 , loadobtained under
current 𝑖𝐿𝑎𝑏𝑐 Scenario
, injection B for𝑖Load
current 2, which include three-phase source
voltage vSabcbefore
current and afteri Labc
, load current , injection
mitigation, current iinjabc
demonstrated , source
by SAPF current
while iSabcthe
applying , and
(a)neutral
proposedcurrent before
STF-dq0
and after mitigation,
and (b) standard demonstrated
dq0 techniques. by SAPF while applying the (a) proposed STF-dq0 and (b) standard
dq0 techniques.
Time (s) Time (s)
(a) (b)
current before and after mitigation, demonstrated by SAPF while applying the (a) proposed STF-dq0
Energies 2018, 11, 2143 18 of 27
Time (s)
Figure 14. Simulation result obtained under Scenario B for Load 2, showing the total dc-link voltage
Vdc , and voltages across split dc-link capacitors Vdc1 and Vdc2 , demonstrated by SAPF while applying
Next, referring to Figure 11, it can be seen that while using the proposed STF-dq0 technique, SAPF
is observed to have successfully mitigated harmonic currents generated by Load 1, where the source
currents have regained sinusoidal shape with THD values (as tabulated in Table 3) complying with
the 5% harmonic limit. In contrast, SAPF that applies the standard dq0 technique is only capable of
reducing distortion level suffered by the source currents but it fails to provide mitigation performance
that complies with IEEE standard 519. In this case, the mitigated source currents fail to recover
the desired sinusoidal shape and the recorded THD values are far beyond 5%. Nevertheless, both
techniques are able to remove excessive neutral currents caused by connection of single-phase loads.
Furthermore, as indicated in Table 3, both techniques are able to direct their respective SAPF
in minimizing the large phase differences that resulted between the source current and voltage.
With minimum phase differences, an almost unity power factor of 0.999 can be achieved when the
proposed STF-dq0 technique is applied. In contrast, due to high-level of distortion retained in the
mitigated source current, the standard dq0 technique can only provide a power factor up to 0.997 even
though the phase differences have been minimized. Similar findings can be observed for Load 2, where
the proposed STF-dq0 technique is revealed to outperform the standard dq0 technique when operating
under non-sinusoidal-balanced source voltage scenario (as indicated in Figure 13 and Table 3).
Moreover, the assessment on behavior of dc-link voltage is also conducted to confirm
correct operation of SAPF under Scenario B, while applying the proposed STF-dq0 technique.
Figures 12 and 14 provide the related results recorded for Loads 1 and 2, respectively. As expected
from the findings, all dc-link voltages of the SAPF are effectively regulated and maintained at the
desired level, i.e., at 880 V for the overall dc-link voltage Vdc and at 440 V (half of overall dc-link
voltage) for the voltages across two split dc-link capacitors (Vdc1 and Vdc2 ). Hence, once again, it is
certain that the proposed STF-dq0 technique can work effectively together with the two PI techniques
applied respectively for regulating the dc-link voltage and ensuring voltage balance of the two split
dc-link capacitors, and eventually directed the SAPF to work as desired under non-sinusoidal-balanced
source voltage scenario.
5.3. Sinusoidal-Unbalanced Source Voltage (Scenario C)

In Scenario C, a sinusoidal-unbalanced (magnitude unbalanced) source voltage is considered.
All the simulation waveforms obtained under this scenario are shown in Figures 15–19. Meanwhile,
Energies 2018, 11, 2143 19 of 27
Table 4 summarizes the findings in comparative manner. Based on Figure 15, the synchronization phase
value ωt (appear in the form of sawtooth wave-shape) detected by the proposed STF-dq0 technique is
found to work in accordance with the desired phase value. In contrast, for the standard dq0 technique,
minor discrepancies can be observed between the detected and desired phase value. Hence, it implies
that the standard dq0 technique cannot work exactly as desired when the magnitude of a three-phase
source voltage is unbalanced across the three phases.
Subsequently, from Figure 16, it is obvious that by using the proposed STF-dq0 technique, SAPF
have successfully mitigated harmonic currents generated by Load 1, where the source currents have
regained sinusoidal shape with THD values (as tabulated in Table 4) complying with the 5% harmonic
limit. In contrast, SAPF that applies the standard dq0 technique fails to perform in accordance to IEEE
standard 519, where the recorded THD values are beyond 5% and the mitigated source currents fail
to regain a complete sinusoidal shape. Nevertheless, both techniques are able to remove excessive
neutral currents caused by connection of single-phase loads. Furthermore, as indicated in Table 4,
both techniques
Energies arePEER
2018, 11, x FOR found to be able to direct their respective SAPF in minimizing the large 20
REVIEW phase
of 29
differences that resulted between the source current and voltage. With minimum phase differences,
proposed
an STF-dq0
almost unity powertechnique
factor ofis0.999
applied.
can beHowever,
achieved due whentothe
higher distortion
proposed STF-dq0 level of the is
technique mitigated
applied.
source current, the standard dq0 technique can only provide a power factor
However, due to higher distortion level of the mitigated source current, the standard dq0 techniqueup to 0.998 even though
the phase
can differences
only provide havefactor
a power been minimized.
up to 0.998 even though the phase differences have been minimized.
On
On the other hand, for the case ofofLoad
the other hand, for the case Load 2 as
2 as illustrated
illustrated in Figure
in Figure 18, 18,
bothboth
the the proposed
proposed STF-dq0
STF-dq0 and
andstandard
the the standard dq0 techniques
dq0 techniques are foundare to
found
performto perform effectively
effectively as the THDas values
the THD havevalues have been
been maintained
maintained
below the 5%below
harmonicthe 5% harmonic
limit, excessivelimit, excessive
neutral currentneutral
have beencurrent havethe
removed, been
largeremoved, the large
phase differences
phase differences have been minimized, and almost unity power factor
have been minimized, and almost unity power factor of 0.999 is achieved. Nevertheless, the proposed of 0.999 is achieved.
Nevertheless,
STF-dq0 the proposed
technique is revealed STF-dq0 technique
to outperform theisstandard
revealeddq0to outperform
technique by the standardTHD
providing dq0 technique
values of
1.88–2.13% lower (as indicated in Table 4). Hence, as an overall, judging from the performanceoverall,
by providing THD values of 1.88 –2.13% lower (as indicated in Table 4). Hence, as an of each
judging from
technique the performance
in dealing with Loads of each
1 and technique
2, the proposed in STF-dq0
dealing technique
with Loads can1 be
and 2, thetoproposed
claimed be more
STF-dq0than
reliable technique can bedq0
the standard claimed to bewhen
technique morethey reliable than thetostandard
are required work under dq0sinusoidal-unbalanced
technique when they
are required to work
source voltage scenario. under sinusoidal-unbalanced source voltage scenario.
Time (s)

Figure 15. Simulation result
result showing
showing the
the detected
synchronizationreference
referencephase value 𝜔𝑡
phasevalue under
ωt under
Scenario C.
Scenario C.

Parameter Phase 𝒂 Phase 𝒃 Phase 𝒄 Phase 𝒂 Phase 𝒃
Phase 𝒄
THD value (%) 118.27 25.99 114.73 12.84 45.09 13.77
Power factor 0.636 0.932 0.651 0.977 0.904 0.977
Energies 2018, 11, 2143 20 of 27
Scenario C.
Load 1 Load 2
Phase a Phase b Phase c Phase a Phase b Phase c
THD value (%) 118.27 25.99 114.73 12.84 45.09 13.77
Power factor 0.636 0.932 0.651 0.977 0.904 0.977
THD value (%) 2.86 2.79 2.89 1.11 1.09 1.17
Power factor 0.999 0.999 0.999 0.999 0.999 0.999
THD value (%) 5.20 5.09 5.72 3.24 2.97 3.13
Energies 2018, 11, x FOR◦PEER REVIEW 21 of 29
Phase difference ( ) 0.30 0.10 0.30 0.90 0.10 0.90
Power factor 0.998 0.998 0.998 0.999 0.999 0.999
Time (s) Time (s)

(a) (b)
Figure 16. Simulation results obtained under Scenario C for Load 1, which include three-phase
source results
voltage 𝑣𝑆𝑎𝑏𝑐 , loadobtained under
current 𝑖𝐿𝑎𝑏𝑐 Scenario
, injection C for𝑖Load
current 1, which include three-phase source
voltage vSabc before
current and afteri Labc
, load current , injection
mitigation, current iinjabc
demonstrated , source
by SAPF current
while iSabcthe
applying , and
(a)neutral
proposedcurrent before
STF-dq0
and mitigation,
and after (b) standard demonstrated
dq0 techniques. by SAPF while applying the (a) proposed STF-dq0 and (b) standard
dq0 techniques.
Time (s) Time (s)
(a) (b)
current
Energies 2018, before and after mitigation, demonstrated by SAPF while applying the (a) proposed STF-dq0 21 of 27
11, 2143
Time (s)
Figure 17. Simulation result obtained under Scenario C for Load 1, showing the total dc-link voltage
Figure 17. Simulation result obtained under Scenario C for Load 1, showing the total dc-link voltage
Vdc , and
𝑉𝑑𝑐 ,voltages acrossacross
and voltages split dc-link capacitors
split dc-link Vdc1 and
capacitors 𝑉𝑑𝑐1 Vand
dc2 , demonstrated by SAPF
𝑉𝑑𝑐2 , demonstrated whilewhile
by SAPF applying
applying the proposed STF-dq0 technique.
Time (s) Time (s)

(a) (b)
Figure 18. Simulation results obtained under Scenario C for Load 2, which include three-phase source
dq0 techniques.
Energies 2018, 11, 2143 22 of 27
Time (s)
Figure
underScenario
Scenario C
C for
for Load
Load 2,2, showing
showing the
thetotal
totaldc-link
dc-linkvoltage
voltage
𝑉
Vdc , 𝑑𝑐 , and voltages across split dc-link capacitors
and voltages across split dc-link capacitors Vdc1 and 𝑉𝑑𝑐1V and , 𝑉𝑑𝑐2 , demonstrated
demonstrated by SAPFby SAPFapplying
while while
dc2
applying the proposed STF-dq0
the proposed STF-dq0 technique. technique.
Moreover, assessment on behavior of dc-link voltage is also conducted to further justify that
Moreover,
the assessment
SAPF is working on behavior
correctly of dc-link
under Scenario voltage
C, while is also the
applying conducted
proposedtoSTF-dq0
furthertechnique.
justify that
theFigures
SAPF is working correctly under Scenario C, while applying the proposed STF-dq0
17 and 19 provide the related results obtained for Loads 1 and 2, respectively. As expected, technique.
Figures 17 and 19 provide the related results obtained for Loads 1 and 2, respectively.
all dc-link voltages of the SAPF are effectively regulated and maintained at the desired level, As expected,
i.e.,
all dc-link
overall voltages
dc-link voltage 𝑉𝑑𝑐 atare
of the SAPF effectively
880 regulated
V and voltages andthe
across maintained
two splitatdc-link
the desired level,(𝑉
capacitors i.e.,
𝑑𝑐1overall
and
𝑉𝑑𝑐2 )voltage
dc-link at 440 VVdc(half
at 880
of V and voltages
overall across theHence,
dc-link voltage). two split
oncedc-link
again,capacitors (Vdc1
it is certain theVdc2
and
that ) at 440
SAPF can V
(half of overall
work dc-link voltage).
appropriately Hence, once again, it issource
under sinusoidal-unbalanced certainvoltage
that thescenario
SAPF can workapplying
while appropriately
the
proposed
under STF-dq0 technique.source voltage scenario while applying the proposed STF-dq0 technique.
sinusoidal-unbalanced
5.4.5.4.
Non-Sinusoidal-Unbalanced
Non-Sinusoidal-UnbalancedSource
SourceVoltage
Voltage(Scenario
(Scenario D)
D)
In In Scenario
Scenario D,D, a non-sinusoidal-unbalanced (harmonic
a non-sinusoidal-unbalanced (harmonic distorted
distortedand andmagnitude
magnitudeunbalanced)
unbalanced)
source
source voltage
voltage is is considered.All
considered. Allthethesimulation
simulationwaveforms
waveforms obtained
obtainedunderunderthis
thisscenario
scenarioareareshown
shown
in Figures
in Figures 20–24.
20–24. Meanwhile,Table
Meanwhile, Table55summarizes
summarizes the the findings
findings inin comparative
comparativemanner.
manner.As Asshown
shown in in
Figure 20, the synchronization phase value 𝜔𝑡 (appear in the form of
Figure 20, the synchronization phase value ωt (appear in the form of sawtooth wave-shape) detected sawtooth wave-shape)
by detected by the
the proposed proposed
STF-dq0 STF-dq0istechnique
technique is in
in line with theline with the
desired phasedesired
value.phase value. In
In contrast, forcontrast, for
the standard
the standard dq0 technique, the detected phase value seems to be oscillating along
dq0 technique, the detected phase value seems to be oscillating along the desired phase value. Hence, the desired phase
value. Hence, once again the findings show that the proposed STF-dq0 technique can accurately
once again the findings show that the proposed STF-dq0 technique can accurately track the desired
track the desired phase value when the source voltage is distorted and unbalanced, while the
phase value when the source voltage is distorted and unbalanced, while the standard dq0 technique
standard dq0 technique has failed to do so.
has failed to do so.
Next, from Figures 21 and 23, it is clear that by using the proposed STF-dq0 technique, the
Next, from Figures 21 and 23, it is clear that by using the proposed STF-dq0 technique, the SAPF
SAPF have successfully mitigated harmonic currents generated by Loads 1 and 2, where the
have successfully mitigated harmonic currents generated by Loads 1 and 2, where the mitigated source
mitigated source currents for both cases have regained sinusoidal shape with THD values (as
currents for both
tabulated cases
in Table 5)have regained
complying withsinusoidal shape with
the 5% harmonic THD
limit. values (as
However, SAPFtabulated in Table
that applies the 5)
complying
standard dq0 technique fails to comply with IEEE standard 519 in both cases, where the recorded to
with the 5% harmonic limit. However, SAPF that applies the standard dq0 technique fails
comply
THD with
valuesIEEE
are standard
beyond 5% 519 in both
and cases, where
the mitigated source thecurrents
recorded failTHD valuesthe
to recover aredesired
beyondsinusoidal
5% and the
mitigated source currents
shape. Nevertheless, fail techniques
both to recover the are desired
able to sinusoidal shape. Nevertheless,
remove excessive neutral currents bothcaused
techniques
by
areconnection
able to remove excessive neutral
of single-phase loads. currents caused by connection of single-phase loads.
In In
addition,
addition,as as indicated
indicated in inTable
Table5, 5, both
both techniques
techniques havehave effectively
effectively minimized
minimized the largethe large
phase
phase differences
differences between
between the source
the source current current and voltage
and voltage causedcaused by connection
by connection of Loadsof1 Loads
and 2. 1With
and 2.
minimum
With minimum phase differences,
phase almostalmost
differences, unity power
unity factor
poweroffactor
0.999 can be achieved
of 0.999 can bewhen the proposed
achieved when the
STF-dq0 technique is applied. However, due to higher distortion level
proposed STF-dq0 technique is applied. However, due to higher distortion level of the mitigated of the mitigated source
source
current, the standard dq0 technique can only provide a power factor up to 0.998 even though the phase
differences have been minimized.
Energies the
current, 2018,standard
11, x FOR PEER
dq0REVIEW 24 of 29the
technique can only provide a power factor up to 0.998 even though
Energies 2018, 11, 2143 23 of 27
phase differences have been minimized.
current, the standard dq0 technique can only provide a power factor up to 0.998 even though the
phase differences have been minimized.

Time (s)
Time (s)
Figure
20.20. Simulation
Simulation resultshowing
result showing thedetected
synchronization reference phase value 𝜔𝑡ωtunder
Figure
Figure 20. Simulation result showingthe
the detected synchronization reference
reference phase
phase value
value under
𝜔𝑡 under
Scenario
Scenario D. D.
Scenario D.

Load
LoadCurrent
Current(A)
(A) Load
Load Current
Current (A)(A)
InjectionCurrent
Injection Current(A)
(A) Injection Current
Injection (A)(A)
Current
SourceCurrent
Source Current(A)
(A) Source
SourceCurrent
Current(A)(A)
Time (s) Time (s)

(a)(s)
Time (b) (s)
Time
(a) (b)
Figure 21. Simulation results obtained under Scenario D for Load 1, which include three-phase source
dq0 techniques.
Figure 21. Simulation results obtained under Scenario D for Load 1, which include three-phase
current
Energies 2018, before and after mitigation, demonstrated by SAPF while applying the (a) proposed STF-dq0 24 of 27
11, 2143
Time (s)
Figure
underScenario
Scenario D
D for
for Load
Load 1,1, showing
showing the
thetotal
totaldc-link
dc-linkvoltage
voltage
𝑉
Vdc , 𝑑𝑐 , and voltages across split dc-link capacitors
and voltages across split dc-link capacitors Vdc1 and 𝑉𝑑𝑐1V and , 𝑉𝑑𝑐2 , demonstrated
demonstrated by SAPFby SAPFapplying
while while
dc2
theapplying
proposed the proposed STF-dq0 technique.
Energies 2018, 11,STF-dq0 technique.
x FOR PEER REVIEW 26 of 29
Time (s) Time (s)

(a) (b)
Figure
23. Simulation results
results obtained
obtained under
under Scenario
Scenario D for
D for LoadLoad 2, which
2, which include
include three-phase
three-phase source
dq0 techniques.

(a) (b)
Figure 23. Simulation results obtained under Scenario D for Load 2, which include three-phase
Energies 2018, 11, 2143 25 of 27
Time (s)
Figure 24. Simulation result obtained under Scenario D for Load 2, showing the total dc-link voltage
Vdc , and voltages across split dc-link capacitors Vdc1 and Vdc2 , demonstrated by SAPF while applying
Scenario D.
Load 1 Load 2
Phase a Phase b Phase c Phase a Phase b Phase c
THD value (%) 116.53 33.38 121.45 19.78 49.10 13.89
Power factor 0.640 0.929 0.628 0.969 0.878 0.980
THD value (%) 2.97 2.60 2.91 1.09 1.07 1.12
Power factor 0.999 0.999 0.999 0.999 0.999 0.999
THD value (%) 8.64 5.87 5.74 6.85 5.14 5.04
Power factor 0.996 0.998 0.998 0.997 0.998 0.998
Furthermore, assessment on behaviour of dc-link voltage is also conducted to justify that

the SAPF is working correctly under Scenario D, while applying the proposed STF-dq0 technique.
Figures 22 and 24 provide the related results obtained for Loads 1 and 2, respectively. From the
results obtained, all dc-link voltages of the SAPF are revealed to have effectively been regulated and
maintained at the desired level, i.e., overall dc-link voltage Vdc at 880 V and voltages across the two
split dc-link capacitors (Vdc1 and Vdc2 ) at 440 V (half of overall dc-link voltage). Hence, once again,
it is certain that the SAPF can work appropriately under non-sinusoidal-unbalanced source voltage
scenario while applying the proposed STF-dq0 technique.
Overall, based on all the findings obtained in Scenarios A to D, design concept and functionality
of the proposed STF-dq0 technique can be confirmed to be correct. By applying the proposed STF-dq0
technique, the SAPF is revealed to perform effectively in dealing with both unbalanced nonlinear loads
and all the scenarios of source voltages which have been considered in this work. The highly distorted
source currents have regained the desired sinusoidal shape with low THD values ranging from 0.92%
Energies 2018, 11, 2143 26 of 27
to 2.97%, complying with IEEE standard 519. Next, excessive neutral currents have been reduced
to a level that the mitigated source currents are balanced. In addition, large phase differences have
been reduced to the range of 0.00–0.80◦ , thereby achieving power factor of 0.999 which is almost unity.
Furthermore, all dc-link capacitor voltages have been regulated as desired and are balanced, thus
ensuring that the SAPF is able to mitigate harmonics appropriately. More importantly, the proposed
STF-dq0 technique outperforms and is more reliable than the standard dq0 technique when dealing
with distorted and unbalanced source voltages.
6. Conclusions
In this paper, a control technique that generates reference current to manage operation of a
three-phase four-wire SAPF has successfully been demonstrated. The proposed technique is named as
the STF-dq0 technique, as it is developed by integrating together the strengths of STF and working
concept of the dq0 principle, without relying on any PLL element. Comprehensive tests and analyses
involving two types of unbalanced nonlinear rectifier loads and four distinct scenarios of source
voltages are conducted to evaluate performance of the proposed STF-dq0 technique in comparison to the
standard dq0 technique. Based on the exhaustive simulation results presented, the proposed technique
is revealed to perform effectively regardless of specifications of nonlinear loads and scenarios of source
voltages. More importantly, the proposed STF-dq0 technique is demonstrated to be superior and
more reliable than the standard dq0 technique especially when dealing with distorted and unbalanced
source voltages. Low THD values complying with IEEE standard 519, synchronized operation of SAPF,
minimized neutral current and power factor reaching almost unity, are the benefits granted by the
proposed technique when it is applied in three-phase four-wire system.
Author Contributions: Y.H. designed and developed the simulation model, conducted all the necessary tests
and analyses for the research work, and prepared the initial draft of the manuscript. M.A.M.R contributed in
the simulation work, verifying the work and improving the manuscript. Both worked together in finalizing
the manuscript.
Funding: This research received no external funding.
Conflicts of Interest: The authors declare no conflict of interest.
References
1. Kale, M.; Ozdemir, E. A new hysteresis band current control technique for a shunt active filter. Turk. J. Electr.
Eng. Comput. Sci. 2015, 23, 654–665. [CrossRef]
2. Ucar, M.; Ozdemir, E. Control of a 3-phase 4-leg active power filter under non-ideal mains voltage condition.
Electr. Power Syst. Res. 2008, 78, 58–73. [CrossRef]
3. Escobar, G.; Valdez, A.A.; Torres-Olguin, R.E.; Martinez-Montejano, M.F. A model-based controller for
a three-phase four-wire shunt active filter with compensation of the neutral line current. IEEE Trans.
Power Electron. 2007, 22, 2261–2270. [CrossRef]
4. Bhattacharya, A.; Chakraborty, C.; Bhattacharya, S. Shunt compensation—Reviewing traditional methods of
reference current generation. IEEE Ind. Electron. Mag. 2009, 3, 38–49. [CrossRef]
5. Green, T.C.; Marks, J.H. Control techniques for active power filters. IEE Proc. Electr. Power Appl. 2005, 152,
369–381. [CrossRef]
6. Kale, M.; Ozdemir, E. An adaptive hysteresis band current controller for shunt active power filter.
Electr. Power Syst. Res. 2005, 73, 113–119. [CrossRef]
7. Mikkili, S.; Panda, A.K. Instantaneous active and reactive power and current strategies for current harmonics
cancellation in 3-ph 4-wire SHAF with both PI and fuzzy controllers. Energy Power Eng. 2011, 3, 285–298.
[CrossRef]
8. Eskandarian, N.; Beromi, Y.A.; Farhangi, S. Improvement of dynamic behavior of shunt active power filter
using fuzzy instantaneous power theory. J. Power Electron. 2014, 14, 1303–1313. [CrossRef]
9. Rodriguez, P.; Pou, J.; Bergas, J.; Candela, J.I.; Burgos, R.P.; Boroyevich, D. Decoupled double synchronous
reference frame PLL for power converters control. IEEE Trans. Power Electron. 2007, 22, 584–592. [CrossRef]
Energies 2018, 11, 2143 27 of 27
10. Campanhol, L.B.G.; Silva, S.A.O.; Goedtel, A. Application of shunt active power filter for harmonic reduction
and reactive power compensation in three-phase four-wire systems. IET Power Electron. 2014, 7, 2825–2836.
[CrossRef]
11. Ucar, M.; Ozdemir, S.; Ozdemir, E. A unified series-parallel active filter system for nonperiodic disturbances.
Turk. J. Electr. Eng. Comput. Sci. 2011, 19, 575–596.
12. Senini, S.; Wolfs, P.J. Analysis and design of a multiple-loop control system for a hybrid active filter.
IEEE Trans. Ind. Electron. 2002, 49, 1283–1292. [CrossRef]
13. Hoon, Y.; Radzi, M.A.M.; Hassan, M.K.; Mailah, N.F. Three-phase three-level shunt active power filter with
simplified synchronous reference frame. In Proceedings of the IEEE Industrial Electronics and Applications
Conference, Kota Kinabalu, Sabah, Malaysia, 20–22 November 2016; pp. 1–6.
14. Monfared, M.; Golestan, S.; Guerrero, J.M. A new synchronous reference frame-based method for
single-phase shunt active power filters. J. Power Electron. 2013, 13, 692–700. [CrossRef]
15. Jain, N.; Gupta, A. Comparison between two compensation current control methods of shunt active power
filter. Int. J. Eng. Res. Gen. Sci. 2014, 2, 603–615.
16. Abdulsalam, M.; Poure, P.; Karimi, S.; Saadate, S. New digital reference current generation for shunt active
power filter under distorted voltage conditions. Electr. Power Syst. Res. 2009, 79, 759–765. [CrossRef]
17. Biricik, S.; Redif, S.; Özerdem, Ö.C.; Khadem, S.K.; Basu, M. Real-time control of shunt active power filter
under distorted grid voltage and unbalanced load condition using self-tuning filter. IET Power Electron. 2014,
7, 1895–1905. [CrossRef]
18. Djazia, K.; Krim, F.; Chaoui, A.; Sarra, M. Active power filtering using the zdpc method under unbalanced
and distorted grid voltage conditions. Energies 2015, 8, 1584–1605. [CrossRef]
19. Jain, S.K.; Agrawal, P.; Gupta, H.O. Design simulation and experimental investigations, on a shunt active
power filter for harmonics, and reactive power compensation. Electr. Power Compon. Syst. 2003, 31, 671–692.
[CrossRef]
20. Krim, F. Parameters estimation of shunt active filter for power quality improvement. In Proceedings of
the 5th International Power Engineering and Optimization Conference (PEOCO), Shah Alam, Selangor,
Malaysia, 6–7 June 2011; pp. 306–311.
21. Jain, S.K.; Agrawal, P.; Gupta, H.O. Fuzzy logic controlled shunt active power filter for power quality
improvement. IEE Proc. Electr. Power Appl. 2002, 149, 317–328. [CrossRef]
22. Institute of Electrical and Electronics Engineers (IEEE). IEEE recommended practice and requirement for
harmonic control in electric power systems. In IEEE Std 519-2014 (Revision of IEEE Std 519-1992); IEEE:
Piscataway, NJ, USA, 2014; pp. 1–29.
© 2018 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access
article distributed under the terms and conditions of the Creative Commons Attribution
(CC BY) license (http://creativecommons.org/licenses/by/4.0/).

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energies

Energies 2018, 11, 2143; doi:10.3390/en11082143 www.mdpi.com/journal/energies

Ideal / Non-ideal Source Load Line

3. Working Principle of the Standard dq0 Technique

iL α Direct (d) i Ld (ac) dq / αβ

e1 (t) = Vdc, re f − (Vdc1 (t) + Vdc2 (t)) (11)

e2 (t) = Vdc2 (t) − Vdc1 (t) (13)

4. Working Principle the Proposed STF-dq0 Technique

vSα vSα (dc)

i Ld(ac) = i Lα(ac) sin(ωt) + i Lβ(ac) cos(ωt) (22)

5. Results and Discussion

Table 1. Nonlinear load configuration for simulation work.

Nonlinear Load Load Descriptions

Analysis is performed in a comparative manner, i.e., by benchmarking performance demonstrated

Voltage Supply Load Current Line Inductance Unbalanced Load

Output Filter SAPF

Dc-link Capacitor Reference Current Hysteresis Switching

Split Capacitor Voltage

Scenario A: Sinusoidal-balanced source voltage:

(THDa = THDb = THDc = 0.00%)

vSa = 326 sin(ωt) (24)

Scenario B: Non-sinusoidal-balanced source voltage:

(THDa = THDb = THDc = 20.80%)

vSa = 326 sin(ωt) + 50 sin(3ωt) + 40 sin(5ωt) + 20 sin(7ωt) + 10 sin(9ωt) (27)

(THDa = THDb = THDc = 0.00%)

vSa = 326 sin(ωt) (30)

Scenario D: Non-sinusoidal-unbalanced source voltage

(THDa = 16.80%, THDb = 15.74%and THDc = 6.99%)

vSa = 326 sin(ωt) + 40 sin(3ωt) + 30 sin(5ωt) + 20 sin(7ωt) + 10 sin(9ωt) (33)

5.1. Sinusoidal-Balanced Source Voltage (Scenario A)

Synchronization phase value 𝜔𝑡 detected by the proposed STF-dq0 (red)

Synchronization phase value 𝜔𝑡 detected by the standard 𝑑𝑞0 (red)

Performance Load 1 Load 2

Source Voltage (V) Source Voltage (V)

Load Current (A) Load Current (A)

Injection Current (A) Injection Current (A)

Source Current (A) Source Current (A)

Time (s) Time (s)

Energies 2018, 11, x FOR PEER REVIEW 14 of 29

Total Dc-link Voltage (V)

Split Dc-link Capacitor Voltage (V)

Split Dc-link Capacitor Voltage (V)

Source Voltage (V) Source Voltage (V)

Load Current (A) Load Current (A)

Injection Current (A) Injection Current (A)

Time (s) Time (s)

Energies 2018, 11, x FOR PEER REVIEW 16 of 29

Source Voltage (V) Source Voltage (V)

Load Current (A) Load Current (A)

Injection Current (A) Injection Current (A)

Source Current (A) Source Current (A)

Time (s) Time (s)

Total Dc-link Voltage (V)

Split Dc-link Capacitor Voltage (V)

Source Voltage (V) Source Voltage (V)

Load Current (A) Load Current (A)

Injection Current (A) Injection Current (A)

Source Current (A) Source Current (A)

Time (s) Time (s)

Total Dc-link Voltage (V)

Split Dc-link Capacitor Voltage (V)

5.3. Sinusoidal-Unbalanced Source Voltage (Scenario C)

Synchronization phase value 𝜔𝑡 detected by the proposed STF-dq0 (red)