DEC Manual-2017

VISVESVARAYA TECHNOLOGICAL UNIVERSITY
K S SCHOOL OF ENGINEERING AND MANAGEMENT

BANGALORE – 109
Department of Electronics and Communication Engg.
DIGITAL ELECTRONICS
LAB MANUAL
(17ECL38)
III SEMESTER B.E (ECE)
Edited By
Mr. Manu D K Associate Professor

Mr. Syed Waseem Tabraiz Assistant Professor
Mrs. Pratibha S N Assistant Professor
NAME: ______________________________
USN: ________________________________
BATCH: _____________________________
LIST OF EXPERIMENTS
Sl.
Experiment
No.
a. Verify DeMorgan’s Theorem for two variables.

1
b. Simulate Mod-8 Synchronous UP/DOWN Counter using simulation tool.
Design and implement

2 (a) Full Adder using (i) Basic logic gates and (ii) NAND gates.
(b) Full subtractor using (i) Basic logic gates and (ii) NAND gates.
3 Design and Implement 4-bit Parallel Adder/ Subtractor using IC 7483.
a. Design and Implementation of 4-bit Magnitude Comparator using IC 7485.

4
b. Simulate Full- Adder using simulation tool.
Realize
a. Adder & Subtractor using IC 74153.
5
b. 3-variable function using IC 74151(8:1MUX).
a. Realize a Boolean expression using decoder IC74139.

6
b. Realize Ring and Johnson counter using IC 7495.
7 Realize Master-Slave JK and D Flip-Flop using NAND Gates.
Realize the following shift registers using IC 7495

8
(a) SISO (b) SIPO (c) PISO (d) PIPO
Realize (i) Mod-8 Asynchronous Counter using IC7490.

9
(ii) Decade Counter using IC7490.
a. Design Pseudo Random Sequence generator using 7495.

10
a. The sum-of product and product-of-sum expressions using universal gates.

11
12
Dept of ECE, KSSEM Page 1

c.
TABLE OF CONTENTS
1. IMPLEMENTATION OF DEMORGAN’S THEOREM AND SOP/POS EXPRESSIONS ......................................... 5
2. FULL ADDER AND FULL SUBTRACTOR ......................................................................................................... 9
3. PARALLEL ADDER AND SUBTRACTOR USING 7483.................................................................................... 13
4. FOUR BIT MAGNITUDECOMPARATOR USING IC 7485 .............................................................................. 17
5. MUX/DEMUX FOR ARITHMETIC CIRCUITS................................................................................................. 19
6. DEMULTIPLEXER/DECODER ....................................................................................................................... 26
7. STUDY OF FLIP-FLOPS ................................................................................................................................ 30
8. STUDY OF SHIFT REGISTERS....................................................................................................................... 34
9. STUDY OF COUNTERS USING IC 7490 ........................................................................................................ 34
10.SEQUENCE GENERATOR ............................................................................................................................ 38

11.SIMULATION OF FULL ADDER USING HDL PROGRAM IN XILINX ............................................................... 44
12.SIMULATION OF MOD 8 UP/DOWN COUNTER USING HDL PROGRAM IN XILINX .................................... 45

Digital Electronics Lab Manual III Sem
IC Pin configurations
Inverter (NOT Gate) - 7404LS 2-Input AND Gate - 7408LS
2-Input OR Gate - 7432LS 2-Input NAND Gate - 7400LS
2-Input NOR Gate - 7402LS 2-Input EX-OR Gate - 7486LS
3-Input NAND Gate - 7410LS 4-Input NAND Gate - 7420LS

A) ̅̅̅̅̅̅̅̅
𝑨+𝑩 ̅. 𝑩
=𝑨 ̅
Truth Table:
A B ̅̅̅̅̅̅̅̅
𝑨+𝑩 ̅
𝑨 ̅
𝑩 ̅ .𝑩
𝑨 ̅
0 0
0 1
1 0
1 1
Logic Diagram:
Given Problem: ̅̅̅̅̅ ̅+𝑩

𝑨. 𝑩 = 𝑨 ̅
Truth Table:
A B ̅̅̅̅̅
𝑨. 𝑩 ̅
𝑨 ̅
𝑩 ̅ +𝑩
𝑨 ̅
0 0
0 1
1 0
1 1
Logic Diagram:

Experiment No. 1 Date: ___/___/_____
IMPLEMENTATION OF DEMORGAN’S THEOREM AND SOP/POS EXPRESSIONS
Aim: 1. To verify
(a) Demorgan’s Theorem for 2 variables
(b) The sum-of product and product-of-sum expressions using universal gates.
Components required: IC 7400, IC 7402, IC 7404, IC 7408, IC 7432, Patch Cords and Trainer Kit.
Theory: Augustus De Morgan, a 19th-century British mathematician developed a pair of important

rules regarding group complementation in Boolean algebra referred to as Demorgan’s theorems.
Applications of these rules include simplification of logical expressions in computer programs and
digital circuit designs. They are as follows.
(i) AB  A  B
Statement: The complement of a product is equal to the sum of complements.
(ii) A  B  A. B
Statement: The complement of a sum term is equal to the product of complements.
In a Boolean function, the variables appear either in complemented or an uncomplemented form. Each
occurrence of a variable in either form is called a “literal”. These literals can be grouped either as a
product term or sum term. A product term is defined as either a literal or product of literals (also called
conjunction). A sum term is defined as either a literal or sum of literals (also called disjunction). These
literals and terms are arranged in two forms.
(i) Sum of Products (SoP): It is the group of product terms ORed together. If each product term
(also called minterm) in SoP contains all literals, then it is called canonical SoP.
(ii) Product of Sum (PoS): It is the group of sum terms ANDed together. If each sum term (also
called maxterm) in PoS contains all literals, then it is called canonical PoS.
Procedure:
1. Identify the IC requiredand place on the trainer kit such that the notch of the IC is facing
towards the Vcc, where the IC pin no. 7 and 14 are connected to ground and VCC respectively.
2. Connections are made as per the logic diagram.
3. Switch on the power supply.
4. Apply suitable logical inputs as per the truth table and verify the output.

NOTE: If correct output is not obtained, each and every gate is to be checked separately and even then
if the output is not obtained, then IC has to be replaced.
B) The sum-of product and product-of-sum expressions using universal gates.

1) Sum of product (SOP): Y=F(A,B,C,D) = ∑(5,7,9,11,13,15)
Simplification using K-map:
Y=BD+AD
ii)Implementation Using NAND gates iii) Implementation Using NOR Gates

2) Product of Sum (POS): Y= F(A,B,C,D) = П(0,1,2,3,4,6,8,10,12,14)
Simplification using K-map:
Y=(A+B) D
ii) Implementation Using NAND gates iii) Implementation Using NOR Gates
Conclusion: The Demorgan’s theorem, sum-of product and product-of-sum expressions are verified
using truth table.

Truth Table
A B Cn-1 Sum Carry

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Full Adder Logic Circuit Using Basic Gates
Full Adder Using NAND Gates

FULL ADDER AND FULL SUBTRACTOR
Aim: To design and Implement

i. Full Adder using basic and Nand Gates
ii. Full Subtractor using basic and Nand Gates
Components Required: IC 7408, IC 7432, IC 7400, IC 7486, and IC 7404.
Theory: Half Adder is a combinational circuit that performs the addition of two bits, this circuit needs
two binary inputs A and B, and two binary outputs sum and carry. Full adder is a combinational logic
circuit that adds two binary numbers along with carry to produce two outputs sum and Carry out. The
Half Subtractor is a combinational circuit that performs the subtraction of two bits, these circuit needs
two binary inputs A and B, and two binary outputs difference and borrows. Full subtractor is a
combinational logic circuit that subtracts two binary numbers along with borrow to produce two
outputs difference and borrow out. The adder and subtractor logic circuits can be realized using basic or
preliminary gates or universal gates such as NAND gates.
Procedure:
1. Verify that the gates are working.
2. Make the connections as per the circuit diagram for the half adder circuit, on the trainer kit.
3. Switch on the VCC power supply and apply the various combinations of the inputs according to
the respective truth tables.
4. Note down the output readings for the half adder circuit for the corresponding combination of
inputs.
5. Verify that the outputs are according to the expected results.
6. Repeat the procedure for the full adder circuit, the half subtractor and full subtractor circuits.
Verify that the sum/difference and carry/borrow bits are according to the expected values.

Truth Table
A B Cn-1 Difference Borrow

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Full Subtractor Logic Circuit Using Basic Gates
Full Subtractor Using NAND Gates

Conclusion: The Full Adder/Subtractor outputs are obtained and verified using truth table.

IC 7483 Pin Diagram
7483
A. IC 7483 as a Full Adder

Logic Diagram

Logic Design Lab Manual III Sem
Truth Table
PARALLEL ADDER AND SUBTRACTOR USING 7483
Aim: To design and implement 4-bit Parallel Adder/ Subtractor using IC 7483.
Components Required: IC 7483, IC 7404, etc.
Theory:
Addition of n-bit numbers requires a chain of n full adders or a chain of one-half adder and n - 1
full adders. In the former case, the input carry to the least significant position is fixed at 0.
Interconnection of four full-adder (FA) circuits is to provide a four-bit binary ripple carry adder. The
augend bits of A and the addend bits of B are designated by subscript numbers from right to left, with
subscript 0 denoting the least significant bit. The carries are connected in a chain through the full
adders. The input carry to the adder is C0, and it ripples through the full adders to the output carry C4.
The S outputs generate the required sum bits. An n-bit adder requires n full adders, with each output
carry connected to the input carry of the next higher order full adder. When carry propagates through n
stages produces more delay reducing execution speed. To overcome this problem carry look ahead
feature is implemented in IC 7483 a 4bit parallel binary adder. Subtraction can also be performed using
this IC.
Input Data A Input Data B Addition

A3 A2 A1 A0 B3 B2 B1 B0 C4 S3 S2 S1 S0
1 0 0 0 0 0 1 0 0 1 0 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0
1 0 1 0 1 0 1 1 1 0 1 0 1
1 1 1 0 1 1 1 1 1 1 1 0 1
1 0 1 0 1 1 0 1 1 0 1 1 1
Procedure:
1. Connect one set of inputs from A0 to A3 pins and the other set from B0 to B3, on the IC 7483.
2. Connect C0 to the ground.
3. Connect the pins from S0 to S3 to output terminals. Connect C4 to the Carry Output pin.
4. In order to implement the IC 7483 as a subtractor, first connect C0 to VCC, Apply the B input
through NOT gates (essentially taking complement of B).
5. Apply the inputs to the adder/ subtractor circuits as shown in the truth tables.
6. Check the outputs and note them down in the table for the corresponding inputs.
7. Verify that the outputs match with the expected results.
A. IC 7483 as a Parallel Subtractor

Logic Diagram
Truth Table:

Conclusion:The4-bit Parallel Adder/ Subtractor using IC 7483 is verified using truth table.
Input Data A Input Data B Subtraction

A3 A2 A1 A0 B3 B2 B1 B0 B4 S3 S2 S1 S0
1 0 0 0 0 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 1 0
1 0 1 0 1 0 1 1 0 1 1 1 1
1 1 1 0 1 1 1 1 0 1 1 1 1
1 0 1 0 1 1 0 1 0 1 1 0 1

Truth Table:
Input A Input B Output
A3 A2 A1 A0 B3 B2 B1 B0 A>B A<B A=B
0 0 0 0 0 0 0 1 0 1 0
0 1 0 1 0 0 1 1 1 0 0
1 0 1 0 1 0 1 0 0 0 1
0 0 1 1 0 1 1 0 0 1 0
0 1 0 0 1 0 0 0 0 1 0
1 1 0 1 1 0 1 1 1 0 0
0 1 1 0 0 1 1 0 0 0 1
1 1 1 1 1 1 1 0 1 0 0
4-Bit Comparator using IC 7485

Logic Design Lab Manual III Sem
FOUR BIT MAGNITUDECOMPARATOR USING IC 7485
Aim: To design and implement 4-bit magnitude comparator using IC 7485.
Components Required: IC 7404, IC 7408, IC 7486, IC 7432, and IC 7485.
Theory: A magnitude digital comparator is a combinational circuit that compares two digital or binary
numbers (consider A and B) and determines their relative magnitudes in order to find out whether one
number is equal, less than or greater than the other digital number. A comparator used to compare two
bits, i.e., two numbers each of single bit is called a single bit comparator. It consists of two inputs for
allowing two single bit numbers and three outputs to generate less than, equal and greater than
comparison outputs. A 2-bit comparator compares two binary numbers, each of two bits and produces
their relation such as one number is equal or greater than or less than the other. The 4-bit comparator is
mostly available in IC form and common type of this IC is 7485. This IC can be used to compare two
4-bit binary words by grounding I (A>B), I (A<B) and I (A=B) connector inputs to Vcc terminal. The
figure below shows the pin diagram of IC7485 comparator. In addition to the normal comparator, this
IC is provided with cascading inputs in order to facilitate the cascading several comparators.

Procedure: A. Comparators Using Logic Gates:

1.Verify the working of the logic gates.
2.Make the connections as per the respective circuit diagrams.
3.Switch on Vcc.
4.Apply the inputs as per the truth tables.
5. Check the outputs and verify that they are according to the truth tables.
Study of IC 7485:
1.Write the truth table for a 4-bit comparator.
2. Connect pin 16 to Vcc and pin 8 to GND for the ICs.
3.Apply the two inputs as shown; making sure that the MSB and LSB is correctly connected.
4.There are two IC’s of 4-bit comparator: CD 74HC85E H9349, 7485N K8413 5A.
5.The 2 IC’s need pin 3 cascade i/p (A=B) to be connected to Vcc.
6. Outputs are recorded at pin 5 (A>B), pin 6 (A=B) and pin 7 (A<B) and are verified according
to the truth table.
Conclusion: The 4-bit magnitude comparator using IC 7485 is verified with truth table.
Truth Table:
Inputs Half Adder Outputs Half Subtractor Outputs
A B Sum Carry Diff Borrow
0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 0 1 0

1 1 0 1 0 0
MUX/DEMUX FOR ARITHMETIC CIRCUITS
Aim: ToRealize
i. Adder & Subtractor using IC 74153.
ii. 3-variable function using IC 74151(8:1MUX).
Components Required: IC 74153, IC 74151, IC 7404, IC 7400, IC 7420,etc.
Procedure:
For MUX IC 74153
1. The Pin [16] is connected to + Vcc and Pin [8] is connected to ground.
2. The inputs are applied either to ‘A’ input or ‘B’ input.
3. If MUX ‘A’ has to be initialized, EA is made low and if MUX ‘B’ has to be initialized,
EB is made low.
4. Based on the selection lines one of the inputs will be selected at the output, and
thus the truth table is verified.

5. In case of half adder using MUX, apply constant inputs at (I0a, I1a, I2a, I3a) and (I0b,
I1b, I2b and I3b) as shown.
6. The corresponding values of select input lines, A and B (S1 and S0) are changed as
per table and the output is taken at Za as sum and Zb as carry.
7. In this case, the inputs A and B are varied. Making Ea and Eb zero andthe output is
taken at Za, and Zb.
8. In case of Half Subtractor, connections are made according to the circuit, Inputs
are applied at A and B as shown, and outputs are taken at Za (Difference) and Zb
(Borrow). Verify outputs.
9. In full adder using MUX, the inputs are applied at Cn-1, An and Bn according to the
truth table. The corresponding outputs are taken at Sn (pin Za) and Cn (pin Zb) and
are verified according to the truth table.
10. In full subtractor using MUX, the inputs are applied at Cn-1, An and Bn according to
the truth table. The corresponding outputs are taken at pin Za(Difference) and pin
Zb(Borrow) and are verified according to the truth table.
Truth Tables for Full Adder/Subtractor using 74153

Inputs Full Adder Outputs Full Subtractor Outputs
A B Cin/Bin S Cout D Bout
0 0 0 0
0 0 0
1 0 1 1
0 0 1
1 0 1 1
0 1 0
0 1 0 1
0 1 1
1 0 1 0
1 0 0
0 1 0 0
1 0 1
0 1 0 0
1 1 0
1 1 1 1
1 1 1

Theory: A multiplexer or MUX, also called a data selector, is a combinational circuit with more than
one input line, one output line and more than one selection line. There are some multiplexer ICs that
provide complementary outputs. Also, multiplexers in IC form almost invariably have an ENABLE or
STROBE input, which needs to be active for the multiplexer to be able to perform its intended function.
A multiplexer selects binary information present on any one of the input lines, depending upon the
logic status of the selection inputs, and routes it to the output line. If there are n selection lines, then the
number of maximum possible input lines is 2nand the multiplexer is referred to as a 2n-to-1multiplexer
or 2n×1 multiplexer. Figures 8.1(a) and (b) respectively show the circuit representation and truth table
of a basic 4-to-1 multiplexer. The practical multiplexer devices are available in IC form such as 8-to-1
and 16-to-1 multiplexers. The8-to-1 multiplexer is IC type number 74151 of the TTL family. It has an
active LOWENABLE input and provides complementary outputs.
Procedure:
1. Make the connections as per the logic diagram.
2. Verify the output with the truth table.

b) Pin Details of IC74151:
Logic Symbol of 8:1 MUX

3-Variable function using IC 74151(8:1 MUX).
F (A,B,C) = ∑m (1,3,5,6)
Truth table
Inputs Output
A B C Y
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1

1 1 0
1 1 1
Conclusion: Adder & Subtractor using IC 74153 and 3-Variable function using IC 74151 (8:1 Mux)
are verified with truth table.

Truth Table
Inputs Half Adder Outputs Half Subtractor Outputs
A B Sum Carry Diff Borrow
0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 0 1 0
1 1 0 1 0 0

DEMULTIPLEXER/DECODER
Aim: To Realize a Boolean expression using decoder IC74139.

Components Required: IC 74139.
Theory: A demultiplexer is a combinational logic circuit with an input line, 2noutput lines and n select
lines. It routes the information present on the input line to any of the output lines. The output line that
gets the information present on the input line is decided by the bit status of the selection lines. A
decoder is a special case of a demultiplexer without the input line a decoder, is a combinational circuit
that decodes the information on n input lines to a maximum of 2nunique output lines. If there are some
unused or ‘don’t care’ combinations in then-bit code, then there will be fewer than 2noutput lines.
For DEMUX IC 74139

1. The Pin [16] is connected to + Vcc and Pin [8] is connected to ground.
2. The inputs are applied either to ‘A’ input or ‘B’ input.
3. If DEMUX ‘A’ has to be initialized, EA is made low and if DEMUX ‘B’ has to be
initialized, EB is made low.
4. Based on the selection lines one of the inputs will be selected at the set of outputs, and
thus the truth table is verified.
5. In case of half adder using DEMUX, Ea is set to 0, the corresponding values of select
input lines, A and B (S1a and S0a) are changed as per table and the output is taken at Sum
and Carry. Verify outputs.
6. In case of Half Subtractor, connections are made according to the circuit, Inputs are
applied at A and B as shown, and outputs are taken at Difference and Borrow. Verify
outputs.
7. In full adder using DEMUX, the inputs are applied at Cn-1, An and Bn according to the
truth table. The corresponding outputs are taken at Sum and Carry, and are verified
according to the truth table.
8. In full subtractor using DEMUX, the inputs are applied at Cn-1, An and Bn according to
the truth table. The corresponding outputs are taken at Difference and Borrow as shown,
and are verified according to the truth table.

Full Adder Using 74139
Full Subtractor Using 74139

Truth Tables:
Inputs Full Adder Outputs Full Subtractor Outputs
A B Cin/Bin S Cout D Bout
0 0 0 0
0 0 0
1 0 1 1
0 0 1
1 0 1 1
0 1 0
0 1 0 1
0 1 1
1 0 1 0
1 0 0
0 1 0 0
1 0 1
0 1 0 0
1 1 0
1 1 1 1
1 1 1
Procedure:
1. Make the connections as per the logic diagram.
2. Verify the output with the truth table.
Conclusion: A Boolean expressions using decoder IC74139 are verified with truth table.

A. J-K Master-Slave Flip-Flop

Truth Table:
Preset Clear J K Clock 𝑸𝒏+𝟏 ̅̅̅̅̅̅̅
𝑸𝒏+𝟏 Status
0 1 X X X 1 0 Set
1 0 X X X 0 1 Reset
1 1 0 0 𝑸𝒏 ̅̅̅̅
𝑸𝒏 No Change
1 1 0 1 0 1 Reset
1 1 1 0 1 0 Set
1 1 1 1 ̅̅̅̅
𝑸𝒏 𝑸𝒏 Toggle
Logic Diagram
B. T-Type Flip-Flop
Logic Diagram
Truth Table:
Preset Clear T Clock 𝑸𝒏+𝟏 ̅̅̅̅̅̅̅
𝑸𝒏+𝟏
1 1 0 𝑸𝒏 ̅̅̅̅
𝑸𝒏
1 1 1 ̅̅̅̅
𝑸𝒏 𝑸𝒏

STUDY OF FLIP-FLOPS
Aim: To realize the following Master Slave, D and T Flip-Flops using Nand gates.
Components Required: -IC 7410, IC 7400, etc.
Theory: Flip-flops and latches are digital memory circuits that can remain in the state in which they
were set even after the input signals have been removed. This means that the circuits have a memory
function and will hold a value (0 or 1) until the circuit is forced to change state. A latch is a memory
device that samples and acts upon its input lines immediately the input lines change. It does not require
any external timing signals.
A flip-flop is a memory device that samples and acts upon its input lines only when it is told to
do so with a special timing signal called the clock. This may be in the form of a level or an edge. A
level trigger means that the flip-flop samples its inputs depending upon the voltage level of the trigger
input. An edge trigger means that the flip-flop samples its inputs depending on a LOW-to-HIGH
transition on the trigger line or a HIGH-to-LOW transition on a trigger line.
Procedure:
1. Make the connections as shown in the respective logic diagrams.
2. Apply inputs as shown in the respective truth tables, for each of the flip-flop circuits.
3. Check the outputs of the circuits; verify that they match that of the respective truth tables.

C. D-Type Flip-Flop
Truth Table:
Preset Clear D Clock 𝑸𝒏+𝟏 ̅̅̅̅̅̅̅
𝑸𝒏+𝟏
1 1 0 0 1
1 1 1 1 0

Conclusion: The Master Slave JK, D and T Flip-Flop are verified with truth table.

IC 7495 Pin Diagram:
A. SIPO Mode (Left Shift)

Logic Diagram Truth Table
Serial
Clock QA QB QC QD
I/P
1 1 X X X 1
2 0 X X 1 0
3 1 X 1 0 1
4 1 1 0 1 1
B. SIPO MODE (Right Shift)

Logic Diagram Truth Table:
Serial
Clock QA QB QC QD
I/P
1 1 1 X X X
2 0 0 1 X X
3 1 1 0 1 X
4 1 1 1 0 1

STUDY OF SHIFT REGISTERS

Aim: Realize the following shift registers using IC7474/IC 7495 (a) SISO (b) SIPO (c) PISO
(d) PIPO (e) Ring and (f) Johnson counter.
Components Required: -IC 7495, IC 7404, etc.
Theory: Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are
a group of flip-flops connected in a chain so that the output from one flip-flop becomes the input of the
next flip-flop. Most of the registers possess no characteristic internal sequence of states. All flip-flop is
driven by a common clock, and all are set or reset simultaneously.
Serial data transmission, over a distance of meters to kilometers, uses shift registers to convert
parallel data to serial form. Serial data communications replaces many slow parallel data wires with a
single serial high speed circuit Serial data over shorter distances of tens of centimeters, uses shift
registers to get data into and out of microprocessors. Numerous peripherals, including analog to digital
converters, digital to analog converters, display drivers, and memory, use shift registers to reduce the
amount of wiring in circuit boards.
Basic shift registers are classified by structure according to the following types:
 Serial-in/serial-out
 Parallel-in/serial-out
 Serial-in/parallel-out
 Parallel-in/parallel-out
Procedure:
A. Serial In-Parallel Out (Left Shift):
1. Make the connections as shown in the respective circuit diagram.
2. Make sure the 7495 is operating in Parallel mode by ensuring Pin 6 (Mode M) is set to
HIGH, and connect clock input to Pin 8 (Clk 2).
3. Apply the first data at pin 5 (D) and apply one clock pulse. We observe that this data
appears at pin 10 (QD).
4. Now, apply the second data at D. Apply a clock pulse. We now observe that the earlier
data is shifted from QD to QC, and the new data appears at QD.
5. Repeat the earlier step to enter data, until all bits are entered one by one.
6. At the end of the 4th clock pulse, we notice that all 4 bits are available at the parallel
output pins QA (MSB), QB, QC, QD (LSB).
7. Enter more bits to see there is a left shifting of bits with each succeeding clock pulse.

C. SISO Mode
Truth Table:
Logic Diagram
Serial
Clock QA QB QC QD
I/P
1 d0=0 0 X X X
2 d1=1 1 0 X X
3 d2=1 1 1 0 X
4 d3=1 1 1 1 0=d0
5 X X 1 1 1=d1
6 X X X 1 1=d2
7 X X X X 1=d3
D. PISO Mode
Mode Clk Parallel I/P Parallel O/P
A B C D QA QB QC QD
1 1 1 0 1 1 1 0 1 1
0 2 X X X X X 1 0 1
0 3 X X X X X X 1 0
0 4 X X X X X X X 1

Digital Electronics Lab Manual (15ECL38) III Sem
B. Serial In-Parallel Out (Right Shift):

1. Make the connections as shown in the respective circuit diagram.
2. Make sure the 7495 is operating in SIPO mode by ensuring Pin 6 (Mode M) is set to
LOW, and connect clock input to Pin 9 (Clk 1).
3. Apply the first data at pin 1 (SD1) and apply one clock pulse. We observe that this data
appears at pin 13 (QA).
4. Now, apply the second data at SD1. Apply a clock pulse. We now observe that the earlier
data is shifted from QA to QB, and the new data appears at QA.
5. Repeat the earlier step to enter data, until all bits are entered one by one.
6. At the end of the 4th clock pulse, we notice that all 4 bits are available at the parallel
output pins QA through QD.
7. Enter more bits to see there is a right shifting of bits with each succeeding clock pulse.
C. Serial In-Serial Out Mode:

1. Connections are made as shown in the SISO circuit diagram.
2. Make sure the 7495 is operating in SIPO mode by ensuring Pin 6 (Mode) is set to LOW,
and connect clock input to Clk 1(Pin 9).
3. The 4 bits are applied at the Serial Input pin (Pin 1), one by one, with a clock pulse in
between each pair of inputs to load the bits into the IC.
4. At the end of the 4th clock pulse, the first data bit, ‘d0’ appears at the output pin QD.
5. Apply another clock pulse, to get the second data bit ‘d1’ at QD. Applying yet another
clock pulse gets the third data bit ‘d2’ at QD, and so on.
6. Thus we see the IC 7495 operating in SISO mode, with serially applied inputs appearing
as serial outputs.
D. Parallel In-Serial Out Mode:

1. Connections are made as shown in the PISO circuit diagram.
2. Now apply the 4-bit data at the parallel input pins A, B, C, D (pins 2 through 5).
3. Keeping the mode control M on HIGH, apply one clock pulse. The data applied at the
parallel input pins A, B, C, D will appear at the parallel output pins Q A, QB, QC, QD
respectively.
4. Now set the Mode Control M to LOW, and apply clock pulses one by one. Observe the
data coming out in a serial mode at QD.
5. We observe now that the IC operates in PISO mode with parallel inputs being transferred
to the output side serially.
Dept. of ECE, KSSEM. Page 30

E. PIPO Mode
Logic Diagram
F. Ring Counter
Mode Clock QA QB QC QD
1 1 1 0 0 0
0 2 0 1 0 0
0 3 0 0 1 0
0 4 0 0 0 1
0 5 1 0 0 0
0 6 0 1 0 0
G. Johnson Counter
Logic Diagram Truth
Table: Mode Clock QA QB QC QD
1 1 1 0 0 0
0 2 1 1 0 0
0 3 1 1 1 0
0 4 1 1 1 1
0 5 0 1 1 1
0 6 0 0 1 1
0 7 0 0 0 1
0 8 0 0 0 0
0 9 1 0 0 0
0 10 1 1 0 0

E. Parallel In-Parallel Out Mode:

1. Connections are made as shown in the PIPO mode circuit diagram.
2. Set Mode Control M to HIGH to enable Parallel transfer.
3. Apply the 4 data bits as input to pins A, B, C, D.
4. Apply one clock pulse at Clk 2 (Pin 8).
5. Note that the 4 bit data at parallel inputs A, B, C, D appears at the parallel output pins
QA, QB, QC, QD respectively.
Theory: A ring counter is a Shift Register (a cascade connection of flip-flops) with the output of the
last flip flop connected to the input of the first. It is initialized such that only one of the flip flop output
is 1 while the remainder is 0. The 1 bit is circulated so the state repeats every n clock cycles if n flip-
flops are used. The MOD of the n flip flop ring counter is n.It can be implemented using D-type flip-
flops (or JK-type flip-flops).
A twisted ring counter, also called switch-tail ring counter named after Robert Royce Johnson -
the connects the complement of the output of the last shift register to the input of the first register and
circulates a stream of ones followed by zeros around the ring. Johnson counters are often favored, not
just because they offer twice as many count states from the same number of shift registers, but because
they are able to self-initialize from the all-zeroes state, without requiring the first count bit to be
injected externally at start-up. The Johnson counter generates a Gray code, a code in which adjacent
states differ by only one bit.
Procedure:
1. Make the connections as shown in the respective circuit diagram for the Ring Counter.
2. Apply an initial input (1000) at the A, B, C, D pins respectively.
3. Keep Select Mode = HIGH (1) and apply one clock pulse.
4. Next, Select Mode = LOW (0) to switch to serial mode and apply clock pulses.
5. Observe the output after each clock pulse, record the observations and verify that they match
the expected outputs from the truth table.
6. Repeat the same procedure as above for the Johnson Counter circuit and verify its operation.
Conclusion: The operations of SIPO, SISO, PISO, PIPO ring counter and Johnson Counter are
performed using IC7495 and Verified with truth table.

A. Decade Counter (using IC 7490)
Truth Table:
Clock QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 0 0 0 0
Logic Diagram

STUDY OF COUNTERS USING IC 7490
Aim: To realize Mod-N Counter using IC 7490
Components Required: IC 7476, IC 7490, IC 7400, IC 7408, IC 7416, IC 7432, etc.
Theory: Counter is a device which stores (and sometimes displays) the number of times a particular
event or process has occurred, often in relationship to a clock signal. The most common type is a
sequential digital logic circuit with an input line called the "clock" and multiple output lines. The values
on the output lines represent a number in the binary or BCD number system. Each pulse applied to the
clock input increments or decrements the number in the counter .A counter circuit is usually
constructed of a number of flip-flops connected in cascade. Counters are a very widely-used component
in digital circuits, and are manufactured as separate integrated circuits and also incorporated as parts of
larger integrated circuits. An asynchronous (ripple) counter is a single d-type flip-flop, with its J (data)
input fed from its own inverted output. This circuit can store one bit, and hence can count from zero to
one before it overflows (starts over from 0). This counter will increment once for every clock cycle and
takes two clock cycles to overflow, so every cycle it will alternate between a transition from 0 to 1 and
a transition from 1 to 0.In synchronous counters, the clock inputs of all the flip-flops are connected
together and are triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in
parallel).
Procedure:
A. Study of Counters IC 7490
1. Connections are made as shown in the respective circuit diagrams.
2. To create a divide-by-10 counter, you first connect pin 5 to +5 volts and pin 10 to
ground to power the chip.
3. Then you connect pin 12 to pin 1 and ground pins 2, 3, 6, and 7.
4. Run the input clock signal in on pin 14.
5. The output appears on QA, QB, QC and QD.

B. Mod-8 Counter (Using IC 7490)

Logic Diagram
Truth Table:
Clock QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 0 0 0 0
9 0 0 0 1

Conclusion: The Mod-N Counter using IC 7490 is verified with truth table.

Logic Diagram
Truth Table: Karnaugh Map:
Map O/p
Clock QA QB QC QD
Value D
15 1 1 1 1 1 0
7 2 0 1 1 1 0
3 3 0 0 1 1 0
1 4 0 0 0 1 1
8 5 1 0 0 0 0
4 6 0 1 0 0 0
2 7 0 0 1 0 1
9 8 1 0 0 1 1
12 9 1 1 0 0 0
6 10 0 1 1 0 1
11 11 1 0 1 1 0
5 12 0 1 0 1 1
10 13 1 0 1 0 1
13 14 1 1 0 1 1
14 15 1 1 1 0 1

SEQUENCE GENERATOR
Aim: To design and study the operation of a Sequence Generator.
Components Required: IC 7495, IC 7486, etc.
Theory:
In order to generate a sequence of length ‘S’, it is necessary to use at least ‘N’ number of
Flip-flops, in order to satisfy the condition 𝑆 ≤ 2𝑁 − 1.
The given sequence length S = 15
Therefore, N = 4
Note: There is no guarantee that the given sequence can be generated by 4 flip-flops. If the sequence is
not realizable by 4 flip-flops, we need to use 5 flip-flops, and so on.
Procedure:
1. Truth table is constructed for the given sequence, and Karnaugh maps are drawn in order to
obtain a simplified Boolean expression for the circuit.
2. Connections are made as shown in the circuit diagram.
3. Mode M is set to LOW (0), and clock pulses are fed through Clk 1 (pin 9).
4. Clock pulses are applied at CLK 1 and the output values are noted, and checked against the
expected values from the truth table.
5. The functioning of the circuit as a sequence generator is verified.
Conclusion: The operation of a Sequence Generator is verified with the Truth Table.

SIMULATION PROGRAM
Procedure:
Create a New Project
To create a new project: Create a new ISE project which will target the FPGA device.
1. Select File>New Project... The New Project Wizard appears.
2. Type tutorial in the Project Name field.
3. Enter or browse to a location (directory path) for the new project. A tutorial subdirectory
is created automatically.
4. Verify that HDL is selected from the Top-Level Source Type list.
5. Click Next to move to the device properties page.
6. The device property table is as shown below:
 Product Category: All
 Family: Spartan3
 Device: XC3S200
 Package: FT256
 Speed Grade: -4
 Top-Level Source Type: HDL
 Synthesis Tool: XST (VHDL/Verilog)
 Simulator: ISE Simulator (VHDL/Verilog)
 Preferred Language: Verilog (or VHDL)
 Verify that Enable Enhanced Design Summary is selected.
7. Click Next to proceed to the Create New Source window in the New Project Wizard. At
the end of the next section, your new project will be complete.
8. Leave the default values in the remaining fields.
9. When the table is complete, your project properties will look like the following:

Create an HDL Source

In this section, you will create the top-level HDL file for your design. Determine the language that
you wish to use for the tutorial. Then, continue either to the “Creating a VHDL Source” section
below, or skip to the “Creating a Verilog Source” section.
Creating a VHDL Source

Create a VHDL source file for the project as follows:
1. Click the New Source button in the New Project Wizard.
2. Select VHDL Module as the source type.
3. Type in the file name.
4. Verify that the Add to project checkbox is selected.
5. Click Next.
6. Declare the ports for the counter design by filling in the port information as shown below:

7. Click Next, then Finish in the New Source Wizard - Summary dialog box to complete the
new source file template.
8. Click Next, then Next, then Finish.
The source file containing the entity/architecture pair displays in the Workspace, and the example
displays in the Source tab, as shown above.

Checking the Syntax of the New example Module

When the source files are complete, check the syntax of the design to find errors and typos.
1. Verify that Implementation is selected from the drop-down list in the Sources window.
2. Select the example design source in the Sources window to display the related processes in the
Processes window
3. Click the “+” next to the Synthesize-XST process to expand the process group.
4. Double-click the Check Syntax process.

Note: You must correct any errors found in your source files. You can check for errors in theConsole tab of the Transcript
window. If you continue without valid syntax, you will not be able to simulate or synthesize your design.
Design Simulation
Verifying Functionality using Behavioral Simulation
Create a test bench waveform containing input stimulus you can use to verify the functionality of the example
module. The test bench waveform is a graphical view of a test bench.
Create the test bench waveform as follows:
1. Select the example HDL file in the Sources window.

2. Create a new test bench source by selecting Project New Source.
3. In the New Source Wizard, select Test Bench Waveform as the source type, and type example
tbw in the File Name field.
4. Click Next.
5. The Associated Source page shows that you are associating the test bench waveform with the
source file example. Click Next.
6. The Summary page shows that the source will be added to the project, and it displays the source
directory, type, and name. Click Finish.
7. Click Finish to complete the timing initialization.
8. Specify the inputs and initialize the clock input to combinational clock.
9. Save the waveform.
10. Double click on simulate Behavioral Model.

Simulating Design Functionality
Verify that the design functions as you expect by performing behavior simulation as follows:
1. Verify that Behavioral Simulation and example_tbw are selected in the Sources
window.
2. In the Processes tab, click the “+” to expand the Xilinx ISE Simulator process and double-
click the Simulate Behavioral Model process.
3. The ISE Simulator opens and runs the simulation to the end of the test bench.
4. To view your simulation results, select the Simulation tab and zoom in on the
transitions.

SIMULATION OF FULL ADDER USING HDL PROGRAM IN XILINX
Aim: To Simulate Full Adder using HDL program
Program Code:
VHDL File Name: FullAdder.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FullAdder is
Port ( a_in, b_in, c_in : in STD_LOGIC;
sum, carry : out STD_LOGIC);
end FullAdder;
architecture Data_Flow of FullAdder is
begin
sum<= a_inxorb_inxorc_in;
carry<= (a_in and b_in) or (b_in and c_in)or (a_in and c_in);
end Data_Flow;
Conclusion: The Simulation of Full Adder using HDL program is performed.

SIMULATION OF MOD 8 UP/DOWN COUNTER USING HDL PROGRAM IN XILINX
Aim: To Simulate Mod 8 up-down counter using HDL program
Program Code:
Entity counter is
Port(clk, clr: in std_logic;
q:out std_logic_vector(3 downto 0)
updown:instd_logic);
End counter;
Architecture count8 of counter is
Signal count: std_logic_vector(3 downto 0)):= "0000";
Begin
Process(clk,clr)
Begin
If clr=’1’ then
Count<= ‘’0000’;
Elsif(clk’event and clk=’1’ ) then
If(( updown = '1') then
Count<= count+1;
Else
Count<= count-1;
End if;
End if;
End process;
Q<= count;
End count8;
Conclusion: The Simulation of Mod 8 up-down counter using HDL program is performed.

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VISVESVARAYA TECHNOLOGICAL UNIVERSITY

K S SCHOOL OF ENGINEERING AND MANAGEMENT

Department of Electronics and Communication Engg.

Mr. Manu D K Associate Professor

a. Verify DeMorgan’s Theorem for two variables.

Design and implement

3 Design and Implement 4-bit Parallel Adder/ Subtractor using IC 7483.

a. Design and Implementation of 4-bit Magnitude Comparator using IC 7485.

a. Realize a Boolean expression using decoder IC74139.

7 Realize Master-Slave JK and D Flip-Flop using NAND Gates.

Realize the following shift registers using IC 7495

Realize (i) Mod-8 Asynchronous Counter using IC7490.

a. Design Pseudo Random Sequence generator using 7495.

a. The sum-of product and product-of-sum expressions using universal gates.

Dept of ECE, KSSEM Page 1

1. IMPLEMENTATION OF DEMORGAN’S THEOREM AND SOP/POS EXPRESSIONS ......................................... 5

2. FULL ADDER AND FULL SUBTRACTOR ......................................................................................................... 9

3. PARALLEL ADDER AND SUBTRACTOR USING 7483.................................................................................... 13

4. FOUR BIT MAGNITUDECOMPARATOR USING IC 7485 .............................................................................. 17

5. MUX/DEMUX FOR ARITHMETIC CIRCUITS................................................................................................. 19

7. STUDY OF FLIP-FLOPS ................................................................................................................................ 30

8. STUDY OF SHIFT REGISTERS....................................................................................................................... 34

9. STUDY OF COUNTERS USING IC 7490 ........................................................................................................ 34

10.SEQUENCE GENERATOR ............................................................................................................................ 38

Dept of ECE, KSSEM Page 2

2-Input OR Gate - 7432LS 2-Input NAND Gate - 7400LS

2-Input NOR Gate - 7402LS 2-Input EX-OR Gate - 7486LS

3-Input NAND Gate - 7410LS 4-Input NAND Gate - 7420LS

Dept of ECE, KSSEM Page 3

Given Problem: ̅̅̅̅̅ ̅+𝑩

Dept of ECE, KSSEM Page 4

Experiment No. 1 Date: ___/___/_____

IMPLEMENTATION OF DEMORGAN’S THEOREM AND SOP/POS EXPRESSIONS

(a) Demorgan’s Theorem for 2 variables

Theory: Augustus De Morgan, a 19th-century British mathematician developed a pair of important

Dept of ECE, KSSEM Page 5

B) The sum-of product and product-of-sum expressions using universal gates.

Simplification using K-map:

ii)Implementation Using NAND gates iii) Implementation Using NOR Gates

Dept of ECE, KSSEM Page 6

2) Product of Sum (POS): Y= F(A,B,C,D) = П(0,1,2,3,4,6,8,10,12,14)

Simplification using K-map:

Dept of ECE, KSSEM Page 7

A B Cn-1 Sum Carry

Full Adder Logic Circuit Using Basic Gates

Full Adder Using NAND Gates

Dept of ECE, KSSEM Page 8

Experiment No. 2 Date: ___/___/_____

FULL ADDER AND FULL SUBTRACTOR

Aim: To design and Implement

Components Required: IC 7408, IC 7432, IC 7400, IC 7486, and IC 7404.

Dept of ECE, KSSEM Page 9

A B Cn-1 Difference Borrow

Full Subtractor Logic Circuit Using Basic Gates

Full Subtractor Using NAND Gates

Dept of ECE, KSSEM Page 10

Dept of ECE, KSSEM Page 11

IC 7483 Pin Diagram

A. IC 7483 as a Full Adder

Dept of ECE, KSSEM Page 12

Experiment No. 3 Date: ___/___/_____

PARALLEL ADDER AND SUBTRACTOR USING 7483

Components Required: IC 7483, IC 7404, etc.

Experiment No. 1 Date: _/_/_____

Experiment No. 2 Date: _/_/_____

Experiment No. 3 Date: _/_/_____

Experiment No. 4 Date: _/_/_____

Experiment No. 5 Date: _/_/_____

Experiment No. 6 Date: _/_/_____

Experiment No. 7 Date: _/_/_____

Experiment No. 8 Date: _/_/_____

Experiment No. 9 Date: _/_/_____