2015.06 Router ICV Incremental Training

IC Compiler K-2015.
06 Incremental
Training
Router and IC Validator Projects
Router Projects:
define_routing_rule Support for the

Discrete Metal Widths Rule
Overview and Benefits
• Overview
– The define_routing_rule –cuts command generates vias according to
the nondefault width rules; however, it does not consider the discrete metal
widths rule
– When via enclosures violate the discrete metal widths rule, Zroute issues a
ZRT-088 error message
• Benefits
– Filters out vias whose upper or lower enclosure does not satisfy the
discrete metal widths rule
– If there are no vias left, the tool issues an RT-566 warning message
© 2015 Synopsys, Inc. 3

Usage
• The tool uses the via enclosure width to determine if a via satisfies the
legal width based on the discrete metal widths rule
– Nondefault vias specified with the -cuts option:

define_routing_rule ruleName \
-cuts {{V1 {Vsm 1}} {V2 {Vsm 1}} V3 {Vsm 1}}}
– Legal metal width rule:
Layer "MetalX" {
xLegal WidthTblSize = N
xLegalWidthTbl = (WX1, WX2, …, WXN)
yLegalWIdthTblSize = M
yLegalWidthTbl = (WY1, WY2, …, WYM)

define_routing_rule Enhancement for
Advanced Processes
Overview
• This project adds support for the following design rules when defining
nondefault vias with the -via_cuts or -cuts options:
– Fat metal contact
– Discrete metal widths
– Legal dimensions
• Enhanced nondefault via filtering

– The define_routing_rule command filters“bad” contact codes
– The router filters “bad” contact codes before routing each partition
• Reduces DRC violations caused by nondefault vias that conflict

with design rules
• Prints warning messages for “bad” contact codes

Fat Metal Contact Rule Checks
• If either the nondefault lower or upper metal width is fat, Zroute uses the
nondefault metal widths to check for fat contacts
• If you specify contact codes that conflict with the fat metal contact rules,
the tool issues RT-567 warning messages
Warning: {VIA02U 2X1 NR} does not satisfy fat metal
contact rule (RT-567)
• If all the nondefault vias for a specific via layer violate the
fat metal contact rules, the tool issues an error message
and the define_routing_rule command fails

Additional Checks
• Supports discrete metal width and legal dimension rules
• Enhanced nondefault via filtering algorithm to filter out “bad” nondefault

contacts

UI
• No new options added
• Both enhancements are on-by-default on starting this release

verify_lvs Support for Real Child Blockages in
the FRAM View
• Provide the capability to check for shorts between top-level nets and
child cell metal and via blockages in the FRAM view
• The -check_child_blockages option is added to the verify_lvs

command to check for shorts in child blockages

Flow
FRAM View
verify_lvs –check_child_blockages
Reports the shorts between real child cell

blockages and top-level nets

Usage
• A cell instance is checked only when its reference cell

has a FRAM view
• The shorts are reported only between the same metal
or via layer
• The geometries are checked only on real metal or via
layers

UI
• Added new –check_child_blockages option to the

verify_lvs command
verify_lvs –check_child_blockages

Shield Threshold Per Layer
Overview
• In previous releases, Zroute shielded wires that are longer than 4 times
the pitch of the layer. Wires that are shorter than this default threshold
were skipped for shielding
• A new Zroute common option,
-min_shield_length_by_layer_name, is provided to specify the layer-
specific length threshold for wires to be shielded
• The report_zrt_shield command is enhanced to exclude wire
segments that are shorter than the length threshold from the shield ratio
calculation

Benefits
• You have more control, on a per-layer basis, over the trade-off

between more shielding wires and more routing resources
• Reporting with the enhanced shield ratio calculation is more accurate;
it reflects the actual effectiveness of the shielding function

Usage: New Option
• Added new Zroute common option

set_route_zrt_common_options
-min_shield_length_by_layer_name
{{layer_name length_value}…}
• The default length threshold for each layer is 4 times the pitch of
the layer
• To reset back to the default

set_route_zrt_common_options
-min_shield_length_by_layer_name
{{layer_name -1}…}

Rule-based track support in
create_track
Overview
• You can now create and report tracks that are restricted to a specific
route width, or to routes created by nondefault routing (NDR) rules of a
specific width
• The create_track command has new options and the
report_track command is enhanced to report the new attributes of
tracks
• The special tracks include:
o non-reserved track with associated width: If the net is routed on this type of
track, the width of the wire is promoted to the specified track width (can be
ordinary or NDR route)
o reserved track with associated width: Can be used only by NDR nets; the NDR
width must match the width associated with the track.

UI Change
• Two new options added to create_track command:
-width and -reserved_for_width
• -width width option restricts track to routes of the specified width
• -reserved_for_width true option reserves the tracks for routes
created by non-default routing rules (used only with the –width
option)
• There is no change to the syntax of report_track, but it now reports
the width and reserved status if they exist on the tracks
• Two new attributes added to track objects: width and
reserved_for_width; you can display them using
list_attributes -class track -application

IC Validator Projects:
Track-Based Signoff Metal Fill Insertion

• The track-based metal fill insertion flow uses technology file attributes
and rules to create fill shapes aligned to tracks
• The track-based metal fill flow has the following benefits as compared
to the pattern-based metal fill flow:
– Achieves higher metal density
– Has better density control
– Provides well-balanced color distribution for double-patterning layers

Flow
Technology Routed Design

file
IC Validator signoff_metal_fill
parameter file –track_fill
auto / user-defined
Metal Fill Data

Usage – New Options
• Required option that enables track-based metal fill insertion

-track_fill
– This option enables sparse track-based metal fill insertion
(skips one track between signal and fill shapes)
• Optional options to modify the default track-fill behavior

– Enable dense track-based metal fill insertion
(does not skip tracks between signal and fill shapes)
-fill_all_tracks
– Enable colored fill for double-patterning layers
-output_colored_fill

Usage – New Options
– Report density results

-report_density on | off | prefix
Default: off
– Maintain proper density gradient across density windows
-max_density_threshold {{layer threshold}}
Default: Values come from technology file
– Prevent fill creation
-create_exclude_layers
Default: off
– Customize parameters for the track fill flow
-track_fill_runset_include_file file_path
Default: Flow uses automatically generated parameter file

Using an IC Validator Parameter File
• What is a parameter file?

– Contains IC Validator parameters used to create metal fill
• To generate and modify a parameter file,

– Run signoff_metal_fill -track_fill, which generates a parameter
file based on the technology file
– Find the user_defined_parms.rh file in the run directory (default run
directory is signoff_fill_run) and modify if needed
– Use one of the following methods to use the modified parameter file in
subsequent runs
– Use the –track_fill_runset_include_file option
– Use the –user_defined_options option

Enabling Foundry-Specific Rules
• To enable foundry-specific rules, set the appropriate variable
– TSMC 20nm/16nm: default, no variable needed
– TSMC 10nm: TRACK_FILL_FOUNDARY_TSMC_10NM
– Samsung 14nm: TRACK_FILL_FOUNDARY_SAMSUNG
– Samsung 10nm: TRACK_FILL_FOUNDARY_SAMSUNG_10NM
• Use one of the following methods to set the variable

– Add the following statement to the parameter file
#define TRACK_FILL_FOUNDARY_foundry
– Set the variable with the –user_defined_options option
signoff_metal_fill \
-user_defined_options {-D TRACK_FILL_FOUNDARY_foundry}

Timing-Driven Track-Based Fill Insertion
You can use the following timing-driven options with the -track_fill
option:
-timing_preserve_setup_slack_threshold
-timing_preserve_hold_slack_threshould
-timing_preserve_nets
-space_to_critical_nets
-fill_over_critical_nets
-space_to_clock_nets
-space_to_critical_nets_adjacent_layers

Example
signoff_metal_fill –track_fill \
–timing_preserve_nets {$list_of_critical_nets} \
–timing_preserve_setup_slack_threshold 0.01 \
–timing_preserve_hold_slack_threshold 0.007 \
–space_to_critical_nets{m2 4x m3 4x m4 4x m5 4x m6 \
5x m7 5x m8 5x} \
–space_to_clock_nets{m2 5x m3 5x m4 5x m5 5x m6 5x \
m7 5x m8 5x}
–space_to_critical_nets_adjacent_layers{m2 3x m3 3x \
m4 3x m5 3x m6 3x m7 4x m8 4x}
–apply_nondefault_rules true

Fixing Density Errors
• When you perform timing-driven metal fill insertion, minimum density

errors can occur because metal fill is not inserted around critical nets
• To automatically fix these errors during metal fill insertion, use the
-fix_density_errors option
• You can use the -fix_density_errors option with the
–track_fill option

Options that can be used along with
Track-Based Metal Fill
–append
–eco
–auto_eco
–select_layers
–bounding_boxes
–excluded_bounding_boxes
-apply_nondefault_rules

Command and UI
• New options added to the signoff_metal_fill command:

-track_fill
-fill_all_tracks
-output_colored_fill
-report_density on | off | prefix
-track_fill_runset_include_file file_path
-create_exclude_layers
-max_density_threshold {{layer threshold}}

Show Error Environment For Mixed
Milkyway/GDS Flow
Milkyway/GDS Flow
Benefits
• In-Design signoff_drc runs with IC Validator can be run with mixed

GDS flows, where CEL and FRAM views are replaced with GDS
source
• The IC Compiler error browser can overlay the polygon data from the
error view over the CEL view
• You can now see the data involved in the DRC violation

Milkyway/GDS Flow
Usage
• Run the signoff_drc command with the following option:

-show_stream_error_environment true | false (default)
• View the violations using the error browser

Milkyway/GDS Flow
Example
• Run the signoff_drc command with the appropriate

user-defined options and the feature option:
icc_shell> signoff_drc \
–show_stream_error_environment true \
–user_defined_options {-ml file_with_mw_options} \
–read_cel_view
– file_with_mw_options is the file with the IC Validator

merge_milkway_library_options() function that
enables the mixed Milkyway/GDS capability
– For more information, see the IC Validator Reference Manual

Milkyway/GDS Flow
View the Violations in the Error Browser
Error Browser … Ctrl+Shift+E

Milkyway/GDS Flow
Select “Signoff DRC” and “Show stream error environment”

Milkyway/GDS Flow - On

Milkyway/GDS Flow - Off

Milkyway/GDS Flow
Summary
• One easy option setting with a corresponding GUI

setup
• The IC Compiler error browser overlays the
polygon data from the error cell over the CEL
view automatically
• You can now see the data involved in the DRC
violation

Behavior Change for Reading Child Cells
During Signoff DRC Checking and Fixing
Overview
• When reading the FRAM view of a macro, signoff_drc processes
large routing blockages that often cover the entire macro, except pins,
as real metal, which could result in reporting false violations around
the macro boundaries
• If these false violations are incorrectly targeted for fixing by
signoff_autofix_drc, it can cause a bad fixing rate and long
runtime
• In this release, the following two new options for signoff_drc and
signoff_autofix_drc enable reading of child cell views with
consistency and flexibility
-ignore_blockages_in_cells true | false
-read_cel_views {list_of_cells}

Benefits
• You can control whether to ignore the blockages in the FRAM views
of macro cells by using the -ignore_blockages_in_cells option
– If blockages in the FRAM view of macro cells are ignored
– signoff_drc will not report false violations around the boundaries of the macros
– DRC fixing with signoff_autofix_drc will not be adversely impacted by the
false violations
• You can use the CEL view only for specific cells by using the
-read_cel_views option
– In previous releases, you had to select either the FRAM or CEL view
for all cells
– The existing signoff_drc -read_cel_view option and
signoff_autofix_drc -read_fram_view_only option
will be removed in a future release

Child Cell Views Based on Option Settings
Set Options Child Child cell view used
cell
-ignore_blockages_ -read_cel_views type signoff_drc signoff_autofix_drc
in_cells
FRAM FRAM
true off Macro
(Pins only) (Pins only)
(default) (default)
Std cell CEL CEL
Macro FRAM FRAM
false off
Std cell FRAM FRAM
Macro CEL CEL
true or false { * }
Std cell CEL CEL
Macro
CEL CEL
“mc*”
true { mc* } All other FRAM FRAM
macros (Pins only) (Pins only)
Std cell CEL CEL
If the CEL view of a cell is not found, the command reads the FRAM view instead.
If the FRAM view of a cell is not found, the cell is ignored during checking.
User Interface
• signoff_drc
[-ignore_blockages_in_cells true | false]
[-read_cel_views list_of_cells]
• signoff_autofix_drc
[-ignore_blockages_in_cells true | false]
[-read_cel_views list_of_cells]

User Interface
Options to Be Removed
• The following options are supported in this

release, but will be removed in a future release:
signoff_drc -read_cel_view
signoff_autofix_drc -read_fram_view_only

User Interface
Examples
Read the CEL view of standard cells and the pins from the FRAM view of all other cells.
> signoff_drc
Read the FRAM view of all child cells. This was the default in previous releases.
> signoff_drc -ignore_blockages_in_cells false
Read the CEL view of all child cells. If the CEL view cannot be found, the command
reads the FRAM view instead.
> signoff_drc -read_cel_views {*}
Read the CEL view of standard cells and the macro cells with master names that match
the pattern “mc*”, and the pins from the FRAM view of all other cells.
> signoff_drc -ignore_blockages_in_cells true -read_cel_views {mc*}

Isolated Via Fixing Flow
Problem Description
• Isolated vias create a problem for foundry processes

• Previous flows required the use of separate scripts and
runsets for checking and fixing
• Users want a fully automated checking and fixing flow

• Uses existing technology to create the best solution

– DRC prevention based on technology file rules
– Considers double-patterning requirements
– Honors nondefault spacing rules
• Uses a single command from within the IC Compiler In-Design system
– No more separate scripts and runsets
– Everything is handled automatically under the hood
– Enhances usability
• Provides a correct-by-construction flow

UI
signoff_fix_isolated_via
-check_only
– Specify this option to use the signoff_fix_isolated_via command only to
check for isolated vias in the design
-save_view
– Specify this option to save the isolated via fixes to the design automatically at the
end of the flow instead of using the save_mw_cel command later
– If you use the -update_track_fill option, all changes are saved in the FILL
view regardless of whether you specify -save_view
-error_view error_view_name
– Specifies the name of the generated error view
– Default: <current_cell_name>_isodrc.err

UI
Continued
-run_dir directory_path
– Specifies the path of the working directory
– Default: signoff_fix_isolated_via_run in the current working directory
-user_defined_options {list_of_IC_Validator_command_line_options}
– Specifies a string of IC Validator command-line options to be used during the run
– Default: {}
-avoid_net_types {list_of_types}
– Specifies the types of nets to exclude from isolated via fixing
– Valid values are clock, pg, none
– Default: {clock pg}

UI
Continued
-update_track_fill
– Reads and updates existing track fill
-track_fill_runset_include_file file_name
– Specifies the name of the track fill runset include file used during track-fill
insertion
– Default: off
set_physical_signoff_options
-isolated_via_max_range { {via_layer distance} … }
– Specifies the via checking range for each via layer

Default Flow
The signoff_fix_isolated_via command performs the following tasks:
1. Identifies lonely vias and regions of interest based on the specified

isolated via checking range
2. Creates track fill shapes in the regions of interest
3. Finds suitable fixing via locations with the following priority:

i. Between existing minWidth signal and fill shapes
• minCut via is instantiated on the minWidth shape
ii. Between extended minWidth signal and fill shapes
• minCut via is instantiated on the minWidth shape
iii. Between wide signal and fill shapes
• Number of vias and contact code for contact array is chosen based on
the upper and lower metal width

Priority 1
Existing minWidth Signal Net
Identified isolated via

Priority 2
Extended minWidth Signal Net

Priority 3
Wide Metal Shape

Incremental Flow Using -update_track_fill
The signoff_fix_isolated_via command performs the following tasks:
1. Reads the existing metal and via fill from the FILL view
2. Identifies lonely vias based on the specified isolated via checking

range
3. Uses existing metal to eliminate isolated vias; selects the fixing via
locations with the following priority:
– Between existing fill shapes
– Track fill remains as is
– New via is inserted between the lower and upper metal fill
– Between minWidth signal and fill shapes
– Track is cut to ensure that it does not connect to a long fill piece

Priority 1
Existing Fill Shapes
New via inserted between upper

and lower track fill shapes

Priority 2
Existing minWidth Signal Net
New via inserted between upper

track fill shape and lower signal

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IC Compiler K-2015.

define_routing_rule Support for the

© 2015 Synopsys, Inc. 3

– Nondefault vias specified with the -cuts option:

© 2015 Synopsys, Inc. 4

• Enhanced nondefault via filtering

• Reduces DRC violations caused by nondefault vias that conflict

• Prints warning messages for “bad” contact codes

© 2015 Synopsys, Inc. 7

• Enhanced nondefault via filtering algorithm to filter out “bad” nondefault

© 2015 Synopsys, Inc. 8

• Both enhancements are on-by-default on starting this release

© 2015 Synopsys, Inc. 9

• The -check_child_blockages option is added to the verify_lvs

© 2015 Synopsys, Inc. 11

Reports the shorts between real child cell

© 2015 Synopsys, Inc. 12

• A cell instance is checked only when its reference cell

© 2015 Synopsys, Inc. 13

• Added new –check_child_blockages option to the

© 2015 Synopsys, Inc. 14

© 2015 Synopsys, Inc. 16

• You have more control, on a per-layer basis, over the trade-off

© 2015 Synopsys, Inc. 17

• Added new Zroute common option

• To reset back to the default

© 2015 Synopsys, Inc. 18

© 2015 Synopsys, Inc. 20

© 2015 Synopsys, Inc. 21

Track-Based Signoff Metal Fill Insertion

© 2015 Synopsys, Inc. 23

Technology Routed Design

Metal Fill Data

© 2015 Synopsys, Inc. 24

• Required option that enables track-based metal fill insertion

• Optional options to modify the default track-fill behavior

© 2015 Synopsys, Inc. 25

– Report density results

© 2015 Synopsys, Inc. 26

• What is a parameter file?

• To generate and modify a parameter file,

© 2015 Synopsys, Inc. 27

• Use one of the following methods to set the variable

© 2015 Synopsys, Inc. 28

© 2015 Synopsys, Inc. 29

© 2015 Synopsys, Inc. 30

• When you perform timing-driven metal fill insertion, minimum density

© 2015 Synopsys, Inc. 31

© 2015 Synopsys, Inc. 32

• New options added to the signoff_metal_fill command:

© 2015 Synopsys, Inc. 33

• In-Design signoff_drc runs with IC Validator can be run with mixed

© 2015 Synopsys, Inc. 35

• Run the signoff_drc command with the following option:

• View the violations using the error browser

© 2015 Synopsys, Inc. 36

• Run the signoff_drc command with the appropriate

– file_with_mw_options is the file with the IC Validator

© 2015 Synopsys, Inc. 37

Error Browser … Ctrl+Shift+E

© 2015 Synopsys, Inc. 38

© 2015 Synopsys, Inc. 39

© 2015 Synopsys, Inc. 40

© 2015 Synopsys, Inc. 41