IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO.
3, MARCH 2018 1931
A Carrier-Based Modulation Scheme to
Reduce the Third Harmonic Component of
Common-Mode Voltage in a Three-Phase
Inverter Under High DC Voltage Utilization
Jin Huang , Member, IEEE, Quanhui Liu, Xulong Wang, and Kaicheng Li, Member, IEEE
Abstract—High dc voltage utilization is one of the im-
portant requirements in a three-phase inverter. Under some
carrier-based pulse width modulations (PWMs), the dc volt-
age utilization can reach the same maximum as that under
the space vector modulation. But the third harmonic com-
ponent of common-mode voltage (CMV) will be increased
markedly while using these carrier-based PWMs in invert-
ers. To improve the situation, this paper proposes that a
midpoint-fluctuation carrier (MFC) scheme should be used
in the three-phase inverter. The MFC is formed by adding a
midpoint-fluctuation signal on the standard symmetrical tri-
angular carrier. By analyzing the linear modulation region of
the midpoint-fluctuation signals, a minimum fluctuant sig-
nal in the linear modulation region is designed in the paper.
Compared with the use of other conventional schemes in
the three-phase inverter, the use of minimum MFC scheme
has higher fundamental amplitude in the output line voltage
and smaller magnitude of the third harmonic in the CMV. The
feasibility and validity of the MFC are proved by experiment
results in a three-phase inverter.
Index Terms—Carrier-based modulation, common-mode
voltage (CMV), dc voltage utilization, linear modulation,
pulse width modulation (PWM).
I. INTRODUCTION
HE input dc voltage utilization is an important figure of
T merit in three-phase inverters. If the dc voltage is fully
utilized in inverters, the restrictions on the power supplies can
be relaxed in some degree.
The maximum dc voltage utilization is closely related to the
maximum modulation index in the linear modulation region. The
Manuscript received February 18, 2017; revised May 25, 2017; ac-
cepted August 18, 2017. Date of publication August 29, 2017; date of
current version December 15, 2017. This work was supported by the
National Natural Science Foundation of China under Grant 51277080.
(Corresponding author: Jin Huang.)
The authors are with the State Key Laboratory of Advanced Electro-
magnetic Engineering and Technology and the School of Electrical and
Electronic Engineering, Huazhong University of Science and Technology,
Wuhan 430074, China (e-mail: huangjin.mail@163.com; 1205110388@
qq.com; 495683498@qq.com; likaicheng@hust.edu.cn).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2017.2745439
0278-0046 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
modulation index Ma can be determined by Ma = 2Vpm /Vdc ,
where Vpm is the amplitude of phase voltage and Vdc is the input
dc voltage in an inverter. Under the sinusoidal pulse width mod-
ulation (SPWM), which is a conventional carrier-based modu-
lation, the linear maximum Ma can only reach 1 in three-phase
inverters. Under the space vector modulation (SVM), the lin-
ear maximum Ma can reach 1.1547, which is the theoretical
maximum of linear modulation in three-phase inverters.
In view of the equivalency between SVM and SPWM [1], [2],
the same high linear modulation index can be achieved by adding
a zero-sequence signal to the reference sinusoid (AZSTRS) in
the carrier-based modulation. The well-known zero-sequence
signals are the third harmonic sinusoid [3]–[5], the max–min
average signal [1], [6], [7], the discontinuous PWM (DPWM)
maximum signal [1], [6], [8], the DPWM minimum signal [1],
[6], [8], and other DPWM signals [7], [9], [10]. Because DPWM
maximum and DPWM minimum signals are asymmetric in the
positive voltage or negative voltage, the top switches and bot-
tom switches of three legs will be unbalanced in practice by
using these signals and thus the reliability of switches will be
degraded. The use of DPWM signals will also lead to the higher
total harmonic distortion (THD) [11]–[13]. The third harmonic
sinusoid and the max–min average signal are the most com-
monly used signals in practice. The amplitude of the third har-
monic sinusoid is 1/6 of the reference sinusoidal amplitude
(abbreviated as “the 1/6 third harmonic sinusoid”) [3] or 1/4 of
the reference sinusoidal amplitude (abbreviated as “the 1/4 third
harmonic sinusoid”) [4], [5].
In the above AZSTRS schemes, the added zero-sequence
signals will increase the common-mode voltage (CMV) of the
three-phase inverter. Because the frequencies of these added sig-
nals are three times of the reference sinusoid frequency f0 , then
the third harmonic component in the CMV will be significantly
increased. This drawback also appears in the standard SVM
process. The high CMV can produce the large common-mode
current (CMC) in three-phase inverters. The large CMC will
lead to electromagnetic interference (EMI) and other hazards
[14]–[17]. The low-frequency CMV may cause the low-
frequency mechanical vibration and bring about the risk in the
system [18]–[22]. Nowadays, the frequency range of the conduc-
tive EMI, which is 150 kHz–30 MHz in the traditional industry,
has been extended to low frequency as hundreds of Hertz or even
30 Hz in some electromagnetic compatibility standards [23].
1932 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 3, MARCH 2018

When the reference sinusoidal amplitude exceeds ±1 (i.e.,

Ma > 1) in the inverter under high dc voltage utilization, a spe-
cific zero-sequence signal Vzs (t) can be added into the reference
signal to ensures its peak between −1 and +1. In this case, the
SPWM wave is generated by

1, [Vref (t) + Vzs (t)] ≥ Vtri (t)
VPW M (t) = (2)
0, [Vref (t) + Vzs (t)] < Vtri (t).

This is the AZSTRS method. Some zero-sequence signals

have been found in previous studies. But it is not easy to find
more zero-sequence signals for linear SPWM.
Fig. 1. Three-phase reference sinusoids.
Obviously, (2) is equivalent to

1, Vref (t) ≥ [Vtri (t) − Vzs (t)]
Some CMV reduction PWM (CMVRPWM) strategies VPW M (t) =
[24]–[30] are put forward to reduce the CMV in three-phase 0, Vref (t) < [Vtri (t) − Vzs (t)]
inverters. Some strategies aim to reduce or even eliminate the 
third harmonic component of CMV [31], [32]. But the CMV is 1, Vref (t) ≥ [Vtri (t) + Vcn (t)]
= (3)
reduced at the cost of sacrificing high dc voltage utilization in 0, Vref (t) < [Vtri (t) + Vcn (t)]
these strategies. In these strategies, the linear maximum Ma is
not greater than 1. Among them, the lowest is only 0.66 [24]. where the carrier’s midpoint Vcn (t) = −Vzs (t). This is the
Some optimized CMVRPWM strategies based on nonlinear pro- carrier-based modulation with MFC presented in this paper. In
gramming models can reduce the CMV while guaranteeing the the carrier-based modulation with MFC, the modulated signal is
maximum modulation index Ma = 1.1547 [33]. However, the still a sine-wave and the triangular carrier is fluctuated according
optimized CMVRPWM strategy has a very complex algorithm to the carrier’s midpoint Vcn (t). In order to obtain more suitable
and a certain difficulty in implementation. carrier’s midpoint functions, the linear modulation region with
This paper presents a midpoint-fluctuation carrier (MFC) MFC should be found.
scheme. In this scheme, the carrier midpoint (the average value
in one period) of the triangular carrier is fluctuated according
B. Linear Modulation Region
to a function Vcn (t). Vcn (t) can be obtained simply and easily
in the linear modulation region. Through optimization, a To find linear modulation region with MFC, the fluctuation
minimum midpoint-fluctuation function Vcn (t) is found in the range of three-phase reference voltages should be clear. As
linear modulation region. Under the minimum MFC scheme, shown in Fig. 1, the maximum reference voltage Vref ,m ax (t) of
the dc voltage utilization of the inverter will be the highest three-phase sinusoids in one period t ∈ [1/(12f0 ), 13/(12f0 )] and
and the third harmonic component of CMV will be the lowest. the minimum reference Vref ,m in (t) of three-phase sinusoids in
In Section II, the MFC modulation theory and the linear one period t∈[−1/(12f0 ), 11/(12f0 )] can be derived as follows:
modulation region are derived. Section III presents the design
of the minimum MFC. The implementation of the minimum Vref ,m ax (t)
MFC modulation and some experimental results are revealed ⎧
⎨VAref (t) = Ma sin(2πf0 t), t ∈ [ 12f , 12f
1 5
in Section IV. Finally, the conclusion is given in Section V. ⎪ 0 0
]
= VBref (t) = Ma sin(2πf0 t − 2π/3), t ∈ [ 12f 0 , 12f 0 ] (4)
5 9
⎪
⎩V
Cref (t) = Ma sin(2πf0 t + 2π/3), t ∈ [ 12f 0 , 12f 0 ]
9 13
II. MIDPOINT-FLUCTUANT CARRIER MODULATION
A. Modulation Process Vref ,m in (t)
⎧
⎨VBref (t) = Ma sin(2πf0 t − 2π/3), t ∈ [− 12f 0 , 4f 0 ]
1 1
In a three-phase inverter, the conventional SPWM wave ⎪
VPW M (t) is generated by comparing the reference sinusoid = VCref (t) = Ma sin(2πf0 t + 2π/3), t ∈ [ 4f1 0 , 12f
7
] (5)
Vref (t) of each phase with a bipolar symmetric triangular car- ⎪
⎩V
0

Aref (t) = Ma sin(2πf0 t), t ∈ [ 12f 0 , 12f 0 ].

7 11
rier Vtri (t). In general, Vref (t) is a normalized voltage (the given
voltage is divided by Vdc /2). As shown in Fig. 1, the reference
sinusoids of Phase A, Phase B, and Phase C in the inverter are Thus, the periodic Vref ,m ax (t) and Vref ,m in (t) can expressed
respectively by
∞


VAref (t) = Ma sin(2πf0 t)  k
Vref ,m ax (t) = Ma sin 2πf0 t −
VBref (t) = Ma sin(2πf0 t − 2π/3) 3f0
k =−∞



VCref (t) = Ma sin(2πf0 t + 2π/3). (1) 4k + 1 4k + 5
× u t− −u t− (6)
12f0 12f0
HUANG et al.: CARRIER-BASED MODULATION SCHEME TO REDUCE THE THIRD HARMONIC COMPONENT OF COMMON-MODE VOLTAGE 1933

and
∞


 k+1
Vref ,m in (t) = Ma sin 2πf0 t −
3f0
k =−∞



4k − 1 4k + 3
× u t− −u t− (7)
12f0 12f0

respectively, where u[•] is the unit step function.

To ensure that the three-phase sinusoids are all in the linear
modulation range in the three-phase inverter, Vref ,m ax (t) and
Vref ,m in (t) must be between the positive peak [Vcn (t) + 1] and
negative peak [Vcn (t) − 1] of the triangular carrier at any time.
If the designed Vcn (t) can satisfy
−1 + Vref ,m ax (t) ≤ Vcn (t) ≤ 1 + Vref ,m in (t) (8)
the modulation of the three-phase reference sinusoids with MFC
will be achieved in the linear region.
According to (7) and (8), the result
Vref ,m ax (t)−Vref ,m in (t)
∞
  
 √ k
= 3Ma cos 2πf0 t −
6f0
k =−∞
    
2k − 1 2k + 1
× u t− −u t− (9)
12f0 12f0
can be calculated. Considering (8) and (9), the√requirement of
the linear modulation with MFC is Ma ≤ 2/ 3. This means
that the dc voltage utilization in the three-phase inverter with
MFC modulation can also reach the maximum value in theory.
As the modulation index is different, the linear modulation Fig. 2. Linear modulation range [i.e., V c n (t) falls in shadow region] at
region of Vcn (t) is also different. Fig. 2 shows the linear modu- (a) M a = 1.1547, (b) M a = 1.1, or (c) M a = 1.0.
lation region (shadow region) when Ma is 1.1547, 1.1, or 1.0. It
can be seen from Fig. 2 that, when Ma is maximum, the linear
modulation region of Vcn (t) is minimum. With the decrease of
Ma , the linear modulation region is evidently enlarged. When
Ma ≤ 1, the line Vcn (t) = 0 is also in the linear modulation
region. This means that a conventional bipolar symmetric trian-
gular carrier can be used to achieve a linear PWM process.

C. Equivalent Modulation of Common AZSTRSs in

MFC Scheme
1) 1/6 Third Harmonic Sinusoid: In the AZSTRS with 1/6
third harmonic sinusoid [3], the zero-sequence signal is
Vz s (t) = (Ma /6)sin(6πf0 t). (10)
The 1/6 third harmonic sinusoid can be used equivalently in
the MFC scheme. That is
Vcn (t) = −Vzs (t) = (Ma /6)sin(6πf0 t + π). (11)
Fig. 3 shows the MFC with the 1/6 third harmonic sinusoid
when Ma = 1.1547. From Fig. 3(a), it can be seen that the Vcn (t)
signal defined by (11) is all in the shadow region of Fig. 2(a).
Fig. 3(b) shows that the three-phase reference sinusoids are Fig. 3. MFC with the 1/6 third harmonic sinusoid when M a = 1.1547.
completely overlaid by the carrier, whose midpoint fluctuates (a) V c n (t) in the linear region and (b) three-phase reference sinusoids
in accordance with (11). In this case, the three-phase sinusoid and the MFC.
1934 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 3, MARCH 2018

Fig. 4. MFC with the max–min average signal when M a = 1.1547.

(a) V c n (t) in the linear region and (b) three-phase reference sinusoids
and the MFC. Fig. 5. MFC with the 1/4 third harmonic sinusoid: (a) V c n (t) in the linear
region and (b) the MFCs when M a = 1.1547 and 1.1222.

modulation is linear. However, in this method, the phase of the overlaid by the carrier, whose midpoint fluctuates in accordance
third harmonic sinusoid must be strictly synchronous with the with (13). This means that the three-phase SPWM with the
phase of the reference sinusoid so as to improve the dc voltage max–min average MFC can be modulated linearly. In the actual
utilization. It will cause the difficulty in the actual generation of operation for getting Vcn (t), the instantaneous measurement of
Vcn (t). the maximum value and minimum value is adopted instead of
2) Max–Min Average Signal: In the AZSTRS with a max– the reference maximum value Vref ,m ax (t) and minimum value
min average signal [1], [6], [7], the zero-sequence signal is Vref ,m in (t). Thus, the problem of the phase synchronization need
Vzs (t) = −0.5[Vref ,m ax (t) + Vref ,m in (t)]. (12) not be taken into consideration.
3) 1/4 Third Harmonic Sinusoid: In the AZSTRS with
By measuring the instantaneous maximum value and mini- 1/4 third harmonic sinusoid [4], [5], the zero- sequence
mum value of the three-phase sinusoids, the max–min average signal is
method no longer needs the strict synchronous requirements of
the phase. The method can be used in the MFC equivalently as Vzs (t) = (Ma /4) sin(6πf0 t). (14)
follows: To achieve the equivalent of the AZSTRS with this signal in
Vcn (t) = −Vzs (t) = 0.5[Vref ,m ax (t) + Vref ,m in (t)] the MFC scheme, the carrier’s midpoint function should be
 Vcn (t) = −Vzs (t) = (Ma /4)sin(6πf0 t + π). (15)
Ma 
∞   
= sin 2πf0 t − 2k6f−3 Fig. 5(a) and (b) shows how the carrier’s midpoint fluctu-
2 0
k =−∞
ates with the 1/4 third harmonic sinusoid when Ma = 1.1547

   
4k − 1 4k + 1 and 1.1222. The local detailed subfigure in the left of Fig. 5(a)
× u t− −u t− reveals that the Vcn (t) (solid curve) is outside the linear re-
12f0 12f0

    gion (between the two dotted lines) during some parts of the
2k + 1 4k + 1 time. This is not a linear modulation. Only when the mod-
+ sin 2πf0 t − u t− ulation index is no more than 1.1222, will the Vcn (t) be all
6f0 12f0
 located in the linear modulation region [as shown in the right of
 
4k + 3
− u t− . (13)
12f0
When Ma = 1.1547, the max–min average MFC is shown in
Fig. 4. In Fig. 4(a), the Vcn (t) looks like a triangular. But in fact,
the rise and fall curves are not straight lines. The curve is the
sinusoid of the angle from −π/6 to π/6 and from 5π/6 to 7π/6.
In Fig. 4(b), the three-phase reference sinusoids are completely
Fig. 5(a)]. Under this condition, the modulation with the MFC
of the 1/4 third harmonic sinusoid is the linear SPWM. This
proves that, by adding a 1/4 third harmonic sinusoid either to
the reference sinusoid in the AZSTRS scheme or to the carrier
in the MFC scheme, the theoretical maximum dc voltage utiliza-
tion of the inverter cannot be obtained in the linear modulation
region.
HUANG et al.: CARRIER-BASED MODULATION SCHEME TO REDUCE THE THIRD HARMONIC COMPONENT OF COMMON-MODE VOLTAGE 1935

Fig. 6. Three-phase inverter system.

TABLE I
PARAMETERS OF THE THREE-PHASE INVERTER

Symbol Value Commentary

Vd c 600 V Input dc voltage

Lf 900 μH Output filter inductor
Cf 25 μF Output filter capacitor
fc 5.1 kH Carrier frequency
f0 50 Hz Output power-frequency

Fig. 7. Simulated relationship between M a and V a b 1 [the global curves

(top) and the local curves (bottom)] under (a) the conventional SPWM, or
D. Linearity and THD in Simulations the MFC with the (b) 1/6 third harmonic sinusoid, (c) max–min average
signal, (d) 1/4 third harmonic sinusoid, or (e) minimum fluctuant signal.
Fig. 6 shows a three-phase inverter system. In Fig. 6, the
mid-point of the inverter dc input and the shell of the motor
or load cabinet are connected with the ground as zero poten-
tial. Considering the large range of modulation index, a Y-type
symmetrical three-phase resistive-inductance circuit is used as
load in the simulation. The resistive-inductance circuit of each
phase is composed of a 270-Ω resistor and a 900-μH inductor
connected in series. The inverter system is simulated according
to the parameters as listed in Table I without considering the
switching dead-time.
Through the simulations, the line voltage vab before the Lf Cf
filter is obtained under different modulation schemes. The THD
of vab is calculated by

1 ∞ Fig. 8. Simulated THD of line voltage v a b under (a) the conventional
THD = V 2 × 100% (16)
Vab1 n = 2 abn SPWM, or the MFC with the (b) 1/6 third harmonic sinusoid, (c) max–min
average signal, (d) 1/4 third harmonic sinusoid, or (e) minimum fluctuant
where Vab1 is the amplitude of fundamental component (f0 ) of signal.
vab and Vabn is the amplitude of harmonic component (nf0 ) of
vab .
The relationship between the modulation index and the fun- III. MINIMUM MFC
damental component will reflect the linearity of a modulation In theory, the carrier-based modulation with the added zero-
scheme. Fig. 7 shows how Vab1 changes as Ma changes from sequence signal will increase the CMV of the three-phase in-
0.2 to 1.1547 under different modulation schemes. In Fig. 7, verter. The zero-sequence signals, which are used to improve
the conventional SPWM appears significant nonlinearity when dc voltage utilization of three-phase inverters, are usually the
Ma > 1. Under other carrier-based modulations with the MFC, periodic signals with the frequency of 3f0 . When this signal is
the fundamental component amplitude of line voltage and the added, the third harmonic component of the CMV will be in-
modulation index maintain linearity approximately. But in the creased significantly whether in the AZSTRS scheme or in the
high modulation index segment (the local detailed subfigure as MFC scheme.
shown in the bottom of Fig. 7), the linear curve under the MFC In the linear modulation region of MFC as given in
with the 1/4 thirrd harmonic sinusoid appears a slight bend when Section II-B, various signals can be designed easily for
Ma > 1.1222. The similar result also appears in the THD of line different purposes to be used in three-phase inverters. In order
voltage before the filter (as shown in Fig. 8). to decrease the third harmonic component of the CMV, a
1936 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 3, MARCH 2018

Fig. 10. Simulated magnitude of the frequency 3f0 in the CMV of

the three-phase inverter under the MFC with the (a) 1/6 third harmonic
sinusoid, (b) max–min average signal, (c) 1/4 third harmonic sinusoid, or
(d) minimum fluctuant signal.

Fig. 9. Under the minimum MFC: (a) V c n (t) in the linear region and
(b) the MFCs when M a = 1.1547, 1.1, and 1.0.

minimum fluctuation signal is designed in the linear region.

The description of this signal is as follows:
⎧
⎨Vref ,m ax − 1, Vref ,m ax − 1 > 0
⎪
Vcn (t) = Vref ,m in + 1, Vref ,m in + 1 < 0 (17)
⎪
⎩0, otherwise. Fig. 11. Modulation of the minimum MFC.

Vref ,m ax (t) and Vref ,m in (t) are obtained from the instanta-
neous measurement of the maximum value and minimum value
in the three-phase fundamental voltages. Therefore, there is no
phase synchronization problem in the implementation of MFC
scheme. The midpoint of the carrier fluctuating as (17) is shown
in Fig. 9. It can be seen from Fig. 9(a) that the signal of (17)
is in the linear region and has the smallest fluctuation. When
Ma ≤ 1, Vcn (t) = 0. This means that the midpoint of the car-
rier will not fluctuate and the carrier is a conventional bipolar
symmetric triangular wave.
The minimum MFC has an excellent linearity (as shown in
Fig. 7), low THD (as shown in Fig. 8), and especially the maxi-
mum amplitude of line voltage at the same Ma (as shown in the
bottom subfigure of Fig. 7).
In the three-phase inverter, the CMV can be obtained by
vcm = (va + vb + vc )/3 (18)
where va , vb , and vc are the output voltages of Leg A, Leg B,
and Leg C, respectively. Through the simulation with the same
parameters as discussed in Section II-D, the third harmonic com-
ponents of CMV under different MFC schemes are analyzed. Fig. 12. Generation of the minimum fluctuant signal.
Fig. 10 shows the simulation results. The third harmonic am-
plitude of CMV in the three-phase inverter is markedly lower
under the minimum MFC than that under other MFC. IV. IMPLEMENTATION AND EXPERIMENT
The use of minimum MFC not only ensures that the in- The modulation process of the minimum MFC is shown in
verter has excellent linearity, low THD, and high dc volt- Fig. 11, where the generation of the minimum fluctuant signal is
age utilization, but also reduces the third harmonic in CMV drawn in Fig. 12. The scheme in Figs. 11 and 12 is implemented
greatly. in a field-programmable gate array.
HUANG et al.: CARRIER-BASED MODULATION SCHEME TO REDUCE THE THIRD HARMONIC COMPONENT OF COMMON-MODE VOLTAGE 1937

Fig. 13. Experimental relationship between M a and V a b 1 [the global

curves (top) and the local curves (bottom)] under (a) the conventional
SPWM, or the MFC with the (b) 1/6 third harmonic sinusoid, (c) max–min
average signal, (d) 1/4 third harmonic sinusoid, or (e) minimum fluctuant
signal.

Fig. 14. Experimental THD of line voltage v a b [the global curves (top)
and the local curves (bottom)] under (a) the conventional SPWM, or
the MFC with the (b) 1/6 third harmonic sinusoid, (c) max–min average
signal, (d) 1/4 third harmonic sinusoid, or (e) minimum fluctuant signal.

In the three-phase inverter system (as shown in Fig. 6), the

switches are implemented by insulated-gate bipolar transistors.
The switching dead-time is set to be 3 μs. The other parameters
of the three-phase inverter are listed in Table I.
In order to measure the linearity and the THD in a wide range
of modulation index, the three-phase resistive-inductance load,
which is the same as that in the simulation of Section II-D, is
Fig. 15. Experimental waveforms of the line voltage v A B (top) and
its FFT (bottom) in the three-phase inverter when M a = 1.1547 under
the (a) conventional SPWM, (b) 1/6 third harmonic sinusoid AZSTRS,
(c) max–min average AZSTRS, (d) 1/4 third harmonic sinusoid AZSTRS,
or (e) minimum MFC.
1938 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 3, MARCH 2018

TABLE II
COMPARISON OF THE MEASURED LINE VOLTAGE v A B AFTER FILTERING
UNDER DIFFERENT MODULATION SCHEMES (M a = 1.1547)

Scheme Amplitude of Frequency f0 (V) THD

Conventional SPWM 563.1 4.17%

1/6 third harmonic sinusoid AZSTRS 589.9 2.28%
Max–min average AZSTRS 593.2 2.57%
1/4 third harmonic sinusoid AZSTRS 593.0 2.82%
Minimum MFC 597.8 2.29%

used in the three-phase inverter experiment first. Fig. 13 shows

the experimental relationship between the modulation index and
the fundamental amplitude of line voltage before the Lf Cf filter
under different schemes. Most of the experimental results are
similar to the simulation results. The difference is that the exper-
imental fundamental with the 1/6 third harmonic sinusoid MFC
is much lower than the simulated one (from 598.3 to 588.3
V when Ma = 1.1547) due to the influence of the switching
dead-time. Comparatively, the decline of the fundamental am-
plitude with the 1/4 third harmonic sinusoid MFC is less. The
minimum MFC achieves the best performance in the funda-
mental amplitude. Fig. 14 shows the experimental THD of line
voltage before the Lf Cf filter under different schemes. Com-
pared with the THDs in Fig. 8, the experimental THDs increase
a little due to the influence of the switching dead-time. The THD
under the minimum MFC is the lowest in the experiments.
Many loads have requirements for THD (no higher than
3%∼5%). In this case, an output differential-mode filter (Lf Cf
filter) is used to connect the load and the inverter. Motors are the
most commonly used three-phase loads. In the next experiments
under high dc voltage utilization, an induction motor (380-V rate
voltage and 1-kW rate power) instead of the previous resistive-
inductance is used as the load of three-phase inverter.
Fig. 15 shows the experimental line voltage vAB behind the
Lf Cf filter under different schemes. Except under the conven-
tional SPWM scheme, the line voltages keep the good sinu-
soidal shape under the AZSTRS and MFC schemes. Because
the inverter with the conventional SPWM scheme works out of
linear region when Ma = 1.1547, the distortion of line volt-
age is obvious. Through the harmonic analysis, the fundamental
amplitudes and the THDs in the line voltages behind the Lf Cf
filter are listed in Table II. It can be seen that, under the MFC or
AZSTRS schemes, the THDs of line voltage behind the filter are
all less than 3%, which meets the requirements of most loads.
Based on the improvement of the dc voltage utilization in use of Fig. 16. Experimental waveforms of the CMV v c m (top) and its
the common method, i.e., 1/6 third harmonic sinusoid AZSTRS, FFT (bottom) in the three-phase inverter when M a = 1.05 under the
the fundamental amplitude is further increased by 1.34% in use (a) conventional SPWM, (b) 1/6 third harmonic sinusoid AZSTRS,
(c) max–min average AZSTRS, (d) 1/4 third harmonic sinusoid AZSTRS,
of the minimum MFC. When Ma = 1.1547, the line voltage un- or (e) minimum MFC.
der the minimum MFC scheme has the maximum fundamental
amplitude and root mean square value [as shown in the ellipses
of Fig. 15(a)–(e)]. conventional AZSTRS schemes [see Fig. 16(b)–(d)]. In the fast
The experimental results of the CMV vcm under different Fourier transform (FFT) calculation from the oscilloscope, no
schemes (Ma = 1.05) are shown in Fig. 16. Viewed from the obvious peak appears at the frequency 3f0 under the conven-
waveforms of CMV, the CMV peaks do not reach the maximum tional SPWM because no zero-sequence signal is added. The
or minimum value in some time-intervals under the minimum magnitudes of 3f0 are similar under the sinusoid AZSTRS and
MFC [see Fig. 16(e)] as that under the conventional SPWM the max–min average AZSTRS. They are all greater than 32
[see Fig. 16(a)]. In contrast, the CMV peaks during every dBV [the locally enlarged view in Fig. 16] because the larger
switching period reach the maximum and minimum under three signals are added. Under the minimum MFC, the magnitude of
HUANG et al.: CARRIER-BASED MODULATION SCHEME TO REDUCE THE THIRD HARMONIC COMPONENT OF COMMON-MODE VOLTAGE 1939

max–min average AZSTRS [see Fig. 17(a)–(c)]. Among them,

the magnitudes of 150 Hz is the highest (about 94.92 dBμV)
under the 1/4 third harmonic sinusoid AZSTRS. Under the min-
imum MFC, the magnitude of 150 Hz is only 77.68 dBμV
[as shown in Fig. 17(d)]. In addition, the sidelobe peaks near
the carrier frequency with the minimum MFC are much lower
than those with other method in the CMV spectrum. Con-
sidering the attenuation of 60 dB, the experimental results
are in correspondence with the simulation analysis as shown
in Fig. 10.

V. CONCLUSION
As with the conventional AZSTRS scheme, the MFC scheme
can increase dc voltage utilization to maximum and maintain
linearity of modulation in the three-phase inverter. Although the
AZSTRS scheme and the MFC scheme are equivalent, the latter
has some unique merits.
1) In the MFC scheme, the linear modulation region can
be displayed clearly by graph. According to different
objectives, various kinds of the fluctuant signals can be
designed easily in the linear region.
2) The proposed minimum MFC can make the dc voltage
utilization of the three-phase inverter maximum. This ad-
vantage is more obvious in the actual dead-time situation.
Compared with the most commonly used method, which
is the 1/6 third harmonic sinusoid AZSTRS or the SVM
(they are equivalent), the dc voltage utilization with min-
imum MFC is improved by 1.34%.
3) The minimum MFC has the minimum third harmonic of
CMV in the MFC schemes. This reduces the risk of low
frequency mechanical vibration.
4) The MFC scheme enriches the carrier-based modulation.
This design of unconventional carrier also provides a
new way for the development of modulation method in
the future.

Fig. 17. Experimental spectra of the CMV v c m in the three-phase
inverter when M a = 1.05 under the (a) 1/6 third harmonic sinusoid
AZSTRS, (b) max–min average AZSTRS, (c) 1/4 third harmonic sinu-
soid AZSTRS, or (d) minimum MFC.
3f0 is less than 18 dBV due to the minimum fluctuant signal
addition.
In order to observe the spectrum of CMV clearly and accu-
rately, the CMV spectra in low-frequency band are measured un-
der different schemes by a spectrum analyzer after 1000 times at-
tenuation (viz. −60 dB). The experimental results show that the
peak at the third harmonic (3f0 = 150 Hz) is the highest except
for the peak at the carrier frequency. The magnitudes of 150 Hz
are all greater than 91 dBμV under the sinusoid AZSTRS and the
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Jin Huang (M’14) received the B.S. degree in
electronic engineering from Shanghai Jiaotong
University, Shanghai, China, in 1992, and the
M.S. and Ph.D. degrees in electrical engineer-
ing from Huazhong University of Science and
Technology, Wuhan, China, in 2003 and 2009,
respectively.
He is currently an Associate Professor with
the State Key Laboratory of Advanced Electro-
magnetic Engineering and Technology, and the
School of Electrical and Electronic Engineering,
Huazhong University of Science and Technology. His research interests
include the control technique, EMC, and reliability of power electronics
devices.
Quanhui Liu received the B.S. degree in elec-
trical engineering from Huazhong University
of Science and Technology, Wuhan, China, in
2016, where he is currently working toward the
M.S. degree in electrical engineering.
His research interests include electromag-
netic compatibility, and reliability of power elec-
tronics devices.
Xulong Wang received the B.S. degree in power
engineering from Naval University of Engineer-
ing, Wuhan, China, in 2009. He is currently work-
ing toward the M.S. degree in electrical engi-
neering in Huazhong University of Science and
Technology, Wuhan, China.
His main research interests include power
quality control, EMC, and reliability of power
electronics devices.
Kaicheng Li (M’15) was born in Hubei Province,
China, in 1962. He received the B.S., M.S., and
Ph.D. degrees in electrical engineering from the
Huazhong University of Science and Technol-
ogy, Wuhan, China, in 1983, 1988, and 1998,
respectively.
He is currently a Professor with the State Key
Laboratory of Advanced Electromagnetic Engi-
neering and Technology, and the School of Elec-
trical and Electronic Engineering, Huazhong
University of Science and Technology. His cur-
rent research interests include electric theory and new technology, mea-
surement and control technology, power quality analysis, and electronic
instrument transformer.