1. Describe multiprocessor and multicomputer justifying the terms tightly coupled and loosely coupled.

2. Write a short note on computer architecture. Describe the various categories of Computer
architecture?

3. Based on what Michael J. Flynn proposed the classification of computer organization. State with
clear block diagram the four-machine configuration.

1. Consider three different processors, P1 P2 and P3, executing the same instruction set. P1 has a 3 GHz clock
rate and a CPI of 1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4.0 GHz clock rate and a CPI of
2.2.
a. Which processor has the highest performance expressed in instructions per second?
b. If the processors each execute a program in 10 seconds, find the number of cycles and the number of
instructions.
c. We are trying to reduce the execution time by 30% but this leads to an increase of 20% in the CPI. What
clock rate should we have to get this time reduction?

2. Consider the following two processors P1 and P2 executing the same instruction set with the clock rates and
CPIs specified in the following table.

Processors P1 P2

Clock rate 2GHz 3GHz

CPI 1.0 2.5

a. Which processor has the highest performance? How much faster than the other two processors?
b. If the processors each execute a program in 100 seconds, find the number of cycles and the number of
instructions for each processor.
c. For processor P2, we are trying to reduce the time by 40% but this leads to an increase of 20% in CPI,
what clock rate should we have to achieve this time reduction?

1. Explain the methods used for handling data dependency.

2. Illustrate hardware organization of 4-stage pipeline using a neat diagram.
3. State branch penalty with suitable example using proper diagram and explanation.
4. Using proper explanation discuss pipeline stall?

1. Determine the page fault rate of FIFO, Optimal and LRU for a particular reference string:
a,b,c,d,a,a,b,d,a,c,d,b,a,c for a memory with 3 frames.
2. Given the following, determine size of the sub field in bits in the address for direct mapping, associative and
set associative mapping cache schemes: We have 256 MB main memory and 1 MB cache memory. The
address space of this processor is 256 MB. The block size is 128 bytes. There are 8 blocks in a cache set.

1. Discuss the concept of C-Access Memory interleaving and give its advantages.
2. What do you mean by bus arbitration problem?
3. Discuss the Remedies of cache coherence problem