EXPERIMENT #1

OBJECT: Introduction to multisim.

 RESISTOR VOLTMETER AMMETER
1. 1K 2.5V 2.5A
2. 1.5K 3.8V 2.5A
3. 2.2K 5.6V 2.5A
 RESISTOR VOLTMETER AMMETER
1. 1K 12V 0.012A
2. 1.5K 12V 7.99A
3. 2.2K 12V 5.45A
 EXPERIMENT#2
OBJECT:
To verify logic gates:
1) NOT GATE:

DEFINITION:
The NOT gate is a single input single output gate. This gate is also
known as Inverter because it performs the inversion of the applied
binary signal, i.e., it converts 0 into 1 or I into 0. In other words, the gate
which has high input signal only when their input signal is low such
type of gate is known as the not gate.

BOOLEAN EXPRESION:

A’
REPRESENTATION:

TRUTH TABLE:
A Q=A’
0 1
1 0
2) AND GATE:

DEFINITION:

An AND gate is a digital device which produces high output only when
all inputs are high and produces low output at all other inputs
conditions. High digital signal means logically 1 and low digital signal
means logically 0.

BOOLEAN EXPRESSION:

A.B

REPREASENTATION:

TRUTH TABLE:
A B A.B
0 0 0
0 1 0
1 0 0
1 1 1
 3) OR GATE:

DEFINITION:

The OR Gate has two or more input signals but a single output signal. If
anyone of the input signal is high the output signal is high.

BOOLEAN EXPRESSION:

A+B
REPRESENTATION:

TRUTH TABLE:
A B A+B
0 0 0
0 1 1
1 0 1
1 1 1
 4) XOR GATE:

DEFINITION:

The XOR (Exclusive- OR) gate gives high output when the
inputs are not at equal logic level. The Exclusive OR operation
is widely used in digital circuit.

BOOLEAN EXPRESSION:

A’B + A.B’
REPRESENTATION:
.

TRUTH TABLE:
A B A’ B’ A’B+AB’
0 0 1 1 0
0 1 1 0 1
1 0 0 1 1
1 1 0 0 0
5) XNOR GATE:

DEFINITION:

The XNOR (Exclusive NOR) gate gives 1 at output, when the

inputs are identical (both 1’s or both 0’s). It performs same
function as XOR gate followed by a NOT gate.

BOOLEAN EXPRESSION:

A’.B’+A.B

REPREASENTATION:

TRUTH TABLE:

A B A’ B’ A’B’+A.B
0 0 1 1 1
0 1 1 0 0
1 0 0 1 0
1 1 0 0 1
 EXPERIMENT#3
OBJECT:
To implement and verify combinational logic circuit.

1) NAND GATE:

DEFINITION:

A NAND Gate is a logical gate which is the opposite of an AND logic gate.
It is a combination of AND and NOT gates and is a commonly used logic
gate. It is considered as a "universal" gate in Boolean algebra as it is
capable of producing all other logic gates.

BOOLEAN EXPRESSION:

(A.B)’

REPREASENTATION:
TRUTH TABLE:

A B A.B (A.B)’
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
 2) XOR GATE:
DEFINITION:
The XOR (Exclusive- OR) gate gives high output when the
inputs are not at equal logic level. The Exclusive OR operation is
widely used in digital circuit.
BOOLEAN REPREASENTATION:

A’B + A.B’
REPREASENTATION:
TRUTH TABLE:

A B A’ B’ A’B+AB’
0 0 1 1 0
0 1 1 0 1
1 0 0 1 1
1 1 0 0 0
3) XNOR GATE:

DEFINITION:

The XNOR (Exclusive NOR) gate gives 1 at output, when the

inputs are identical (both 1’s or both 0’s). It performs same
function as XOR gate followed by a NOT gate.

BOOLEAN EXPRESSION:

A’.B’+A.B

REPREASENTATION:
TRUTH TABLE:

A B A’ B’ A’B’+A.B
0 0 1 1 1
0 1 1 0 0
1 0 0 1 0
1 1 0 0 1
 EXPERIMENT#4
OBJECT:

To implement and verify complex equation using logic gates:

1) A.B + A.C’
TRUTH TABLE:

A B C D (A.B) E (C’) F (A.E) Q (D+F)

0 0 0 0 1 0 0
0 0 1 0 0 0 0
0 1 0 0 1 0 0
0 1 1 0 0 0 0
1 0 0 0 1 1 1
1 0 1 0 0 0 0
1 1 0 1 1 1 1
1 1 1 1 0 1 1
2) (A+B) . (C+D)’
TRUTH TABLE:

A B C D E (A+B) F (C+D) G Q (E.G)

(C+D)’
0 0 0 0 0 0 1 0
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 0
0 0 1 1 0 1 0 0
0 1 0 0 1 0 1 1
0 1 0 1 1 1 0 0
0 1 1 0 1 1 0 0
0 1 1 1 1 1 0 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 0
1 1 0 0 1 0 1 1
1 1 0 1 1 1 0 0
1 1 1 0 1 1 0 0
1 1 1 1 1 1 0 0
3) (A.B.C)’
TRUTH TABLE:

A B C D (A.B.C) Q (A.B.C)’
0 0 0 0 1
0 0 1 0 1
0 1 0 0 1
0 1 1 0 1
1 0 0 0 1
1 0 1 0 1
1 1 0 0 1
1 1 1 1 0
 4) A’(A.B)

TRUTH TABLE:

A B C (A’) D (A.B) Q {A’(A.B)}

0 0 1 0 0
0 1 0 0 0
1 0 1 0 0
1 1 0 1 0
 EXPERIMENT#5
OBJECT:
To verify logic gates using 74 IC’s:

AND GATE IC:

The pin number of AND gate IC is 74LS08.

INTERNAL PIN DIAGRAM:

CIRCUITAL VERIFICATION:

TRUTH TABLE:

A B A.B
0 0 0
0 1 0
1 0 0
1 1 1
NOT GATE IC:
The pin number of NOT gate ic is 74LS04.

INTERNAL PIN DIAGRAM:

CIRCUITAL VERIFICATION:

TRUTH TABLE:

A Q=A’
0 1
1 0
OR GATE IC:
The pin number of OR gate IC is 74LS32.

INTERNAL PIN DIAGRAM:

CIRCUITAL VERIFICATION:
TRUTH TABLE:
A B A+B
0 0 0
0 1 1
1 0 1
1 1 1
 EXPERIMENT#6
OBJECT:
To verify combinational gate using 74 IC’s:

NAND GATE IC:

The pin number of NAND gate ic is 74LS00.

INTERNAL PIN DIAGRAM:

CIRCUITAL VERIFICATION:

TRUTH TABLE:

A B A.B (A.B)’
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
NOR GATE IC’S:
The pin number of NOR gate IC is 74LS02.

INTERNAL PIN DIAGRAM:

CIRCUITAL VERIFICATION:
TRUTH TABLE:

A B A+B (A+B)’
0 0 0 1
0 1 1 0
1 0 1 0
1 1 1 0

XOR GATE IC:

The pin number of XOR gate IC is 74LS86.
INTERNAL PIN DIAGRAM:

CIRCUITAL VERIFICATION:

TRUTH TABLE:
A B A’ B’ A’B+AB’
0 0 1 1 0
0 1 1 0 1
1 0 0 1 1
1 1 0 0 0
 EXPERIMENT#7
OBJECT:
To verify De ’Morgan’s law using logic gates:

1)(ABC)’ = A’ . B’ . C’

TRUTH TABLE:

A B C A’ B’ C’ ABC (ABC)’ A’+B’+C’

0 0 0 1 1 1 0 1 1
0 0 1 1 1 0 0 1 1
0 1 0 1 0 1 0 1 1
0 1 1 1 0 0 0 1 1
1 0 0 0 1 1 0 1 1
1 0 1 0 1 0 0 1 1
1 1 0 0 0 1 0 1 1
1 1 1 0 0 0 1 0 0
2) (A+B+C)’ = A’ . B’.C’

TRUTH TABLE:
A B C A’ B’ C’ A+B+C (A+B+C)’ A’. B’.C’
0 0 0 1 1 1 0 1 1
0 0 1 1 1 0 1 0 0
0 1 0 1 0 1 1 0 0
0 1 1 1 0 0 1 0 0
1 0 0 0 1 1 1 0 0
1 0 1 0 1 0 1 0 0
1 1 0 0 0 1 1 0 0
1 1 1 0 0 0 1 0 0
OBJECT:

To verify De ‘Morgan’s law using IC’s:

1)(ABC)’ = A’ . B’ . C’

TRUTH TABLE:
A B C A’ B’ C’ ABC (ABC)’ A’+B’+C’
0 0 0 1 1 1 0 1 1
0 0 1 1 1 0 0 1 1
0 1 0 1 0 1 0 1 1
0 1 1 1 0 0 0 1 1
1 0 0 0 1 1 0 1 1
1 0 1 0 1 0 0 1 1
1 1 0 0 0 1 0 1 1
1 1 1 0 0 0 1 0 0
2) (A+B+C)’ = A’. B’.C’

TRUTH TABLE:
A B C A’ B’ C’ A+B+C (A+B+C)’ A’. B’.C’
0 0 0 1 1 1 0 1 1
0 0 1 1 1 0 1 0 0
0 1 0 1 0 1 1 0 0
0 1 1 1 0 0 1 0 0
1 0 0 0 1 1 1 0 0
1 0 1 0 1 0 1 0 0
1 1 0 0 0 1 1 0 0
1 1 1 0 0 0 1 0 0
 EXPERIMENT#8
OBJECT:

To verify 74 IC’s on hardware:

1) OR GATE IC:

VERIFICATION:
1 OK
2 OK
3 OK
4 OK
5 OK
6 OK
7 GROUND
8 OK
9 OK
10 OK
11 OK
12 OK
13 OK
14 VCC
2)NOT GATE IC:

VERIFICATION:
1 OK
2 OK
3 OK
4 OK
5 NOT OK
6 NOT OK
7 GROUND
8 OK
9 OK
10 OK
11 OK
12 OK
13 OK
14 VCC
 3)AND GATE IC:

VERIFICATION:
1 OK
2 OK
3 OK
4 OK
5 OK
6 OK
7 GROUND
8 OK
9 OK
10 OK
11 OK
12 OK
13 OK
14 VCC
 EXPERIMENT#9
OBJECT:

To verify complex equation using 74 IC’S

(1) (A+B)’+(C.D)’
A B C D A+B C.D (A+B)’ (C.D)’ Q
0 0 0 0 0 0 1 1 1
0 0 0 1 0 0 1 1 1
0 0 1 0 0 0 1 1 1
0 0 1 1 0 1 1 0 1
0 1 0 0 1 0 0 1 1
0 1 0 1 1 0 0 1 1
0 1 1 0 1 0 0 1 1
0 1 1 1 1 1 0 0 0
1 0 0 0 1 0 0 1 1
1 0 0 1 1 0 0 1 1
1 0 1 0 1 0 0 1 1
1 0 1 1 1 1 0 0 0
1 1 0 0 1 0 0 1 1
1 1 0 1 1 0 0 1 1
1 1 1 0 1 0 0 1 1
1 1 1 1 1 1 0 0 0
(2) A.(A+B)

A B A+B A . A+B
0 0 0 0
0 1 1 0
1 0 1 1
1 1 1 1
(3) A’.B+B.C

A B C A’ A’.B B.C Q
0 0 0 1 0 0 0
0 0 1 1 0 0 0
0 1 0 1 1 0 1
0 1 1 1 1 1 1
1 0 0 0 0 0 0
1 0 1 0 0 0 0
1 1 0 0 0 0 0
1 1 1 0 0 1 1
 EXPERIMENT#10
OBJECT:

To verify 74LS47 IC.

PIN DETAIL:

74LS47 is a BCD to 7-segment decoder/driver IC. It accepts a binary coded

decimal as input and converts it into a pattern to drive a seven-segment for
displaying digits 0 to 9. Binary coded decimal (BCD) is an encoding in which
each digit of a number is represented by its own binary sequence (usually of
four bits).

PIN DIAGRAM:
TRUTH TABLE:

A B C D a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 1 0 1 1

VERIFICATION: