Title: VHDL Program of Not Using Nand

TITLE: VHDL PROGRAM OF NOT USING NAND
VHDL PROGRAM:
Library IEEE
Use IEEE.STD_LOGIC_1164.ALL
Use IEEE.STD_LOGIC_ARITH.ALL
Use IEEE.STD_LOGIC_UNSIGNED.ALL
Entity notgate is
Port ( A: in STD_LOGIC;
Y: out STD_LOGIC);
end notgate;
architecture behavioral of notgate is
begin
Y<=(A nand A);
end behavioral ;
TEST BENCH WAVEFORM:
SIMULATION RESULT:
NAME:SOUMYA PRASAD ROY UNIVERSITY ROLL NO:23900315034 PAGE

TITLE: VHDL PROGRAM OF OR USING NAND
VHDL PROGRAM:
Library IEEE
Entity orgate is
B: in STD_LOGIC;
Y: out STD_LOGIC);
end orgate;
architecture behavioral of orgate is
begin
Y<=(A nand A) nand (B nand B);
end behavioral ;
SIMULATION RESULT:

TITLE: VHDL PROGRAM OF AND USING NAND
VHDL PROGRAM:
Library IEEE
Entity andgate is
Port ( a: in STD_LOGIC;
b: in STD_LOGIC;
C: out STD_LOGIC);
end andgate;
architecture behavioral of andgate is
begin
C<=(a nand b) nand (a nand b);
end behavioral ;
SIMULATION RESULT:

TITLE: VHDL PROGRAM OF NOT USING NOR
VHDL PROGRAM:
Library IEEE
Entity notgate is
Y : out STD_LOGIC);
end notgate;
begin
Y<=(A nor A);
end behavioral ;
SIMULATION RESULT:

TITLE: VHDL PROGRAM OF OR USING NOR
VHDL PROGRAM:
Library IEEE
Entity orgate is
B: in STD_LOGIC;
Y: out STD_LOGIC);
end orgate;
begin
Y<=(A nor B) nor (A nor B);
end behavioral ;
SIMULATION RESULT:

TITLE: VHDL PROGRAM OF AND USING NOR
VHDL PROGRAM:
Library IEEE
Entity andgate is
b: in STD_LOGIC;
C: out STD_LOGIC);
end andgate;
begin
C<=(A nor A) nor (B nor B);
end behavioral ;
SIMULATION RESULT:

TITLE: VHDL PROGRAM OF HALF ADDER
VHDL PROGRAM:
Library IEEE
Entity halfadder is
b: in STD_LOGIC;
s: out STD_LOGIC
c: out STD_LOGIC);
end halfadder;
architecture behavioral of halfadder is
begin
s<=(a xor b) ;
c<=(a and b) ;
end behavioral ;
SIMULATION RESULT:

TITLE: VHDL PROGRAM OF HALF SUBTRACTOR
VHDL PROGRAM:
Library IEEE
Entity halfsub is
b: in STD_LOGIC;
s: out STD_LOGIC
bR: out STD_LOGIC);
end halfsub;
architecture behavioral of halfsub is
begin
s<=(a xor b) ;
bR<=((not a) and b) ;
end behavioral ;
SIMULATION RESULT:

TITLE: VHDL PROGRAM OF FULL ADDER
VHDL PROGRAM:
Library IEEE
Entity fulladder is
b: in STD_LOGIC;
c: in STD_LOGIC;
s: out STD_LOGIC
ca: out STD_LOGIC);
end fulladder;
architecture behavioral of fulladder is
begin
s<=((a xor b) xor c) ;
ca<=((a xor b) and c) or (a and b) ;
end behavioral ;
SIMULATION RESULT:

TITLE: VHDL PROGRAM OF FULL SUBSTRACTOR
VHDL PROGRAM:
Library IEEE
Entity fullsub is
b: in STD_LOGIC;
c: in STD_LOGIC;
s: out STD_LOGIC
br: out STD_LOGIC);
end fullsub;
architecture behavioral of fullsub is
begin
s<=((a xor b) xor c) ;
br<=((a xor b) and ( not c)) or (( not a) and b) ;
end behavioral ;

SIMULATION RESULT:

TITLE: VHDL PROGRAM OF MULTIPLEXTUR
VHDL PROGRAM:
Library IEEE
Entity mux is
Port ( i0: in STD_LOGIC;
I1: in STD_LOGIC;
I2: in STD_LOGIC;
I3: in STD_LOGIC;
s0: in STD_LOGIC;
s1: in STD_LOGIC;
y: out STD_LOGIC);
end mux;
architecture behavioral of mux is
begin
y<=(((i0 and (not s0)) and (not s1)) or ((i1 and (not s0)) and (not s1))) or (((i2 and (not s0)) and (not
s1)) or ((i3 and (not s0)) and (not s1)));
end behavioral ;

SIMULATION RESULT:

TITLE: VHDL PROGRAM OF NOT USING BEHAVIORAL MODALING
VHDL PROGRAM:
Library IEEE
Entity notgate is
y: out STD_LOGIC);
end notgate;
begin
process(a)
begin
if a=’1’ then
y<=’0’;
else y<=’1’;
end if;
end process;
end behavioral ;

SIMULATION RESULT:
TITLE: VHDL PROGRAM OF OR USING BEHAVIORAL MODALING
VHDL PROGRAM:
Library IEEE
Entity orgate is
b: in STD_LOGIC;
Y: out STD_LOGIC);
end orgate;
begin
process(a,b)
begin
if a=’0’ then
if b=’0’ then
Y<=’0’;
else Y<=’1’;
end if;
else Y<=’1’;

end if;
end process;
end behavioral ;
SIMULATION RESULT:

TITLE: VHDL PROGRAM OF AND USING BEHAVIORAL MODALING
VHDL PROGRAM:
Library IEEE
Entity andgate is
b: in STD_LOGIC;
Y: out STD_LOGIC);
end andgate;
begin
process(a,b)
begin
if a=’1’ then
if b=’1’ then
Y<=’1’;
else Y<=’0’;
end if;
else Y<=’1’;
end if;
end process;
end behavioral ;

SIMULATION RESULT:
TITLE: VHDL PROGRAM OF NOR USING BEHAVIORAL MODALING
VHDL PROGRAM:
Library IEEE
Entity norgate is
b: in STD_LOGIC;
C: out STD_LOGIC);
end norgate;
architecture behavioral of norgate is
begin
process(a,b)
begin
if a=’1’ then
if b=’1’ then
C<=’0’;
else C<=’1’;
end if;
else C<=’1’;

end if;
end process;
end behavioral ;
SIMULATION RESULT:

TITLE: VHDL PROGRAM OF NAND USING BEHAVIORAL MODALING
VHDL PROGRAM:
Library IEEE
Entity nandgate is
b: in STD_LOGIC;
C: out STD_LOGIC);
end nandgate;
architecture behavioral of nandgate is
begin
process(a,b)
begin
if a=’0’ then
if b=’0’ then
C<=’1’;
else C<=’0’;
end if;
else C<=’0’;
end if;
end process;
end behavioral ;

SIMULATION RESULT:

TITLE: VHDL PROGRAM OF XOR USING BEHAVIORAL MODALING
VHDL PROGRAM:
Library IEEE
Entity xorgate is
b: in STD_LOGIC;
S: out STD_LOGIC);
end xorgate;
architecture behavioral of xorgate is
begin
process(a,b)
begin
if a=’0’ then
if b=’0’ then
S<=’0’;
else S<=’1’;
end if;
else
if b=’0’ then
S<=’1’;
else S<=’0’;
end if;
end if;
end process;
end behavioral ;

SIMULATION RESULT:

TITLE: VHDL PROGRAM OF XNOR USING BEHAVIORAL MODALING
VHDL PROGRAM:
Library IEEE
Entity xnorgate is
b: in STD_LOGIC;
C: out STD_LOGIC);
end xnorgate;
architecture behavioral of xnorgate is
begin
process(a,b)
begin
if a=’0’ then
if b=’0’ then
C<=’1’;
else C<=’0’;
end if;
else
if b=’0’ then
C<=’0’;
else o<=’1’;
end if;
end if;
end process;
end behavioral ;

SIMULATION RESULT:

Lab Card For: VLSI design Lab (EC-792)
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
ADAMAS INSTITUTE OF TECHNOLOGY, BARASAT
Name of Student : Soumya Prasad Roy

Year: 4th Sem: 7th Class Roll No: 06
Stream: E.C.E University Roll No : 23900315034
Expt. Date of Date of Signature

No. Name of the experiment experiment submission of the
Teacher
1. VHDL PROGRAM OF NOT USING 6.8.18

BEHAVIORAL MODALING
2. VHDL PROGRAM OF OR USING 6.8.18
BEHAVIORAL MODALING
3. VHDL PROGRAM OF AND USING 6.8.18
BEHAVIORAL MODALING
4. VHDL PROGRAM OF X-OR USING 6.8.18
BEHAVIORAL MODALING
5. VHDL PROGRAM OF X-NOR USING 6.8.18
BEHAVIORAL MODALING
6. VHDL PROGRAM OF NOT USING NAND 13.8.18
7. VHDL PROGRAM OF OR USING NAND 13.8.18
8. VHDL PROGRAM OF AND USING NAND 13.8.18
9. VHDL PROGRAM OF NOT USING NOR 13.8.18
10. VHDL PROGRAM OF OR USING NOR 13.8.18
11. VHDL PROGRAM OF AND USING NOR 13.8.18
12. VHDL PROGRAM OF HALF ADDER 27.8.18
13. VHDL PROGRAM OF HALF SUBTRACTOR 27.8.18
14. VHDL PROGRAM OF FULL ADDER 27.8.18
15. VHDL PROGRAM OF FULL SUBTRACTOR 27.8.18
16. VHDL PROGRAM OF MULTIPLEXTUR
17. VHDL PROGRAM OF NOT USING 10.9.18

BEHAVIORAL MODALING

18. VHDL PROGRAM OF OR USING 10.9.18
BEHAVIORAL MODALING
19. VHDL PROGRAM OF AND USING 10.9.18
BEHAVIORAL MODALING
20. VHDL PROGRAM OF NOR USING 10.9.18
BEHAVIORAL MODALING
21. VHDL PROGRAM OF NAND USING 10.9.18
BEHAVIORAL MODALING
22. VHDL PROGRAM OF XOR USING 10.9.18
BEHAVIORAL MODALING
23. VHDL PROGRAM OF XNOR USING 10.9.18
BEHAVIORAL MODALING

TITLE: VHDL PROGRAM OF NOT USING BEHAVIORAL MODALING
VHDL PROGRAM:
Library IEEE
Entity notgate is
Y: out STD_LOGIC);
end notgate;
begin
Y<=(A not A);
end behavioral ;
SIMULATION RESULT:

TITLE: VHDL PROGRAM OF OR USING BEHAVIORAL MODALING
VHDL PROGRAM:
Library IEEE
Entity orgate is
B: in STD_LOGIC;
Y: out STD_LOGIC);
end orgate;
begin
Y<=(A or B);
end behavioral ;
SIMULATION RESULT:

TITLE: VHDL PROGRAM OF AND USING BEHAVIORAL MODALING
VHDL PROGRAM:
Library IEEE
Entity andgate is
b: in STD_LOGIC;
C: out STD_LOGIC);
end andgate;
begin
C<=(a and b);
end behavioral ;
SIMULATION RESULT:

TITLE: VHDL PROGRAM OF X-OR USING BEHAVIORAL MODALING
VHDL PROGRAM:
Library IEEE
Entity xorgate is
b: in STD_LOGIC;
s: out STD_LOGIC);
end xorgate;
begin
s<=(a xor b);
end behavioral ;
SIMULATION RESULT:

TITLE: VHDL PROGRAM OF X-NOR USING BEHAVIORAL MODALING
VHDL PROGRAM:
Library IEEE
Entity xnorgate is
b: in STD_LOGIC;
s: out STD_LOGIC);
end xnorgate;
begin
s<=(a xnor b);
end behavioral ;
SIMULATION RESULT:


Title: VHDL Program of Not Using Nand

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Title: VHDL Program of Not Using Nand

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TITLE: VHDL PROGRAM OF NOT USING NAND

architecture behavioral of notgate is

Y<=(A nand A);

TEST BENCH WAVEFORM:

NAME:SOUMYA PRASAD ROY UNIVERSITY ROLL NO:23900315034 PAGE

architecture behavioral of orgate is

Y<=(A nand A) nand (B nand B);

TEST BENCH WAVEFORM:

NAME:SOUMYA PRASAD ROY UNIVERSITY ROLL NO:23900315034 PAGE

architecture behavioral of andgate is

C<=(a nand b) nand (a nand b);

TEST BENCH WAVEFORM:

NAME:SOUMYA PRASAD ROY UNIVERSITY ROLL NO:23900315034 PAGE

architecture behavioral of notgate is

Y<=(A nor A);

TEST BENCH WAVEFORM:

NAME:SOUMYA PRASAD ROY UNIVERSITY ROLL NO:23900315034 PAGE

architecture behavioral of orgate is

Y<=(A nor B) nor (A nor B);

TEST BENCH WAVEFORM:

NAME:SOUMYA PRASAD ROY UNIVERSITY ROLL NO:23900315034 PAGE

architecture behavioral of andgate is

C<=(A nor A) nor (B nor B);

TEST BENCH WAVEFORM:

NAME:SOUMYA PRASAD ROY UNIVERSITY ROLL NO:23900315034 PAGE

architecture behavioral of halfadder is

TEST BENCH WAVEFORM:

NAME:SOUMYA PRASAD ROY UNIVERSITY ROLL NO:23900315034 PAGE

bR: out STD_LOGIC);

architecture behavioral of halfsub is

TEST BENCH WAVEFORM:

NAME:SOUMYA PRASAD ROY UNIVERSITY ROLL NO:23900315034 PAGE

ca: out STD_LOGIC);

architecture behavioral of fulladder is

s<=((a xor b) xor c) ;

ca<=((a xor b) and c) or (a and b) ;

NAME:SOUMYA PRASAD ROY UNIVERSITY ROLL NO:23900315034 PAGE

br: out STD_LOGIC);

architecture behavioral of fullsub is

s<=((a xor b) xor c) ;

br<=((a xor b) and ( not c)) or (( not a) and b) ;

NAME:SOUMYA PRASAD ROY UNIVERSITY ROLL NO:23900315034 PAGE

NAME:SOUMYA PRASAD ROY UNIVERSITY ROLL NO:23900315034 PAGE

Port ( i0: in STD_LOGIC;

architecture behavioral of mux is

NAME:SOUMYA PRASAD ROY UNIVERSITY ROLL NO:23900315034 PAGE

NAME:SOUMYA PRASAD ROY UNIVERSITY ROLL NO:23900315034 PAGE

architecture behavioral of notgate is

TEST BENCH WAVEFORM:

NAME:SOUMYA PRASAD ROY UNIVERSITY ROLL NO:23900315034 PAGE

TITLE: VHDL PROGRAM OF OR USING BEHAVIORAL MODALING

architecture behavioral of orgate is

NAME:SOUMYA PRASAD ROY UNIVERSITY ROLL NO:23900315034 PAGE

TEST BENCH WAVEFORM:

NAME:SOUMYA PRASAD ROY UNIVERSITY ROLL NO:23900315034 PAGE

architecture behavioral of andgate is

TEST BENCH WAVEFORM:

NAME:SOUMYA PRASAD ROY UNIVERSITY ROLL NO:23900315034 PAGE

TITLE: VHDL PROGRAM OF NOR USING BEHAVIORAL MODALING

architecture behavioral of norgate is

NAME:SOUMYA PRASAD ROY UNIVERSITY ROLL NO:23900315034 PAGE

TEST BENCH WAVEFORM: