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Electronics Lab

BPPH 68

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Reg. No :________________________________________

Prepared by

SRI BHARATHI WOMEN’S ARTS & SCIENCE COLLEGE

Kunnathur – Arni – 632 314

Certificate

_____________________________________ bearing the Reg. No. ______________________

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____________________________ laboratory during the Academic year ___________________

under our supervision.

Principal

INDEX

No.

1 Op – Amp – Voltage follower, adder, subtractor, 1

averager (inverting mode). IC 741

using op-amp IC 741

3 15

Half adder and Full adder – using NAND gate only.

only.

5 22

Verification of De Morgan’s Theorems.

8085.

Binary to BCD, Hex to ASCII using 8085.

16 Emitter Follower 59

17 62

response

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Exp. No

Verify the operation of op – amp

Voltage follower, Adder, Subtraction and Average

Date

Aim:

Design and verify the operation of op – amp as a Voltage follower, Adder, Subtraction

and Average.

Apparatus:

connecting wire.

Procedure:

3. Appropriate input voltage is applied to the inverting input terminal of the Op-Amp.

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𝑽𝒊𝒏 = 𝑽𝒐𝒖𝒕

S.No Vin Input Volt

(volts) (volts)

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The circuit consists of an op-amp and a wire connecting the output voltage to the input

i.e. the output voltage is equal to the input voltage, both in magnitude and phase.V0 = Vi

Since the output voltage of the circuit follows the input voltage, the circuit is called

voltage follower. It offers very high input impedance of the order of MD and very low output

impedance.

Therefore, this circuit draws negligible current from the source. Thus, the voltage

follower can be used as a buffer between a high impedance source and a low impedance load for

impedance matching applications.

Calculation:

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2. Adder (summer):

If R1 = R2 = Rf then,

𝐑𝐟

𝐕𝟎 = − (𝐕 + 𝐕𝟐 )

𝐑𝟏 𝟏

S.No

V1 V2 Observed V0 Calculated V0

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2. Adder (summer):

This is one of the liner applications of the Op-Amp. A circuit whose output is the sum of

several input signals is called a summer.

Now, with the right-hand sides of the three averaging resistors connected to the virtual

ground is now held at 0 volts by the op-amp’s negative feedback, whereas before it was free to

float to the average value of V1, V2, and V3.

However, with all resistor values equal to each other, the currents through each of the

three resistors will be proportional to their respective input voltages.

Since those three currents will add at the virtual ground node, the algebraic sum of those

currents through the feedback resistor will produce a voltage at Vout equal to V1 + V2 + V3,

except with reversed polarity.

V0 = - (V1+V2+V3)

Calculation:

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3. Subtractor:

If R1 = R2 = Rf ≠R3 then,

𝑹𝟑

𝑽𝟎 = − (𝑽𝟐 − 𝑽𝟏 )

𝑹𝟏

Thus, the circuit amplifier the difference of two input signals.

S.No

V1 V2 Observed Calculated

1

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3. Subtractor:

A basic differential amplifier can be used as a subtractor as shown in the figure. If all

resistors are equal in value, then the output voltage can be derived by using superposition

principle.

Then the circuit of figure as shown in the above becomes a non-inverting amplifier

having input voltage V1 and V2 at the non-inverting input terminal and the output becomes;

Thus the output voltage Vo due to both the inputs can be written as

Vo=V2 - V1

Calculation:

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4. Averager:

If R1 ≠ R2 ≠ Rf then

𝑽𝟏 + 𝑽𝟐

𝑽𝟎 = 𝟐

S.No

V1 V2 Observed(V0) Calculated(V0)

1

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4. Averager:

If we take three equal resistors and connect one end of each to a common point, then apply

three input voltages (one to each of the resistors’ free ends), the voltage seen at the common

point will be the mathematical average of the three.

This circuit is really nothing more than a practical application of Millman’s Theorem.

The large equation to the right of the averager circuit comes from Millman’s Theorem, which

describes the voltage produced by multiple voltage sources connected together through

individual resistances.

Since the three resistors in the averager circuit are equal to each other, we can simplify

Millman’s formula by writing R1, R2, and R3.

𝑉1 + 𝑉2 + 𝑉3

𝑉0 =

3

If R1 = R2 = Rf then,

Calculation:

Result:

Using Op-amp IC 741, Voltage follower, Adder (Summer), Difference ( Subtractor), and

Average circuits are constructed and their performances have been studied.

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

differentiator

Date

Aim:

Design and verify the operation of op – amp as an integrator and differentiator.

Apparatus:

Op-amp kit, IC 741, Resistance (1KΩ, 10KΩ, 100KΩ), Capacitor (0.01µF), Function

generator, CRO, Connecting wire.

PROCEDURE:

2. Apply DC input signal to the input terminals of an op-amp.

3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input

voltage is applied to the inverting input terminal of the Op-Amp.

4. Observe the output wave forms on CRO.

5. Measure the DC output voltage using multimeter.

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Circuit Diagram:

a) Integrator

Waveforms:

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OP-Amp Integrator

1. Define integrator.

fundamental operation in calculus. The integration function is often part of engineering and

scientific calculations. Electronic analog integrators were the basis of analog computers.

An integrator is a circuit that performs integration of the input signal. The most important

application of an integrator is to produce a ramp output voltage.

Shows the circuit of an OP-Amp integrator. When a signal is applied to the input of this circuit,

the output-signal waveform will be the integration of input-signal waveform. It consists of an

OP-Amp, input resistor R and feedback capacitor C.

Circuit Analysis

Since point A in fig. is at virtual ground, the virtual ground equivalent circuit of operational

integrator will be as shown in fig.

Because of virtual ground and infinite impedance of the OP-Amp, all of the input current flows

through the capacitor i.e.

To find out the output voltage, we integrate both sides of the above equation to get,

This equation shows that the output is the integral of the input with an inversion and scale

multiplier of 1/RC.

Output Voltage

If a fixed voltage is applied to the input of an integrator, the output voltage grows over a period

of time, providing a ramp voltage.

The output ramp voltage is opposite in polarity to the input voltage and is multiplied by a factor

1//RC.

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Circuit Diagram:

a) Differentiator:

Waveforms:

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OP-Amp Differentiator :

2. Define differentiator.

Ans: A Differentiator is a circuit that is designed such that the output of the circuit is

proportional to the time derivative of the input.

A differentiator is a circuit that performs differentiation of the input signal. That means, a

differentiator produces an output voltage that is proportional to the rate of change of the input

voltage. Its important application is to produce a rectangular output from a ramp input.

Circuit Analysis

Since point A in fig.5 (i) is at virtual ground, the virtual-ground equivalent circuit of the

operational differentiator will be as shown in fig.

Because of virtual ground and infinite impedance of OP-Amp, all the input current ic flows

through the feedback resistor R. i.e.

The above equation shows that output is the differentiation of the input with an inversion and

scale multiplier of RC.

If the input voltage is constant, dvi/dt is zero and the output voltage is zero.

The faster the input voltage changes, the larger the magnitude of the output voltage.

Integrators have use as low pass filter in audio applications; differentiators are used as

high pass filters. To separate vertical sync signal from analog TV signal integrators are used,

differentiators are used to recover horizontal sync signal

Result:

Differentiator and integrator circuits are constructed and their wave forms have been

studied using Op-Amp 741.

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Exp. No

HALFADDER & FULL ADDER

Date

Aim:

To realize half/full adder using NAND gate IC 7400.

Components Required:

Digital logic kit and IC 7400

Theory:

Half-Adder:

Half Adder is a combinational logic circuit which is designed by connecting one EX-OR

gate and one AND gate. It adds two one-bit numbers and generates the sum as the output. It

consists of two input terminals and two output terminals, one is SUM, and the other is CARRY.

S =A B

C=A.B

Full-Adder: Full Adder is the circuit which consists of the circuit which consists of two

EX-OR gates, two AND gates and one OR gate. It adds three binary digits, among which two are

the inputs, and one is the carry obtained from previous addition. A combinational logic circuit

that adds two data bits, A and B, and a carry-in bit, Cin , is called a full-adder. The Boolean

functions describing the full-adder are:

S = A B Cin

C = A . B+ A . C

Definition Half Adder is combinational logic Full Adder is a combinational logic

circuit which adds two 1-bit circuit which adds three 1-bit

digits. digits.

Carry Addition Carry generated from previous Carry generated from previous

addition is not added in next step. addition is added in the next step.

Hardware It consists of one EX-OR gate and It consists of two EX-OR, two

components one AND gate. AND gate and one OR gate.

Applications Calculators, computers, digital Multiple bit addition, digital

measuring devices etc. processors etc.

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a) Half-Adder

Table

A B SUM CARRY

0 0 0 0

0 1 1 0

1 0 1 0

1 1 1 1

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2. Full Adder

Table

A B C SUM CARRY

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Similarities

1. Half Adder and Full Adder, both are the combinational digital circuit. This means both

the circuit does not have any memory element like sequential circuits.

2. The above two combinational circuits are crucial for arithmetic operation. Both the

combinational circuits provide the addition of binary numbers.

RESULT:

The Half and Full adder circuit was constructed and their truth tables are verified using

IC 7400.

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Exp. No

HALF & FULL SUBTRACTOR

Date

Aim:

To realize half and full Subtractor using NAND gate IC 7400.

Apparatus:

Half Subtractor:

Subtracting a single-bit binary value B from another A (i.e. A -B) produces a difference

bit D and a borrow out bit Br. This operation is called half subtraction and the circuit to realize it

is called a half subtractor.

Half subtractor is the most essential combinational logic circuit which is used in digital

electronics. Basically, this is an electronic device or in other terms, we can say it as a logic

circuit.

Half subtractor is used to perform two binary digits subtraction. In the previous article,

we have already discussed the concepts of half adder and a full adder circuit which uses the

binary numbers for the calculation.

Similarly, the subtractor circuit uses binary numbers (0, 1) for the subtraction. The circuit

of the half subtractor can be built with two logic gates namely NAND and EX-OR gates. This

circuit gives two elements such as the difference as well as the borrow.

D =A B

Br = 𝑨 . 𝑩

It can be used in amplifiers to reduce the sound distortion

Half subtractor is used in ALU of processor

It can be used to increase and decrease operators and also calculates the addresses

Half subtractor is used to subtract the least significant column numbers. For subtraction

of multi-digit numbers, it can be used for the LSB.

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

A) Half Subtractor:

Table:

A B DIFF BRO

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

B) Full Subtractor:

Full subtractor is an electronic device or logic circuit which performs subtraction of two

binary digits. It is a combinational logic circuit used in digital electronics. Many combinational

circuits are available in integrated circuit technology namely adders, encoders, decoders and

multiplexers.

Subtracting two single-bit binary values, B, Cin from a single-bit value A produces a

difference bit D and a borrow out Br bit. This is called full subtraction.

The full subtractor is one of the most used and essential combinational logic circuits. It is

a basic electronic device, used to perform subtraction of two binary numbers. In the earlier

article, already we have given the basic theory of half adder & a full adder which uses the binary

digits for the computation.

The full-subtractor uses binary digits like 0,1 for the subtraction. The circuit of full

subtractor can be built with logic gates such as OR, Ex-OR, NAND gate. The inputs of this

subtractor are A, B, Bin and outputs are D, Bout.

D=ABC

Br = 𝑨 . B + 𝑨 . C + B . C

These are generally employed for ALU (Arithmetic logic unit) in computers to subtract

as CPU & GPU for the applications of graphics to decrease the circuit difficulty.

Subtractors are mostly used for performing arithmetical functions like subtraction, in

electronic calculators as well as digital devices.

These are also applicable for different microcontrollers for arithmetic subtraction, timers,

and program counter (PC)

Subtractors are used in processors to compute tables, address, etc.

It is also useful for DSP and networking based systems.

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

B) Full Subtractor:

Table

A B C DIFF BOR

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

RESULT:

The Half and Full adder circuit was constructed and their truth tables are verified using

IC 7400.

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Exp. No

De-Morgan’s theorem

Date

Components required: IC 7404, 7432, 7408, Digital IC Trainer Kit, Patch cards

Theory:-

De-Morgan’s Theorem is mainly used to solve the various Boolean algebra expressions.

The De-Morgan’s theorem defines the uniformity between the gate with same inverted input and

output. It is used for implementing the basic gate operation likes NAND gate and NOR gate. The

De-Morgan’s theorem mostly used in digital programming and for making digital circuit

diagram. There are two De-Morgan’s Theorems. They are described below in detail.

Theorem 1: The compliment of the product of two variables is equal to the sum of the

compliment of each variable. Thus according to De-Morgan’s laws or De-Morgan's theorem if A

and B are the two variables or Boolean numbers. Then accordingly,

𝑨. 𝑩 = 𝑨 + 𝑩

Theorem 2:

The compliment of the sum of two variables is equal to the product of the compliment of each

variable. Thus according to De Morgan’s theorem if A and B are the two variables then,

𝑨+𝑩=𝑨.𝑩

De-Morgan's laws can also be implemented in Boolean algebra in the following steps:-

That is (+) is replaced with (.) and (.) is replaced with (+).

2. Compliment of each of the term is to be found.

Procedure:

1. Realize the De-Morgan’s theorem using logic gates.

2. Connect VCC and ground as shown in the pin diagram.

3. Make connections as per the logic gate diagram.

4. Apply the different combinations of input according to the truth tables.

Verify that the results are correct.

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Theorem 1:

Truth table:

A B 𝑨. 𝑩 𝑨+𝑩

0 0 1 1

0 1 1 1

1 0 1 1

1 1 0 0

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Theorem 2:

Truth table:

A B 𝑨+𝑩 𝑨.𝑩

0 0 1 1

0 1 0 0

1 0 0 0

1 1 0 0

Result:

De-Morgan’s circuits (theorem) were constructed and verify their truth tables.

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Exp. No

SQUARE AND SQUARE ROOT OF 8085

Date

Aim:

To write an Assembly Language Program to find the square root of a number using 8085

Apparatus:

8085 kit

1. Start.

2. Load into register pair HL from memory address 9000H.

3. Initialize accumulator A with 00.

4. Move contents of memory M into register C.

5. Add the contents of memory M with the contents of accumulator A and store the result in

accumulator A.

6. Decrement the register C by 1.

7. If no zero is present, go to step 5 else go to step 8.

8. Store the contents of accumulator into memory location 9100H.

9. Terminate the program.

1. Load the HL pair with the address of the number whose square root is to be found.

2. Copy the number to accumulator.

3. Initialize E with 0.

4. Subtract content of E from accumulator.

5. Increment register E by 2.

6. Increment content C register by 1.

7. Compare accumulator content with 0.

8. If accumulator content is not zero then go to step 4 else go to step 9.

9. Store the square root in to the memory.

10. Terminate the program.

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8100 LDA 8300 3A,00,83 Load the data in accumulator

8103 MOV C , A 4F Move the data from Reg. A to Reg. C

8104 MOV B , A 47 Move the data from Reg. A to Reg. B

8105 XRA A AF Exclusive OR Accumulator

8106 (L1) ADD B 80 [A] [A] + [B]

8107 DCR C 0D Decrement Reg. C

8108 JNZ (L1) C2,06,81 Jump on non-zero to the label LOOP

810B STA 32,00,84 Store the square in 4500

810E HLT 76 Stop the Program

02 04

03 09

04 10

0D 09

07 31

0E C4

3F 81

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8100 LDA 8200 3A,00,82 Load the data in Accumulator

8103 MVI C , 00 0E, 00 Initialize C as 0

8105 MVI D , 00 16 , 01 Initialize D as 0

8107 (L2)INR C 0C Increment register C

8108 SUB D 92 [A] [A] + [D]

8109 JZ (L1) CA,11,81 Jump on zero to the label LOOP

810C INR D 14 Increment register D

810D INR D 14 Increment register D

810E JMP (L2) C3,07,81 Jump to the label LOOP

8111 (L1)MOV A,C 79 Copy content of register C to accumulator

8112 STA 32,00,85 Store the square root in 8500

8115 HLT 76 Stop the Program

25 05

64 0A

81 3F

49 1D

09 03

36 1D

0A 1D

Result:

The assembly language program square and square root of 8 bit numbers was executed

successfully by using 8085 micro processing kit.

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Exp. No

Microprocessor – Sum of N elements

Date

AIM:

To write an assembly language program for sum of N-elements of 8-bit using 8085

Apparatus:

8085 kit

Algorithm:

Step 1: Start the microprocessor

Step 2: Load the number of values in series in accumulator and move it to register C and

load the starting address of array

Step 3: Initialize the value of A as ‘00’

Step 4: Move the value of ‘A’ to ‘B’ register

Step 5: Add the content of accumulator with the data pointed by ‘HL’ pair

Step 6: If there exists a carry, increment ‘B’ by 1, if not continue

Step 7: Increment the pointer to next data

Step 8: Decrement the value of ‘C’ by 1, which is used as counter

Step 9: If ‘C’ is equal to zero, go to step 10 if not go to step 5.

Step 10: Store the value of ‘A’ to memory, it shows the result

Step 11: Move the content of B to A

Step 12: Store the value of A to memory

Step 13: Stop the program.

8200 LXIH , 8400 21 , 00, 84 Load the content of memory in acc. A

8203 MOV C , M 4E Move the value of acc. M in Reg. C

8204 INX H 23 Increment Reg. H

8205 MVI E , 00 1E , 00 Initialize E to 0

8207 XRA A AF Exclusive OR in accumulator A

8208 L2) ADD M 86 Add the data M to Reg. A

8209 JNC (L1) D2 , 0D, 82 Jump on non-zero to the label LOOP

820C INR E 1C Increment Reg. E

820D L1) INX H 23 Increment Reg. H

820E DCR C 0D Decrement Reg. C

820F JNZ (L2) C2 , 08, 82 Jump to the given step if there is not zero

8212 STA 8600 32 , 00, 86 Store the data in memory 8600

8215 MOV A , E 7B Move the data Reg. E to Reg. A

8216 STA 8601 32 , 01, 86 Store the data in memory with carry

8219 HLT 76 Stop the Process.

No. of

OUTPUT

eleme SUM OF N- ELEMENTS INPUT DATA

DATA

nt

8400 8401 8402 8403 8404 8405 8406 8407 8408 8409 840A 840B 8601 8600

04 01 5C 0A 03 00 6A

05 4C 1D 04 5F 0F 00 DB

06 5F 3E 06 08 0A 1B 00 D0

07 7F 2B 1D 09 5B 2C 5D 01 B4

08 25 3E 5F 2A 1E 3F 20 15 01 7E

09 5C 30 12 1C 2A 5B 50 15 3D 01 E1

0A 15 6E 4C 09 83 5F 32 14 1D 3A 02 57

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0B 20 14 0F 8C 2D 3B 18 06 29 5B 6C 02 45

Result: The assembly language program for sum of N-Elements was executed successfully using

Page 29

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Date BCD to binary, Binary to BCD, Hex to ASCII using 8085

AIM:

To write an assembly language program for BCD to binary, Binary to BCD of 8-bit

using 8085

Step 2: Get the BCD data in accumulator and save it in register ‘E’

Step 3: Mark the lower nibble of BCD data in accumulator

Step 4: Rotate upper nibble to lower nibble and save it in register ‘B’

Step 5: Clear the accumulator

Step 6: Move 0AHto ‘C’ register

Step 7: Add ‘A’ and ‘B’ register

Step 8: Decrement ‘C’ register. If zf = 0, go to step 7

Step 9: Save the product in ‘B’

Step 10: Get the BCD data in accumulator from ‘E’ register and mark the upper nibble

Step 11: Add the units (A-ug) to product (B-ug)

Step 12: Store the binary value in memory

Step 13: End the program

Step 2: Clear ‘D’ and ‘E’ register to account for hundred’s and ten’s load the binary data

in accumulator

Step 3: Compare ‘A’ with 64 if carry = 01, go step C otherwise next step

Step 4: Subtract 64 from (64+1) ‘A’ register

Step 5: Increment ‘E’ register

Step 6: Compare the register ‘A’ with ‘0A’, if carry=1, go to step 11, otherwise next step

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Step 8: Increment D register

Step 9: Go to step 7

Step 10: Combine the units and tens to from 8 bit result

Step 11: Save the units, tens and hundred’s in memory

Step 12: Stop the program execution

8500 LXI H, 8200 21,00,82 Load the data in HL pair Reg.

8503 MOV A , M 7E Move the content Reg. M in Reg. A

8504 ANI 0F E6 , 0F Mask of the least significant four bits

8506 MOV C , A 4F Copy A to C

8507 MOV A , M 7E Copy M to A

8508 ANI F0 E6 , F0 Mask of the most significant four bits

850A RRC 0F Rotate accumulator right with carry

850B RRC 0F Rotate accumulator right with carry

850C RRC 0F Rotate accumulator right with carry

850D RRC 0F Rotate accumulator right with carry

850E MOV E , A 5F Load the count value to the Reg. E

850F MVI D , 0A 16 , 0A Initialize Reg. D with 0AH

8511 XRA A AF Clear the contents of the accumulator A

8512 (L1)ADD E 83 Add the contents of Reg. E to A

8513 DCR D 15 Decrement the count by 1 until 0 is reached

8514 JNZ (L1) C2 ,12,85 Jump on non-zero label loop

8517 ADD C 81 Add the contents of Reg. C to A

8518 STA 8300 32,00,83 Store the data in 8300

851B HLT 76 Stop the Program

Table: BCD to Binary

BCD 8200( I/P) Binary 8300 (O/P) BCD 8200( I/P) Binary 8300 (O/P)

22 16

40 28

15 0F

54 36

75 4B

92 5C

0B 0B

FF A5

0C 0D

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8500 XRA A AF Clear Accumulator

8501 LXI H 8200 21,00,82 Initialize memory pointer

8504 MOV A , M 7E Get HEX data

8505 MVI D , FF 16,FF Move D- Reg. for Most significant Byte

8507 MVI B , 64H 06, 64 Move the data with 64

8509 (L1)INR D 14 Increment Reg. D

850A SUB B 90 Subtract the data in Reg. B

850B JNZ (L1) D2,09,85 Jump on non-zero to label loop

850E ADD B 80 Add ‘A’ and ‘B’

850F MVI C , FF 0E,FF Move the data FF in Reg. A

8511 MVI E , 0AH 1E,0A Compare the Reg. E with OA

8513 (L2) INR C 0C Increment Reg. C

8514 SUB E 93 Subtract Reg. E with Reg. A

8515 JNC (L2) D2,13,85 Jump on no carry to label loop

8518 ADD E 83 Add Reg. E

8519 STA 8300 32,00,83 Store the data in specific memory

851C MOV A , C 79 Move the data from Reg. C to Reg. A

851D STA 8301 32,01,83 Store the data in memory

8520 MOV A , D 7A Move the data from Reg. D to Reg. A

8521 STA 8302 32,02,83 Store the data in memory

8524 HLT 76 Stop the process

I/P (8200) 100’S(8302) 10’S(8301) 1’S (8300) EQUIVALANT

2B 00 04 03 43

0A 00 01 00 10

5A 00 09 00 90

60 00 09 06 96

5F 00 09 05 95

Result:

Thus the BCD to Binary, Binary to BCD conversion was executed successfully using

microprocessor 8085 kit.

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Exp. No

8-BIT ADDITION AND SUBTRACTION

Date

AIM:

To write and execute an assembly language program to perform the addition and

subtraction two eight bit numbers using 8085 kit.

a) ADDITION

ALGORITHM:

Step 1: Start.

Step 2: Clear C register for carry

Step 3: Load the first data from memory to accumulator and move it to B register.

Step 4: Load the second data from memory to accumulator.

Step 5: Add the content of B register to the accumulator.

Step 6: Check for carry. If carry = 1, go to step 7 else if carry =0, go to step 8.

Step 7: Increment the C register.

Step 8: Store the sum in memory

Step 9: Move the carry to accumulator and store in memory

Step 10: End Program

b) SUBTRACTION:

ALGORITHM:

Step 1: Start.

Step 2: Clear C register to account for sign of the result.

Step 3: Load the subtrahend (the data to be subtracted) from memory to accumulator and move it

to B register.

Step 4: Load the minuend from memory to accumulator.

Step 5: Subtract the content of B register from the content of the accumulator.

Step 6: Check for carry. If carry = 1, go to step 7 else if carry =0, go to step 8.

Step 7: Increment the C register. Complement the accumulator and add 01H.

Step 8: Store the difference in memory.

Step 9: Move the content of C register (sign bit) to accumulator and store in memory.

Step 10: End program

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8100 LDA 8200H 3A, 00,82 Load the 8 bit data in HL pair

8103 MOV B, A 47 Move the Reg. A to Reg. B

8104 LDA 8201H 3A, 01, 82 Load the 8 bit data in HL pair

8107 MVI C, 00H 0E, 00 Clear Reg. C

8109 ADD B 80 [A] = [A] + [B]

810A JNC (L) D2, 0E, 81 Jump on no zero to label loop

810D INR C 0C Increment Reg. C

810E (L) STA 8500 32, 00, 85 Store the first bit in 8500

8110 MOV A, C 79 Move the data in Reg. C to Reg. A

8111 STA 8501 32, 01, 85 Store the second bit in 8501

8114 HLT 76 Stop the Program

8200 H 8201 H 8500 H 8501 H

02 06 08 00

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

8100 MVI C, OO 0E, 00 Initialize Reg. C to 00

8102 LDA 8200 H 3A, 00, 82 Load the data in HL pair

8105 MOV B, A 47 Move the data Reg. A to Reg. B

8106 LDA 8201 H 3A, 01, 82 Load the data in HL pair

8109 SUB B 90 [A] = [A] – [B]

810A JNC (L) D2, 10, 81 Jump on no carry to label loop

810D INR C 0C Increment Reg. C

810E CMA 2F Compare to Reg. A

810F INR A 3C Increment Reg. A

8110 (L) STA 8500 32, 00, 85 Store the first bit data in 8500

8113 MOV A, C 79 Move the data in Reg. C to Reg. A

8114 STA 8501 H 32, 01, 85 Store the second bit data in 8501

8117 HLT 76 Stop the Process

8200 H 8201 H 8500 H 8501 H

AF EF 40 00

RESULT:

An assembly language program to perform the addition and subtraction two eight bit

numbers using 8085 kit is written and executed.

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Exp. No

NAND, NOR as universal gates

Date

Aim: Realization of logic functions with the help of universal gates-NAND Gate

Apparatus:

logic trainer kit, NAND gates (IC 7400), wires.

Theory:

NAND gate is actually a combination of two logic gates: AND gate followed by NOT

gate. So its output is complement of the output of an AND gate.

This gate can have minimum two inputs, output is always one. By using only NAND

gates, we can realize all logic functions: AND, OR, NOT, X-OR, X-NOR, NOR. So this gate is

also called universal gate.

A NOT produces complement of the input. It can have only one input, tie the inputs of a

NAND gate together. Now it will work as a NOT gate. Its output is

Y=𝑨

A NAND produces complement of AND gate. So, if the output of a NAND gate is

inverted, overall output will be that of an AND gate.

Y=A.B

From De-Morgan’s theorems: (A.B)’ = A’ + B’

=> (A’.B’)’ = A’’ + B’’ = A + B

So, give the inverted inputs to a NAND gate, obtain OR operation at output.

Y=A+B

NOR gates as NOT gate

A NOT produces complement of the input. It can have only one input, tie the inputs of a

NOR gate together. Now it will work as a NOT gate. Its output is

Y=𝑨

NOR gates as OR gate

A NOR produces complement of OR gate. So, if the output of a NOR gate is inverted,

overall output will be that of an OR gate.

Y = (A+B)

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

=> ̿̿̿̿̿̿̿̿

𝐴 + 𝐵 = 𝐴̿ . 𝐵̿ = A B

So, give the inverted inputs to a NOR gate, obtain AND operation at output.

Y=A+B

A Y=𝑨

A B Y=A.B

A B Y=A+B

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

A Y=𝑨

A B Y=A+B

A B Y=A.B

Result:

The Universal logic gates were constructed and verify their truth tables.

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Exp. No

RS, Clocked RS, and D Flip Flops using NAND gate

Date

AIM:

To Setup the following flip flops using NAND gates and verify the truth table also familiarize

the flip flop ICs

3. D flip flop

COMPONENTS REQUIRED:

PRINCIPLE:

Flip flops are the basic building blocks in any memory systems since its output will

remain in its state until it is forced to change it by some means

S=R FLIP FLOP and stands for set and reset. There are four input combination possible

at the inputs. But 𝑆 = 𝑅 = 1 is forbidden since the output will be indeterminate

The SET-RESET flip flop is not designed with the help of two NOR gates and also two

NAND gates. These flip flops are also called S-R Latch.

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The design of such a flip flop includes two inputs, called the SET [S] and RESET [R].

There are also two outputs, Q and Q’.

S R Q 𝑸 COMMENTS

0 0 1 1 Invalid(Not allowed)

0 1 1 0 Set

1 0 0 1 Reset

1 1 X X No change

From the diagram it is evident that the flip flop has mainly four states. They are

S=1, R=0 → Q=1, Q’=0 This state is also called the SET state.

S=0, R=1 → Q=0, Q’=1 This state is known as the RESET state.

This is an invalid state because the values of both Q and Q’ are 0. They are supposed to be

compliments of each other. Normally, this state must be avoided.

If both the values of S and R are switched to 0, then the circuit remembers the value of S and R

in their previous state.

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It is also called a Gated S-R flip flop. The problems with S-R flip flops using NAND gate

is the invalid state. This problem can be overcome by using a bistable SR flip-flop that can

change outputs when certain invalid states are met, regardless of the condition of either the Set or

the Reset inputs. For this, a clocked S-R flip flop is not designed by adding two AND neither

gates to a basic NOR does Gate flip flop.

CLK S R Q 𝑸 Comments

0 1 1 X X No change

1 0 0 X X No change

1 0 1 1 0 Reset

1 1 0 0 1 Set

1 1 1 1 1 Invalid

A clock pulse [CP]is given to the inputs of the AND Gate. When the value of the clock

pulse is ’0′, the outputs of both the AND Gates remain ’0′. As soon as a pulse is given the value

of CP turns ’1′. This makes the values at S and R to pass through the NOR Gate flip flop. But

when the values of both S and R values turn ’1′, the HIGH value of CP causes both of them to

turn to ’0′ for a short moment. As soon as the pulse is removed, the flip flop state becomes

intermediate..

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

D Q 𝑸 Comments

X X X

0 0 1 Reset

1 1 0 Set

D flip flop is actually a slight modification of the above explained clocked SR flip-flop.

From the figure you can see that the D input is connected to the S input and the complement of

the D input is connected to the R input. The D input is passed on to the flip flop when the value

of CP is ’1′. When CP is HIGH, the flip flop moves to the SET state. If it is ’0′, the flip flop

switches to the CLEAR state.

Result:

The flip flops RS flip flop, Clocked (Gated) RS flip flop and D flip flops were set up

using NAND gates and their truth tables are verified.

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Exp. No

Date SHIFT REGISTERS

Aim: To study IC 7473/7476, and the realization of shift operations using the same.

Components required: IC 7473/7476, Digital IC Trainer kit etc.

Theory:

• A shift register is a group of flip-flops (typically 4 or 8) that are arranged so that the values

stored in the flip-flops are shifted from one flip-flop to the next for every clock.

• Shift registers are used extensively in logic circuits to control digital displays.

• A classic example is numbers being typed into a calculator. As the numbers are entered, the

digits shift to the left one position. This shifting is controlled by a shift register.

Procedure:

1. Connections are made as shown in the SIPO circuit diagram.

2. On applying the first bit of data and then a clock pulse, it can be observed that this data

appears at (Q3).

3. Now, applying the second bit of data and a clock pulse, the bit at Q3 shifts to Q2 and Q3 will

be loaded with the new data.

4. This repeats until all 4 data bits are loaded.

5. At the end of the 4th clock pulse, all 4 bits are available at the parallel output pins Q3 through

Q0.

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Circuit Diagram:

Truth Table:

CLK Q3 Q2 Q1 Q0

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 0 0 0 0

Result:

The performances of shift registers are set up and studied using IC 7473/7476.

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Exp. No

4-BIT RIPPLE COUNTER

Date

Aim:

Principle:

Ripple Counter:

Ripple counter is an asynchronous counter. So clock pulse is given to any one of the flip

flop and output of the flip flop is from 0000 to 1111.

In order to make a mod 10 counter, the counter should be reset to 0000 after reaching

1001. To achieve this, we can use a NAND gate whose inputs are the outputs of third and first

flip flop so that when both of them are ‘1’, flip flops will be cleared.

Then by using the BCD 7 segment decoder IC, we will produce the outputs, which are the

inputs of 7-segment display.

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Result:

Thus 4 bit Ripple Counter was constructed and verified with their truth table.

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Exp. No

Field Effect Transistor (FET)

Date

Aim:

To study Drain Characteristics and Transfer Characteristics of a Field Effect Transistor (FET).

Components:

1 JFET (BFW11/ BFW10) 1(One) No.

2 Resistor (1K ,100K ) 1(One) No. Each

3 Bread board 1(One) No.

4 Dual DC Regulated Power supply (0 - 30 V) 1(One) No.

5 Digital Ammeters ( 0 - 200 mA) 1(One) No.

6 Digital Voltmeter (0 - 20V) 2(Two) No.

7 Connecting wires (Single Strand)

Specifications:

Forward Gain Current IGF = 10mA

Maximum Power Dissipation PD = 300mW

Circuit Diagram:

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Top View

Bottom View

Operation:

The circuit diagram for studying drain and transfer characteristics is shown in the figure1.

1. Drain characteristics are obtained between the drain to source voltage (VDS) and drain

current (ID) taking gate to source voltage (VGS) as the constant parameter.

2. Transfer characteristics are obtained between the gate to source voltage (VGS) and drain

current (ID) taking drain to source voltage (VDS) as the constant parameter.

Procedure:

Drain Characteristics:

2. Keep VGS = 0V by varying VGG.

3. Varying VDD gradually in steps of 1V up to 10V note down drain current ID and drain to

source voltage (VDS).

4. Repeat above procedure for VGS = -1V.

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Transfer Characteristics:

2. Set voltage VDS = 2V/5V (BFW10/ BFW11).

3. Varying VDD in steps of 0.5V until the current ID reduces to minimum value.

4. Varying VGG gradually, note down both drain current ID and gate-source voltage (VGS).

5. Repeat above procedure (step 3) for VDS = 4V/ 8V (BFW10/ BFW11).

Observations:

Drain Characteristics

VGS = 0V VGS = -1V

VDD (Volts) VDS(Volts) ID(mA) VDS(Volts) ID(mA)

Transfer Characteristics

VDS = 2V/5V VDS = 4V/8V

VGG (Volts) VGS(Volts) ID(mA) VGS(Volts) ID(mA)

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Graph:

1. Plot the drain characteristics by taking VDS on X-axis and ID on Y-axis at a constant VGS.

2. Plot the transfer characteristics by taking VGS on X-axis and taking ID on Y-axis at

constant VDS.

1. Drain Resistance (rd): It is given by the relation of small change in drain to source

voltage( VDS) to the corresponding change in Drain Current( ID) for a constant gate to

source voltage ( VGS), when the JFET is operating in pinch-off region.

∆𝑟𝑟𝑟

𝑟𝑟 = at a constant VGS (from drain characteristics)

∆𝑟𝑟

2. Trans Conductance (gm): Ratio of small change in drain current ( ID) to the

corresponding change in gate to source voltage ( VGS) for a constant VDS.

∆𝑟

𝑟𝑟 = ∆𝑟 𝑟 at constant VDS (from transfer characteristics).

𝑟𝑟

3. Amplification factor (µ): It is given by the ratio of small change in drain to source

voltage ( VDS) to the corresponding change in gate to source voltage ( VGS) for a

constant drain current (ID).

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Inference:

1. As the gate to source voltage (VGS) is increased above zero, pinch off voltage is increased

at a smaller value of drain current as compared to that when VGS = 0V.

2. The value of drain to source voltage (VDS) is decreased as compared to that when VGS =

0V.

Precautions:

1. While performing the experiment do not exceed the ratings of the FET. This may lead to

damage of FET.

2. Connect voltmeter and ammeter with correct polarities as shown in the circuit diagram.

3. Do not switch ON the power supply unless the circuit connections are checked as per the

circuit diagram.

4. Properly identify the Source, Drain and Gate terminals of the transistor.

Result:

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Exp. No

Uni Junction Transistor (UJT) Characteristics

Date

Aim:

Components:

1. UJT 2N 2646 1(One) No.

2. Resistors (1 K Ohm) 2(Two) No.

3. Bread board 1(One) No.

4. Dual DC Regulated Power supply (0 - 30 V) 1(One) No.

5. Digital Ammeters ( 0 - 200 mA) 1(One) No.

6. Digital Voltmeter (0 - 20V) 2(Two) No.

7. Connecting wires (Single Strand)

Specifications:

Continuous emitter current (IE) = 50mA

Inter Base Voltage (VBB) = 35V

Emitter Base Reverse Voltage (VEB2) = -30V

Power dissipation at 25°C = 300mW

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Circuit Diagram:

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Operation:

The UJT- junction is a 3 - terminal solid-state device (emitter and the two bases). The simplified

equivalent circuit is shown below:

The device has only one PN junction and hence it is known as UNI-JUNCTION transistor. The

PN emitter to base junction is shown as diode D1. The inter base resistance R BB of the N-type Si

bar appears as two resistors RB1 and RB2.

1. When no voltage is applied between B1 and B2 with emitter open, the inter base

resistance is give by RBB = RB1 + RB2.

2. When a voltage VBB is applied between B1 and B2 with emitter open, voltage will divide

up across RB1 and RB2.

The VBB across RB1 reverse biased diode thereby dropping the emitter current to zero.

3. When supply is connected at the emitter, the diode is forward biased making the input

voltage to exceed by VD %u200BVp = VBB + Vb

Since the diode is conducting, the resistance between emitter and base (B1) reduces and hence

the internal drop from emitter to B1 decreases.

The emitter conductivity characteristics are such that as IE increases the emitter to base (B1)

voltage decreases. At a peak point Vp and the valley point Vv, the slope of the emitter

characteristics is 0. At points to the left of VB to E-B1 is forward biased and IE exists. Between

Vp and Vv increase in IE is accompanied by a relation in emitter voltage VE. This is the negative

resistance region of UJT. Beyond the valley point Vv an increase in IE is accomplished by an

increase in VE. This region is known as the saturation region.

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Procedure:

2. Set output voltage VBB1 = 5V by varying VBB.

3. Varying VEE gradually, note down both emitter current IE and emitter voltage (VE).

4. Step size is not fixed because of non linear curve. Initially Vary VEE in steps of 1V.

Current IE remains zero. As voltage is varied further, current starts increasing while

voltage VE drops. Note down the readings VE and IE.

5. Repeat above procedure (step 3) for VBB1 = 10V.

Observations:

IE(mA) VE(V) IE(mA) VE(V)

Expected graph:

Plot the tabulated readings on a graph sheet with IE on X-axis and VE on Y-axis.

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Inference:

2. Increase in VBB1 increases the value of peak and valley voltages.

Precautions:

1. While performing the experiment do not exceed the ratings of the UJT. This may lead to

damage of the UJT.

2. Connect voltmeter and ammeter in correct polarities as shown in the circuit diagram.

3. Do not switch ON the power supply unless you have checked the circuit connections as

per the circuit diagram.

4. Make sure while selecting the emitter, base-1, base-2 terminals of UJT.

Result:

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Exp. No

EMITTER FOLLOWER

Date

AIM:

To construct an emitter follower circuit and

(i) Measure the gain

(ii) Plot its input and output waveforms

OBJECTIVES:

On completion of the experiment students will be able to

COMPONENTS:

Resistors (1K, 2.2K, 10K, 22K, 33K), Capacitor 1 μF , Transistor BC 107, Function

generator 0 to 1 MHz, Oscilloscope 0 to 20 MHz, Multimeter, etc.

PRINCIPLE:

Emitter follower is the popular name for common collector amplifier. Its voltage gain is

approximately unity (without RL voltage gain is unity). It has high input impudence and low

output impedance. Thus emitter follower has less loading effect and is suitable for impedance

matching.

Since collector is directly connected to dc source, it appears to be grounded for ac signal.

Output is taken from the emitter terminal. The output voltage is in phase and is equal to the input

signal. Since the amplitude and phase of the output (emitter) follows the input (base), the circuit

is called emitter follower. In this circuit voltage divider biasing is used for base bias. RE acts as

the load for signal at the output circuit.RE also provides a negative feedback in the circuit.

PROCEDURE

1) Test the components

2) Assemble the circuit

3) Measure the dc condition using multimeter and verify whether the transistor is in active region

4) Apply 1Vpp,1 KHz sinusoidal signal as input

5) observe the voltages at input point (Vin), at base, at emitter and at the output point (VO)

without RL

6) Measure the amplitudes and dc levels

7) Plot the waveforms

8) Observe and measure VO with RL = 10 KΩ and RL = 1KΩ

9) Calculate the voltage gain for the above three conditions of RL

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

CIRCUIT DIAGRAM:

OBSERVATIONS

1. DC Condition (multimeter)

VCC =

VCE =

VBE =

Note : At proper biased condition, VBE should be 0.6V to 0.7V, VCE should be approximately

half of VCC

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

3. Voltage gain

(i) Without load (RL = ∞)

VO = 1V

𝑉

Gain =𝑉 0 = 1

𝑖𝑛

VO =

Gain =

VO =

Gain =

RESULT:

calculated.

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Date response

Aim:

To design inverting amplifier for a given the frequency gain response of an op-amp

amplifier.

Apparatus:

IC 741, Resistors, Multimeter, CRO, Probes,

Procedure:

1. Rig up the circuit as shown in figure.

2. Connect the Vcc, VEE supply as +15V and -15V carefully to the respective pins of the

IC - μA 741

3. Set the suitable frequency & amplitude in the source (Vsin) to get the distortion less output.

Note down the amplitude of the input signal.

4. Keeping the input amplitude constant, Vary the frequency in suitable steps and note down the

corresponding output amplitude.

5. Calculate AV and gain in decibels. Plot a graph of frequency Vs gain in dB. From the graph

calculate f L, f H and band width.

Design:

Inverting amplifier:

Given Gain Value Av =1

R1 = 10KΩ

C1=C2=0.1μF

𝑅2

𝐴𝑣 =

𝑅1

Therefore R2 = 10KΩ.

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

Ideal Graph:

Circuit Diagram:

Sri Bharathi Women’s Arts & Science College, Kunnathur, Arni – 632 314

ii) The mid frequency gain of the amplifier = ____________________ (from graph)

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