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CMOS IC
LC7940YC,7941YC
Overview
The LC7940YC and LC7941YC are segment driver ICs
for driving large, dot–matrix LCD displays. They read 4–
bit parallel or serial input, display data from a controller
into an 80–bit latch, and then generate LCD drive signals
corresponding to that data.
The LC7940YC and LC7941YC feature mirror–image pin
assignments, allowing them to be used together to increase
component density. They are designed to be used with the
LC7942YC common driver to drive large LCD panels.
Features
• 80 built–in LCD display drive circuits
• 1/8 to l/128 display duty cycle
• Serial or 4–bit parallel data input
• Chip disable for low power dissipation for large–sized
panels
• Bias supply voltags can be supplied externally
• Operating supply voltage and ambient temperature
- 2.7 to 5.5 V logic supply ( VDD) at Ta = –20 to +85°C
- 8 to 20V LCD supply (VDD – VEE ) at Ta = –20 to
+85 °C
• CMOS process
Specifications
The following electrical characteristics apply when sealed in a Sanyo standard QIC-100 package.
■ Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
■ SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
Ratings
Parameter Symbol Conditions Unit
min typ max
Logic supply voltage VDD 2.7 – 5.5 V
LCD supply voltage VDD – VEE See Notes 1 and 2. 8 – 20 V
CP, CDl, DI1 to DI3, M,
HIGH–level input voltage VIH SDl, P/S, DISPOFF and 0.8VDD – – V
LOAD
CP, CDI, Dl1 to DI3, M,
LOW–level inpvt voltage VIL SDl, P/S,DISPOFF and – – 0.2VDD V
LOAD
CP shift clock frequency fCP – 3.3 MHz
CP pulsewidth tWC 100 – – ns
LOAD pulsewidth tWL 100 – – ns
DIn and SDI to CP setup time tSETUP 80 – – ns
DIn and SDI to CP hold time tHOLD 80 – – ns
tCL1 0 – – ns
CP to LOAD time
tCL2 100 – – ns
LOAD to CP time tLC 100 – – ns
CP rise time tR – – 50 ns
CP fall time tF – – 50 ns
LOAD rise time tRL – – 50 ns
LOAD fall time tFL – – 50 ns
Notes
1. VDD ≥ Vl > V3 > V4 > VEE
2. At turn ON, the LCD supply should be energized after or simultaneously with the logic supply. At turn OFF, the logic supply
should be cut after or simultaneously with the LCD supply.
Ratings
Parameter Symbol Conditions Unit
min typ max
VIN =VDD; LOAD, CP, CDI,
HIGH–level input current IIH P/S, DI1 to DI3, SDl, M, – – 1 µA
and DISPOFF
VIN = VSS; LOAD, CP,
LOW–level input current IIL CDl, P/S, DI1 to DI3, SDI, – – –1 µA
M, and DISPOFF
CDO HIGH–level output voltage VOH IOH = –400 µA VDD – 0.4 – – V
CDO LOW–levef output voltage VOL IOL = 400 µA – – 0.4 V
VDD – VEE = 18 V,
O1 to O80 driver ON resistance RON |VDE – VO|= 0.25 V. – 2 4 kΩ
See note
No. 6157—2/13
LC7940YC, LC7941YC
Ratings
Parameter Symbol Conditions Unit
min typ max
CDI = VDD,
VDD – VEE = 18 V,
VDD to VSS standby supply current IST – – 200 µA
fCP = 3.3 MHz,
no output load ; VSS
VDD – VEE = 18 V,
fCP = 3.3 MHz,
VDD to Vss operating supply current ISS – – 1.0 mA
ILOAD= 5.156 kHz,
fM = 52 Hz ;VSS
VDD – VEE = 18V,
fCP = 3.3 MHz,
VDD to VEE operating supply current IEE – – 0.1 mA
fLOAD = 5,156 kHz,
fM = 52 Hz ; VEE
CP input capacitance CI fCP = 3.3 MHz ; CP – 5 – pF
Note
VDE = V1 or V3, or V4 or VEE, V1 = VDD, V3 = 9/11 × (VDD – VEE), V4 = 2/11 × (VDD – VEE)
Ratings
Parameter Symbol Conditions Unit
min typ max
CDO output delay time tD CL = 30 pF – – 200 ns
tWC tWC
tR tF
0.8VDD
CP
0.2VDD
tSET
UP tHOLD
SDI
DI1 to 3
tLC
LOAD
tWL
tD tD
CDO
No. 6157—3/13
LC7940YC, LC7941YC
DISPOFF
LOAD
CDO
CDI
SDI
P/S
DI3
DI2
DI1
VDD
VEE
VSS
CP
V1
V3
V4
O1 O80
O2 O79
O3 O78
O4 O77
O5 O76
O6 O75
O7 O74
O8 O73
O9 O72
O10 O71
O11 O70
O12 O69
O13 O68
O14 O67
O15 LC7940YC O66
O16 O65
O17 O64
O18 O63
O19 O62
O20 O61
O21 O60
O22 O59
O23 O58
O24 O57
O25 O56
O26 O55
O27 O54
O28 O53
O29 O52
O30 O51
O31
O32
O33
O34
O35
O36
O37
O38
O39
O40
O41
O42
O43
O44
O45
O46
O47
O48
O49
O50
DISPOFF
LOAD
CDO
CDI
SDI
VDD
P/S
DI1
DI2
DI3
VSS
VEE
CP
M
V4
V3
V1
O80 O1
O79 O2
O78 O3
O77 O4
O76 O5
O75 O6
O74 O7
O73 O8
O72 O9
O71 O10
O70 O11
O69 O12
O68 O13
O67 O14
O66 LC7941YC O15
O65 O16
O64 O17
O63 O18
O62 O19
O61 O20
O60 O21
O59 O22
O58 O23
O57 O24
O56 O25
O55 O26
O54 O27
O53 O28
O52 O29
O51 O30
O50
O49
O48
O47
O46
O45
O44
O43
O42
O41
O40
O39
O38
O37
O36
O35
O34
O33
O32
O31
No. 6157—4/13
LC7940YC, LC7941YC
No. 6157—5/13
LC7940YC, LC7941YC
No. 6157—6/13
LC7940YC, LC7941YC
Block Diagram
01 02 03 079 080
V1
V3 4 Level LCD Drive Circuit VDD
M 80 DISP OFF
80
1st Latch (80 bits)
4 20
SDI
4 bits Address Decoder
DI3 CLK
Data Bus
DI2
Interface Address Counter
DI1 (7 bits)
CP
LOAD
Pin Functions
Pin No.
Symbol I/O Function
LC7940YC LC7941YC
91 90 VDD
VDD – VSS is the logic supply.
86 95 VSS Supply
VDD – VEE is the LCD supply.
87 94 VEE
92 89 V1
LCD panel drive voltage supplies
89 92 V3 Supply V1 and VEE are selected levels.
V3 and V4 are not–selected levels.
88 93 V4
l00 81 CP I Display data Input clock (falling–edge trigger).
Chip disable.
99 82 CDI I
Data is read in when LOW, and not road in when HIGH.
Display data latch clock (falling–edge trigger).
98 83 LOAD I
On the falling edge, the LCD drive signals set by the display data are output.
97 84 SDI I Serial data input.
96 85 DI3 4–bit parallel data input pins.
95 86 DI2 Data input LCD driver outputs
SDI O4 O8 O80
I DI3 O3 O7 O79
94 87 D11 DI2 O2 O6 O78
DI1 O1 O5 O77
In serial data input mode, DI1 to DI3 should all be tied HIGH or LOW.
No. 6157—7/13
LC7940YC, LC7941YC
Pin No.
Symbol I/O Function
LC7940YC LC7941YC
93 88 M I LCD panel drive voltage output alternation control signal.
85 96 P/S I Data input mode select. 4–bit parallel input when HIGH, and serial input when LOW
Cascade connection pin for extension segment drivers. Data is read out when HIGH.
82 99 CDO O
Goes LOW after data is read out. Connected to the CDI input of the next chip.
LCD drive outputs.
The output drive level is determined by the display data, M signal and DISP OFF
input as shown below.
Note
x = don’t care (tied HIGH or LOW)
O1 to O80 output control input pin.
84 97 DISPOFF I
When LOW, V1 is output on the O1 to 080 outputs, See the truth table.
81 91 NC
83 98 NC – No connection.
90 100 NC
No. 6157—8/13
2
OD1 ED1
CP
LOAD
4
LCD Panel 1
CP CP CP CP
SDI SDI SDI SDI
M V1 V3 LOAD M V1 V3 LOAD M V1 V3 LOAD M V1 V3 LOAD
M V1 V3 M V1 V3 M V1 V3 M V1 V3
OD1
V4 VEE V4 VEE V4 VEE V4 VEE
ED1 (LC7940YC) CDI CDO (LC7940YC) CDI CDO (LC7940YC) CDI CDO (LC7940YC) CDI
LC7941YC LC7941YC LC7941YC LC7941YC
FLM
DI01
controller M M 01
2
1
640
639
482
481
480
479
322
321
320
319
162
161
160
159
LC7942YC
CL1 CP 064
DI064
CL2 V1 V2
V5 VEE 100
OD2
DI01
M 01
LC7942YC
LC7940YC, LC7941YC
962
961
960
959
802
801
800
799
642
641
CP 036
1280
1279
1122
1121
1120
1119
VDD
V1
V1 V2
LA5311M V5 VEE LC7940YC LC7940YC LC7940YC LC7940YC
R V2
–
+ (LC7941YC) (LC7941YC) (LC7941YC) (LC7941YC)
6 4
R V3
–
+ M M M M CP
SDI
4 V1 V3 V1 V3 V1 V3 V1 V3 LOAD
7R V4
– LC7941YC V4 VEE LC7941YC V4 VEE LC7941YC V4 VEE LC7941YC V4 VEE
+
R V5 V1 V3
– V4 VEE
+
R 4 4
M
LOAD
VEE CP
OD2 ED2
–11 to –13V
No. 6157—9/13
4
LCD Panel 2
2 4 2 4 2 4 2 4
M V1 V3
V4 VEE CP
LOAD
4bit Data
CDO
4bit Data LC7941YC-#8 LC7941YC-#2 LC7941YC-#1 CDI
080 01
FLM
DI01
controller M M 01
LOAD CP 064
LC7942YC-#1
CP
100
100
DI01
M 01
CP 036
LC7940YC, LC7941YC
VDD
LC7942YC-#2
V1
V1 V2
LA5311M V5 VEE
R V2
–
+ CDO 080 01 CDI
6 4
R V3 4bit Data
–
+
7R 4 CP LOAD
– V4
LC7941YC-#8 LC7941YC-#2 LC7941YC-#1
+
V1 V3 2 4 2 4 2 4 V1 V3 2 4
R V5 M
– V4 VEE
+ V4 VEE 4
R 4
VEE
–11 to –13V
4
No. 6157—10/13
LC7940YC, LC7941YC
DI01 01 1,1 1,2 1,79 1,80 1,81 1,82 1,160 1,161 1,240
--- --- ---
RS/LS 02 2,1 2,2 2,240
LC7942YC
LCD Panel (100 × 240 pixels)
---
---
---
#1
---
CP
M 063 63,1 63,2
DI064 064 64,1 64,2 --- 64,80 64,81 --- 64,160 64,161 --- 64,240
DI01 01 65,1 65,2 65,80 65,81 65,160 65,161 65,240
66,1 66,2
--- --- ---
RS/LS 02
LC7942YC
---
---
---
---
#2
CP
M 100,1 100,2 --- 100,79 100,80 100,81 100,82 --- 100,160 100,161 --- 100,240
036
DI064
O37 to O64
are open.
01 02 079 080 01 02 080 01 080
LOAD
LOAD
SDI
SDI
SDI
P/S
P/S
P/S
DI1
DI2
DI3
DI1
DI2
DI3
DI1
DI2
DI3
CP
CP
CP
M
M
Alternating signal
Data latch clock
Serial Data
Data Shift
clock
No. 6157—11/13
LC7940YC, LC7941YC
LOAD
CP
SDI 1,1 1,2 --- 1,79 1,80 1,81 --- 1,160 1,161 --- 1,240
#1
SDO #2
#3
Chip 1 data read Chip 2 data read Chip 3 data read
LOAD
CP
SDI 1,1 1,2 --- 1,239 1,240 2,1 --- 2,240 3,1 --- 100,240
#1 DIO1
LOAD
01 1,1 2,1 --- 98,1 99,1 100,1 1,1 --- 99,1 100,1
02 1,2 2,2 --- 98,2 99,2 100,2 1,2 --- 99,2 100,2
#1
01 1,81 2,81 --- 98,81 99,81 100,81 1,81 --- 99,81 100,81
---
#2
080 1,160 2,160 --- 98,160 99,160 100,160 1,160 --- 99,160 100,160
01 1,161 2,161 --- 98,161 99,161 100,161 1,161 --- 99,161 100,161
---
#3
080 1,240 2,240 --- 98,240 99,240 100,240 1,240 --- 99,240 100,240
No. 6157—12/13
LC7940YC, LC7941YC
--- ---
01 080 01 080 01 070
LOAD
SDI m,1 m,2 --- ,228 m,229 m,230 m+1,1 m+1,2 ,228 m+1,229 m+1,230
If this timing data is sent, data elements (m, 229), (m, in 4–bit units, which also decreases power dissipation . For
230), (m+1, 229), (m+1. 230)... will not appear in the data that is not a multiple of 4, like 230, the following
output (O69 and O70 on chip 3). This is because the scheme is used.
LC7940YC (or LC7941YC) converts serial/parallel data
LOAD
Multiple of 4
■ Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
■ SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could give
rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that
could cause damage to other property. When designing equipment, adopt safety measures so that these
kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits
and error prevention circuits for safe design, redundant design, and structural design.
■ In the event that any or all SANYO products(including technical data,services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products
must not be exported without obtaining the export license from the authorities concerned in accordance
with the above law.
■ No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or
otherwise, without the prior written permission of SANYO Electric Co. , Ltd.
■ Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for
the SANYO product that you intend to use.
■ Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no
guarantees are made or implied regarding its use or any infringements of intellectual property rights or
other rights of third parties.
This catalog provides information as of June, 1999. Specifications and information herein are subject to
change without notice.
No. 6157—13/13