PERCOBAAN 1

GERBANG-GERBANG LOGIKA (AND,OR,NOT,NAND.NOR,EXOR)

Percobaan 1:

A. IC 7408 (AND)
INPUT OUTPUT
A B X
0 0 0
0 1 0
1 0 0
1 1 1

B. IC 7432 (OR)
INPUT OUTPUT
A B X
0 0 0
0 1 1
1 0 1
1 1 1

C. IC 7404 (NOT)
INPUT OUTPUT
A X
0 1
1 0

D. IC 7437 (NAND)
INPUT OUTPUT
A B X
0 0 1
0 1 1
1 0 1
 1 1 0

E. IC 7402 (NOR)
INPUT OUTPUT
A B X
0 0 1
0 1 0
1 0 0
1 1 0

F. IC 7486 (EX-OR)
INPUT OUTPUT
A B X
0 0 0
0 1 1
1 0 1
1 1 0

Percobaan 2 :
IC 7411 & 7408
INPUT OUTPUT
B0 B1 B2 OUTPUT X OUTPUT Y OUTPUT Z
0 0 0 0 0 0
0 0 1 0 0 0
0 1 0 0 0 0
0 1 1 0 0 0
1 0 0 0 0 0
1 0 1 0 0 0
1 1 0 0 0 0
1 1 1 1 1 1
Percobaan 3 :
INPUT OUTPUT
B0 B1 B2 OUTPUT X OUTPUT Y OUTPUT Z
0 0 0 0 0 0
0 0 1 1 1 1
0 1 0 1 1 1
0 1 1 1 1 1
1 0 0 1 1 1
1 0 1 1 1 1
1 1 0 1 1 1
1 1 1 1 1 1

Percobaan 4 :
INPUT OUTPUT
B0 OUTPUT X
0 1
1 0

Percobaan 5 :
INPUT OUTPUT
B0 B1 OUTPUT X
0 0 1
0 1 1
1 0 1
1 1 0

Percobaan 6 :
INPUT OUTPUT
B0 B1 OUTPUT X
0 0 1
0 1 0
1 0 0
1 1 0
Percobaan 7 :
INPUT OUTPUT
B0 B1 OUTPUT X
0 0 0
0 1 1
1 0 1
1 1 0
 PERCOBAAN 2

RANGKAIAN MULTILEVEL NAND DAN NOR

Percobaan 1 :

Tabel kebenaran
INPUT OUTPUT
B0 B1 L
0 0 0
0 1 1
1 0 1
1 1 0

H= B0 . BI + B0 . B1

Rangkaian Padanan

Percobaan 2 :
Padanan NAND

Padanan NOR

Tabel kebenaran
INPUT OUTPUT
A B C D L NAND NOR
0 0 0 0 0 0 0
0 0 0 1 0 0 0
0 0 1 0 0 0 0
0 0 1 1 1 1 1
0 1 0 0 0 0 0
0 1 0 1 0 0 0
0 1 1 0 0 0 0
0 1 1 1 1 1 1
1 0 0 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 0 0 0
 1 0 1 1 1 1 1
1 1 0 0 1 1 1
1 1 0 1 1 1 1
1 1 1 0 1 1 1
1 1 1 1 1 1 1

Percobaan 3 :

Konversi NAND

Konversi NOR
Tabel kebenaran
INPUT OUTPUT
A B C D L NAND NOR
0 0 0 0 0 0 0
0 0 0 1 0 0 0
0 0 1 0 0 0 0
0 0 1 1 1 1 1
0 1 0 0 0 0 0
0 1 0 1 0 0 0
0 1 1 0 0 0 0
0 1 1 1 1 1 1
1 0 0 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 0 0 0
1 0 1 1 1 1 1
1 1 0 0 0 0 0
1 1 0 1 1 1 1
1 1 1 0 0 0 0
1 1 1 1 1 1 1
 PERCOBAAN 3

RANGKAIAN DASAR DAN PENYEDERHANAAN BOOLEAN

Percobaan 1 :

a) Table kebenaran
INPUT OUTPUT
B0 B1 L
0 0 1
0 1 0
1 0 0
1 1 1

H= B0 . B1 + B0.BI

Gambar rangkaian menggunakan gerbang AND dan OR

b) H= (AB+ A C)BC+ A BC+ A B

C B A AB A C AB+ A C (AB+ A C) A BC A B H

BC
0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 1 1
0 1 1 1 0 1 0 0 0 0
1 0 0 0 1 1 0 0 0 0
1 0 1 0 0 0 0 0 0 0
1 1 0 0 1 1 1 1 1 1
1 1 1 1 0 1 1 0 0 1
Rangkaian

Percobaan 2 :

H= X (X Y Z )+( X Y+Y+X Y ).(X+ Z ). Y Z+Z

= ( X Y+Y+X Y ).(X Y Z+ Y Z Z)+Z
= ( X Y+Y+X Y ).(X Y Z)+Z
= X XY Y Z+XY Y Z+XX Y Y Z+Z
= X Y Z+Z
= Z(X Y +1)
=Z

Gambar Rangkaian
Tabel Kebenaran
INPUT OUTPUT
X Y Z H
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1

H= (𝐴𝐵 + 𝐴̅ 𝐶).𝐵𝐶 +𝐴̅𝐵𝐶 + 𝐴̅𝐵

= 𝐴𝐵𝐵𝐶 + 𝐴̅𝐶𝐶𝐵 + 𝐴̅𝐵𝐶 + 𝐴̅𝐵
= 𝐴𝐵𝐶 + 𝐴̅𝐵𝐶 + 𝐴̅𝐵𝐶 + 𝐴̅𝐵
= 𝐴𝐵𝐶 + 𝐴̅𝐵𝐶 + 𝐴̅𝐵
= 𝐵𝐶(𝐴 + 𝐴̅ ) + 𝐴̅𝐵
= 𝐵𝐶. (1) + 𝐴̅𝐵
= 𝐵𝐶 + 𝐴̅𝐵
= 𝐵(𝐴̅ + 𝐶)

Gambar Rangkaian yang sudah di sederhanakan

Gambar Rangkaian yang belum di sederhanakan

Tabel Kebenaran
INPUT OUTPUT
A B C H
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1

H= 𝑍̅ (𝑋𝑌̅ + 𝑌 + 𝑋̅𝑌). (𝑋 + 𝑍̅)𝑌 + 𝑋̅(𝑋̅𝑌 + 𝑋𝑌̅𝑍̅) + 𝑍

= (𝑋𝑌̅𝑍̅ + 𝑍̅𝑌 + 𝑋̅𝑌𝑍̅). (𝑋𝑌 + 𝑌𝑍̅) + 𝑋̅𝑋̅𝑌 + 𝑋̅𝑋𝑌̅𝑍̅) + 𝑍
= (𝑋𝑋𝑌̅𝑌𝑍̅ + 𝑋𝑌𝑌𝑍̅ + 𝑋̅𝑋𝑌𝑌𝑍̅ + 𝑋𝑌̅𝑌𝑍̅𝑍̅ + 𝑌𝑌𝑍̅𝑍̅ + 𝑋̅𝑌𝑌𝑍̅𝑍̅) + 𝑋̅𝑌 + 𝑍
= 𝑋𝑌𝑍̅ + 𝑌𝑍̅ + 𝑋̅𝑌𝑍̅ + 𝑋̅𝑌 + 𝑍
= 𝑋𝑌𝑍̅ + 𝑌𝑍̅ + 𝑋̅𝑌𝑍̅ + 𝑋̅𝑌 + 𝑍
= 𝑋𝑌𝑍̅ + 𝑋̅𝑌𝑍̅ + 𝑌𝑍̅ + 𝑋̅𝑌 + 𝑍
= 𝑌𝑍̅(𝑋 + 𝑋̅) + 𝑌𝑍̅ + 𝑋̅𝑌 + 𝑍
= 𝑌𝑍̅ + 𝑌𝑍̅ + 𝑋̅𝑌 + 𝑍
= 𝑌𝑍̅ + 𝑋̅𝑌 + 𝑍
= (𝑍 + 𝑌𝑍̅) + 𝑋̅𝑌
= 𝑍 + 𝑌 + 𝑋̅𝑌
= 𝑍 + 𝑌(1 + 𝑋̅)
= 𝑍 + 𝑌(1)
=𝑌+𝑍
Gambar Rangkaian

Tabel Kebenaran
INPUT OUTPUT
X Y Z H
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
 PERCOBAAN 4

RANGKAIAN DASAR DAN PENYEDERHANAAN DENGAN PETA KARNAUGH

(KARNAUGH MAP)

Percobaan 1 :

a) H = A C D + C (A+ B D )+AD( B +BC)+AC( B +B D )+ A BC D

Tabel kebenaran
A B C D A C D C (A+ B D ) AD( B +BC) AC( B +B D ) A BC D H

0 0 0 0 1 1 0 0 0 1
0 0 0 1 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0 0 0
0 1 0 0 1 0 0 0 0 1
0 1 0 1 0 0 0 0 0 0
0 1 1 0 0 0 0 0 1 1
0 1 1 1 0 0 0 0 0 0
1 0 0 0 0 1 0 0 0 1
1 0 0 1 0 1 1 0 0 1
1 0 1 0 0 0 0 1 0 1
1 0 1 1 0 0 1 1 0 1
1 1 0 0 0 1 0 0 0 1
1 1 0 1 0 1 0 0 0 1
1 1 1 0 0 0 0 1 0 1
1 1 1 1 0 0 1 0 0 1
K-Map

H = A+ C D +B D
 Rangkaian :

b) AB (B+C) + A

Tabel kebenaran
A B C AB(B+C) AB(B+C)+A
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 0 0
1 0 0 0 1
1 0 1 0 1
1 1 0 1 1
1 1 1 1 1
K-Map

H A
B Not wired
C
c) Tabel kebenaran
Z Y X H X=1 X=0
0 0 0 0 0 0
0 0 1 1 1 1
0 1 0 0 0 0
0 1 1 X 1 0
1 0 0 1 1 1
1 0 1 X 1 0
1 1 0 0 0 0
1 1 1 1 1 1

K-Map

H=X+ Y Z

Rangkaian :
 PERCOBAAN 5
RANGKAIAN ARITMATIKA

Percobaan 1:
Half Adder

Tabel kebenaran
INPUT OUTPUT
A B S Co
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Full Adder
Tabel kebenaran
INPUT OUTPUT
A B Cin S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Percobaan 2 :
Half Subtractor

Tabel kebenaran
INPUT OUTPUT
X Y D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Full Subtractor

Tabel kebenaran
INPUT OUTPUT
X Y Z D B
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
 Percobaan 3 :
Multiplier

Tabel kebenaran
INPUT OUTPUT
A B N
A1 A0 B1 B0 N3 N2 N1 N0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0
0 0 1 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 0
0 1 0 1 0 0 0 1
0 1 1 0 0 0 1 0
0 1 1 1 0 0 1 1
1 0 0 0 0 0 0 0
1 0 0 1 0 0 1 0
1 0 1 0 0 1 0 0
1 0 1 1 0 1 1 0
1 1 0 0 0 0 0 0
1 1 0 1 0 0 1 1
1 1 1 0 0 1 1 0
1 1 1 1 1 0 0 1
 PERCOBAAN 6
CODE CONVERTER
Percobaan 1 :
Code converter decimal ke kode BCD 8421

Table Kebenaran
INPUT OUTPUT
1 2 3 4 5 6 7 8 H3 H2 H1 H0
1 0 0 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 0 0 1 1
0 0 0 1 0 0 0 0 0 1 0 0
0 0 0 0 1 0 0 0 0 1 0 1
0 0 0 0 0 1 0 0 0 1 1 0
0 0 0 0 0 0 1 0 0 1 1 1
0 0 0 0 0 0 0 1 1 0 0 0
Code converter kode BCD to Excess-3

Table Kebenaran
INPUT OUTPUT
A B C D W X Y Z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
Rangkaian BCD to 7 Segmen

Tabel kebenaran
INPUT OUTPUT
D C B A a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 0 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 0 0 1 1
1 0 1 0 0 0 0 1 1 0 1
1 0 1 1 0 0 1 1 0 0 1
1 1 0 0 0 1 0 0 0 1 1
1 1 0 1 1 0 0 1 0 1 1
1 1 1 0 0 0 0 1 1 1 1
1 1 1 1 0 0 0 0 0 0 0
 PERCOBAAN 7
RANGKAIAN KOMBINASI DENGAN FUNGSI KHUSUS

Percobaan 1 :
Encoder

Table kebenaran
INPUT OUTPUT
D1 D2 D3 D4 D5 D6 D7 X Y Z
0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
Percobaan 2 :
Priority Encoder

Table kebenaran
INPUT OUTPUT
D0 D1 D2 D3 X Y V
0 0 0 0 0 0 0
0 0 0 1 1 1 1
0 0 1 0 1 0 1
0 0 1 1 1 1 1
0 1 0 0 0 1 1
0 1 0 1 1 1 1
0 1 1 0 1 0 1
0 1 1 1 1 1 1
1 0 0 0 0 0 1
1 0 0 1 1 1 1
1 0 1 0 1 0 1
1 0 1 1 1 1 1
1 1 0 0 0 1 1
1 1 0 1 1 1 1
1 1 1 0 1 0 1
1 1 1 1 1 1 1
Percobaan 3
4 to 1 Line Multiplexer

Table kebenaran
Untuk Enable = 0
INPUT OUTPUT
EN A1 A0 D3 D2 D1 D0 Y
0 0 0 0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
 INPUT OUTPUT
EN A1 A0 D3 D2 D1 D0 Y
0 1 0 0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

INPUT OUTPUT
EN A1 A0 D3 D2 D1 D0 Y
0 0 1 0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
 1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 1

INPUT OUTPUT
EN A1 A0 D3 D2 D1 D0 Y
0 1 1 0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
Untuk Enable = 1
INPUT OUTPUT
EN A1 A0 D3 D2 D1 D0 Y
1 1 1 0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

Percobaan 4 :
2 to 1 Line Multiplexer untuk 1 bit data
Table kebenaran
INPUT OUTPUT
ENABLE SELECT DATA
En G A0 B0 Y0
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 1 X X 0
1 0 X X 0

Percobaan 5 :
1 to Line Demultiplexer
Table kebenaran
INPUT OUTPUT
ENABLE SELECT DATA
En A1 A0 D Y3 Y2 Y1 Y0
0 0 0 0 1 1 1 1
0 0 0 1 1 1 1 0
0 0 1 0 1 1 1 1
0 0 1 1 1 1 0 1
0 1 0 0 1 1 1 1
0 1 0 1 1 0 1 1
0 1 1 0 1 1 1 1
0 1 1 1 0 1 1 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 1
1 1 0 0 1 1 1 1
1 1 0 1 1 1 1 1
1 1 1 0 1 1 1 1
1 1 1 1 1 1 1 1

Percobaan 6 :
Parity Controller/Generator
Table kebenaran
INPUT OUTPUT
B0 B1 H0 H
0 0 1 1
0 1 0 0
1 0 0 0
1 1 1 1
 PERCOBAAN 8
FLIP-FLOP
a) NAND

Tabel kebenaran
INPUT OUTPUT
PRESENT STATE NEXT STATE
S R Q Q’ Qn Qn’
0 0 0 1 1 1
0 0 1 0 1 1
0 1 0 1 1 0
0 1 1 0 1 0
1 0 0 1 0 1
1 0 1 0 0 1
1 1 0 1 0 1
1 1 1 0 1 0

b) NOR
 Table kebenaran
INPUT
PRESENT STATE
S R
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
OUTPUT
NEXT STATE
Q Q’ Qn Qn’
0 1 0 1
1 0 1 0
0 1 0 1
1 0 0 1
0 1 1 0
1 0 1 0
0 1 0 0
1 0 0 0

c) JK
Tabel kebenaran
CLK INPUT PRESENT NEXT STATE
STATE
CLR J K Q Q’ Q Q’
0 X X 1 0 0 1
1 0 0 1 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 1 0
1 1 1 1 0 0 1

d) T
Tabel kebenaran
CLK INPUT CLK 1 CLK 2 CLK 3
CLR T Q Q’ Q Q’ Q Q’
0 X 0 1 0 1 0 1
1 0 0 1 0 1 0 1
1 1 0 1 1 0 0 1
e) D
Table kebenaran
CLK INPUT CLK 1 CLK 2 CLK 3
CLR T Q Q’ Q Q’ Q Q’
0 X 0 1 0 1 0 1
1 0 0 1 0 1 0 1
1 1 0 1 1 0 1 0