Basic Concepts in RTL Design

By : Kapil Saxena

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 AGENDA

● CDC issues and checks

● Reset Synchronizers
● Linting Issues and checks
● Fifo Depth Calculations

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 CDC issues and checks
● What is CDC?
● CDC is clock domain crossing , and as the name suggests ,
whenever there is a data transfer from one clock domain to the
other , we have to make sure that the data is properly latched at
the receiving clock domain without any glitches or any metastable
issues.
● What are CDC issues?
● DATA LOSS
● DATA COHERENCY
● METASTABILITY
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 Metastability
● Figure shows that a metastable output that traverses additional logic in
the receiving clock domain can cause illegal signal values to be
propagated throughout the rest of the design. Since the CDC signal
can fluctuate for some period of time, the input logic in the receiving
clock domain might recognize the logic level of the fluctuating signal to
be different values and hence propagate erroneous signals into the
receiving clock domain.

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 Synchronizers
● Synchronizers are required so as to make the data input be in
synch with the sample clock , the clock at which that input needs
to be sampled.
● Types of Synchronizations required :
● There are two scenarios that are possible when passing signals
across CDC boundaries, and it is important to determine which
scenario applies to your design:
● (1) It is permitted to miss samples that are passed between clock
domains.
● (2) Every signal passed between clock domains must be
sampled.
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 Two flop synchronizer

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 SYNCHONIZATION SCENARIOS
● Synchronizing fast signals into slow clock domains
● The "three edge" requirement
● sampling a long CDC pulse - but not long enough
● Slow to fast domains

● PS. Refer to sunburst paper for details

● www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf

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 Reset Synchronizers
● Which reset to opt for ? Synchronous or Asynchronous
● Why is reset synchronization required?
● Effects of not using a reset synchronizer?

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 Reset Synchronizer

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 ● An external reset signal asynchronously resets a pair of master reset flip-
flops, which in turn drive the master reset signal asynchronously through the
reset buffer tree to the rest of the flipflops in the design. The entire design
will be asynchronously reset.
● Reset removal is accomplished by de-asserting the reset signal, which then
permits the d-input ofthe first master reset flip-flop (which is tied high) to be
clocked through a reset synchronizer.
● It typically takes two rising clock edges after reset removal to synchronize
removal of the master reset.
● Two flip-flops are required to synchronize the reset signal to the clock pulse
where the second flip-flop is used to remove any metastability that might be
caused by the reset signal being removed asynchronously and too close to
the rising clock edge.

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 Reset Synchronizer Metastability
● The first flip-flop of the reset synchronizer does have potential metastability
problems because the input is tied high, the output has been
asynchronously reset to a 0 and the reset could be removed within the
specified reset recovery time of the flip-flop (the reset may go high too close
to the rising edge of the clock input to the same flip-flop).
● This is why the second flip-flop is required.
● The second flip-flop of the reset synchronizer is not subject to recovery time
metastability because the input and output of the flip-flop are both low when
reset is removed.
● There is no logic differential between the input and output of the flip-flop so
there is no chance that the output would oscillate between two different logic
values.
● PS. Refer to sunburst paper for details www.sunburst-
design.com/papers/CummingsSNUG2003Boston_Resets.pdf

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 Introduction to Linting:
● Linting in layman terms is a tool which helps in purification of RTL code,
● Lint checking is also known as PLDRC (Pre layout Design Rule Checking).
This is basically done on RTL to check for errors. We generally use a tool
called Spyglass to perform the linting.
● In general Lint tools that flag suspicious and non- portable usage of language
construct in any programming language. It points out the code where it likely
to be bugs.
In chip design world Lint tools (some time referred as Design Rule Checker)
check the cleanliness and portability of the HDLs code for various EDA tools.
Usually compiler does not show the errors and warnings which detected by
lint tools.
There are many advantages of it, for example when design style enforced by
lint tool it avoids a situation where the synthesis tools implements something
different than expected from RTL code.
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 Atrenta Console has broken up the SpyGlass run into 3 major steps:

● Design Setup
● Goal Set up and Run
● Analysis

1. Design Setup : design files and SGDC file are added.

2. Goal Set up and Run : In Goal Set up and Run, we specify the goals, the severity level of rules (error, warning,
info) and run the goals.
3. Analysis: While in analysis, the results of the tool run on the set up goals are analyzed and reports are generated.

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 FEATURES OF SPYGLASS

●Full language support for Verilog , System Verilog and VHDL.

●A rich suite of in-built rules, including:

• File checks, such as file names, design units per file and headers
• Naming checks on signals, ports, parameters, constants, clocks and other constructs
●Style and related checks

●Coding for synthesis and related checks

●Design practice and related checks

●Area, timing, and synchronization checks

●Clock and reset checks

●DFT, Low Power, Constraints, ERC and similar checks (cost options)

●Built-in engines, including RTL synthesis and flattening, to enable

detailed implementation tests including clocking, reset and synchronization of asynchronous signals
●A Graphical User Interface (GUI) called Atrenta Console

●A batch execution program for integration in corporate design flows

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