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5 4 3 2 1

Foxconn Precision Co. Inc.


D G31M05 Schematic D

Fab.A
Data: 2008/1/03
Page Index
01. Index Page 25. ICH7 -1
02. Topology 26. ICH7 -2
03. Rest Map 27. ICH7 -3
04. Clock Distribution 28. REAR USB
C
05. Power Delivery Map 29. TPM C

06. Power Sequence 30. PCIE1X


07. BLANK 31. PCI Slot
08. CK505 ClockGen 32. LAN-RTL8101E/RTL8111C
09. Power / MISC Connectors 33. AUDIO 662
10. Voltage Regulator Down 11 34. AUDIO PORT
11. OUTPUT CAP 35. Super I/O ITE8718F/GX
12. 1D25V 1D5V FSB 36. Keyboard / Mouse / Fan
13. STR1D8V 3D3_DUAL 37. Serial / Parallel
14. LGA775 -1 38. FRONT USB
B

15. LGA775 -2 39. changlist B

16. Broadwater -GMCH -1


17. Broadwater -GMCH -2
18. Broadwater -GMCH -3
19. DDR2 Channel A Termination
20. DDR2 Channel A DIMM1, 2
21. DDR2 Channel B Termination
22. DDR2 Channel B DIMM1, 2
23. PCI Express x16 Gfx Slot
A 24. VGA Connector A

FOXCONN PCEG
Title
Index Page
Size Document Number Rev
C G31M05 A

Date: Friday, January 18, 2008 Sheet 1 of 41


5 4 3 2 1
5 4 3 2 1

Cedar Mill, Presler ,


Conroe & Allendale
VRD 11
LGA775 Processor
3 Phase PWM
D Socket T D

800/1066/1333 FSB
CK-505 Clock

PCI Express x 16 Channel A DDR2


PCI Express x16 Port DDR2 667/800
External Graphics
DIMM1
Card

GMCH DDR2 667/800 Channel B DDR2


VGA Connector
Broadwater DIMM1

C C

Back Panel
PCIe port
USB2.0 Port 7 LAN
4 Lanes
USB2.0 Port 8 Reltek
Direct Media Interface (DMI)
USB2.0 Port 9 Controller Link
USB2.0 Port 10

SPI Flash
PCI Slot 1X2

ICH7

B Header B

USB2.0 Port 1
Serial ATA ⒑

LPC I/F
USB2.0 Port 2 SATA Connector 1
AHCI, RAID0,1,5,10

SATA Connector 2
USB2.0 Port 3
USB2.0 Port 4 SPI Flash SATA Connector 3
(BIOS) SATA Connector 4

HDA Codec
TPM Realtek ALC662
TPM(Optional)
LPC I/F
Super I/O
IT8718/GX
A A

Floppy
Serial & Parallel
Drive Connector
FOXCONN PCEG
Title
TOPOLOGY
Size Document Number Rev
C G31M05 A

Date: Friday, January 04, 2008 Sheet 2 of 39


5 4 3 2 1
5 4 3 2 1

CPU
(Cedar Mill/Presler/Conroe/Allendale)

CPU_PWRGD

CPURST#
D
LGA775 processor D

ATX
Power
Vtt_PwrGd CK505

Translation PWRGD_3V
PWRGD_PS PWROK CPURST#
Circuitry PCI Express x16
PS_ON#
GMCH
Broadwater
C
RSTIN# C

ICH7
ICH_PWRGD
CK_PWRGD
SLP_M#
PCIRST#

PLTRST#

Front Panel PWROK ACZ_RST#


RST# Audio
FR_RST SYS_RESET# LAN_RSTSYNC

B B
SW_ON PWRBTN#
RSMRST#

RCIN#

SLP_S3#

RST#
TPM

RST#
RST#
Power on/off KBRST PCI Slot 1
circuit RSMRST#
Super IO
RST# PCIe Slot
SLP_S3# PCIe LAN
PSOUT
PSIN RST#
A IDE Controller A

PSOUT#

RSMRST circuit FOXCONN PCEG


Title
Reset Map
Size Document Number Rev
C G31M05 A

Date: Friday, January 04, 2008 Sheet 3 of 39


5 4 3 2 1
5 4 3 2 1

14.318MHz

CPU

D
CPU 200/266/333 MHz Diff Pair D

MCH 200/266/333 MHz Diff Pair

PCI Express 100 MHz Diff Pair PCI Express x16 Gfx Channel A DDR2
DIMM1
GMCH
DOT 96 MHz Diff Pair Broadwater

Channel B DDR2
DIMM1
PCI Express/DMI 100 MHz Diff Pair
C C
CK-505

PCI Express/DMI 100 MHz Diff Pair

USB/SIO 48 MHz

ICH 33 MHz

REF 14 MHz
SPI Clock SPI

ICH7
Azalia Bit Clock

B
PCI 33 MHz PCI Slot 1 B

TPM 33 MHz TPM

32.768KHz

HD Audio

SIO 33 MHz Super I/O

SATA 100 MHz Diff Pair


PCI Express 100 Mhz Diff Pair
A A

FOXCONN PCEG
Title
Clock Distribution
Size Document Number Rev
C G31M05 A

Date: Friday, January 04, 2008 Sheet 4 of 39


5 4 3 2 1
5 4 3 2 1

3.3V Super I/O


ATX P/S 3.3V
Icc(Max)=50mA
Proceessor
Vccp (CPU Vcore)
5V 5VSB VRD 11 3.3SBV
12V Voltage=1.15~1.5V 5V
Switching Icc(Max)=50mA(S0)
Icc(Max)=125A
Three Phase
5VDUAL 3-Phases Swithing 3.3SBV
D
DDR2 Channel A Icc(Max)= Icc(Max)=38mA(S3)
D

1.2V FSB 5VSB


Vdd (Core)=1.8V 10A Vtt=5.3A
Ivdd(Max)=TBD(per channel)
5VDUAL
USB2.0 10 Ports Icc(Max)=
+5V DUAL=5A(S0, S1)
Vtt (Core)
0.9V Single Phase Switch Broadwater GMCH +5V DUAL=20mA(S3) 4.345A(S0,S1)
5V to 1.8V 22mA(S3)
Ivterm(Max)=200mA FSB_Vtt
(per channel) Ivdd(Max)=TBD Linear 1.8V
LDO to 1.2V
1.2V FSB Vtt PS2
1.8V to 0.9V Icc(Max)=1.3A +5V DUAL=345mA(S0, S1)
6A +5V DUAL=2mA(S3)
Ivterm(Max)=1.2A
DDR2 Channel B
1.8V VCCSM FWH
Vdd (Core)=1.8V 1.8V VCC_SMCLK
Ivdd(Max)=TBD(per channel) 3.3V=107mA(S0, S1)

GMCH 1.25 V Vcore (Core Logic) PCI Express X16


Vtt (Core) 3.3V 21.34A 1.25V
0.9V Switching Icc(Max)=18.8A(Integrated) slot (1)
Ivterm(Max)=200mA 12V
*1.25V (DMI&PCIe) +12V=5.5A
(per channel) VCCA_EXP 2.5A
3.3VSB
C
1.25V C
Icc(Max)=0.375A(wake)
VCC_CL 3.8A
Icc(Max)=0.02A(no wake)

+3.3V=3A
3.3V VCCA_DAC 70mA
3.3V VCC3_3 15.8mA
PCI Express X1
Per slot (1)
+12V=0.5A
HDA Codec
3.3VSB
Vcc LDO Icc(Max)=0.375A(wake)
5V 12V ICH7 Icc(Max)=0.02A(no wake)
Icc(Max)=200mA to 5V
1.25V VCCDMI 40mA
Vcc +3.3V=3A
3.3V Linear 1.25V 1.2V VCC_CPU_IO 14mA
Icc(Max)=40mA to 1.05V
V_1P05V_ICH 1.05V (Core) VCC1_05
2A 1.17A PCI Per Slot (X2)
1.5V (USB &SATA) VCC1_5A -12V
B
1.12A Icc(Max)=0.1A -12V B
Linear 1.8V
to 1.5V 1.5V (PCIe)VCC1_5B
V_1P5V_ICH 0.77A 5V
2.2A 1.5V VCCGLAN1_5 Icc(Max)=5A
5V
74mA
3.3V
RTC
5VSB RTC=5uA Icc(Max)=7.6A
Battery
12V
3.3V VccCL3_3 12mA Icc(Max)=0.5A
5V_STBY to 3.3SB 3.3V VccSUS3_3 141mA
1.5A 3.3V VccLAN (10/100) 12mA 3.3VSB
3.3V VccSUSHDA 4mA Icc(Max)=0.375A(wake)
3.3V VCC3_3 310mA Icc(Max)=0.02A(no wake)

3.3V
3.3V VccGLAN3_3 1mA
3.3V VccHDA 4mA

Nineveh GbE Lan


3.3V STBY
A IO LED 15.5nA A

1.8V ANALOG 418.2mA BJT


CK505
1.0V Internal 1.8
to 1.0 VR core Vdd (Core) FOXCONN PCEG
277.2mA 3.3V Title
Ivdd(Max)=250mA Power Delivery Map
Size Document Number Rev
C G31M05 A

Date: Friday, January 04, 2008 Sheet 5 of 39


5 4 3 2 1
5 4 3 2 1

S0->S5
+12V_SYS +12V_SYS
S5->S0
D D
+5V_DUAL +5V_SYS +5V_SYS +5V_DUAL

+3D3V_DUAL +3D3V_SYS +3D3V_SYS +3D3V_DUAL


+1D8V_STR +1D8V_STR

VTT_DDR
VTT_DDR
VTT_VR VTT_VR

Vcc Vcc

1ms to 10ms
Vcc_PWRGD
Vcc_PWRGD
VRM_OUTEN
VRM_OUTEN
VIDPWRGD VIDPWRGD PS_ONJ
C
PS_ONJ C

S0->S3 S3->S0
+12V_SYS +12V_SYS

+5V_SYS +5V_DUAL +5V_DUAL +5V_SYS

+3D3V_SYS +3D3V_DUAL +3D3V_DUAL +3D3V_SYS


B B

+1D8V_STR +1D8V_STR +1D8V_STR +1D8V_STR

VTT_DDR
VTT_DDR
VTT_VR VTT_VR

Vcc Vcc

1ms to 10ms
Vcc_PWRGD
Vcc_PWRGD
VRM_OUTEN
VRM_OUTEN
VIDPWRGD PS_ONJ VIDPWRGD
PS_ONJ

A A

FOXCONN PCEG
Title
Power Sequence
Size Document Number Rev
C G31M05 A

Date: Friday, January 04, 2008 Sheet 6 of 39


5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A FOXCONN PCEG A

Title
BLANK
Size Document Number Rev
A G31M05 A

Date: Friday, January 04, 2008 Sheet 7 of 39


5 4 3 2 1
5 4 3 2 1

3D3V_CLK
3D3V_SYS

FB10 0 3D3V_CLK 3D3V_CLK_SATA_25M

4.7uFC136

4.7uFC105
+/-5% r0805h6

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

25V, X7R, +/-10%


3D3V_CLK C107 C111

1
10nFC156
* * * 10nF
* 10nF

25V, X7R, +/-10%


25V, X7R, +/-10%
Dummy
C153 C110 C160 C119

2
1
D
* 10nF
* 10nF
25V, X7R, +/-10% * 10nF
25V, X7R, +/-10% * *
25V, X7R, +/-10%
10nF
25V, X7R, +/-10%
D
Dummy

2
Change to 0Ohm RES or not

3D3V_CLK_REF_A

C101 C155 C140

25V, X7R, +/-10%

25V, X7R, +/-10%


1
3D3V_CLK_48M * 4.7uF
6.3V, X5R, +/-10% * 10nF
* 10nF

2
C151

3D3V_CLK
* 10nF
25V, X7R, +/-10%
TBD
3D3V_CLK
R88

* 4.7K
+/-5%
r0402h4
U8

1 **RLATCH 25Mhz_0F_2x 64
2 GND GND 63
+/-5% 3D3V_CLK 3 62 3D3V_CLK_SATA_25M
R94

*
33 R89 4.7K +/-5% r0402h4 24M_1394 VDD VDD25Mhz_STB 3D3V_CLK_SATA_25M
4 61
**

CK_33M_SIO 3D3V_CLK **GSEL/24.576Mhz VDDSATA_STB SATA_100M_P_ICH


35 CK_33M_SIO 5 VDDPCI SATACLKT_LR 60 CK_SATA_100M_P_ICH 26
27 CK_33M_ICH CK_33M_ICH 6 59 SATA_100M_N_ICH
CK_SATA_100M_N_ICH 26

*
R102 33 R95 4.7K Dummy GND SATACLKC_LR
7 58
*

*
CK_33M_TPM R104
+/-5% 33 +/-5% @TPM +/-5% r0402h4 **DOC1 GND R96 33 +/-5% r0402h4
29 CK_33M_TPM 8 PCICLK0 REF0_2x/FSLC 57 CK_14M_ICH 25
ICS_FSBSEL2
ICS_FSBSEL1
9
10
*Freerun/PCICLK1_2x GND 56
55
? X2
FSLB/PCICLK2_2x X1
9,14,25 ICH_SYS_RSTJ 11 SELRSET/RESET#/PCICLK32 X2 54 1 2
*1 RN13 12 53 3D3V_CLK_REF_A

*
CK_33M_PCI1 2 33 R107 4.7K Dummy PCICLK4 VDDREF_STB C102 C103
C 13 52 C

ICS9LPRS511
31 CK_33M_PCI1 3 4 +/-5% **DOC0 SDATA SMB_DATA_MAIN 20,22,36
CK_48M_ICH 3D3V_CLK_48M 27pFXTAL-14.318MHz 27pF
25 CK_48M_ICH
35 CK_48M_SIO
CK_48M_SIO 5
7
6 8p4r0603h7
8
ICS_FSBSEL0
+/-5% r0402h4 14
15
VDD48
FSLA/USB_48MHz
SCLK
GND
51
50
SMB_CLK_MAIN 20,22,36 * +/-5% *
+/-5%
16 49 200M_P_CPU c0402h6 c0402h6
CK_200M_P_CPU 14
*

R1264.7K +/-5% r0402h4 *SEL24_48#/24_48Mhz CPUT_LR0 200M_N_CPU


17 GND CPUC_LR0 48 CK_200M_N_CPU 14
VRMPWRGD 18 47 3D3V_CLK
96M_P_GMCH Vtt_PwrGd/WOL_STOP# VDDCPU 200M_P_GMCH
16 CK_96M_P_GMCH 19 DOT96T_LR/PCIeT_LR0 CPUT_LR1 46 CK_200M_P_GMCH 16
96M_N_GMCH 20 45 200M_N_GMCH
16 CK_96M_N_GMCH DOT96C_LR/PCIeC_LR0 CPUC_LR1 CK_200M_N_GMCH 16
21 44 3D3V_CLK
GND VDDI/O
32 CK_PE_100M_P_LAN 22 PCIeT_LR1 GNDA 43
32 CK_PE_100M_N_LAN 23 42 3D3V_CLK_REF_A
PCIeC_LR1 VDDA_STB
24 PCIeT_LR2 PCIeT_LR8 41
25 PCIeC_LR2 PCIeC_LR8 40
26 39 PE_100M_P_GMCH
GND PCIeT_LR7 CK_PE_100M_P_GMCH 16
PE_100M_P_16PORT 27 38 PE_100M_N_GMCH
23 CK_PE_100M_P_16PORT PCIeT_LR3 PCIeC_LR7 CK_PE_100M_N_GMCH 16
PE_100M_N_16PORT 28 37
23 CK_PE_100M_N_16PORT PCIeC_LR3 GND
29 PCIeT_LR4 PCIeT_LR6 36
30 PCIeC_LR4 PCIeC_LR6 35
31 34 PE_100M_P_ICH CK_PE_100M_P_ICH 25
3D3V_CLK GND PCIeT_LR5 PE_100M_N_ICH
32 VDDPCIEX PCIeC_LR5 33 CK_PE_100M_N_ICH 25

ICS9LPRS511EGLF-T

3D3V_CLK

*R124
8.2K
+/-5%
r0402h4
B B
VRMPWRGD VRMPWRGD 10,14,25

FSB SELECT
Host Clock
FSBSEL2 FSBSEL1 FSBSEL0 Frequency
1 0 0 333MHz
0 0 0 266MHz
0 1 0 200MHz
* * *

CK_33M_PCI1 ICS_FSBSEL0 R1222.2K +/-5% r0402h4 FSBSEL0


0 0 1 133MHz
CK_48M_SIO
ICS_FSBSEL1 R105 +/-5% FSBSEL1
CK_48M_ICH 2.2K r0402h4

CK_33M_SIO ICS_FSBSEL2 R1032.2K +/-5% r0402h4 FSBSEL2


Reserved
CK_33M_ICH

CK_14M_ICH
50V, NPO, +/-5%

C144 CK_33M_TPM
* 10pF
FSB_VTT
50V, NPO, +/-5%

50V, NPO, +/-5%

Dummy
50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

C154 C152 C118 C137 C114 C138


* 10pF
* 10pF
* 10pF
* 10pF
* 10pF
* 10pF

A Dummy Dummy Dummy Dummy Dummy Dummy A

RN11
*1 2 FSBSEL0
3 4 FSBSEL0 14,16
FSBSEL1
5 6 FSBSEL1 14,16
FSBSEL2
7 8 FSBSEL2 14,16
470
+/-5%
8p4r0603h7 FOXCONN PCEG
Title
CK505 Clock Gen
Size Document Number Rev
C G31M05 A

Date: Tuesday, January 08, 2008 Sheet 8 of 39


5 4 3 2 1
5 4 3 2 1

5V_SYS 5V_SYS 5V_SYS 5V_SYS

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%


C314 C317 C447 C80
*
Dummy
0.1uF
*
Dummy
0.1uF
* 0.1uF
* 0.1uF

5V_SB -12V_SYS 3D3V_SYS 3D3V_SYS 12V_SYS 5V_SB

5V_SYS
5V_SYS
*R359
4.7K 13
PWR1
+3.3V3 +3.3V1 1
D +/-5% 14 2 D
r0402h4 -12V +3.3V2
15 GND4 GND1 3
16 4 -12V_SYS 12V_SYS 12V_SYS
35 PS_ONJ PSON +5V1

25V, X7R, +/-10%

25V, X7R, +/-10%

25V, X7R, +/-10%


17 GND5 GND2 5
C446 18 6
GND6 +5V2

1
Del R32, R33, Q3
* 0.1uF
16V, Y5V, +80%/-20%
19
20
GND7 GND3
RSVD PWR0K
7
8 PWRG_ATX
PWRG_ATX 13,35
* C445 * C448 * C449
21 9 0.1uF 0.1uF Dummy
0.1uF

2
+5V3 +5V_AUX C450
22 +5V4 +12V_1 10
23
24
+5V5
GND8
+12V_2
+3.3V4
11
12
* 0.1uF
16V, Y5V, +80%/-20%

HM1512E-EP1 Dummy

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%


3D3V_SYS 3D3V_SYS 3D3V_SYS
C457

*
C456
0.1uF
*
C145
0.1uF * 0.1uF

Dummy Dummy
5V_SYS 3D3V_SB 5V_SYS
5V_SB

R374 1D25V_MCH
*R375 5V_SB 5V_SB

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%


330 10K
C
+-5% +/-5% R370 *R371
4.7K C451 C169
C

FP1
330
+-5%
+/-5%
r0402h4 * 0.1uF
*
C98
0.1uF * 0.1uF

1 2
HDD_LEDJ 3 4 16V, Y5V, +80%/-20%
Dummy
26 HDD_LEDJ

*
5 6 R97
PBTNJ_SIO 35
7 8 33 +/-5%
8,14,25 ICH_SYS_RSTJ
9 X C461 C462 C126

1
Header_2X5_K10 * 220pF
Dummy * 220pF
Dummy * 10nF

C468 C469 25V, X7R, +/-10%

2
* 220pF 220pF
50V, NPO, +/-5% 50V, NPO, +/-5% *
Dummy Dummy TBD 3D3V_SYS

*R368
10K
+/-5%
Q34 r0402h4

C
Reserved
Front Panel Switch/LED

*
MMBT3904-7-F B R369 1K S1_LED 35
+/-1% r0402h4
HD_LED+ 1 2 Power Reserved

E
HD_LED- 3 4 Power LED(Green) Change to 5% or not

B
GND 5 6 Power button B
Reset button 7 8 Power
NC 9 10 Key

SPEAKER HEADER
SPEAKER
1 1
5V_SYS
Confirm must use or not

3 3
4 4
5V_SYS RN39
*1 2
Header_1X4_K2
Reserved
3 4
5 6
7 8
*R348
4.7K 100 Ohm
+/-5% +/-5%
r0402h4 8p4r0603h7

D44
C

A 25 SPKR 1 A
*

3 R358 2.2K B Q30 C442


MMBT3904-7-F
35 SIO_BEEP 2 +/-5% r0402h4
* 0.1uF
16V, Y5V, +80%/-20%
E

BAT54C FOXCONN PCEG


Title
Power/MISC Connectors
Size Document Number Rev
Custom G31M05 A

Date: Monday, January 07, 2008 Sheet 9 of 39


5 4 3 2 1
5 4 3 2 1

50V, X7R, +/-10%


R220
Dummy
D C252 R215 D
1K

*
Dummy +/-1% R226 100 Ohm
+/-1% VCCP

*
C236
* RT2
Dummy 16V, NPO, +/-5%
C292 R219 R218
T 10K 22K 2.2nF 1.3K

25V, NPO, +/-5%


R199 C255 VCC_SENSE 14

*
+/-1%

*
* 1nF
+/-1%R179
Dummy
+/-1%

*
470pF 0 0

2
1K C291
+/-1% 50V, NPO, +/-5%
+/-5% C286 * +/-5% * 16V, X7R, +/-10%
Dummy

25V, NPO, +/-5%


C281 C248 3.3nF 0.1uF
25V, NPO, +/-5%

1
* 1nF
*
Dummy
1nF
R197
Dummy
10nF
25V, X7R, +/-10%
R205 1K Dummy FBRTN
200 Ohm +/-1%
+/-1% VIN
5VCC
C273
25V, NPO, +/-5%

* 1nF
R200 2.2+/-5% 12V_VRM

A
LS4148-F C262 C261LS4148-F C260 Q5 C94

1
D33
* * 0.1uF D34
* * 1uF AOD452
* 4.7uF
ISP1
*R208
1.6K 2.2nF
25V, X7R, +/-10% C244
2.2nF
+/-10%
C277
25V, Y5V, +80%/-20% R181 6.2k Ohm
+/-1%

2
+/-1% 50V, X7R, +/-10% 50V, X7R, +/-10% Boot1 R211 2.2+/-5% 1 20.22uF 25V, R51
X7R, +/-10% G C246

*
Dummy
Dummy UG1 * R58 * 0.1uF
25V, X7R, +/-10%

S
C280 10K L16 Choke 400nH
22nF Phase1 +/-5% 2 1
0

*
FBRTN 50V, X7R, +/-10%

D
Phase1

1
+/-5%
* Boot1
* C78

Boot2
UG1

LG1
LG1 Q8 Q7 1nF
50V, X7R, +/-10%

2
G G
AOD472 AOD472 R49
41

26

30

29

28

27

22
3

U10 2.2

S
+/-5%
GND2

SS/EN

VCC12

BOOT1

UGATE1

PHASE1

LGATE1

BOOT2
COMP

FB
ADJ

C 23 UG2 C
UGATE2
35 PVID7 33 VID 7
34 24 Phase2
35 PVID6 VID 6 PHASE2

35 PVID5 35 VID 5
25 LG2
LGATE2
35 PVID4 36 VID 4
37 21 VIN
35 PVID3 VID 3 PWM3
38 20
35 PVID2
39
VID 2
GND PWM 4

35 PVID1 VID 1
GND1 10
40 Q9 C106

D
35 PVID0 VID 0

1
+/-5%ISP1
ISP1 18 R185 0 AOD452
* 4.7uF

RT8841 *
VID_SELECT:VR10.1 connect GND; VR11 connect VTT 1 25V, Y5V, +80%/-20% R182 6.2k Ohm
+/-1% ISP2
14,25 VID_SELECT VIDSEL
17 R186 * 620 VCCP C266

2
ISN1

2
+/-5% Boot2 R190 2.2+/-5% 1 20.22uF 25V, R114
X7R, +/-10% G C247

*
VRM_EN
11 VRM_EN 32 EN/VTT
15 R188 0 +/-5%ISP2
*C234
Dummy
0.1uF UG2 * R123 * 0.1uF
25V, X7R, +/-10%

S
ISP2
*
16V, X7R, +/-10% 10K L25 Choke 400nH
*

16 R187 620 C241VCCP Phase2 +/-5% 2 1 VCCP


ISN2 0

*
31 +/-5%
* 0.1uF

D
8,14,25 VRMPWRGD PWRGD

1
+/-5%
16V, X7R, +/-10%
Dummy * C192
FBRTN
VCC5

LG2 Q12 Q15 1nF


IMAX

ISN4

ISN3
ISP4

ISP3
OFS

2 50V, X7R, +/-10%


RT

2
G G
AOD472 AOD472 R161
19

12

11

13

14

RT8841PQW 2.2

S
+/-5%

*R189
25V, NPO, +/-5%

R192 39K
*

120K +/-5%
+/-1% 5VCC

B B
C254 C251
* 1uF
* 1nF *R183
9.1K Changelist------10/12 by power
+/-10% R193
Dummy +/-1%
* 0 change R381 1.2Kohm to 1.6Kohm
+/-5% chagne R411 402Kohm to 120Kohm
change R245 30Kohm to 43Kohm
FBRTN

5VCC change R246 3.3Kohm to 6.2Kohm

VSS_SENSE 14
Changelist------11/05by power
25V, X7R, +/-10% change R181 43K to 39K
C285 chagne R176 6.2K to 9.1K
1

* 10nF
* R214

Dummy +/-1%
2

100 Ohm

A A

FOXCONN PCEG
Title
Voltage Regulator Down 11
Size Document Number Rev
C G31M05 A

Date: Thursday, January 10, 2008 Sheet 10 of 39


5 4 3 2 1
5 4 3 2 1

VCCP

D D

12V_VRM
DEL EC19, EC17,EC42
2

PWR2
Header_2X2 Input LC circuit
EC32 EC31 EC17 EC18 EC28
* 680uF * 680uF * 680uF * 680uF * 680uF
1

4V,+/-20% 4V,+/-20% 4V,+/-20% 4V,+/-20%


VIN 4V,+/-20%
L11
1.2uH@100KHz
*

C318 EC26 EC21 EC8 EC9


1

* 0.1uF
16V, Y5V, +80%/-20%
* 1000uF
+/-20%
* 1000uF
+/-20%
* 1000uF
+/-20%
* 1000uF
+/-20% EC34 EC15 EC16
Dummy * 680uF * 680uF * 680uF
2

4V,+/-20% 4V,+/-20% 4V,+/-20%


Dummy

C C

TC2 TC1

VTT_OUT_RIGHT
* 100uF
2V,+30/-20%
* 100uF
2V,+30/-20%
Dummy Dummy
R245
680
VTT_OUT_RIGHT 5V_SB
* +/-5%

VTT_PWRGD 14
*R262
20K C190 C195 C204 C208 C175 C176
R247
4.7K
+/-1%
Q18 * 6.3V, X5R, +/-10%*
10uF
Dummy 6.3V, X5R, +/-10%*
10uF
Dummy 6.3V, X5R, +/-10%*
10uF
Dummy 6.3V, X5R, +/-10%*
10uF
Dummy
10uF
* 10uF
6.3V, X5R, +/-10%
+/-5% 2N7002 6.3V, X5R, +/-10%

1
BOM need update
CP9
C

100K X_COPPER
*

R248 Dummy B Q20


MMBT3904-7-F 2
+/-5% 12V_VRM VTT_OUT_RIGHT
E

B
C311 *R258
10K
Dummy
R243
680
Dummy C203 C197 C196 C191 C205 C177 B
1 2 +/-5% +/-5%
* 10uF
* 10uF
* 10uF
* 10uF
* 10uF
* 10uF
*

6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10%
VRM_EN Dummy Dummy
2.2uF VRM_EN 10

Dummy C312
Q19
*
0.1uF R246
2N7002 Dummy Dummy
4.7K *
+/-5%

* C210
10uF
*
C189
10uF
*
C209
10uF
*
C217
10uF
*
C216
10uF
*
C215
10uF
6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10%
Dummy Dummy Dummy Dummy

A A

FOXCONN PCEG
Title
OUTPUT CAP
Size Document Number Rev
Custom G31M05 A

Date: Monday, January 07, 2008 Sheet 11 of 39


5 4 3 2 1
5 4 3 2 1

Intel design guide (333):


3.3V SUPPLY must ramp up before VCC (GMCH Core power
VCC (GMCH Core power ) must rampdown before the 3.3V supply 12V_SYS
C213
D32
A C 125V_PHASE * L28

*
*
12V_SYS R166 10 LS4148-F 1uH@1KHz
+/-5% 1uF
16V, X7R, +/-10%

close to Q61 Drain


5V_SB C202 1uF 16V, X7R, +/-10%

*
R169 C219 EC33 C222

1
*R170 Open 14.3K
* 0.1uF * 330uF
* 4.7uF

D
5
D D
4.7K
Dummy +/-1% U9 25V, X7R, +/-10% +/-20% 25V, Y5V, +80%/-20%
3D3V_SYS +/-5% L 1 Q16

VCC

2
L r0402h4 Rocset BOOT
Open 7 2 R175 0 +/-5% G
H COMP/OCSET UGATE AOD452 1D25V_MCH

C
Open L26 Need to change to RUBYCON 16MBZ470MEFC8X11.5

*
S
R174 L B DummyQ13 6 8 125V_PHASE 1D25V_MCH
2KOhm MMBT3904-7-F FB PHASE
Dummy

GND
* +/-1% L 4

E
LGATE R194 2.5uH@100KHz

D
*R172 APW7120KE-TRL 2.2

1
R173
Q14
B Dummy
MMBT3904-7-F
200
+/-1%
Q17 +/-5%
*
C321
*
EC37
1000uF *
EC36
1000uF * C279
10uF

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%


0.1uF

10V, Y5V, +80%/-20%

2.2uF C253

2.2uF C214

2.2uF C232

1uF C287

1uF C226

1uF C225
1.3KOhm
Dummy r0402h4 R176 0 +/-5% G C269 +/-20% +/-20%

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%


16V, Y5V, +80%/-20%

2
E

1
+/-1% AOD472
* 2.2nF
50V, X7R, +/-10% * * * * * *

S
Near MOSFET

2
VOUT= 0.8V(1+R638 / R658)
R638,R658 must less than 1k
Pull FB trace out after Cout

*
R167 115 Ohm +/-1% r0402h4

R168 C201

*
220 18nF
+/-1% 50V, Y5V, +80%/-20%

Dummy Dummy
1D25V FOR CHIP
C C

12V_SYS
3D3V_SB 12V_SYS
1D8V_STR

50 mils
1

* R343
* C431 U14D

4
1.8KOhm 0.1uF
+/-1% 12
2

+
25V, X7R, +/-10% 14
D

U14A 1D5V_CORE 13 -
4

Q24
@1.5V 1D5V_REF 3 LM324DR2G

11
+
2
1 G
AP15N03H 1A
-
50 mils
S

LM324DR2G R354
11

R347 C441 1K
Dummy
* *
1.5KOhm 0.1uF +/-5%
+/-1% 16V, Y5V, +80%/-20%
Can change to 0402 or not EC41 C337

R355
* 1000uF
+/-20% * 0.1uF
16V, Y5V, +80%/-20%
1K
+/-1%

B Check to dummy or not B

1D5V_SYS
3D3V_SB
1D5V_CORE

FSB_VTT 3D3V_SB R324 12V_SYS 50 mils


3D3V_SB 1D8V_STR 2.2K
+/-1%
50 mils

D
12V_SYS
*R317 *R352 FSB_VTT 1D5V_CORE U14B 1D05V_SYS

4
1K VTT_SEL 2.1K Q22
+/-5%
DummyVTT_SEL
*R318 *R322
8.2K
+/-1% @1.05V 1.8V 5 +
7 G 1A
D

14 VTT_SEL r0402h4 1K +/-1% AP15N03H


U14C 6
C

-
4

+/-5% Q11 D40 50 mils

S
1D5V_CORE Reserved 1.8V Dummy LM324DR2G R323
@1.2V 10

11

*
+
r0402h4
9
8 G
AP15N03H LS4148-F *R342 * C422
0.1uF
1K
Dummy
+/-5%
C

-
*R319 1K
+/-1% 16V, Y5V, +80%/-20%
S

470 Q27 LM324DR2G R321 Can change to 0402 or not EC42 C404
B
11

+/-5% MMBT3904-7-F R346 C430 1K


Dummy * 1000uF
* 0.1uF
1.2K
* 1uF +/-5%
6.3A 50 mils R325 +/-20% 16V, Y5V, +80%/-20%
C

+/-1% 10V, Y5V, +80%/-20% 1K


Q26 Can change to 0402 or not EC23 C142 C148 +/-1%
B

C401
MMBT3904-7-F
* 1000uF
+/-20% * 10uF
* 0.1uF
16V, Y5V, +80%/-20%
Dummy
Need to Check Change to Dummy
E

A
* 1uF
10V, Y5V, +80%/-20%
R320
1K Dummy A
+/-1% 6.3V, Y5V, +80%/-20%

1D05V_SYS
FSB_VTT FSB_VTT

C115 C116 FOXCONN PCEG


* 0.1uF
16V, Y5V, +80%/-20%
Dummy * 0.1uF
Title

16V, Y5V, +80%/-20%


1D25V 1D5V FSB
Dummy
FSB_VTT Size
C
Document Number
G31M05
Rev
A

Date: Tuesday, January 08, 2008 Sheet 12 of 39


5 4 3 2 1
5 4 3 2 1

DDR_VTT
D D
VCC_DUAL
D41 D42
12V_SYS 1 1
3 3 C396 18V_PHASE * L37
1.8V Voltage

*
5V_SB 2 2 1uF
16V, X7R, +/-10% 1uH@1KHz

*
R305 10 1.8V Power requires 1D8V_STR 3D3V_SYS
BAT54C +/-5% BAT54C
17A maximum current
close to Q61 Drain
5V_SB C371 EC48

*
R314
1uF
16V, X7R, +/-10% EC52
* 1000uF
+/-20% U15

1
*R313 Open 14.3K
* C459 * 470uF
* C470 1 8 VTT_DDR

D
VIN VCNTL

5
4.7K +/-1% U13 0.1uF 6.3V, +/-20% 10uF 7
+/-5% L Q36 c0805h14 VCNTL
1 Dummy
*R341 6

VCC

2
L r0402h4 Rocset BOOT 25V, X7R, +/-10% 10V, Y5V, +80%/-20% 100KOhm VCNTL
VCNTL 5
Open 7 2 R377 0 +/-5% G +/-1%
H COMP/OCSET UGATE AOD452 1D8V_STR r0402h4 4
C

L36 VOUT

16V, Y5V, +80%/-20%


Open

*
S
L B Q25 6 8 18V_PHASE 3 2
MMBT3904-7-F FB PHASE REFEN GND

GND
L RT9173 C440 EC44 C428
LGATE 4
E

R372 2.5uH@100KHz

1
* R326 C417
* 0.1uF * 1000uF
* 4.7uF
C

D
First H Need to Apply
*R308 APW7120KE-TRL 2.2 100KOhm
* 0.1uF +/-20% Dummy
*

3
R291 1K B Q23 91 Ohm Q29 +/-5% C452 EC45 EC46 +/-1% 16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%


25 SLP_S4J

2
S5
+/-5%
L
r0402h4 MMBT3904-7-F +/-1%
R328 0 +/-5% G C464 * 0.1uF * 1000uF
+/-20%
* 1000uF r0402h4
E

1
S0 H Don't in CIS
AOD472
* 2.2nF
50V, X7R, +/-10%
+/-20%

S
Near MOSFET Need to Check Change to Dummy

2
S3 H

VOUT= 0.8V(1+R638 / R658)


R638,R658 must less than 1k
Pull FB trace out after Cout
*
R307 115 Ohm
C +/-1% C
*

R303 220 +/-1% C364 18nF


*
Dummy Dummy 50V, Y5V, +80%/-20%
R304 R292
442 Ohm 1.02KOhm
+/-1% +/-1%
Reserved r0402h4

25 1D8V_GPIO13

25 1D8V_GPIO14

1D8V_STR

5V_SB

3D3V_SB
B B
U16 AZ1085D-ADJTRE1
3 Max. output current = 3A
VIN VOUT 2
ADJ

*R361
301
12V_SYS 5V_SB
1

+/-1%
5V_SB
3D3VADJ * R356
EC47 C443 EC50 1K
* 1000uF
+/-20% * 1uF
10V, Y5V, +80%/-20%
* 1000uF 915 series failure issue L
+/-5%
Dummy
*R366
499
+/-20%
H PWOK+ r0402h4
* R360

S
+/-1%
PWOK+ G APM2301AAC-TRL 1K
5V_SYS +/-5%
Q32
Q33 2N7002 PWOKJ r0402h4
EC51

D
G
* 1000uF
+/-20%

Q35 Q31
AP15N03H 2N7002 PWRG_ATX
PWRG_ATX 9,35
Vout=Vref(1+R2/R1)+IadjR2 D VCC_DUAL

R1 is Up Resistor.
Iadj=50uA
Vref=1.25V

A A

3D3V_DUAL 5V_DUAL

FOXCONN PCEG
Title
STR 1D8V 3D3V_DUAL 5V_DUAL
Size Document Number Rev
C G31M05 A

Date: Tuesday, January 08, 2008 Sheet 13 of 39


5 4 3 2 1
5 4 3 2 1

HAJ[35..3]
16 HAJ[35..3]

HDJ[63..0]
HDJ[63..0] 16 U11A
HAJ3 L5 D2 3 OF 7
HAJ4 A03# ADS# HADSJ 16 U11C
P6 A04# BNR# C2 HBNRJ 16
2 OF 7 HAJ5 M5 D4 P2 F26 TESTHI_0
U11B A05# HIT# HITJ 16 26 SMIJ SMI# TESTHI00
HAJ6 L4 H4 TP_RSPJ K3 W3 TESTHI_1
A06# RSP# TP1 26 A20MJ A20M# TESTHI01
HAJ7 M4 G8 R3 P1 TESTHI_11
A07# BPRI# HBPRIJ 16 26 FERRJ FERR#/PBE# TESTHI11
HDJ0 B4 G16 HDJ32 HAJ8 R4 B2 K1 W2 TESTHI_12
D00# D32# A08# DBSY# HDBSYJ 16 26 INTR LINT0 TESTHI12
HDJ1 C5 E15 HDJ33 HAJ9 T5 C1 L1 F25
D01# D33# A09# DRDY# HDRDYJ 16 26 NMI LINT1 TESTHI02
HDJ2 A4 E16 HDJ34 HAJ10 U6 E4 N2 G25
D02# D34# A10# HITM# HITMJ 16 26 IGNNEJ IGNNE# TESTHI03
HDJ3 C6 G18 HDJ35 HAJ11 T4 AB2 HIERRJ M3 G27
D03# D35# A11# IERR# 26 STPCLKJ STPCLK# TESTHI04
HDJ4 A5 G17 HDJ36 HAJ12 U5 P3 G26
HDJ5 D04# D36# HDJ37 HAJ13 A12# INIT# INITJ 26 TESTHI05
D
B6 D05# D37# F17 U4 A13# LOCK# C3 HLOCKJ 16 15 HVCCA A23 VCCA TESTHI06 G24 D
HDJ6 B7 F18 HDJ38 HAJ14 V5 E3 B23 F24 TESTHI_2_7
D06# D38# A14# TRDY# HTRDYJ 16 15 HVSSA VSSA TESTHI07
HDJ7 A7 E18 HDJ39 HAJ15 V4 AD3 TP_BINITJ VCC_PLL D23 AK6 FORCEPHJ
D07# D39# A15# BINIT# TP2 RSVD5 FORCEPH
HDJ8 A10 E19 HDJ40 HAJ16 W5 G7 C23 G6
D08# D40# A16# DEFER# HDEFERJ 16 15 HVCCIOPLL VCCIOPLL RSVD11
HDJ9 A11 F20 HDJ41 N4 F2 HGTLREF_1
HDJ10 D09# D41# HDJ42 RSVD1 EDRDY# TP_MCERRJ TESTHI_13
B10 D10# D42# E21 16 HREQJ[4..0] P5 RSVD2 MCERR# AB3 TP3 TESTHI13 L2 TESTHI_13 26
HDJ11 C11 F21 HDJ43 HREQJ0 K4 VID0 AM2 AH2
D11# D43# REQ0# 35 VID0 VID0 RSVD12
HDJ12 D8 G21 HDJ44 HREQJ1 J5 U2 TP_APJ0 VID1 AL5 N1
D12# D44# REQ1# AP0# TP4 35 VID1 VID1 PWRGOOD CPU_PWRG 25
HDJ13 B12 E22 HDJ45 HREQJ2 M6 U3 TP_APJ1 VID2 AM3 AL2 PROCHOTJ
D13# D45# REQ2# AP1# TP5 35 VID2 VID2 PROCHOT#
HDJ14 C12 D22 HDJ46 HREQJ3 K6 VID3 AL6 M2
D14# D46# REQ3# 35 VID3 VID3 THERMTRIP# THERMTRIPJ 26
HDJ15 D11 G22 HDJ47 HREQJ4 J6 F3 HBR0J VID4 AK4
D15# D47# HAJ[35..3] REQ4# BR0# HBR0J 16 35 VID4 VID4
HDBIJ0 A8 D19 HDBIJ2 R6 G3 TESTHI_8 VID5 AL4
16 HDBIJ0 DBI0# DBI2# HDBIJ2 16 16 HAJ[35..3] 16 HADSTBJ0 ADSTB0# TESTHI08 35 VID5 VID5
C8 G20 G5 G4 TESTHI_9 VID6 AM5 A13 HCOMP0
16 HDSTBNJ0 DSTBN0# DSTBN2# HDSTBNJ2 16 35 PECI PCREQ# TESTHI09 35 VID6 FC11 COMP0
B9 G19 H5 TESTHI_10 VID7 AM7 T1 HCOMP1
16 HDSTBPJ0 DSTBP0# DSTBP2# HDSTBPJ2 16 TESTHI10 35 VID7 FC12 COMP1
HAJ17 AB6 VID_SELECT AN7 G2 HCOMP2
A17# 10,25 VID_SELECT FC16 COMP2
HDJ16 G9 D20 HDJ48 HAJ18 W6 J16 TP_DPJ0 F28 R1 HCOMP3
D16# D48# A18# DP0# TP6 8 CK_200M_P_CPU BCLK0 COMP3
HDJ17 F8 D17 HDJ49 HAJ19 Y6 H15 TP_DPJ1 G28 J2 HCOMP4
D17# D49# A19# DP1# TP8 8 CK_200M_N_CPU BCLK1 COMP4
HDJ18 F9 A14 HDJ50 HAJ20 Y4 H16 TP_DPJ2 T2 HCOMP5
D18# D50# 4 mils width, 10 mils spacing A20# DP2# TP9 COMP5
HDJ19 E9 C15 HDJ51 HAJ21 AA4 J17 TP_DPJ3 AE8
D19# D51# A21# DP3# TP10 TP11 SKTOCC#
HDJ20 D7 C14 HDJ52 HAJ22 AD6 N5
HDJ21 D20# D52# HDJ53 HAJ23 A22# HGTLREF_1 RSVD13
E10 D21# D53# B15 AA5 A23# GTLREF1 H2 RSVD14 AE6
HDJ22 D10 C18 HDJ54 HAJ24 AB5 H1 HGTLREF_0 AL1 C9 H_TEST
D22# D54# A24# GTLREF0 35 THERMDA THERMDA RSVD15
HDJ23 F11 B16 HDJ55 HAJ25 AC5 E24 MCH_GTLREF_CPU AK1 G10 HGTLREF_0
D23# D55# A25# CS_GTLREF MCH_GTLREF_CPU 16 35 THERMDC THERMDC RSVD16
HDJ24 F12 A17 HDJ56 HAJ26 AB4 D16
HDJ25 D24# D56# HDJ57 HAJ27 A26# RSVD17
D13 D25# D57# B18 AF5 A27# AN3 VCCSENSE RSVD18 A20
HDJ26 E13 C21 HDJ58 HAJ28 AF4 G23 AN4 E23
HDJ27 D26# D58# HDJ59 HAJ29 A28# RESET# HCPURSTJ 16 VSSSENSE RSVD19
G13 D27# D59# B21 AG6 A29# 10 VCC_SENSE AN5 VCC_MB_REG RSVD21 F23
HDJ28 F14 B19 HDJ60 HAJ30 AG4 B3 AN6 J3
D28# D60# A30# RS0# HRSJ0 16 10 VSS_SENSE VSS_MB_REG RSVD24
HDJ29 G14 A19 HDJ61 HAJ31 AG5 F5
HDJ30 D29# D61# HDJ62 HAJ32 A31# RS1# HRSJ1 16 Changed pin name MS_ID1
F15 D30# D62# A22 AH4 A32# RS2# A3 HRSJ2 16 MSID1 V1
HDJ31 G15 D31# D63# B22 HDJ63 HAJ33 AH5 A33# F29 from RSV
RSVD9 MSID0 W1 MS_ID0
HDBIJ1 G11 C20 HDBIJ3 HAJ34 AJ5
16 HDBIJ1 DBI1# DBI3# HDBIJ3 16 A34#
G12 A16 HAJ35 AJ6
16 HDSTBNJ1 DSTBN1# DSTBN3# HDSTBNJ3 16 A35# THERMDA/THERMDC
E12 C17 AC4 Y1 CPU_BOOT
16 HDSTBPJ1 DSTBP1# DSTBP3# HDSTBPJ3 16 RSVD3 1. width=10 mils, spacing=10 mils. BOOTSELECT TP12
AE4 V2 TP_CPU_V2
RSVD4 2. route the lines in parallel LL_ID0 TP13
AD5 AA2 TP_CPU_AA2
16 HADSTBJ1 ADSTB1# LL_ID1 TP14
Socket-IntelPrescottCPU
Socket-IntelPrescottCPU
C 1 OF 7 C
Socket-IntelPrescottCPU

* *
R239 62 HTCK
VTT_OUT_RIGHT +/-5% r0402h4
1D5V_CORE
R242 62 HTRSTJ

*
R241 62 HTDO +/-5% r0402h4
VTT_OUT_LEFT MSID0: NC = 2005 Mainstream / Value, 2006 65W FMB +/-5% r0402h4 Dummy
Vss = 2005 Performance FMB
MSID1: Vss = 2005 Performance,2005 Mainstream/Value,2006 65W FMB In Design Guide is NC
Place at CPU end of route
*

R227 62 +/-5% r0402h4 HBR0J U11D 4 OF 7 FSB_VTT


* *

MS_ID0 R252 51 Ohm +/-5% r0402h4 VCC_PLL HTCK AE1 A29


Place at CPU end of route VTT_OUT_RIGHT HTDI TCK VTT1
AD1 TDI VTT2 B25
C112 C120 HTDO AF1 B29
TDO VTT3

1
MS_ID1 R235 51 Ohm +/-5% r0402h4 10uF
* * 10nF
25V, X7R, +/-10%
HTMS
HTRSTJ
AC1
AG1
TMS
TRST#
VTT4
VTT5
B30
C29
RN22 TESTHI_9 R263 130 +/-1% r0402h4 FORCEPHJ 10V, Y5V, +80%/-20% Reserved A26

2
51 7 8 TESTHI_8 VTT6
5 6 VTT7 B27
+/-5% TESTHI_10 R256 130 +/-1% r0402h4 PROCHOTJ HBPM0J AJ2 C28
8p4r0603h7 3 4 H_TEST HBPM1J BPM0# VTT8
* 1 2 AJ1 BPM1# VTT9 A25
VTT_OUT_RIGHT placed near pin D23, within 500 mils HBPM2J AD2 A28
HBPM3J BPM2# VTT10
AG2 BPM3# VTT11 A27
RN24 VID2 VTT_OUT_RIGHT HBPM4J AF2 C30
7 8 680 VID4 HBPM5J BPM4# VTT12
5 6 AG3 BPM5# VTT13 A30
RN17 TESTHI_12 +/-5% VID5 C25
* **

51 7 8 TESTHI_11 *3 4 8p4r0603h7 VID0 R238 62 +/-5% r0402h4 HIERRJ ICH_SYS_RSTJ AC2


VTT14
C26
8,9,25 ICH_SYS_RSTJ
+/-5% 5 6 TESTHI_1 1 2 DBR# VTT15
C27 VRMPWRGD 8,10,25
8p4r0603h7 3 4 TESTHI_13 R236 62 +/-5% r0402h4 HCPURSTJ VTT16
*
1 2 RN23 VID3 Place at CPU end of route
AK3
AJ3
ITPCLKOUT0 VTT17 B26
D27 *R244
0

*
7 8 680 VID6 PROCHOTJ R257 0 +/-5% ITPCLKOUT1 VTT18 +/-5%
D28
*

R231 49.9 +/-1% r0402h4 HCOMP4 5 6 +/-5% VID7 R264 1K +/-1% r0402h4VID_SELECT r0402h4 Dummy ICH_THRM_UP 25,35 FSBSEL0 VTT19 Dummy
B 3 4 8,16 FSBSEL0 G29 BSEL0 VTT20 D25 B
Reserved 10 mils width * 8p4r0603h7 VID1 FSBSEL1 H30 D26 r0402h4
7 mils spacing to low speed signals 1 2 8,16 FSBSEL1 FSBSEL2 BSEL1 VTT21
Stuff to enable Thermal event 8,16 FSBSEL2 G30 BSEL2 VTT22 B28
14mils spacing to high speed signals D29 VTT_PWRGD 11
max. 1200mils VTT23
VTT24 D30
FSB_VTT VTT_OUT_RIGHT AM6 VTT_OUT_RIGHT VTT_OUT_LEFT
**

R230 49.9 +/-1% r0402h4 HCOMP2 VTTPWRGD


AA1 VTT_OUT_RIGHT
* *

R162 49.9 +/-1% r0402h4 HCOMP0 R92 51 Ohm +/-5% r0402h4 TESTHI_0 VTT_OUT1 VTT_OUT_LEFT
VTT_OUT2 J1
VTT_SEL F27
VTT_OUT_LEFT VTT_SEL 12
10 mils width R91 51 Ohm +/-5% r0402h4 TESTHI_2_7 Socket-IntelPrescottCPU
7 mils spacing to low speed signals RN18 HBPM2J
14mils spacing to high speed signals 7 8 51 HBPM3J
max. 1200mils 5 6 +/-5% HTDI R229
* 3 4 8p4r0603h7 HTMS 51 Ohm
1 2 * +/-5%
***

R232 49.9 +/-1% r0402h4 HCOMP3 r0402h4 VTT_OUT_RIGHT VTT_OUT_LEFT


R233 49.9 +/-1% r0402h4 HCOMP1 RN19 HBPM1J
R234 49.9 +/-1% r0402h4 HCOMP5 7 8 51 HBPM0J TP_CPU_G1 C306 C305
VTT_OUT_LEFT 5 6 TP_CPU_G1 15
HBPM5J
Dummy
* 3
1
4
2
+/-5%
8p4r0603h7 HBPM4J * 0.1uF
* 0.1uF

16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%


Place BPM termination near CPU reserve for Kentsfield CPU support Dummy Dummy

VTT_OUT_RIGHT VTT_OUT_RIGHT

GTLREF voltage should be 0.63*VTT


12 mils width, 15 mils spacing
*R261
115 Ohm *R260
115 Ohm divider should be within 1.5" of the GTLREF pin
0.22nF caps should be placed near CPU pin
+/-1% +/-1%
A place series resistor as close to divider A
*

*
R253 10 HGTLREF_0 R250 10 HGTLREF_1
+/-1% +/-1%
C303

C313
* *R254
200
*
C304
220pF
C319
1uF * *R259
200 * 220pF
50V, NPO, +/-5%
1uF +/-1% 50V, NPO, +/-5% 10V, Y5V, +80%/-20% +/-1%
10V, Y5V, +80%/-20%
FOXCONN PCEG
Title
LGA775-1
Size Document Number Rev
C G31M05 A

Date: Monday, January 07, 2008 Sheet 14 of 39


5 4 3 2 1
5 4 3 2 1

VCCP VCCP VCCP


U11G 7 OF 7
U11E 5 OF 7 U11F 6 OF 7 FSB_VTT
AG22 VCCP1 VCCP93 AK12 AF9 VCCP185 VSS41 AL23 H22 VSS126 VSS211 D5
K29 VCCP2 VCCP94 AH22 AF22 VCCP186 VSS42 A12 H21 VSS127 VSS212 A9
AM26 VCCP3 VCCP95 T29 AH11 VCCP187 VSS43 L25 H20 VSS128 VSS213 D3 PLL Supply Filter
AL8 VCCP4 VCCP96 AM14 AJ14 VCCP188 VSS44 J7 H19 VSS129 VSS214 B1
AE12 AM25 AH19 AE28 H18 B5 R113
VCCP5 VCCP97 VCCP189 VSS45 VSS130 VSS215 0
AE11 VCCP6 VCCP98 AE9 AH29 VCCP190 VSS46 AE29 AB7 VSS131 VSS216 B8
W23 Y29 AH27 K5 H17 AJ4 +/-5%
VCCP7 VCCP99 VCCP191 VSS47 VSS132 VSS217
W24 VCCP8 VCCP100 AK25 AG28 VCCP192 VSS48 J4 AJ24 VSS133 VSS218 AE26
D W25 VCCP9 VCCP101 AK19 AL26 VCCP193 VSS49 AE30 AM17 VSS134 VSS219 AH1 D
T25 AG15 AM12 AN20 AC3 E29 TP_CPU_E29
VCCP10 VCCP102 VCCP194 VSS50 VSS135 VSS220 TP15
Y28 VCCP11 VCCP103 J22 J24 VCCP195 VSS51 AF10 H14 VSS136 VSS221 V7
AL18 VCCP12 VCCP104 T24 J13 VCCP196 VSS52 AE24 P28 VSS137 VSS222 C13
AC25 VCCP13 VCCP105 AG21 T28 VCCP197 VSS53 AM24 V6 VSS138 VSS223 AK24
W30 AM21 W28 AN23 AK2 AB30 HVCCIOPLL
VCCP14 VCCP106 VCCP198 VSS54 VSS139 VSS224 14 HVCCIOPLL
Y30 VCCP15 VCCP107 J25 J12 VCCP199 VSS55 H9 P27 VSS140 VSS225 L6
AN14 VCCP16 VCCP108 U30 J27 VCCP200 VSS56 H8 P26 VSS141 VSS226 L7
AD28 AL21 AG19 H13 AM28 AB29 HVCCA
VCCP17 VCCP109 VCCP201 VSS57 VSS142 VSS227 14 HVCCA
Y26 VCCP18 VCCP110 AG25 AL9 VCCP202 VSS58 AC6 AJ13 VSS143 VSS228 M1
AC29 VCCP19 VCCP111 AJ18 AD30 VCCP203 VSS59 AC7 W4 VSS144 VSS229 AB28
M29 J19 AF21 AH6 P25 E8 EC24
VCCP20 VCCP112 VCCP204 VSS60 VSS145 VSS230
U24
J23
VCCP21 VCCP113 AH30
J15
Y24
AK14
VCCP205 VSS61 C16
AM16
AJ20
W7
VSS146 VSS231 AG20
AN17
* 100uF
+/-20%
VCCP22 VCCP114 VCCP206 VSS62 VSS147 VSS232
AC27 VCCP23 VCCP115 AG12 J9 VCCP207 VSS63 AE25 P23 VSS148 VSS233 AB27
AM18 VCCP24 VCCP116 AJ22 M27 VCCP208 VSS64 AE27 AG13 VSS149 VSS234 AB26
AM19 VCCP25 VCCP117 J20 AF14 VCCP209 VSS65 AJ28 AG16 VSS150 VSS235 AN16
AB8 VCCP26 VCCP118 AH18 J30 VCCP210 VSS66 AJ7 AG17 VSS151 VSS236 M7
AC26 AH26 AG18 F19 C7 AB25 HVSSA
VCCP27 VCCP119 VCCP211 VSS67 VSS152 VSS237 14 HVSSA
J8 VCCP28 VCCP120 W27 AA8 VCCP212 VSS68 AH13 Y2 VSS153 VSS238 AB24
J28 AL25 AG8 AD7 L30 AB23 Notes:
VCCP29 VCCP121 VCCP213 VSS69 VSS154 VSS239 1. Cap. should be within 1.5" mils of the VCCA and VSSA pins
T30 VCCP30 VCCP122 AN8 AL29 VCCP214 VSS70 AH16 L29 VSS155 VSS240 N3
AM9 AH14 AD29 AK17 D15 AA30 2. VCCA route should be parallel and next to VSSA route to
VCCP31 VCCP123 VCCP215 VSS71 VSS156 VSS241 minimize loop area
AF15 VCCP32 VCCP124 U27 W8 VCCP216 VSS72 E17 AL27 VSS157 VSS242 F4
3. VCCIOPLL route should be parallel and next to VSSA route
AC8 VCCP33 VCCP125 T23 AH8 VCCP217 VSS73 AH17 Y7 VSS158 VSS243 AG10
to minimize loop area
AE14 VCCP34 VCCP126 R8 N24 VCCP218 VSS74 AH20 L27 VSS159 VSS244 AE13
3. Min. 12 mils trace from the filter to the processor pins
N23 VCCP35 VCCP127 AK22 AN22 VCCP219 VSS75 AE5 AA29 VSS160 VSS245 AF30 4. The inductors should be close to the cap.
C W29 VCCP36 VCCP128 AN29 J14 VCCP220 VSS76 AH23 N6 VSS161 VSS246 H28 C
U29 VCCP37 VCCP129 AG11 K26 VCCP221 VSS77 AE7 N7 VSS162 VSS247 F7
AC24 VCCP38 VCCP130 AK26 AF19 VCCP222 VSS78 AM13 AA28 VSS163 VSS248 AF29
AC23 VCCP39 VCCP131 J10 N8 VCCP223 VSS79 AH24 AN13 VSS164 VSS249 AF28
Y23 VCCP40 VCCP132 AJ15 AF12 VCCP224 VSS80 AJ30 AA27 VSS165 VSS250 G1 TP_CPU_G1 14
AN26 VCCP41 VCCP133 AG26 M28 VCCP225 VSS81 AJ10 AA26 VSS166 VSS251 AF27
AN25 VCCP42 VCCP134 AN9 AK9 VCCP226 VSS82 AF3 P4 VSS167 VSS252 AF26
AN11 VCCP43 VCCP135 AH15 VSS83 AK5 AA25 VSS168 VSS253 AF25
AN18 VCCP44 VCCP136 AF18 VSS84 AJ16 AA24 VSS169 VSS254 AN28
Y27 VCCP45 VCCP137 AL15 C10 VSS1 VSS85 AF6 P7 VSS170 VSS255 AN27
Y25 VCCP46 VCCP138 J26 D12 VSS2 VSS86 AK29 E26 VSS171 VSS256 AF24
AD24 J18 AJ17 V30 AF23 VTT_OUT_RIGHT
VCCP47 VCCP139 VSS87 VSS172 VSS257
AE23 VCCP48 VCCP140 J21 C24 VSS4 VSS88 F22 R2 VSS173 VSS258 AG24
AE22 VCCP49 VCCP141 AG27 K2 VSS5 VSS89 AH3 V29 VSS174 VSS259 AF17
AN19 VCCP50 VCCP142 AK15 C22 VSS6 VSS90 AK10 V28 VSS175 VSS260 AN24
V8 VCCP51 VCCP143 AF11 AN1 VSS7 VSS91 AM10 R5 VSS176 VSS261 H3
K8 AD23 B14 F16 V27

**
VCCP52 VCCP144 VSS8 VSS92 VSS177 R237 49.9 +/-1% r0402h4 HCOMP6
AE21 VCCP53 VCCP145 AM15 K7 VSS9 VSS93 AJ23 R7 VSS178 VSS263 P24
AM30 AF8 AE16 F13 E20 AE20 Dummy
VCCP54 VCCP146 VSS10 VSS94 VTT_OUT_LEFT VSS179 VSS264 R240 49.9 +/-1% r0402h4 HCOMP7
AE19 VCCP55 VCCP147 AK21 B11 VSS11 VSS95 AG7 AN10 VSS180 VSS265 AE17
AC30 AG30 AL10 F10 V25 E27 Reserved
VCCP56 VCCP148 VSS12 VSS96 VSS181 VSS266
AE15 VCCP57 VCCP149 AJ21 AK23 VSS13 VSS97 L26 T3 VSS182 VSS267 T7
M30 AM11 H12 AD4 R255 V24 R30 10 mils width
K27
VCCP58
VCCP59
VCCP150
VCCP151 AL11 AF7
VSS14
VSS15
VSS98
VSS99 H11 *
51 Ohm V23
VSS183
VSS184
VSS268
VSS269 AJ27 7 mils spacing to low speed signals
14mils spacing to high speed signals
M24 AJ11 AK7 L24 +/-5% T6 AB1
VCCP60 VCCP152 VSS16 VSS100 r0402h4 VSS185 VSS270 max. 1200mils
AN21 VCCP61 VCCP153 K30 H7 VSS17 VSS101 L23 AL7 VSS186 VSS271 AM4
T8 VCCP62 VCCP154 AL14 E14 VSS18 VSS102 AM23 E25 VSS187 VSS272 V26
B AC28 VCCP63 VCCP155 AN30 L28 VSS19 VSS103 A15 U1 VSS188 VSS273 AA23 B
N25 VCCP64 VCCP156 AH25 Y5 VSS20 VSS104 AH10 R29 VSS189 VSS274 AL28
AE18 AL12 E11 H29 R28 AF20 R163
TP17

*
VCCP65 VCCP157 VSS21 VSS105 VSS190 VSS275 24.9 HCOMP8
W26 VCCP66 VCCP158 AJ9 AL16 VSS22 VSS106 B24 R27 VSS191 VSS276 AG23
AD25 AK11 AL24 L3 R26 +/-1%
VCCP67 VCCP159 VSS23 VSS107 VSS192
M8 VCCP68 VCCP160 AG14 AK13 VSS24 VSS108 H27 R25 VSS193
N30 VCCP69 VCCP161 N29 TP68 AL3 VSS25 VSS109 A21 U7 VSS194
AD26 VCCP70 VCCP162 AL30 D21 VSS26 VSS110 AE2 R24 VSS195
AJ26 AJ25 AL20 AJ29 R23 15 mils width
*

VCCP71 VCCP163 VSS27 VSS111 VSS196 7 mils spacing to low speed signals
AM29 VCCP72 VCCP164 AH9 D18 VSS28 VSS112 A24 P30 VSS197
M25 J29 AN2 AK27 V3 14mils spacing to high speed signals
VCCP73 VCCP165 VRDSEL VSS29 VSS113 R100 VSS198 max. 1200mils
M26 VCCP74 VCCP166 J11 AK16 VSS30 VSS114 AK28 P29 VSS199
L8 K25 AK20 B20 1K AF16 F6 IMPSEL
VCCP75 VCCP167 VSS31 VSS115 +/-5% VSS200 RSVD26
U25 VCCP76 VCCP168 P8 AM27 VSS32 VSS116 AM20 AE10 VSS201
Y8 K23 AM1 H26 r0402h4 AF13 Y3 HCOMP6
VCCP77 VCCP169 VSS33 VSS117 Dummy VSS202 RSVD28 HCOMP7
AJ12 VCCP78 VCCP170 AL19 AL13 VSS34 VSS118 B17 H6 VSS203 RSVD29 AE3
AD27 AM8 AL17 H25 A18

*
VCCP79 VCCP171 VSS35 VSS119 VSS204 R228 51 Ohm IMPSEL
U23 VCCP80 VCCP172 T26 C19 VSS36 VSS120 H24 A2 VSS205 RSVD31 E7
M23 N28 E28 AA3 E2 B13 HCOMP8 +/-5% r0402h4
VCCP81 VCCP173 VSS37 VSS121 VSS206 RSVD32
AG29 VCCP82 VCCP174 AH12 AH7 VSS38 VSS122 AA7 D9 VSS207 RSVD33 D14
N27 VCCP83 VCCP175 AL22 AK30 VSS39 VSS123 H23 C4 VSS208 RSVD34 E6
AM22 VCCP84 VCCP176 AN15 D24 VSS40 VSS124 AA6 A6 VSS209 RSVD35 D1
U28 VCCP85 VCCP177 AJ8 VSS125 H10 D6 VSS210 RSVD36 E5
K28 VCCP86 VCCP178 U26
U8 VCCP87 VCCP179 AJ19 Socket-IntelPrescottCPU Socket-IntelPrescottCPU
AK18 VCCP88 VCCP180 T27
AD8 VCCP89 VCCP181 AK8
A K24 VCCP90 VCCP182 AN12 A
AH28 VCCP91 VCCP183 AG9
AH21 VCCP92 VCCP184 N26

Socket-IntelPrescottCPU FOXCONN PCEG


Title
LGA775-2
Size Document Number Rev
Custom G31M05 A

Date: Saturday, January 05, 2008 Sheet 15 of 39


5 4 3 2 1
5 4 3 2 1

*R412
27 *R393
39 *R413
27 *R394
39
+/-1% +/-1% +/-1% +/-1%
U1MCH HDJ[63..0] r0603h6 r0603h6 r0603h6 r0603h6
14 HAJ[35..3] U12B HDJ[63..0] 14 Placed both Resistors close to GMCH
@946 @G31 @946 @G31
HAJ3 J42 R40 HDJ0 Within 750 mils
HAJ4 HA3# HD0# HDJ1 U12E W=4 mils, S=10 mils from GMCH to connector
L39 HA4# HD1# P41
HAJ5 J40 R41 HDJ2

**
HAJ6 HA5# HD2# HDJ3 U1MCH BSEL0 HSYNC_P R150 39 +/-1% #R393#R412
L37 HA6# HD3# N40 U12A G20 BSEL0 HSYNC C15 HSYNC 24
HAJ7 L36 R42 HDJ4 BSEL1 J20 D15 VSYNC_P R145 39 +/-1% #R394#R413
HAJ8 HA7# HD4# HDJ5 EXP_RXP0 EXP_TXP0 BSEL2 BSEL1 VSYNC Modify by Steven 051707 Apply 0402 or not VSYNC 24
K42 HA8# HD5# M39 23 EXP_RXP0 F15 EXP_RXP0 EXP_TXP0 D11 EXP_TXP0 23 J18 BSEL2
HAJ9 N32 N41 HDJ6 EXP_RXN0 G15 D12 EXP_TXN0 TP16 TP_ALLZTEST K20 B18
HA9# HD6# 23 EXP_RXN0 EXP_RXN0* EXP_TXN0* EXP_TXN0 23 ALLZTEST RED RED 24
HAJ10 N34 N42 HDJ7 EXP_RXP1 K15 B11 EXP_TXP1 F20 C19
HA10# HD7# 23 EXP_RXP1 EXP_RXP1 EXP_TXP1 EXP_TXP1 23 XORTEST GREEN GREEN 24
HAJ11 M38 L41 HDJ8 EXP_RXN1 J15 A10 EXP_TXN1 G18 B20

FSB
HA11# HD8# 23 EXP_RXN1 EXP_RXN1* EXP_TXN1* EXP_TXN1 23 RESERVED_24 BLUE BLUE 24
HAJ12 N37 J39 HDJ9 EXP_RXP2 F12 C10 EXP_TXP2 GMCH_EXP_SLR E18 C18 R157 R158 R159
HA12# HD9# 23 EXP_RXP2 EXP_RXP2 EXP_TXP2 EXP_TXP2 23 EXP_SLR RED#
HAJ13 HDJ10 EXP_RXN2 EXP_TXN2
M36 HA13# HD10# L42 23 EXP_RXN2 E12 EXP_RXN2* EXP_TXN2* D9 EXP_TXN2 23 K17 RESERVED_25 GREEN# D19
*150 150 150
+/ -1% *+/ -1% *+/ -1%

VGA
HAJ14 R34 J41 HDJ11 EXP_RXP3 J12 B9 EXP_TXP3 GMCH_EXP_EN_HDR J17 D20
D HA14# HD11# 23 EXP_RXP3 EXP_RXP3 EXP_TXP3 EXP_TXP3 23 EXP_EN BLUE# D
HAJ15 N35 K41 HDJ12 EXP_RXN3 H12 B7 EXP_TXN3 H18 r0402h4 r0402h4 r0402h4
HA15# HD12# 23 EXP_RXN3 EXP_RXN3* EXP_TXN3* EXP_TXN3 23 RESERVED
HAJ16 N38 G40 HDJ13 EXP_RXP4 J11 D7 EXP_TXP4 L13 DDCA_DATA
HA16# HD13# 23 EXP_RXP4 EXP_RXP4 EXP_TXP4 EXP_TXP4 23 DDC_DATA DDCA_DATA 24
HAJ17 U37 F41 HDJ14 EXP_RXN4 H11 D6 EXP_TXN4 L17 M13 DDCA_CLK
HA17# HD14# 23 EXP_RXN4 EXP_RXN4* EXP_TXN4* EXP_TXN4 23 RESERVED_1 DDC_CLK DDCA_CLK 24 Placed close to
HAJ18 N39 F42 HDJ15 EXP_RXP5 F7 B5 EXP_TXP5 N17
HA18# HD15# 23 EXP_RXP5 EXP_RXP5 EXP_TXP5 EXP_TXP5 23 RESERVED_2 GMCH within
HAJ19 R37 C42 HDJ16 EXP_RXN5 E7 B6 EXP_TXN5 N18 A20 REFSET
HA19# HD16# 23 EXP_RXN5 EXP_RXN5* EXP_TXN5* EXP_TXN5 23 RESERVED_3 REFSET 300 mils
HAJ20 P42 D41 HDJ17 EXP_RXP6 E5 B3 EXP_TXP6 N15
HA20# HD17# 23 EXP_RXP6 EXP_RXP6 EXP_TXP6 EXP_TXP6 23 RESERVED_4
HAJ21 R39 F38 HDJ18 EXP_RXN6 F6 B4 EXP_TXN6 M20 C14 CK_96M_P_GMCH
HA21# HD18# 23 EXP_RXN6 EXP_RXN6* EXP_TXN6* EXP_TXN6 23 RESERVED_5 DREFCLKP CK_96M_P_GMCH 8
HAJ22 V36 G37 HDJ19 EXP_RXP7 C2 F2 EXP_TXP7 L15 D13 CK_96M_N_GMCH
HA22# HD19# 23 EXP_RXP7 EXP_RXP7 EXP_TXP7 EXP_TXP7 23 Controller Link Routing RESERVED_6 DREFCLKN CK_96M_N_GMCH 8
HAJ23 R38 E42 HDJ20 EXP_RXN7 D2 E2 EXP_TXN7 L18 L12
HA23# HD20# 23 EXP_RXN7 EXP_RXN7* EXP_TXN7* EXP_TXN7 23 1. width=4 mils, Spacing=7 mils RESERVED_7 VCC 1D25V_MCH
HAJ24 U36 E39 HDJ21 EXP_RXP8 G6 F4 EXP_TXP8 M18 M11

PCIE
HA24# HD21# 23 EXP_RXP8 EXP_RXP8 EXP_TXP8 EXP_TXP8 23 2. CL_CLK and CL_DATA should be length RESERVED_8 VSS
HAJ25 U33 E37 HDJ22 EXP_RXN8 G5 G4 EXP_TXN8
HA25# HD22# 23 EXP_RXN8 EXP_RXN8* EXP_TXN8* EXP_TXN8 23 matched to within 100 mils
HAJ26 R35 C39 HDJ23 EXP_RXP9 L9 J4 EXP_TXP9
HA26# HD23# 23 EXP_RXP9 EXP_RXP9 EXP_TXP9 EXP_TXP9 23
HAJ27 V33 B39 HDJ24 EXP_RXN9 L8 K3 EXP_TXN9
HA27# HD24# 23 EXP_RXN9 EXP_RXN9* EXP_TXN9* EXP_TXN9 23
HAJ28 V35 G33 HDJ25 EXP_RXP10 M8 L2 EXP_TXP10 TP19 AD12 F13 TP_MCH_F13
HA28# HD25# 23 EXP_RXP10 EXP_RXP10 EXP_TXP10 EXP_TXP10 23 CL_DATA RESERVED_001 TP20
HAJ29 Y34 A37 HDJ26 EXP_RXN10 M9 K1 EXP_TXN10 TP18 AD13 F17
HA29# HD26# 23 EXP_RXN10 EXP_RXN10* EXP_TXN10* EXP_TXN10 23 CL_CLK RESERVED_23
HAJ30 V42 F33 HDJ27 EXP_RXP11 M4 N2 EXP_TXP11 CL_VREF_MCH AM5 A14 TP_MCH_A14

MISC
HA30# HD27# 23 EXP_RXP11 EXP_RXP11 EXP_TXP11 EXP_TXP11 23 CL_VREF RESERVED_26 TP22
HAJ31 V38 E35 HDJ28 EXP_RXN11 L4 M2 EXP_TXN11 PLTRSTJR206 1.65KOhm CL_RST AA12 AM18 ICH_PLTRSTJ
HA31# HD28# 23 EXP_RXN11 EXP_RXN11* EXP_TXN11* EXP_TXN11 23 CL_RST# RSTIN# PLTRSTJ 25,29,35
HAJ32 Y36 K32 HDJ29 EXP_RXP12 M5 P3 EXP_TXP12 +/-1% r0402h4 AM15 AM17 PWRGD_3V
EXP_TXP12 23 PWRGD_3V 25,35

*
HAJ33 HA32# HD29# HDJ30 23 EXP_RXP12 EXP_RXN12 EXP_RXP12 EXP_TXP12 EXP_TXN12 R210 1K CL_PWROK PWROK ICH_SYNCJ
Y38 HA33# HD30# H32 23 EXP_RXN12 M6 EXP_RXN12* EXP_TXN12* N4 EXP_TXN12 23 ICH_SYNC# J13 ICH_SYNCJ 25
HAJ34 Y39 B34 HDJ31 EXP_RXP13 R9 R2 EXP_TXP13 +/-1% r0402h4
HA34# HD31# 23 EXP_RXP13 EXP_RXP13 EXP_TXP13 EXP_TXP13 23
HAJ35 AA37 J31 HDJ32 EXP_RXN13 R10 P1 EXP_TXN13 A42 TP_MCH_DET_N
HA35# HD32# 23 EXP_RXN13 EXP_RXN13* EXP_TXN13* EXP_TXN13 23 NC TP23
F32 HDJ33 EXP_RXP14 T4 U2 EXP_TXP14 PWRGD_3V
HD33# 23 EXP_RXP14 EXP_RXP14 EXP_TXP14 EXP_TXP14 23
M31 HDJ34 EXP_RXN14 R4 T2 EXP_TXN14 AA10
14 HREQJ[4..0] HD34# 23 EXP_RXN14 EXP_RXN14* EXP_TXN14* EXP_TXN14 23 RESERVED_9
HREQJ0 F40 E31 HDJ35 EXP_RXP15 R6 V3 EXP_TXP15 AA9 BC43 TP_MCH_CGC_1
HREQ0# HD35# 23 EXP_RXP15 EXP_RXP15 EXP_TXP15 EXP_TXP15 23 RESERVED_10 TEST0 TP24
HREQJ1 L35 K31 HDJ36 EXP_RXN15 R7 U4 EXP_TXN15 AA11 BC1 TP_MCH_CGC_2
HREQ1# HD36# 23 EXP_RXN15 EXP_RXN15* EXP_TXN15* EXP_TXN15 23 RESERVED_11 TEST1 TP26
HREQJ2 L38 G31 HDJ37 Y12 A43 TP_MCH_CGC_3
HREQ2# HD37# RESERVED_12 TEST2 TP25
HREQJ3 G43 K29 HDJ38 DMI_RXP0 W2 V7 C2390.1uF 16V, X7R, +/-10% DMI_TXP0
DMI_TXP0 25

********
HREQJ4 HREQ3# HD38# HDJ39 25 DMI_RXP0 DMI_RXN0 DMI_RXP0 DMI_TXP0 C2380.1uF 16V, X7R, +/-10% DMI_TXN0
J37 HREQ4# HD39# F31 25 DMI_RXN0 V1 DMI_RXN0* DMI_TXN0* V6 DMI_TXN0 25 U30 RESERVED_13
J29 HDJ40 DMI_RXP1 Y8 W4 C2290.1uF 16V, X7R, +/-10% DMI_TXP1 U31 N20
HD40# 25 DMI_RXP1 DMI_RXP1 DMI_TXP1 DMI_TXP1 25 RESERVED_14 NC_1
M34 F29 HDJ41 DMI_RXN1 Y9 Y4 C2330.1uF 16V, X7R, +/-10% DMI_TXN1 R29 BC42
14 HADSTBJ0 HADSTB0# HD41# 25 DMI_RXN1 DMI_RXN1* DMI_TXN1* DMI_TXN1 25 RESERVED_15 NC_2

DMI
U34 L27 HDJ42 DMI_RXP2 AA7 AC8 C2400.1uF 16V, X7R, +/-10% DMI_TXP2 R30 BC2
14 HADSTBJ1 HADSTB1# HD42# 25 DMI_RXP2 DMI_RXP2 DMI_TXP2 DMI_TXP2 25 RESERVED_16 NC_3
K27 HDJ43 DMI_RXN2 AA6 AC9 C2450.1uF 16V, X7R, +/-10% DMI_TXN2 BB43
HD43# 25 DMI_RXN2 DMI_RXN2* DMI_TXN2* DMI_TXN2 25 NC_4
L40 H26 HDJ44 DMI_RXP3 AB3 Y2 C2370.1uF 16V, X7R, +/-10% DMI_TXP3 U12 BB1
14 HDSTBPJ0 HDSTBP0# HD44# 25 DMI_RXP3 DMI_RXP3 DMI_TXP3 DMI_TXP3 25 RESERVED_17 NC_5
M43 L26 HDJ45 DMI_RXN3 AA4 AA2 C2430.1uF 16V, X7R, +/-10% DMI_TXN3 U11 B43
14 HDSTBNJ0 HDSTBN0# HD45# 25 DMI_RXN3 DMI_RXN3* DMI_TXN3* DMI_TXN3 25 RESERVED_18 NC_6
HDBIJ0 M40 J26 HDJ46 R12 B42 3D3V_SYS
14 HDBIJ0 HDINV0# HD46# RESERVED_19 NC_7
G35 M26 HDJ47 R13 B2
14 HDSTBPJ1 HDSTBP1# HD47# RESERVED_20 5 OF 7 NC_8
H33 C33 HDJ48 CK_PE_100M_P_GMCH B12 R191
14 HDSTBNJ1 HDSTBN1# HD48# 8 CK_PE_100M_P_GMCH GCLKP
C HDBIJ1 J33 LE82G31 C35 HDJ49 CK_PE_100M_N_GMCH B13 AC11 GMCH_EXP_COMP 24.9 1D25V_MCH C
14 HDBIJ1 HDINV1# HD49# 8 CK_PE_100M_N_GMCH GCLKN* EXP_COMPO
G27 E41 HDJ50 AC12 +/-1%
14 HDSTBPJ2 HDSTBP2# HD50# HDJ51 EXP_COMPI
14 HDSTBNJ2 H27 HDSTBN2# HD51# B41 23 SDVO_CTRLDATA G17 SDVO_CTRLDATA LE82G31
HDBIJ2 G29 D42 HDJ52 E17 width 10 mils, spacing 6 mils at breakout
14 HDBIJ2

*
HDINV2# HD52# HDJ53 23 SDVO_CTRLCLK SDVO_CTRLCLK 2 OF 7 10 mils after that bga1226_1h25 ICH_SYNCJ R156 1K
14 HDSTBPJ3 B38 HDSTBP3# HD53# C40
HDJ54 Del R934,R935 0Ohm RES +/-5% r0402h4
14 HDSTBNJ3 D38 HDSTBN3# HD54# D35 LE82G31
HDBIJ3 E33 B40 HDJ55
14 HDBIJ3 HDINV3# HD55# #U27#U28
R200,R201,R205,R208,R209,R210 USE 0 OHM FOR 946PL.
C38 HDJ56 bga1226_1h25
HD56# HDJ57 DUMMY R192,R194.
W40 D37

*
14 HADSJ HADS# HD57# HDJ58 PWRGD_3V R62 10K
14 HTRDYJ Y40 HTRDY# HD58# B33
W41 D33 HDJ59 #U27#U28 +/-5% Dummy
14 HDRDYJ HDRDY# HD59# HDJ60
14 HDEFERJ T43 HDEFER# HD60# C34
Y43 B35 HDJ61
14 HITMJ HHITM# HD61# HDJ62 1D25V_MCH
14 HITJ U42 HHIT# HD62# A32
V41 D32 HDJ63
14 HLOCKJ HLOCK# HD63#
AA42

****
14 HBR0J HBREQ0# HSWING DMI_RXP0 R177 4.7K +/-5% R160
14 HBNRJ W42 HBNR# HSWING B25
G39 D23 HRCOMP 1.3KOhm REFSET
14 HBPRIJ HBPRI# HRCOMP HSCOMP DMI_RXP1 R178 4.7K +/-5% +/-1%
14 HDBSYJ U40 HDBSY# HSCOMP C25
U41 D25 HSCOMPJ
14 HRSJ0 HRS0# HSCOMP# MCH_GTLREF DMI_RXP2 R180 4.7K +/-5%
14 HRSJ1 AA41 HRS1# HDVREF D24
U39 B24 placed close to GMCH within 500 mils
14 HRSJ2 HRS2# HACCVREF DMI_RXP3 R184 4.7K +/-5% 4 mils width
14 HCPURSTJ C31 HCPURST# HCLKP R32 CK_200M_P_GMCH 8
U32 6 mils spacing to static signals
HCLKN CK_200M_N_GMCH 8 12 mils spacing to toppling signals
1 OF 7

bga1226_1h25

#U27#U28
FSB_VTT FSB_VTT COMP SIGNAL TERMINATION
*

HSCOMPJ
*R139
301 Resistor and Capacitor
next to each other.
R154
+/-1%
49.9
r0402h4
* 3.3pF
+/-1% C185 50V, NPO, +/-0.25pF
B
Dummy B
*

R152 49.9 HSWING

***
+/-1% r0402h4 FSBSEL0 R135 10K BSEL0
*

R151 49.9 HSCOMP +/-5% 1D25V_MCH


R142 C165 +/-1% r0402h4 C184 FSBSEL1 R136 10K BSEL1
* 100 Ohm
* 10nF
* 3.3pF +/-5%
+/-1% 25V, X7R, +/-10% 50V, NPO, +/-0.25pF FSBSEL2 R134 10K BSEL2

HSWING voltage should be 0.25*FSB_VTT


Dummy 23 GMCH_EXP_EN_HDR
GMCH_EXP_EN_HDR +/-5% *R212
1K
+/-1%
10 mils width, 10 mils spacing r0402h4
max. 3 inches long
CL_VREF_MCH
4 mils width, 6 mils spacing in the breakout FSBSEL0
4 mils width, 14 mils spacing after the breakout 8,14 FSBSEL0
max. 750 mils
routed on a single layer and matched within 50mils
*R207
392
*
C275
0.1uF
0.349V
FSBSEL1 +/-1% 16V, Y5V, +80%/-20%
R155 8,14 FSBSEL1 r0402h4
HRCOMP 16.9 Place close to VREF Pin
+/-1% FSBSEL2
change to 16.9ohm 8,14 FSBSEL2

10 mils width, 7 mils spacing min. 4 mils width


max. 500 mils 10 mils spacing
*

5 on 5 mils in breakout, max 250 mils GMCH_EXP_SLR 5 mils min. for max. of 300 mils in breakout
1D25V_MCH R146 1K
+/-5% r0402h4
ATX: 1
BTX: 0

FSB_VTT
Not used for CoreTM2 Duo and Wolfdale with G31 Chipset
Del or not in G31
*

*R132 R128
100 Ohm +/-5%
0
MCH_GTLREF_CPU 14
+/-1%
*

A R144 MCH_GTLREF A

C164 10

* 1uF *R131
200 +/-1%
*
C167
220pF
+/-1% 50V, NPO, +/-5%
10V, Y5V, +80%/-20%

GTLREF voltage should be 0.63*VTT = 0.75V FOXCONN PCEG


12 mils width, 15 mils spacing
divider should be within 1.5" of the GTLREF pin Title
220pF caps should be placed near MCH pin
place series resistor as close to divider BearLake-GMCH-1
Resistor and Capacitor next to each other Size Document Number Rev
C G31M05 A

Date: Saturday, January 05, 2008 Sheet 16 of 39


5 4 3 2 1
5 4 3 2 1

U12D U1MCH
U12C U1MCH
21,22 M_MAA_B[14..0] M_DQS_B[7..0] 22
M_MAA_B0 BB17 AV6 M_DQS_B0
19,20 M_MAA_A[14..0] M_DQS_A[7..0] 20 SMA_B0 SDQS_B0 M_DQS_BJ[7..0] 22
M_MAA_A0 BA31 AU4 M_DQS_A0 M_MAA_B1 AY17 AU5 M_DQS_BJ0
SMA_A0 SDQS_A0 M_DQS_AJ[7..0] 20 SMA_B1 SDQS_B0# M_DQM_B[7..0] 22
M_MAA_A1 BB25 AR3 M_DQS_AJ0 M_MAA_B2 BA17 AR7 M_DQM_B0
SMA_A1 SDQS_A0# M_DQM_A[7..0] 20 SMA_B2 SDM_B0 M_DATA_B[63..0] 22
M_MAA_A2 BA26 AR2 M_DQM_A0 M_MAA_B3 BC16
SMA_A2 SDM_A0 M_DATA_A[63..0] 20 SMA_B3
M_MAA_A3 BA25 M_MAA_B4 AW15 AN7 M_DATA_B0
M_MAA_A4 SMA_A3 M_DATA_A0 M_MAA_B5 SMA_B4 SDQ_B0 M_DATA_B1
AY25 SMA_A4 SDQ_A0 AR5 BA15 SMA_B5 SDQ_B1 AN8
M_MAA_A5 BA23 AR4 M_DATA_A1 M_MAA_B6 BB15 AW5 M_DATA_B2
M_MAA_A6 SMA_A5 SDQ_A1 M_DATA_A2 M_MAA_B7 SMA_B6 SDQ_B2 M_DATA_B3
AY24 SMA_A6 SDQ_A2 AV3 BA14 SMA_B7 SDQ_B3 AW7
M_MAA_A7 AY23 AV2 M_DATA_A3 M_MAA_B8 AY15 AN5 M_DATA_B4
M_MAA_A8 SMA_A7 SDQ_A3 M_DATA_A4 M_MAA_B9 SMA_B8 SDQ_B4 M_DATA_B5
BB23 SMA_A8 SDQ_A4 AP3 BB14 SMA_B9 SDQ_B5 AN6
M_MAA_A9 BA22 AP2 M_DATA_A5 M_MAA_B10 AW18 AN9 M_DATA_B6
M_MAA_A10 SMA_A9 SDQ_A5 M_DATA_A6 M_MAA_B11 SMA_B10 SDQ_B6 M_DATA_B7
AY33 SMA_A10 SDQ_A6 AU1 BB13 SMA_B11 SDQ_B7 AU7
M_MAA_A11 BB22 AV4 M_DATA_A7 M_MAA_B12 BA13
D SMA_A11 SDQ_A7 SMA_B12 M_DQS_B[7..0] 22 D
M_MAA_A12 AW21 M_MAA_B13 AY29 AR12 M_DQS_B1
SMA_A12 M_DQS_A[7..0] 20 SMA_B13 SDQS_B1 M_DQS_BJ[7..0] 22
M_MAA_A13 AY38 BB3 M_DQS_A1 M_MAA_B14 AY13 AP12 M_DQS_BJ1
SMA_A13 SDQS_A1 M_DQS_AJ[7..0] 20 SMA_B14 SDQS_B1# M_DQM_B[7..0] 22
M_MAA_A14 BA21 BA4 M_DQS_AJ1 AW9 M_DQM_B1
SMA_A14 SDQS_A1# M_DQM_A[7..0] 20 SDM_B1 M_DATA_B[63..0] 22
BA2 M_DQM_A1 BA27
SDM_A1 M_DATA_A[63..0] 20 21,22 M_WE_BJ SWE_B#
BB34 AW29 AT11 M_DATA_B8
19,20 M_WE_AJ SWE_A# M_DATA_A8 21,22 M_CAS_BJ SCAS_B# SDQ_B8 M_DATA_B9
19,20 M_CAS_AJ AY35 SCAS_A# SDQ_A8 AY2 21,22 M_RAS_BJ AW26 SRAS_B# SDQ_B9 AU11
BB33 AY3 M_DATA_A9 AP13 M_DATA_B10
19,20 M_RAS_AJ SRAS_A# SDQ_A9 M_DATA_A10 21,22 M_BS_B[2..0] M_BS_B0 SDQ_B10 M_DATA_B11
SDQ_A10 BB5 AY19 SBS_B0 SDQ_B11 AR13
M_BS_A0 BA33 AY6 M_DATA_A11 M_BS_B1 BA18 AR11 M_DATA_B12
M_BS_A1 SBS_A0 SDQ_A11 M_DATA_A12 M_BS_B2 SBS_B1 SDQ_B12 M_DATA_B13
AW32 SBS_A1 SDQ_A12 AW2 BC12 SBS_B2 SDQ_B13 AU9
M_BS_A2 BB21 AW3 M_DATA_A13 AV12 M_DATA_B14
SBS_A2 SDQ_A13 M_DATA_A14 SDQ_B14 M_DATA_B15
19,20 M_BS_A[2..0] SDQ_A14 BA5 21,22 M_SCS_B0J BB27 SCS_B0# SDQ_B15 AU12
AW35 BB4 M_DATA_A15 BB30
19,20 M_SCS_A0J SCS_A0# SDQ_A15 21,22 M_SCS_B1J SCS_B1# M_DQS_B[7..0] 22
BA35 AY27 AP15 M_DQS_B2
19,20 M_SCS_A1J SCS_A1# M_DQS_A[7..0] 20 SCS_B2# SDQS_B2 M_DQS_BJ[7..0] 22
BA34 BB9 M_DQS_A2 AY31 AR15 M_DQS_BJ2
SCS_A2# SDQS_A2 M_DQS_AJ[7..0] 20 SCS_B3# SDQS_B2# M_DQM_B[7..0] 22
BB38 BA9 M_DQS_AJ2 AW13 M_DQM_B2
SCS_A3# SDQS_A2# M_DQM_A[7..0] 20 21,22 M_SCKE_B[1..0] SDM_B2 M_DATA_B[63..0] 22
AY9 M_DQM_A2 M_SCKE_B0 AY12
19,20 M_SCKE_A[1..0] SDM_A2 M_DATA_A[63..0] 20 SCKE_B0
M_SCKE_A0 BC20 M_SCKE_B1 AW12 AU15 M_DATA_B16
M_SCKE_A1 SCKE_A0 M_DATA_A16 SCKE_B1 SDQ_B16 M_DATA_B17
AY20 SCKE_A1 SDQ_A16 AY7 BB11 SCKE_B2 SDQ_B17 AV13
AY21 BC7 M_DATA_A17 BA11 AU17 M_DATA_B18
SCKE_A2 SDQ_A17 M_DATA_A18 21,22 M_ODT_B[1..0] M_ODT_B0 SCKE_B3 SDQ_B18 M_DATA_B19
BA19 SCKE_A3 SDQ_A18 AW11 BA29 SODT_B0 SDQ_B19 AT17
AY11 M_DATA_A19 M_ODT_B1 BA30 AU13 M_DATA_B20
19,20 M_ODT_A[1..0] M_ODT_A0 SDQ_A19 M_DATA_A20 SODT_B1 SDQ_B20 M_DATA_B21
AY37 SODT_A0 SDQ_A20 BB6 BB29 SODT_B2 SDQ_B21 AM13
M_ODT_A1 BA38 BA6 M_DATA_A21 BB31 AV15 M_DATA_B22
SODT_A1 SDQ_A21 M_DATA_A22 SODT_B3 SDQ_B22 M_DATA_B23
BB35 SODT_A2 SDQ_A22 BA10 SDQ_B23 AW17
BA39 BB10 M_DATA_A23 AV31
SODT_A3 SDQ_A23 22 CK_M_200M_P_DDR0_B SCLK_B0 M_DQS_B[7..0] 22
AW31 AT24 M_DQS_B3
M_DQS_A[7..0] 20 22 CK_M_200M_N_DDR0_B SCLK_B0# SDQS_B3 M_DQS_BJ[7..0] 22
AU31 AT20 M_DQS_A3 AU27 AU26 M_DQS_BJ3
20 CK_M_200M_P_DDR0_A SCLK_A0 SDQS_A3 M_DQS_AJ[7..0] 20 22 CK_M_200M_P_DDR1_B SCLK_B1 SDQS_B3# M_DQM_B[7..0] 22
AR31 AU18 M_DQS_AJ3 AT27 AP23 M_DQM_B3
20 CK_M_200M_N_DDR0_A SCLK_A0# SDQS_A3# M_DQM_A[7..0] 20 22 CK_M_200M_N_DDR1_B SCLK_B1# SDM_B3 M_DATA_B[63..0] 22
AP27 AN18 M_DQM_A3 AV32
20 CK_M_200M_P_DDR1_A SCLK_A1 SDM_A3 M_DATA_A[63..0] 20 22 CK_M_200M_P_DDR2_B SCLK_B2
AN27 AT32 AV24 M_DATA_B24
20 CK_M_200M_N_DDR1_A SCLK_A1# M_DATA_A24 22 CK_M_200M_N_DDR2_B SCLK_B2# SDQ_B24 M_DATA_B25
20 CK_M_200M_P_DDR2_A AV33 SCLK_A2 SDQ_A24 AT18 AU29 SCLK_B3 SDQ_B25 AT23
AW33 AR18 M_DATA_A25 AR29 AT26 M_DATA_B26
20 CK_M_200M_N_DDR2_A SCLK_A2# SDQ_A25 M_DATA_A26 SCLK_B3# SDQ_B26 M_DATA_B27
AP29 SCLK_A3 SDQ_A26 AU21 AV29 SCLK_B4 SDQ_B27 AP26
AP31 AT21 M_DATA_A27 AW27 AU23 M_DATA_B28
SCLK_A3# SDQ_A27 M_DATA_A28 SCLK_B4# SDQ_B28 M_DATA_B29
AM26 SCLK_A4 SDQ_A28 AP17 AN33 SCLK_B5 SDQ_B29 AW23
AM27 AN17 M_DATA_A29 AP32 AR24 M_DATA_B30
SCLK_A4# SDQ_A29 M_DATA_A30 SCLK_B5# SDQ_B30 M_DATA_B31
C AT33 SCLK_A5 SDQ_A30 AP20 SDQ_B31 AN26 C
AU33 AV20 M_DATA_A31
SCLK_A5# SDQ_A31 M_DQS_B[7..0] 22
AW39 M_DQS_B4
M_DQS_A[7..0] 20 SDQS_B4 M_DQS_BJ[7..0] 22
AR41 M_DQS_A4 AU39 M_DQS_BJ4
SDQS_A4 M_DQS_AJ[7..0] 20 SDQS_B4# M_DQM_B[7..0] 22
AR40 M_DQS_AJ4 AU37 M_DQM_B4
SDQS_A4# M_DQM_A[7..0] 20 SDM_B4 M_DATA_B[63..0] 22
AU43 M_DQM_A4
SDM_A4 M_DATA_A[63..0] 20
AW37 M_DATA_B32
M_DATA_A32 SDQ_B32 M_DATA_B33
SDQ_A32 AV42 SDQ_B33 AV38
AU40 M_DATA_A33 BB2 AN36 M_DATA_B34
SDQ_A33 M_DATA_A34 RESERVED_1 SDQ_B34 M_DATA_B35
SDQ_A34 AP42 AW42 RESERVED_2 SDQ_B35 AN37
AN39 M_DATA_A35 AN32 AU35 M_DATA_B36
SDQ_A35 M_DATA_A36 RESERVED_3 SDQ_B36 M_DATA_B37
SDQ_A36 AV40 AM31 RESERVED_4 SDQ_B37 AR35
AV41 M_DATA_A37 AG32 AN35 M_DATA_B38
SDQ_A37 M_DATA_A38 RESERVED_5 SDQ_B38 M_DATA_B39
SDQ_A38 AR42 AF32 RESERVED_6 SDQ_B39 AR37
AP41 M_DATA_A39 TP_MCH_AP21 AP21
SDQ_A39 TP51 SM_SLEWIN0 M_DQS_B[7..0] 22
TP_MCH_AA39 AA39 AL35 M_DQS_B5
M_DQS_A[7..0] 20 TP52 SM_SLEWIN1 SDQS_B5 M_DQS_BJ[7..0] 22
AL41 M_DQS_A5 AL34 M_DQS_BJ5
SDQS_A5 M_DQS_AJ[7..0] 20 SDQS_B5# M_DQM_B[7..0] 22
AL40 M_DQS_AJ5 AM37 M_DQM_B5
SDQS_A5# M_DQM_A[7..0] 20 SDM_B5 M_DATA_B[63..0] 22
AM43 M_DQM_A5
SDM_A5 M_DATA_A[63..0] 20
AM35 M_DATA_B40
M_DATA_A40 SDQ_B40 M_DATA_B41
SDQ_A40 AN41 SDQ_B41 AM38
AM39 M_DATA_A41 AJ34 M_DATA_B42
SDQ_A41 M_DATA_A42 SDQ_B42 M_DATA_B43
SDQ_A42 AK42 SDQ_B43 AL38
AK41 M_DATA_A43 AR39 M_DATA_B44
SDQ_A43 M_DATA_A44 SDQ_B44 M_DATA_B45
SDQ_A44 AN40 SDQ_B45 AM34
AN42 M_DATA_A45 AL37 M_DATA_B46
SDQ_A45 M_DATA_A46 SDQ_B46 M_DATA_B47
SDQ_A46 AL42 SDQ_B47 AL32
AL39 M_DATA_A47
SDQ_A47 M_DQS_B[7..0] 22
AG35 M_DQS_B6
M_DQS_A[7..0] 20 SDQS_B6 M_DQS_BJ[7..0] 22
AG42 M_DQS_A6 AG36 M_DQS_BJ6
SDQS_A6
SDQS_A6# AG41 M_DQS_AJ6
M_DQS_AJ[7..0] 20
M_DQM_A[7..0] 20
DDR_1 SDQS_B6#
SDM_B6 AG39 M_DQM_B6
M_DQM_B[7..0] 22
M_DATA_B[63..0] 22
AG40 M_DQM_A6
SDM_A6 M_DATA_A[63..0] 20
AG38 M_DATA_B48
M_DATA_A48 SDQ_B48 M_DATA_B49
SDQ_A48 AJ40 SDQ_B49 AJ38
AH43 M_DATA_A49 AF35 M_DATA_B50
SDQ_A49 M_DATA_A50 SDQ_B50 M_DATA_B51
SDQ_A50 AF39 SDQ_B51 AF33
AE40 M_DATA_A51 AJ37 M_DATA_B52
SDQ_A51 M_DATA_A52 SDQ_B52 M_DATA_B53
B SDQ_A52 AJ42 SDQ_B53 AJ35 B
AJ41 M_DATA_A53 TP_MCH_AM21 AM21 AG33 M_DATA_B54
SDQ_A53 TP53 RESERVED_7 SDQ_B54
AF41 M_DATA_A54 AF34 M_DATA_B55
SDQ_A54 M_DATA_A55 DDR_GMCH_VREF SDQ_B55
SDQ_A55 AF42 AM6 SVREF M_DQS_B[7..0] 22
AC36 M_DQS_B7
M_DQS_A[7..0] 20 SDQS_B7 M_DQS_BJ[7..0] 22
AC42 M_DQS_A7 AC37 M_DQS_BJ7
DDR_0 SDQS_A7
SDQS_A7# AC41 M_DQS_AJ7
M_DQS_AJ[7..0] 20
M_DQM_A[7..0] 20
SDQS_B7#
SDM_B7 AD38 M_DQM_B7
M_DQM_B[7..0] 22
M_DATA_B[63..0] 22
AC40 M_DQM_A7
SDM_A7 M_DATA_A[63..0] 20
AD36 M_DATA_B56
TP_MCH_AN21 M_DATA_A56 SRCOMP0 SDQ_B56 M_DATA_B57
TP54 AN21 RESERVED SDQ_A56 AD40 AN2 SRCOMP0 SDQ_B57 AC33
AD43 M_DATA_A57 SRCOMP1 AN3 AA34 M_DATA_B58
SDQ_A57 M_DATA_A58 SRCOMP2 SRCOMP1 SDQ_B58 M_DATA_B59
SDQ_A58 AB41 BB40 SRCOMP2 SDQ_B59 AA36
AA40 M_DATA_A59 SRCOMP3 BA40 AD34 M_DATA_B60
SDQ_A59 M_DATA_A60 SMRCOMPVOL SRCOMP3 SDQ_B60 M_DATA_B61
SDQ_A60 AE42 DDR2 Compensation Group Signals AM8 SMRCOMPVOL SDQ_B61 AF38
AE41 M_DATA_A61 SMRCOMPVOH AM10 AC34 M_DATA_B62
SDQ_A61 M_DATA_A62 SMRCOMPVOH SDQ_B62 M_DATA_B63
SDQ_A62 AC39 BB19 RESERVED SDQ_B63 AA33
AB42 M_DATA_A63 R203 20 SRCOMP0
SDQ_A63 +/-1% 4 OF 7
3 OF 7

1D8V_STR LE82G31 bga1226_1h25


LE82G31 bga1226_1h25
R198 20 SRCOMP1
C270 +/-1% #U27#U28
#U27#U28 * 0.1uF
16V, Y5V, +80%/-20%

1D8V_STR 1D8V_STR 1D8V_STR

R224 20 SRCOMP2
+/-1% 1D8V_STR
C295 C294
* 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% *R196
1K 1D8V_STR
+/-1% *R204
1K
r0402h4 R223 20 SRCOMP3 +/-1%
SMRCOMPVOH +/-1% r0402h4
C268 DDR_GMCH_VREF
A
* R195
3.01K * 10nF
25V, X7R, +/-10%
A

+/-1% *R209
1K
*
C272
0.1uF
r0402h4 +/-1% 16V, Y5V, +80%/-20%
SMRCOMPVOL r0402h4

*R202
1K C264
+/-1%
r0402h4 * 10nF
25V, X7R, +/-10%
5 mils width, 10 mils spacing, max 500 mils length for breakout region
Place CAP./RES. within 1" of GMCH package. width 10 mils, spacing 10 mils
1D8V_STR: 10 mils width/10 mils spacing.
SMRCOMPVOH: 0.8 *VCCSM
5 mils width/spacing minimum for max. of 300 mils
in GMCH break-out area
FOXCONN PCEG
SMRCOMPVOL: 0.2 *VCCSM Placed close to GMCH pin Title
BearLake-GMCH-2
Size Document Number Rev
C G31M05 A

Date: Monday, January 07, 2008 Sheet 17 of 39


5 4 3 2 1
5 4 3 2 1

1D25V_MCH
U1_1 U12F
8D 8 U12_1 U12G
7 7 1D25V_MCH
2 2 VCC_81 AG25
A D
1 1 VCC_172 AG24 BC37 VSS_1 VSS_181 AF5
VCC_173 AG23 BC32 VSS_2 VSS_182 AF3
FOXCONN AJ12 VCC_1 VCC_174 AG22 BC28 VSS_3 VSS_183 AF2
AJ11 VCC_2 VCC_82 AG21 BC24 VSS_4 VSS_184 AF1
B 5C 5 AJ10 VCC_3 VCC_83 AG20 BC10 VSS_5 VSS_185 AD42
6 6 U27 LE82G31
AJ9 VCC_4 VCC_84 AG19 BC5 VSS_6 VSS_186 AD39
3 3 AJ8 VCC_5 VCC_85 AG18 BB7 VSS_7 VSS_187 AD37
4 B4 Heatsink AJ7 VCC_6 VCC_86 AG17 AY41 VSS_8 VSS_188 AD35
AJ6 VCC_7 VCC_87 AG15 AY4 VSS_9 VSS_189 AD33
G31 AJ5 AG14 AW43 AD25
Heatsink VCC_8 VCC_88 VSS_10 VSS_190
AJ4 VCC_9 VCC_89 AF26 AW41 VSS_11 VSS_191 AD23
AJ3 VCC_10 VCC_90 AF25 AW1 VSS_12 VSS_192 AD21
CLIP1N @G31 AJ2 AF24 AV37 AD19
CLIP2S CLIP4S VCC_11 VCC_91 VSS_13 VSS_193
1 AH4 VCC_12 AV35 VSS_14 VSS_194 AC38
1 1 AH2 AF22 AV27 AC35

GND
POWER
VCC_13 VCC_93 VSS_15 VSS_195
2 AH1 VCC_14 VCC_94 AF20 AV23 VSS_16 VSS_196 AC24
2 2 U28 LE82946GZ AG13 AF18 AV21 AC22
Clip_2P VCC_15 VCC_95 VSS_17 VSS_197
AG12 VCC_16 VCC_96 AF17 AV17 VSS_18 VSS_198 AC20
D Clip_2P Clip_2P AG11 AF15 AV11 AC10 D
946GZ VCC_17 VCC_97 VSS_19 VSS_199
This is for ICH7 heatsink hook. For GMCH heatsink hook AG10 VCC_18 VCC_98 AF14 AV9 VSS_20 VSS_200 AC7
AG9 VCC_19 VCC_99 AE27 AV7 VSS_21 VSS_201 AC5
CLIP3N AG8 AE26 AU42 AB43
@946 VCC_20 VCC_100 VSS_22 VSS_202
1 AG7 VCC_21 VCC_101 AE25 AU38 VSS_23 VSS_203 AB25
AG6 VCC_22 VCC_102 AE23 AU32 VSS_24 VSS_204 AB23
2 AG5 VCC_23 VCC_103 AE21 AU24 VSS_25 VSS_205 AB21
AG4 VCC_24 VCC_104 AE19 AU20 VSS_26 VSS_206 AB19
Clip_2P AG3 AE17 AU6 AB2
VCC_25 VCC_105 VSS_27 VSS_207
AG2 VCC_26 VCC_106 AD27 AU2 VSS_28 VSS_208 AB1
AF13 VCC_27 VCC_107 AD26 AT31 VSS_29 VSS_209 AA38
AF12 VCC_28 VCC_108 AD18 AT29 VSS_30 VSS_210 AA35
AF11 VCC_29 VCC_109 AD17 AT15 VSS_31 VSS_211 AA24
AD24 VCC_30 VCC_110 AD15 AT13 VSS_32 VSS_212 AA22
AD22 VCC_31 VCC_111 AD14 AT12 VSS_33 VSS_213 AA20
1D25V_MCH AD20 AC27 AR38 AA8
VCC_32 VCC_112 VSS_34 VSS_214
AC25 VCC_80 VCC_113 AC26 AR33 VSS_35 VSS_215 AA5
AC23 VCC_34 VCC_114 AC17 AR32 VSS_36 VSS_216 Y42
L31 1D25V_MCHPCIE AC21 AC15 AR27 Y37
0 VCC_35 VCC_115 VSS_37 VSS_217
AC19 VCC_36 VCC_116 AC14 AR26 VSS_38 VSS_218 Y35
C258 C250 EC35 1D25V_MCH AC13 AB27 AR23 Y33
VCC_37 VCC_117 VSS_39 VSS_219
1

* 10uF
* 0.1uF
16V, Y5V, +80%/-20%
* 220uF
6.3V, +/-20%
AC6
AB24
VCC_38 VCC_118 AB26
AB18
AR21
AR20
VSS_40 VSS_220 Y25
Y23

10V, Y5V, +80%/-20%


VCC_39 VCC_119 VSS_41 VSS_221

10uF C327
AB22 AB17 AR17 Y21
2

VCC_40 VCC_120 VSS_42 VSS_222

1
*
Dummy
AB20
AA25
VCC_41
VCC_42
VCC_121
VCC_122
AA27
AA26
AR9
AR6
VSS_43
VSS_44
VSS_223
VSS_224
Y19
Y10
AA23 AA17 AP43 Y7

2
VCC_43 VCC_123 VSS_45 VSS_225
AA21 VCC_44 VCC_124 AA15 AP24 VSS_46 VSS_226 Y5
AA19 VCC_45 VCC_125 AA14 AP18 VSS_47 VSS_227 Y1
AA13 VCC_46 VCC_126 Y27 AP1 VSS_48 VSS_228 W3
1D25V_MCH AA3 Y26 AN38 V43
VCC_47 VCC_127 VSS_49 VSS_229
Y24 VCC_48 VCC_128 Y18 AN31 VSS_50 VSS_230 V39
Y22 VCC_49 VCC_129 Y17 AN29 VSS_51 VSS_231 V37
Y20 VCC_50 VCC_130 Y15 AN24 VSS_52 VSS_232 V34
Y13 VCC_51 VCC_131 Y14 AN23 VSS_53 VSS_233 V32
Place in 1D25V_MCH_CL plane Y6 W27 AN20 V11
(less than 100 mils from the package) VCC_52 VCC_132 VSS_54 VSS_234
V13 VCC_53 VCC_133 W26 AN15 VSS_55 VSS_235 V8
V12 VCC_54 VCC_134 W25 AN13 VSS_56 VSS_236 V5
V10 VCC_55 VCC_135 W23 AN12 VSS_57 VSS_237 V2
V9 W21 AN11 U38
*

L22 270nH VCCA_HPLL VCC_56 VCC_136 VSS_58 VSS_238


U13 VCC_57 VCC_137 W19 AN4 VSS_59 VSS_239 U35
+/-20% C170 U10 W18 AM42 U8
VCC_58 VCC_138 VSS_60 VSS_240
1

* 2.2uF
6.3V, Y5V, +80%/-20%
U9
U6
VCC_59
VCC_60
VCC_139
VCC_140
W17
V27
AM40
AM36
VSS_61
VSS_62
VSS_241
VSS_242
U7
U5
U3 V26 AM33 T42
2

VCC_61 VCC_141 VSS_63 VSS_243


N12 VCC_62 VCC_142 V25 AM29 VSS_64 VSS_244 T1
N11 VCC_63 VCC_143 V24 AM24 VSS_65 VSS_245 R36
N9 VCC_64 VCC_144 V23 AM23 VSS_66 VSS_246 R33
1D8V_STR Connect ground sides of caps with traces to GND balls N8 V22 AM20 R31
*

L27 2.2uH VCCA_MPLL (less than 100 mils from the package) VCC_65 VCC_145 VSS_67 VSS_247
N6 VCC_66 VCC_146 V21 AM11 VSS_68 VSS_248 R11
C +/-20% N3 V20 AM9 R8 C
6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%


R133 1 VCC_67 VCC_147 VSS_69 VSS_249
L6 VCC_68 VCC_148 V19 AM7 VSS_70 VSS_250 R5
+/-5% J6 V18 AM4 R3
VCC_69 VCC_149 VSS_71 VSS_251
C301

C300

C297 J3 V17 AM2 P43


VCC_70 VCC_150 VSS_72 VSS_252
1

C157
* * * J2 VCC_71 VCC_151 V15 AM1 VSS_73 VSS_253 P30
1

R130 1
* 10uF G2 VCC_72 VCC_152 V14 AL36 VSS_74 VSS_254 P21
2.2uF

2.2uF

2.2uF

+/-5% 10V, Y5V, +80%/-20% F11 U26 AL33 P18


2

VCC_73 VCC_153 VSS_75 VSS_255


F9 U25 AK43 P17
2

VCC_74 VCC_154 VSS_76 VSS_256


D4 VCC_75 VCC_155 U24 AJ39 VSS_77 VSS_257 P2
1D25V_MCH C13 U23 AJ36 N36
VCC_76 VCC_156 VSS_78 VSS_258
C9 U22 AJ33 N33
6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

VCC_77 VCC_157 VSS_79 VSS_259


C307

C425

C296

1D25V_MCH P20 U21 AH42 N31


VCC_78 VCC_158 VSS_80 VSS_260
1

* * * VCC_159
VCC_160
U20
U19
AG37
AG34
VSS_81
VSS_82
VSS_261
VSS_262
N27
N21
2.2uF

2.2uF

2.2uF

L0805 1uH Y11 U18 AF43 N13


2

L23 1 R137 1 VCCA_EXPPLL GMCH Memory Decoupling VCC_CL_PLL VCC_79 VCC_161 VSS_83 VSS_263
2 Y32 VCC_CL_PLL VCC_162 U17 AF37 VSS_84 VSS_264 N10
+/-10% +/-5% C172 C180 VCCA_EXPPLL B15 U15 AF36 N7
VCCA_EXPPLL VCC_163 VSS_85 VSS_265
1

R138 1 * 10uF
10V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20% * Dummy VCCA_HPLL C23
V31
VCCA_HPLL
RESERVED_002
VCC_164
VCC_165
U14
R20
AF10
AF9
VSS_86
VSS_87
VSS_266
VSS_267
N5
M42
+/-5% VCCA_MPLL A24 R18 AF8 M37
2

VCCA_DPLLA VCCA_MPLL VCC_166 VSS_88 VSS_268


A22 VCCA_DPLLA VCC_167 R17 AF7 VSS_89 VSS_269 M35
3D3V_SYS VCCA_DPLLB C22 R15 AF6 M33
VCCA_DPLLB VCC_168 VSS_90 VSS_270
VCC_169 R14 M27 VSS_91 VSS_271 BC41
1D25V_MCH P15 M21 BC3
VCC_170 VSS_92 VSS_272
B17 VCC3_3 VCC_171 P14 M17 VSS_93 VSS_273 BA1
L0805 10uH FSB_VTT 1D25V_MCH M15 AY40
L20 1 VCCA_DPLLA VSS_94 VSS_274
2 M10 VSS_95 VSS_275 AF23
+/-20% EC29 C186 C182 P29 AL26 M7 AF21
VTT_1 VCC_CL_1 VSS_96 VSS_276
* 220uF
* 0.1uF
* 0.1uF P27 AL24 M1 AF19
10V, Y5V, +80%/-20%

VTT_2 VCC_CL_2 VSS_97 VSS_277


10uF C265

6.3V, +/-20% 16V, Y5V, +80%/-20% C143 16V, Y5V, +80%/-20% P26 AL23 L33 AE24
VTT_3 VCC_CL_3 VSS_98 VSS_278
1

10uF
10V, Y5V, +80%/-20% * * P24
P23
VTT_4
VTT_5
VCC_CL_4
VCC_CL_5
AL21
AL20
L32
L31
VSS_99
VSS_100
VSS_279
VSS_280
AE22
AE20
L19 L0805 10uH Dummy N29 AL18 L29 AE18
2

VCCA_DPLLB VTT_6 VCC_CL_6 VSS_101 VSS_281


1 2 N26 VTT_7 VCC_CL_7 AL17 L21 VSS_102 VSS_282 AC18
EC30 C183 N24 AL15 L20 AA18
VTT_8 VCC_CL_8 VSS_103 VSS_283
+/-20% * 220uF
6.3V, +/-20% * 0.1uF
16V, Y5V, +80%/-20%
N23
M29
VTT_9 VCC_CL_9 AK30
AK29
L11
L7
VSS_104 VSS_284 W24
W22
VTT_10 VCC_CL_10 VSS_105 VSS_285
M24 VTT_11 VCC_CL_11 AK27 L5 VSS_106 VSS_286 W20
Place in the PCI-E power plane M23 AJ31 L3 R21
1D8V_STR (less than 100 mils from the package) VTT_12 VCC_CL_12 VSS_107 VSS_287
L24 VTT_13 VCC_CL_13 AG31 K43 VSS_108 VSS_288 E1
Intel DG: 220uF L23 AF31 K26 C43
VTT_14 VCC_CL_14 VSS_109 VSS_289
K24 VTT_15 VCC_CL_15 AD32 K21 VSS_110 VSS_290 C1
K23 VTT_16 VCC_CL_16 AC32 K18 VSS_111 VSS_291 A41
J24 VTT_17 VCC_CL_17 AA32 K13 VSS_112 VSS_292 A5
1D5V_CORE CP6 J23 AJ30 K12 A3
VTT_18 VCC_CL_18 VSS_113 VSS_293
H24 VTT_19 VCC_CL_19 AJ29 K2 VSS_114
X_COPPER H23 AJ27 J38
FSB_VTT VTT_20 VCC_CL_20 VSS_115
G26 VTT_21 VCC_CL_21 AG30 J35 VSS_116
R148 Need to Check Change to Dummy G24 AG29 J32
*

L21 10 VCCDQ_CRT VTT_22 VCC_CL_22 VSS_117


G23 VTT_23 VCC_CL_23 AG27 J27 VSS_118
B +/-5% r0805h6 F26 AG26 J21 B
VTT_24 VCC_CL_24 VSS_119
2.2uF C159

2.2uF C147

2.2uF C158

1 F24 AF30 J9
6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

VTT_25 VCC_CL_25 VSS_120


1

*R127
Dummy
0
*
C163
1uF
+/-5%
* * * F23
E29
VTT_26
VTT_27
VCC_CL_26
VCC_CL_27
AF29
AF27
J7
J5
VSS_121
VSS_122
+/-5% 10V, Y5V, +80%/-20% E27 AD30 H31
2

Reserved VTT_28 VCC_CL_28 VSS_123


E26 VTT_29 VCC_CL_29 AD29 H29 VSS_124
E23 VTT_30 VCC_CL_30 AC30 H21 VSS_125
Dummy D29 AC29 H20
Dummy VTT_31 VCC_CL_31 VSS_126
D28 VTT_32 VCC_CL_32 AL12 H17 VSS_127
D27 VTT_33 VCC_CL_33 AL11 H15 VSS_128
C30 VTT_34 VCC_CL_34 AL10 H13 VSS_129
Place in FSB_VTT plane as close to the GMCH as possible C29 AL9 G42
L0805 10uH (less than 100 mils from the package) VTT_35 VCC_CL_35 VSS_130
C27 VTT_36 VCC_CL_36 AL8 G38 VSS_131
L29 1 2 VCCD_CRT B30 AL7 G32
+/-20% VTT_37 VCC_CL_37 VSS_132
B29 VTT_38 VCC_CL_38 AL6 G21 VSS_133
C173 C171 B28 AL5 G13
VTT_39 VCC_CL_39 VSS_134
* 4.7uF
6.3V, X5R, +/-10% * 0.1uF
16V, Y5V, +80%/-20%
B27
A30
VTT_40
VTT_41
VCC_CL_40
VCC_CL_41
AL4
AL3
G12
G11
VSS_135
VSS_136
Reserved A28 AL2 G9
VTT_42 VCC_CL_42