G31MV PDF

5 4 3 2 1
Foxconn Precision Co. Inc.

D G31M05 Schematic D
Fab.A
Data: 2008/1/03
Page Index
01. Index Page 25. ICH7 -1
02. Topology 26. ICH7 -2
03. Rest Map 27. ICH7 -3
04. Clock Distribution 28. REAR USB
C
05. Power Delivery Map 29. TPM C
06. Power Sequence 30. PCIE1X

07. BLANK 31. PCI Slot
08. CK505 ClockGen 32. LAN-RTL8101E/RTL8111C
09. Power / MISC Connectors 33. AUDIO 662
10. Voltage Regulator Down 11 34. AUDIO PORT
11. OUTPUT CAP 35. Super I/O ITE8718F/GX
12. 1D25V 1D5V FSB 36. Keyboard / Mouse / Fan
13. STR1D8V 3D3_DUAL 37. Serial / Parallel
14. LGA775 -1 38. FRONT USB
B
15. LGA775 -2 39. changlist B
16. Broadwater -GMCH -1

19. DDR2 Channel A Termination
20. DDR2 Channel A DIMM1, 2
21. DDR2 Channel B Termination
22. DDR2 Channel B DIMM1, 2
23. PCI Express x16 Gfx Slot
A 24. VGA Connector A
FOXCONN PCEG
Title
Index Page
Size Document Number Rev
C G31M05 A
Date: Friday, January 18, 2008 Sheet 1 of 41

5 4 3 2 1
5 4 3 2 1
Cedar Mill, Presler ,

Conroe & Allendale
VRD 11
LGA775 Processor
3 Phase PWM
D Socket T D
800/1066/1333 FSB
CK-505 Clock
PCI Express x 16 Channel A DDR2

PCI Express x16 Port DDR2 667/800
External Graphics
DIMM1
Card
GMCH DDR2 667/800 Channel B DDR2

VGA Connector
Broadwater DIMM1
C C
Back Panel
PCIe port
USB2.0 Port 7 LAN
4 Lanes
USB2.0 Port 8 Reltek
Direct Media Interface (DMI)
USB2.0 Port 9 Controller Link
USB2.0 Port 10
SPI Flash
PCI Slot 1X2
ICH7
B Header B
USB2.0 Port 1
Serial ATA ⒑
LPC I/F
USB2.0 Port 2 SATA Connector 1
AHCI, RAID0,1,5,10
SATA Connector 2
USB2.0 Port 3
USB2.0 Port 4 SPI Flash SATA Connector 3
(BIOS) SATA Connector 4
HDA Codec
TPM Realtek ALC662
TPM(Optional)
LPC I/F
Super I/O
IT8718/GX
A A
Floppy
Serial & Parallel
Drive Connector
FOXCONN PCEG
Title
TOPOLOGY
C G31M05 A

5 4 3 2 1
5 4 3 2 1
CPU
(Cedar Mill/Presler/Conroe/Allendale)
CPU_PWRGD
CPURST#
D
LGA775 processor D
ATX
Power
Vtt_PwrGd CK505
Translation PWRGD_3V
PWRGD_PS PWROK CPURST#
Circuitry PCI Express x16
PS_ON#
GMCH
Broadwater
C
RSTIN# C
ICH7
ICH_PWRGD
CK_PWRGD
SLP_M#
PCIRST#
PLTRST#
Front Panel PWROK ACZ_RST#

RST# Audio
FR_RST SYS_RESET# LAN_RSTSYNC
B B
SW_ON PWRBTN#
RSMRST#
RCIN#
SLP_S3#
RST#
TPM
RST#
RST#
Power on/off KBRST PCI Slot 1
circuit RSMRST#
Super IO
RST# PCIe Slot
SLP_S3# PCIe LAN
PSOUT
PSIN RST#
A IDE Controller A
PSOUT#
RSMRST circuit FOXCONN PCEG

Title
Reset Map
C G31M05 A

5 4 3 2 1
5 4 3 2 1
14.318MHz
CPU
D
CPU 200/266/333 MHz Diff Pair D
MCH 200/266/333 MHz Diff Pair
PCI Express 100 MHz Diff Pair PCI Express x16 Gfx Channel A DDR2
DIMM1
GMCH
DOT 96 MHz Diff Pair Broadwater
Channel B DDR2
DIMM1
PCI Express/DMI 100 MHz Diff Pair
C C
CK-505
PCI Express/DMI 100 MHz Diff Pair
USB/SIO 48 MHz
ICH 33 MHz
REF 14 MHz
SPI Clock SPI
ICH7
Azalia Bit Clock
B
PCI 33 MHz PCI Slot 1 B
TPM 33 MHz TPM
32.768KHz
HD Audio
SIO 33 MHz Super I/O
SATA 100 MHz Diff Pair

PCI Express 100 Mhz Diff Pair
A A
FOXCONN PCEG
Title
Clock Distribution
C G31M05 A

5 4 3 2 1
5 4 3 2 1
3.3V Super I/O

ATX P/S 3.3V
Icc(Max)=50mA
Proceessor
Vccp (CPU Vcore)
5V 5VSB VRD 11 3.3SBV
12V Voltage=1.15~1.5V 5V
Switching Icc(Max)=50mA(S0)
Icc(Max)=125A
Three Phase
5VDUAL 3-Phases Swithing 3.3SBV
D
DDR2 Channel A Icc(Max)= Icc(Max)=38mA(S3)
D
1.2V FSB 5VSB

Vdd (Core)=1.8V 10A Vtt=5.3A
Ivdd(Max)=TBD(per channel)
5VDUAL
USB2.0 10 Ports Icc(Max)=
+5V DUAL=5A(S0, S1)
Vtt (Core)
0.9V Single Phase Switch Broadwater GMCH +5V DUAL=20mA(S3) 4.345A(S0,S1)
5V to 1.8V 22mA(S3)
Ivterm(Max)=200mA FSB_Vtt
(per channel) Ivdd(Max)=TBD Linear 1.8V
LDO to 1.2V
1.2V FSB Vtt PS2
1.8V to 0.9V Icc(Max)=1.3A +5V DUAL=345mA(S0, S1)
6A +5V DUAL=2mA(S3)
Ivterm(Max)=1.2A
DDR2 Channel B
1.8V VCCSM FWH
Vdd (Core)=1.8V 1.8V VCC_SMCLK
Ivdd(Max)=TBD(per channel) 3.3V=107mA(S0, S1)
GMCH 1.25 V Vcore (Core Logic) PCI Express X16

Vtt (Core) 3.3V 21.34A 1.25V
0.9V Switching Icc(Max)=18.8A(Integrated) slot (1)
Ivterm(Max)=200mA 12V
*1.25V (DMI&PCIe) +12V=5.5A
(per channel) VCCA_EXP 2.5A
3.3VSB
C
1.25V C
Icc(Max)=0.375A(wake)
VCC_CL 3.8A
Icc(Max)=0.02A(no wake)
+3.3V=3A
3.3V VCCA_DAC 70mA
3.3V VCC3_3 15.8mA
PCI Express X1
Per slot (1)
+12V=0.5A
HDA Codec
3.3VSB
Vcc LDO Icc(Max)=0.375A(wake)
5V 12V ICH7 Icc(Max)=0.02A(no wake)
Icc(Max)=200mA to 5V
1.25V VCCDMI 40mA
Vcc +3.3V=3A
3.3V Linear 1.25V 1.2V VCC_CPU_IO 14mA
Icc(Max)=40mA to 1.05V
V_1P05V_ICH 1.05V (Core) VCC1_05
2A 1.17A PCI Per Slot (X2)
1.5V (USB &SATA) VCC1_5A -12V
B
1.12A Icc(Max)=0.1A -12V B
Linear 1.8V
to 1.5V 1.5V (PCIe)VCC1_5B
V_1P5V_ICH 0.77A 5V
2.2A 1.5V VCCGLAN1_5 Icc(Max)=5A
5V
74mA
3.3V
RTC
5VSB RTC=5uA Icc(Max)=7.6A
Battery
12V
3.3V VccCL3_3 12mA Icc(Max)=0.5A
5V_STBY to 3.3SB 3.3V VccSUS3_3 141mA
1.5A 3.3V VccLAN (10/100) 12mA 3.3VSB
3.3V VccSUSHDA 4mA Icc(Max)=0.375A(wake)
3.3V VCC3_3 310mA Icc(Max)=0.02A(no wake)
3.3V
3.3V VccGLAN3_3 1mA
3.3V VccHDA 4mA
Nineveh GbE Lan

3.3V STBY
A IO LED 15.5nA A
1.8V ANALOG 418.2mA BJT

CK505
1.0V Internal 1.8
to 1.0 VR core Vdd (Core) FOXCONN PCEG
277.2mA 3.3V Title
Ivdd(Max)=250mA Power Delivery Map
C G31M05 A

5 4 3 2 1
5 4 3 2 1
S0->S5
+12V_SYS +12V_SYS
S5->S0
D D
+5V_DUAL +5V_SYS +5V_SYS +5V_DUAL
+3D3V_DUAL +3D3V_SYS +3D3V_SYS +3D3V_DUAL

+1D8V_STR +1D8V_STR
VTT_DDR
VTT_DDR
VTT_VR VTT_VR
Vcc Vcc
1ms to 10ms
Vcc_PWRGD
Vcc_PWRGD
VRM_OUTEN
VRM_OUTEN
VIDPWRGD VIDPWRGD PS_ONJ
C
PS_ONJ C
S0->S3 S3->S0
+12V_SYS +12V_SYS
+5V_SYS +5V_DUAL +5V_DUAL +5V_SYS
+3D3V_SYS +3D3V_DUAL +3D3V_DUAL +3D3V_SYS

B B
+1D8V_STR +1D8V_STR +1D8V_STR +1D8V_STR
VTT_DDR
VTT_DDR
VTT_VR VTT_VR
Vcc Vcc
1ms to 10ms
Vcc_PWRGD
Vcc_PWRGD
VRM_OUTEN
VRM_OUTEN
VIDPWRGD PS_ONJ VIDPWRGD
PS_ONJ
A A
FOXCONN PCEG
Title
Power Sequence
C G31M05 A

5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A FOXCONN PCEG A
Title
BLANK
A G31M05 A

5 4 3 2 1
5 4 3 2 1
3D3V_CLK
3D3V_SYS
FB10 0 3D3V_CLK 3D3V_CLK_SATA_25M
4.7uFC136
4.7uFC105
+/-5% r0805h6
6.3V, X5R, +/-10%
6.3V, X5R, +/-10%
25V, X7R, +/-10%

3D3V_CLK C107 C111
1
10nFC156
* * * 10nF
* 10nF
25V, X7R, +/-10%

25V, X7R, +/-10%
Dummy
C153 C110 C160 C119
2
1
D
* 10nF
* 10nF
25V, X7R, +/-10% * 10nF
25V, X7R, +/-10% * *
25V, X7R, +/-10%
10nF
25V, X7R, +/-10%
D
Dummy
2
Change to 0Ohm RES or not
3D3V_CLK_REF_A
C101 C155 C140
25V, X7R, +/-10%
25V, X7R, +/-10%

1
3D3V_CLK_48M * 4.7uF
6.3V, X5R, +/-10% * 10nF
* 10nF
2
C151
3D3V_CLK
* 10nF
25V, X7R, +/-10%
TBD
3D3V_CLK
R88
* 4.7K
+/-5%
r0402h4
U8
1 **RLATCH 25Mhz_0F_2x 64
2 GND GND 63
+/-5% 3D3V_CLK 3 62 3D3V_CLK_SATA_25M
R94
*
33 R89 4.7K +/-5% r0402h4 24M_1394 VDD VDD25Mhz_STB 3D3V_CLK_SATA_25M
4 61
**
CK_33M_SIO 3D3V_CLK **GSEL/24.576Mhz VDDSATA_STB SATA_100M_P_ICH

35 CK_33M_SIO 5 VDDPCI SATACLKT_LR 60 CK_SATA_100M_P_ICH 26
27 CK_33M_ICH CK_33M_ICH 6 59 SATA_100M_N_ICH
CK_SATA_100M_N_ICH 26
*
R102 33 R95 4.7K Dummy GND SATACLKC_LR
7 58
*
*
CK_33M_TPM R104
+/-5% 33 +/-5% @TPM +/-5% r0402h4 **DOC1 GND R96 33 +/-5% r0402h4
29 CK_33M_TPM 8 PCICLK0 REF0_2x/FSLC 57 CK_14M_ICH 25
ICS_FSBSEL2
ICS_FSBSEL1
9
10
*Freerun/PCICLK1_2x GND 56
55
? X2
FSLB/PCICLK2_2x X1
9,14,25 ICH_SYS_RSTJ 11 SELRSET/RESET#/PCICLK32 X2 54 1 2
*1 RN13 12 53 3D3V_CLK_REF_A
*
CK_33M_PCI1 2 33 R107 4.7K Dummy PCICLK4 VDDREF_STB C102 C103
C 13 52 C
ICS9LPRS511
31 CK_33M_PCI1 3 4 +/-5% **DOC0 SDATA SMB_DATA_MAIN 20,22,36
CK_48M_ICH 3D3V_CLK_48M 27pFXTAL-14.318MHz 27pF
25 CK_48M_ICH
35 CK_48M_SIO
CK_48M_SIO 5
7
6 8p4r0603h7
8
ICS_FSBSEL0
+/-5% r0402h4 14
15
VDD48
FSLA/USB_48MHz
SCLK
GND
51
50
SMB_CLK_MAIN 20,22,36 * +/-5% *
+/-5%
16 49 200M_P_CPU c0402h6 c0402h6
CK_200M_P_CPU 14
*
R1264.7K +/-5% r0402h4 *SEL24_48#/24_48Mhz CPUT_LR0 200M_N_CPU

17 GND CPUC_LR0 48 CK_200M_N_CPU 14
VRMPWRGD 18 47 3D3V_CLK
96M_P_GMCH Vtt_PwrGd/WOL_STOP# VDDCPU 200M_P_GMCH
16 CK_96M_P_GMCH 19 DOT96T_LR/PCIeT_LR0 CPUT_LR1 46 CK_200M_P_GMCH 16
96M_N_GMCH 20 45 200M_N_GMCH
16 CK_96M_N_GMCH DOT96C_LR/PCIeC_LR0 CPUC_LR1 CK_200M_N_GMCH 16
21 44 3D3V_CLK
GND VDDI/O
32 CK_PE_100M_P_LAN 22 PCIeT_LR1 GNDA 43
32 CK_PE_100M_N_LAN 23 42 3D3V_CLK_REF_A
PCIeC_LR1 VDDA_STB
24 PCIeT_LR2 PCIeT_LR8 41
25 PCIeC_LR2 PCIeC_LR8 40
26 39 PE_100M_P_GMCH
GND PCIeT_LR7 CK_PE_100M_P_GMCH 16
PE_100M_P_16PORT 27 38 PE_100M_N_GMCH
23 CK_PE_100M_P_16PORT PCIeT_LR3 PCIeC_LR7 CK_PE_100M_N_GMCH 16
PE_100M_N_16PORT 28 37
23 CK_PE_100M_N_16PORT PCIeC_LR3 GND
29 PCIeT_LR4 PCIeT_LR6 36
30 PCIeC_LR4 PCIeC_LR6 35
31 34 PE_100M_P_ICH CK_PE_100M_P_ICH 25
3D3V_CLK GND PCIeT_LR5 PE_100M_N_ICH
32 VDDPCIEX PCIeC_LR5 33 CK_PE_100M_N_ICH 25
ICS9LPRS511EGLF-T
3D3V_CLK
*R124
8.2K
+/-5%
r0402h4
B B
VRMPWRGD VRMPWRGD 10,14,25
FSB SELECT
Host Clock
FSBSEL2 FSBSEL1 FSBSEL0 Frequency
1 0 0 333MHz
0 0 0 266MHz
0 1 0 200MHz
* * *
CK_33M_PCI1 ICS_FSBSEL0 R1222.2K +/-5% r0402h4 FSBSEL0

0 0 1 133MHz
CK_48M_SIO
ICS_FSBSEL1 R105 +/-5% FSBSEL1
CK_48M_ICH 2.2K r0402h4
CK_33M_SIO ICS_FSBSEL2 R1032.2K +/-5% r0402h4 FSBSEL2

Reserved
CK_33M_ICH
CK_14M_ICH
50V, NPO, +/-5%
C144 CK_33M_TPM
* 10pF
FSB_VTT
50V, NPO, +/-5%
50V, NPO, +/-5%
Dummy
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%
C154 C152 C118 C137 C114 C138

* 10pF
* 10pF
* 10pF
* 10pF
* 10pF
* 10pF
A Dummy Dummy Dummy Dummy Dummy Dummy A
RN11
*1 2 FSBSEL0
3 4 FSBSEL0 14,16
FSBSEL1
5 6 FSBSEL1 14,16
FSBSEL2
7 8 FSBSEL2 14,16
470
+/-5%
8p4r0603h7 FOXCONN PCEG
Title
CK505 Clock Gen
C G31M05 A
Date: Tuesday, January 08, 2008 Sheet 8 of 39

5 4 3 2 1
5 4 3 2 1
5V_SYS 5V_SYS 5V_SYS 5V_SYS
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%

C314 C317 C447 C80
*
Dummy
0.1uF
*
Dummy
0.1uF
* 0.1uF
* 0.1uF
5V_SB -12V_SYS 3D3V_SYS 3D3V_SYS 12V_SYS 5V_SB
5V_SYS
5V_SYS
*R359
4.7K 13
PWR1
+3.3V3 +3.3V1 1
D +/-5% 14 2 D
r0402h4 -12V +3.3V2
15 GND4 GND1 3
16 4 -12V_SYS 12V_SYS 12V_SYS
35 PS_ONJ PSON +5V1
25V, X7R, +/-10%
25V, X7R, +/-10%
25V, X7R, +/-10%

17 GND5 GND2 5
C446 18 6
GND6 +5V2
1
Del R32, R33, Q3
* 0.1uF
16V, Y5V, +80%/-20%
19
20
GND7 GND3
RSVD PWR0K
7
8 PWRG_ATX
PWRG_ATX 13,35
* C445 * C448 * C449
21 9 0.1uF 0.1uF Dummy
0.1uF
2
+5V3 +5V_AUX C450
22 +5V4 +12V_1 10
23
24
+5V5
GND8
+12V_2
+3.3V4
11
12
* 0.1uF
16V, Y5V, +80%/-20%
HM1512E-EP1 Dummy
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%

3D3V_SYS 3D3V_SYS 3D3V_SYS
C457
*
C456
0.1uF
*
C145
0.1uF * 0.1uF
Dummy Dummy
5V_SYS 3D3V_SB 5V_SYS
5V_SB
R374 1D25V_MCH
*R375 5V_SB 5V_SB
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%

330 10K
C
+-5% +/-5% R370 *R371
4.7K C451 C169
C
FP1
330
+-5%
+/-5%
r0402h4 * 0.1uF
*
C98
0.1uF * 0.1uF
1 2
HDD_LEDJ 3 4 16V, Y5V, +80%/-20%
Dummy
26 HDD_LEDJ
*
5 6 R97
PBTNJ_SIO 35
7 8 33 +/-5%
8,14,25 ICH_SYS_RSTJ
9 X C461 C462 C126
1
Header_2X5_K10 * 220pF
Dummy * 220pF
Dummy * 10nF
C468 C469 25V, X7R, +/-10%
2
* 220pF 220pF
50V, NPO, +/-5% 50V, NPO, +/-5% *
Dummy Dummy TBD 3D3V_SYS
*R368
10K
+/-5%
Q34 r0402h4
C
Reserved
Front Panel Switch/LED
*
MMBT3904-7-F B R369 1K S1_LED 35
+/-1% r0402h4
HD_LED+ 1 2 Power Reserved
E
HD_LED- 3 4 Power LED(Green) Change to 5% or not
B
GND 5 6 Power button B
Reset button 7 8 Power
NC 9 10 Key
SPEAKER HEADER
SPEAKER
1 1
5V_SYS
Confirm must use or not
3 3
4 4
5V_SYS RN39
*1 2
Header_1X4_K2
Reserved
3 4
5 6
7 8
*R348
4.7K 100 Ohm
+/-5% +/-5%
r0402h4 8p4r0603h7
D44
C
A 25 SPKR 1 A
*
3 R358 2.2K B Q30 C442

MMBT3904-7-F
35 SIO_BEEP 2 +/-5% r0402h4
* 0.1uF
16V, Y5V, +80%/-20%
E
BAT54C FOXCONN PCEG

Title
Power/MISC Connectors
Custom G31M05 A
Date: Monday, January 07, 2008 Sheet 9 of 39

5 4 3 2 1
5 4 3 2 1
50V, X7R, +/-10%

R220
Dummy
D C252 R215 D
1K
*
Dummy +/-1% R226 100 Ohm
+/-1% VCCP
*
C236
* RT2
Dummy 16V, NPO, +/-5%
C292 R219 R218
T 10K 22K 2.2nF 1.3K
25V, NPO, +/-5%

R199 C255 VCC_SENSE 14
*
+/-1%
*
* 1nF
+/-1%R179
Dummy
+/-1%
*
470pF 0 0
2
1K C291
+/-1% 50V, NPO, +/-5%
+/-5% C286 * +/-5% * 16V, X7R, +/-10%
Dummy
25V, NPO, +/-5%

C281 C248 3.3nF 0.1uF
25V, NPO, +/-5%
1
* 1nF
*
Dummy
1nF
R197
Dummy
10nF
25V, X7R, +/-10%
R205 1K Dummy FBRTN
200 Ohm +/-1%
+/-1% VIN
5VCC
C273
25V, NPO, +/-5%
* 1nF
R200 2.2+/-5% 12V_VRM
A
LS4148-F C262 C261LS4148-F C260 Q5 C94
1
D33
* * 0.1uF D34
* * 1uF AOD452
* 4.7uF
ISP1
*R208
1.6K 2.2nF
25V, X7R, +/-10% C244
2.2nF
+/-10%
C277
25V, Y5V, +80%/-20% R181 6.2k Ohm
+/-1%
2
+/-1% 50V, X7R, +/-10% 50V, X7R, +/-10% Boot1 R211 2.2+/-5% 1 20.22uF 25V, R51
X7R, +/-10% G C246
*
Dummy
Dummy UG1 * R58 * 0.1uF
25V, X7R, +/-10%
S
C280 10K L16 Choke 400nH
22nF Phase1 +/-5% 2 1
0
*
FBRTN 50V, X7R, +/-10%
D
Phase1
1
+/-5%
* Boot1
* C78
Boot2
UG1
LG1
LG1 Q8 Q7 1nF
50V, X7R, +/-10%
2
G G
AOD472 AOD472 R49
41
26
30
29
28
27
22
3
U10 2.2
S
+/-5%
GND2
SS/EN
VCC12
BOOT1
UGATE1
PHASE1
LGATE1
BOOT2
COMP
FB
ADJ
C 23 UG2 C
UGATE2
35 PVID7 33 VID 7
34 24 Phase2
35 PVID6 VID 6 PHASE2
35 PVID5 35 VID 5
25 LG2
LGATE2
35 PVID4 36 VID 4
37 21 VIN
35 PVID3 VID 3 PWM3
38 20
35 PVID2
39
VID 2
GND PWM 4
35 PVID1 VID 1
GND1 10
40 Q9 C106
D
35 PVID0 VID 0
1
+/-5%ISP1
ISP1 18 R185 0 AOD452
* 4.7uF
RT8841 *
VID_SELECT:VR10.1 connect GND; VR11 connect VTT 1 25V, Y5V, +80%/-20% R182 6.2k Ohm
+/-1% ISP2
14,25 VID_SELECT VIDSEL
17 R186 * 620 VCCP C266
2
ISN1
2
+/-5% Boot2 R190 2.2+/-5% 1 20.22uF 25V, R114
X7R, +/-10% G C247
*
VRM_EN
11 VRM_EN 32 EN/VTT
15 R188 0 +/-5%ISP2
*C234
Dummy
0.1uF UG2 * R123 * 0.1uF
25V, X7R, +/-10%
S
ISP2
*
16V, X7R, +/-10% 10K L25 Choke 400nH
*
16 R187 620 C241VCCP Phase2 +/-5% 2 1 VCCP

ISN2 0
*
31 +/-5%
* 0.1uF
D
8,14,25 VRMPWRGD PWRGD
1
+/-5%
16V, X7R, +/-10%
Dummy * C192
FBRTN
VCC5
LG2 Q12 Q15 1nF

IMAX
ISN4
ISN3
ISP4
ISP3
OFS
2 50V, X7R, +/-10%

RT
2
G G
AOD472 AOD472 R161
19
12
11
13
14
RT8841PQW 2.2
S
+/-5%
*R189
25V, NPO, +/-5%
R192 39K
*
120K +/-5%
+/-1% 5VCC
B B
C254 C251
* 1uF
* 1nF *R183
9.1K Changelist------10/12 by power
+/-10% R193
Dummy +/-1%
* 0 change R381 1.2Kohm to 1.6Kohm
+/-5% chagne R411 402Kohm to 120Kohm
change R245 30Kohm to 43Kohm
FBRTN
5VCC change R246 3.3Kohm to 6.2Kohm
VSS_SENSE 14
Changelist------11/05by power
25V, X7R, +/-10% change R181 43K to 39K
C285 chagne R176 6.2K to 9.1K
1
* 10nF
* R214
Dummy +/-1%
2
100 Ohm
A A
FOXCONN PCEG
Title
Voltage Regulator Down 11
C G31M05 A
Date: Thursday, January 10, 2008 Sheet 10 of 39

5 4 3 2 1
5 4 3 2 1
VCCP
D D
12V_VRM
DEL EC19, EC17,EC42
2
PWR2
Header_2X2 Input LC circuit
EC32 EC31 EC17 EC18 EC28
* 680uF * 680uF * 680uF * 680uF * 680uF
1
4V,+/-20% 4V,+/-20% 4V,+/-20% 4V,+/-20%

VIN 4V,+/-20%
L11
1.2uH@100KHz
*
C318 EC26 EC21 EC8 EC9

1
* 0.1uF
16V, Y5V, +80%/-20%
* 1000uF
+/-20%
* 1000uF
+/-20%
* 1000uF
+/-20%
* 1000uF
+/-20% EC34 EC15 EC16
Dummy * 680uF * 680uF * 680uF
2
4V,+/-20% 4V,+/-20% 4V,+/-20%

Dummy
C C
TC2 TC1
VTT_OUT_RIGHT
* 100uF
2V,+30/-20%
* 100uF
2V,+30/-20%
Dummy Dummy
R245
680
VTT_OUT_RIGHT 5V_SB
* +/-5%
VTT_PWRGD 14
*R262
20K C190 C195 C204 C208 C175 C176
R247
4.7K
+/-1%
Q18 * 6.3V, X5R, +/-10%*
10uF
Dummy 6.3V, X5R, +/-10%*
10uF
Dummy 6.3V, X5R, +/-10%*
10uF
Dummy 6.3V, X5R, +/-10%*
10uF
Dummy
10uF
* 10uF
6.3V, X5R, +/-10%
+/-5% 2N7002 6.3V, X5R, +/-10%
1
BOM need update
CP9
C
100K X_COPPER
*
R248 Dummy B Q20

MMBT3904-7-F 2
+/-5% 12V_VRM VTT_OUT_RIGHT
E
B
C311 *R258
10K
Dummy
R243
680
Dummy C203 C197 C196 C191 C205 C177 B
1 2 +/-5% +/-5%
* 10uF
* 10uF
* 10uF
* 10uF
* 10uF
* 10uF
*
6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10%
VRM_EN Dummy Dummy
2.2uF VRM_EN 10
Dummy C312
Q19
*
0.1uF R246
2N7002 Dummy Dummy
4.7K *
+/-5%
* C210
10uF
*
C189
10uF
*
C209
10uF
*
C217
10uF
*
C216
10uF
*
C215
10uF
6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10%
Dummy Dummy Dummy Dummy
A A
FOXCONN PCEG
Title
OUTPUT CAP
Custom G31M05 A

5 4 3 2 1
5 4 3 2 1
Intel design guide (333):

3.3V SUPPLY must ramp up before VCC (GMCH Core power
VCC (GMCH Core power ) must rampdown before the 3.3V supply 12V_SYS
C213
D32
A C 125V_PHASE * L28
*
*
12V_SYS R166 10 LS4148-F 1uH@1KHz
+/-5% 1uF
16V, X7R, +/-10%
close to Q61 Drain

5V_SB C202 1uF 16V, X7R, +/-10%
*
R169 C219 EC33 C222
1
*R170 Open 14.3K
* 0.1uF * 330uF
* 4.7uF
D
5
D D
4.7K
Dummy +/-1% U9 25V, X7R, +/-10% +/-20% 25V, Y5V, +80%/-20%
3D3V_SYS +/-5% L 1 Q16
VCC
2
L r0402h4 Rocset BOOT
Open 7 2 R175 0 +/-5% G
H COMP/OCSET UGATE AOD452 1D25V_MCH
C
Open L26 Need to change to RUBYCON 16MBZ470MEFC8X11.5
*
S
R174 L B DummyQ13 6 8 125V_PHASE 1D25V_MCH
2KOhm MMBT3904-7-F FB PHASE
Dummy
GND
* +/-1% L 4
E
LGATE R194 2.5uH@100KHz
D
*R172 APW7120KE-TRL 2.2
1
R173
Q14
B Dummy
MMBT3904-7-F
200
+/-1%
Q17 +/-5%
*
C321
*
EC37
1000uF *
EC36
1000uF * C279
10uF
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%

0.1uF
10V, Y5V, +80%/-20%
2.2uF C253
2.2uF C214
2.2uF C232
1uF C287
1uF C226
1uF C225
1.3KOhm
Dummy r0402h4 R176 0 +/-5% G C269 +/-20% +/-20%
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%
2
E
1
+/-1% AOD472
* 2.2nF
50V, X7R, +/-10% * * * * * *
S
Near MOSFET
2
VOUT= 0.8V(1+R638 / R658)
R638,R658 must less than 1k
Pull FB trace out after Cout
*
R167 115 Ohm +/-1% r0402h4
R168 C201
*
220 18nF
+/-1% 50V, Y5V, +80%/-20%
Dummy Dummy
1D25V FOR CHIP
C C
12V_SYS
3D3V_SB 12V_SYS
1D8V_STR
50 mils
1
* R343
* C431 U14D
4
1.8KOhm 0.1uF
+/-1% 12
2
+
25V, X7R, +/-10% 14
D
U14A 1D5V_CORE 13 -
4
Q24
@1.5V 1D5V_REF 3 LM324DR2G
11
+
2
1 G
AP15N03H 1A
-
50 mils
S
LM324DR2G R354
11
R347 C441 1K
Dummy
* *
1.5KOhm 0.1uF +/-5%
+/-1% 16V, Y5V, +80%/-20%
Can change to 0402 or not EC41 C337
R355
* 1000uF
+/-20% * 0.1uF
16V, Y5V, +80%/-20%
1K
+/-1%
B Check to dummy or not B
1D5V_SYS
3D3V_SB
1D5V_CORE
FSB_VTT 3D3V_SB R324 12V_SYS 50 mils

3D3V_SB 1D8V_STR 2.2K
+/-1%
50 mils
D
12V_SYS
*R317 *R352 FSB_VTT 1D5V_CORE U14B 1D05V_SYS
4
1K VTT_SEL 2.1K Q22
+/-5%
DummyVTT_SEL
*R318 *R322
8.2K
+/-1% @1.05V 1.8V 5 +
7 G 1A
D
14 VTT_SEL r0402h4 1K +/-1% AP15N03H

U14C 6
C
-
4
+/-5% Q11 D40 50 mils
S
1D5V_CORE Reserved 1.8V Dummy LM324DR2G R323
@1.2V 10
11
*
+
r0402h4
9
8 G
AP15N03H LS4148-F *R342 * C422
0.1uF
1K
Dummy
+/-5%
C
-
*R319 1K
+/-1% 16V, Y5V, +80%/-20%
S
470 Q27 LM324DR2G R321 Can change to 0402 or not EC42 C404
B
11
+/-5% MMBT3904-7-F R346 C430 1K

Dummy * 1000uF
* 0.1uF
1.2K
* 1uF +/-5%
6.3A 50 mils R325 +/-20% 16V, Y5V, +80%/-20%
C
+/-1% 10V, Y5V, +80%/-20% 1K

Q26 Can change to 0402 or not EC23 C142 C148 +/-1%
B
C401
MMBT3904-7-F
* 1000uF
+/-20% * 10uF
* 0.1uF
16V, Y5V, +80%/-20%
Dummy
Need to Check Change to Dummy
E
A
* 1uF
10V, Y5V, +80%/-20%
R320
1K Dummy A
+/-1% 6.3V, Y5V, +80%/-20%
1D05V_SYS
FSB_VTT FSB_VTT
C115 C116 FOXCONN PCEG

* 0.1uF
16V, Y5V, +80%/-20%
Dummy * 0.1uF
Title
16V, Y5V, +80%/-20%

1D25V 1D5V FSB
Dummy
FSB_VTT Size
C
Document Number
G31M05
Rev
A

5 4 3 2 1
5 4 3 2 1
DDR_VTT
D D
VCC_DUAL
D41 D42
12V_SYS 1 1
3 3 C396 18V_PHASE * L37
1.8V Voltage
*
5V_SB 2 2 1uF
16V, X7R, +/-10% 1uH@1KHz
*
R305 10 1.8V Power requires 1D8V_STR 3D3V_SYS
BAT54C +/-5% BAT54C
17A maximum current
close to Q61 Drain
5V_SB C371 EC48
*
R314
1uF
16V, X7R, +/-10% EC52
* 1000uF
+/-20% U15
1
*R313 Open 14.3K
* C459 * 470uF
* C470 1 8 VTT_DDR
D
VIN VCNTL
5
4.7K +/-1% U13 0.1uF 6.3V, +/-20% 10uF 7
+/-5% L Q36 c0805h14 VCNTL
1 Dummy
*R341 6
VCC
2
L r0402h4 Rocset BOOT 25V, X7R, +/-10% 10V, Y5V, +80%/-20% 100KOhm VCNTL
VCNTL 5
Open 7 2 R377 0 +/-5% G +/-1%
H COMP/OCSET UGATE AOD452 1D8V_STR r0402h4 4
C
L36 VOUT
16V, Y5V, +80%/-20%

Open
*
S
L B Q25 6 8 18V_PHASE 3 2
MMBT3904-7-F FB PHASE REFEN GND
GND
L RT9173 C440 EC44 C428
LGATE 4
E
R372 2.5uH@100KHz
1
* R326 C417
* 0.1uF * 1000uF
* 4.7uF
C
D
First H Need to Apply
*R308 APW7120KE-TRL 2.2 100KOhm
* 0.1uF +/-20% Dummy
*
3
R291 1K B Q23 91 Ohm Q29 +/-5% C452 EC45 EC46 +/-1% 16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%

25 SLP_S4J
2
S5
+/-5%
L
r0402h4 MMBT3904-7-F +/-1%
R328 0 +/-5% G C464 * 0.1uF * 1000uF
+/-20%
* 1000uF r0402h4
E
1
S0 H Don't in CIS
AOD472
* 2.2nF
50V, X7R, +/-10%
+/-20%
S
Near MOSFET Need to Check Change to Dummy
2
S3 H
VOUT= 0.8V(1+R638 / R658)

R638,R658 must less than 1k
Pull FB trace out after Cout
*
R307 115 Ohm
C +/-1% C
*
R303 220 +/-1% C364 18nF

*
Dummy Dummy 50V, Y5V, +80%/-20%
R304 R292
442 Ohm 1.02KOhm
+/-1% +/-1%
Reserved r0402h4
25 1D8V_GPIO13
25 1D8V_GPIO14
1D8V_STR
5V_SB
3D3V_SB
B B
U16 AZ1085D-ADJTRE1
3 Max. output current = 3A
VIN VOUT 2
ADJ
*R361
301
12V_SYS 5V_SB
1
+/-1%
5V_SB
3D3VADJ * R356
EC47 C443 EC50 1K
* 1000uF
+/-20% * 1uF
10V, Y5V, +80%/-20%
* 1000uF 915 series failure issue L
+/-5%
Dummy
*R366
499
+/-20%
H PWOK+ r0402h4
* R360
S
+/-1%
PWOK+ G APM2301AAC-TRL 1K
5V_SYS +/-5%
Q32
Q33 2N7002 PWOKJ r0402h4
EC51
D
G
* 1000uF
+/-20%
Q35 Q31
AP15N03H 2N7002 PWRG_ATX
PWRG_ATX 9,35
Vout=Vref(1+R2/R1)+IadjR2 D VCC_DUAL
R1 is Up Resistor.
Iadj=50uA
Vref=1.25V
A A
3D3V_DUAL 5V_DUAL
FOXCONN PCEG
Title
STR 1D8V 3D3V_DUAL 5V_DUAL
C G31M05 A

5 4 3 2 1
5 4 3 2 1
HAJ[35..3]
16 HAJ[35..3]
HDJ[63..0]
HDJ[63..0] 16 U11A
HAJ3 L5 D2 3 OF 7
HAJ4 A03# ADS# HADSJ 16 U11C
P6 A04# BNR# C2 HBNRJ 16
2 OF 7 HAJ5 M5 D4 P2 F26 TESTHI_0
U11B A05# HIT# HITJ 16 26 SMIJ SMI# TESTHI00
HAJ6 L4 H4 TP_RSPJ K3 W3 TESTHI_1
A06# RSP# TP1 26 A20MJ A20M# TESTHI01
HAJ7 M4 G8 R3 P1 TESTHI_11
A07# BPRI# HBPRIJ 16 26 FERRJ FERR#/PBE# TESTHI11
HDJ0 B4 G16 HDJ32 HAJ8 R4 B2 K1 W2 TESTHI_12
D00# D32# A08# DBSY# HDBSYJ 16 26 INTR LINT0 TESTHI12
HDJ1 C5 E15 HDJ33 HAJ9 T5 C1 L1 F25
D01# D33# A09# DRDY# HDRDYJ 16 26 NMI LINT1 TESTHI02
HDJ2 A4 E16 HDJ34 HAJ10 U6 E4 N2 G25
D02# D34# A10# HITM# HITMJ 16 26 IGNNEJ IGNNE# TESTHI03
HDJ3 C6 G18 HDJ35 HAJ11 T4 AB2 HIERRJ M3 G27
D03# D35# A11# IERR# 26 STPCLKJ STPCLK# TESTHI04
HDJ4 A5 G17 HDJ36 HAJ12 U5 P3 G26
HDJ5 D04# D36# HDJ37 HAJ13 A12# INIT# INITJ 26 TESTHI05
D
B6 D05# D37# F17 U4 A13# LOCK# C3 HLOCKJ 16 15 HVCCA A23 VCCA TESTHI06 G24 D
HDJ6 B7 F18 HDJ38 HAJ14 V5 E3 B23 F24 TESTHI_2_7
D06# D38# A14# TRDY# HTRDYJ 16 15 HVSSA VSSA TESTHI07
HDJ7 A7 E18 HDJ39 HAJ15 V4 AD3 TP_BINITJ VCC_PLL D23 AK6 FORCEPHJ
D07# D39# A15# BINIT# TP2 RSVD5 FORCEPH
HDJ8 A10 E19 HDJ40 HAJ16 W5 G7 C23 G6
D08# D40# A16# DEFER# HDEFERJ 16 15 HVCCIOPLL VCCIOPLL RSVD11
HDJ9 A11 F20 HDJ41 N4 F2 HGTLREF_1
HDJ10 D09# D41# HDJ42 RSVD1 EDRDY# TP_MCERRJ TESTHI_13
B10 D10# D42# E21 16 HREQJ[4..0] P5 RSVD2 MCERR# AB3 TP3 TESTHI13 L2 TESTHI_13 26
HDJ11 C11 F21 HDJ43 HREQJ0 K4 VID0 AM2 AH2
D11# D43# REQ0# 35 VID0 VID0 RSVD12
HDJ12 D8 G21 HDJ44 HREQJ1 J5 U2 TP_APJ0 VID1 AL5 N1
D12# D44# REQ1# AP0# TP4 35 VID1 VID1 PWRGOOD CPU_PWRG 25
HDJ13 B12 E22 HDJ45 HREQJ2 M6 U3 TP_APJ1 VID2 AM3 AL2 PROCHOTJ
D13# D45# REQ2# AP1# TP5 35 VID2 VID2 PROCHOT#
HDJ14 C12 D22 HDJ46 HREQJ3 K6 VID3 AL6 M2
D14# D46# REQ3# 35 VID3 VID3 THERMTRIP# THERMTRIPJ 26
HDJ15 D11 G22 HDJ47 HREQJ4 J6 F3 HBR0J VID4 AK4
D15# D47# HAJ[35..3] REQ4# BR0# HBR0J 16 35 VID4 VID4
HDBIJ0 A8 D19 HDBIJ2 R6 G3 TESTHI_8 VID5 AL4
16 HDBIJ0 DBI0# DBI2# HDBIJ2 16 16 HAJ[35..3] 16 HADSTBJ0 ADSTB0# TESTHI08 35 VID5 VID5
C8 G20 G5 G4 TESTHI_9 VID6 AM5 A13 HCOMP0
16 HDSTBNJ0 DSTBN0# DSTBN2# HDSTBNJ2 16 35 PECI PCREQ# TESTHI09 35 VID6 FC11 COMP0
B9 G19 H5 TESTHI_10 VID7 AM7 T1 HCOMP1
16 HDSTBPJ0 DSTBP0# DSTBP2# HDSTBPJ2 16 TESTHI10 35 VID7 FC12 COMP1
HAJ17 AB6 VID_SELECT AN7 G2 HCOMP2
A17# 10,25 VID_SELECT FC16 COMP2
HDJ16 G9 D20 HDJ48 HAJ18 W6 J16 TP_DPJ0 F28 R1 HCOMP3
D16# D48# A18# DP0# TP6 8 CK_200M_P_CPU BCLK0 COMP3
HDJ17 F8 D17 HDJ49 HAJ19 Y6 H15 TP_DPJ1 G28 J2 HCOMP4
D17# D49# A19# DP1# TP8 8 CK_200M_N_CPU BCLK1 COMP4
HDJ18 F9 A14 HDJ50 HAJ20 Y4 H16 TP_DPJ2 T2 HCOMP5
D18# D50# 4 mils width, 10 mils spacing A20# DP2# TP9 COMP5
HDJ19 E9 C15 HDJ51 HAJ21 AA4 J17 TP_DPJ3 AE8
D19# D51# A21# DP3# TP10 TP11 SKTOCC#
HDJ20 D7 C14 HDJ52 HAJ22 AD6 N5
HDJ21 D20# D52# HDJ53 HAJ23 A22# HGTLREF_1 RSVD13
E10 D21# D53# B15 AA5 A23# GTLREF1 H2 RSVD14 AE6
HDJ22 D10 C18 HDJ54 HAJ24 AB5 H1 HGTLREF_0 AL1 C9 H_TEST
D22# D54# A24# GTLREF0 35 THERMDA THERMDA RSVD15
HDJ23 F11 B16 HDJ55 HAJ25 AC5 E24 MCH_GTLREF_CPU AK1 G10 HGTLREF_0
D23# D55# A25# CS_GTLREF MCH_GTLREF_CPU 16 35 THERMDC THERMDC RSVD16
HDJ24 F12 A17 HDJ56 HAJ26 AB4 D16
HDJ25 D24# D56# HDJ57 HAJ27 A26# RSVD17
D13 D25# D57# B18 AF5 A27# AN3 VCCSENSE RSVD18 A20
HDJ26 E13 C21 HDJ58 HAJ28 AF4 G23 AN4 E23
HDJ27 D26# D58# HDJ59 HAJ29 A28# RESET# HCPURSTJ 16 VSSSENSE RSVD19
G13 D27# D59# B21 AG6 A29# 10 VCC_SENSE AN5 VCC_MB_REG RSVD21 F23
HDJ28 F14 B19 HDJ60 HAJ30 AG4 B3 AN6 J3
D28# D60# A30# RS0# HRSJ0 16 10 VSS_SENSE VSS_MB_REG RSVD24
HDJ29 G14 A19 HDJ61 HAJ31 AG5 F5
HDJ30 D29# D61# HDJ62 HAJ32 A31# RS1# HRSJ1 16 Changed pin name MS_ID1
F15 D30# D62# A22 AH4 A32# RS2# A3 HRSJ2 16 MSID1 V1
HDJ31 G15 D31# D63# B22 HDJ63 HAJ33 AH5 A33# F29 from RSV
RSVD9 MSID0 W1 MS_ID0
HDBIJ1 G11 C20 HDBIJ3 HAJ34 AJ5
16 HDBIJ1 DBI1# DBI3# HDBIJ3 16 A34#
G12 A16 HAJ35 AJ6
16 HDSTBNJ1 DSTBN1# DSTBN3# HDSTBNJ3 16 A35# THERMDA/THERMDC
E12 C17 AC4 Y1 CPU_BOOT
16 HDSTBPJ1 DSTBP1# DSTBP3# HDSTBPJ3 16 RSVD3 1. width=10 mils, spacing=10 mils. BOOTSELECT TP12
AE4 V2 TP_CPU_V2
RSVD4 2. route the lines in parallel LL_ID0 TP13
AD5 AA2 TP_CPU_AA2
16 HADSTBJ1 ADSTB1# LL_ID1 TP14
Socket-IntelPrescottCPU
C 1 OF 7 C
* *
R239 62 HTCK
VTT_OUT_RIGHT +/-5% r0402h4
1D5V_CORE
R242 62 HTRSTJ
*
R241 62 HTDO +/-5% r0402h4
VTT_OUT_LEFT MSID0: NC = 2005 Mainstream / Value, 2006 65W FMB +/-5% r0402h4 Dummy
Vss = 2005 Performance FMB
MSID1: Vss = 2005 Performance,2005 Mainstream/Value,2006 65W FMB In Design Guide is NC
Place at CPU end of route
*
R227 62 +/-5% r0402h4 HBR0J U11D 4 OF 7 FSB_VTT

* *
MS_ID0 R252 51 Ohm +/-5% r0402h4 VCC_PLL HTCK AE1 A29

Place at CPU end of route VTT_OUT_RIGHT HTDI TCK VTT1
AD1 TDI VTT2 B25
C112 C120 HTDO AF1 B29
TDO VTT3
1
MS_ID1 R235 51 Ohm +/-5% r0402h4 10uF
* * 10nF
25V, X7R, +/-10%
HTMS
HTRSTJ
AC1
AG1
TMS
TRST#
VTT4
VTT5
B30
C29
RN22 TESTHI_9 R263 130 +/-1% r0402h4 FORCEPHJ 10V, Y5V, +80%/-20% Reserved A26
2
51 7 8 TESTHI_8 VTT6
5 6 VTT7 B27
+/-5% TESTHI_10 R256 130 +/-1% r0402h4 PROCHOTJ HBPM0J AJ2 C28
8p4r0603h7 3 4 H_TEST HBPM1J BPM0# VTT8
* 1 2 AJ1 BPM1# VTT9 A25
VTT_OUT_RIGHT placed near pin D23, within 500 mils HBPM2J AD2 A28
HBPM3J BPM2# VTT10
AG2 BPM3# VTT11 A27
RN24 VID2 VTT_OUT_RIGHT HBPM4J AF2 C30
7 8 680 VID4 HBPM5J BPM4# VTT12
5 6 AG3 BPM5# VTT13 A30
RN17 TESTHI_12 +/-5% VID5 C25
* **
51 7 8 TESTHI_11 *3 4 8p4r0603h7 VID0 R238 62 +/-5% r0402h4 HIERRJ ICH_SYS_RSTJ AC2

VTT14
C26
8,9,25 ICH_SYS_RSTJ
+/-5% 5 6 TESTHI_1 1 2 DBR# VTT15
C27 VRMPWRGD 8,10,25
8p4r0603h7 3 4 TESTHI_13 R236 62 +/-5% r0402h4 HCPURSTJ VTT16
*
1 2 RN23 VID3 Place at CPU end of route
AK3
AJ3
ITPCLKOUT0 VTT17 B26
D27 *R244
0
*
7 8 680 VID6 PROCHOTJ R257 0 +/-5% ITPCLKOUT1 VTT18 +/-5%
D28
*
R231 49.9 +/-1% r0402h4 HCOMP4 5 6 +/-5% VID7 R264 1K +/-1% r0402h4VID_SELECT r0402h4 Dummy ICH_THRM_UP 25,35 FSBSEL0 VTT19 Dummy
B 3 4 8,16 FSBSEL0 G29 BSEL0 VTT20 D25 B
Reserved 10 mils width * 8p4r0603h7 VID1 FSBSEL1 H30 D26 r0402h4
7 mils spacing to low speed signals 1 2 8,16 FSBSEL1 FSBSEL2 BSEL1 VTT21
Stuff to enable Thermal event 8,16 FSBSEL2 G30 BSEL2 VTT22 B28
14mils spacing to high speed signals D29 VTT_PWRGD 11
max. 1200mils VTT23
VTT24 D30
FSB_VTT VTT_OUT_RIGHT AM6 VTT_OUT_RIGHT VTT_OUT_LEFT
**
R230 49.9 +/-1% r0402h4 HCOMP2 VTTPWRGD

AA1 VTT_OUT_RIGHT
* *
R162 49.9 +/-1% r0402h4 HCOMP0 R92 51 Ohm +/-5% r0402h4 TESTHI_0 VTT_OUT1 VTT_OUT_LEFT
VTT_OUT2 J1
VTT_SEL F27
VTT_OUT_LEFT VTT_SEL 12
10 mils width R91 51 Ohm +/-5% r0402h4 TESTHI_2_7 Socket-IntelPrescottCPU
7 mils spacing to low speed signals RN18 HBPM2J
14mils spacing to high speed signals 7 8 51 HBPM3J
max. 1200mils 5 6 +/-5% HTDI R229
* 3 4 8p4r0603h7 HTMS 51 Ohm
1 2 * +/-5%
***
R232 49.9 +/-1% r0402h4 HCOMP3 r0402h4 VTT_OUT_RIGHT VTT_OUT_LEFT

R233 49.9 +/-1% r0402h4 HCOMP1 RN19 HBPM1J
R234 49.9 +/-1% r0402h4 HCOMP5 7 8 51 HBPM0J TP_CPU_G1 C306 C305
VTT_OUT_LEFT 5 6 TP_CPU_G1 15
HBPM5J
Dummy
* 3
1
4
2
+/-5%
8p4r0603h7 HBPM4J * 0.1uF
* 0.1uF
16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%

Place BPM termination near CPU reserve for Kentsfield CPU support Dummy Dummy
VTT_OUT_RIGHT VTT_OUT_RIGHT
GTLREF voltage should be 0.63*VTT

12 mils width, 15 mils spacing
*R261
115 Ohm *R260
115 Ohm divider should be within 1.5" of the GTLREF pin
0.22nF caps should be placed near CPU pin
+/-1% +/-1%
A place series resistor as close to divider A
*
*
R253 10 HGTLREF_0 R250 10 HGTLREF_1
+/-1% +/-1%
C303
C313
* *R254
200
*
C304
220pF
C319
1uF * *R259
200 * 220pF
50V, NPO, +/-5%
1uF +/-1% 50V, NPO, +/-5% 10V, Y5V, +80%/-20% +/-1%
10V, Y5V, +80%/-20%
FOXCONN PCEG
Title
LGA775-1
C G31M05 A

5 4 3 2 1
5 4 3 2 1
VCCP VCCP VCCP

U11G 7 OF 7
U11E 5 OF 7 U11F 6 OF 7 FSB_VTT
AG22 VCCP1 VCCP93 AK12 AF9 VCCP185 VSS41 AL23 H22 VSS126 VSS211 D5
K29 VCCP2 VCCP94 AH22 AF22 VCCP186 VSS42 A12 H21 VSS127 VSS212 A9
AM26 VCCP3 VCCP95 T29 AH11 VCCP187 VSS43 L25 H20 VSS128 VSS213 D3 PLL Supply Filter
AL8 VCCP4 VCCP96 AM14 AJ14 VCCP188 VSS44 J7 H19 VSS129 VSS214 B1
AE12 AM25 AH19 AE28 H18 B5 R113
VCCP5 VCCP97 VCCP189 VSS45 VSS130 VSS215 0
AE11 VCCP6 VCCP98 AE9 AH29 VCCP190 VSS46 AE29 AB7 VSS131 VSS216 B8
W23 Y29 AH27 K5 H17 AJ4 +/-5%
VCCP7 VCCP99 VCCP191 VSS47 VSS132 VSS217
W24 VCCP8 VCCP100 AK25 AG28 VCCP192 VSS48 J4 AJ24 VSS133 VSS218 AE26
D W25 VCCP9 VCCP101 AK19 AL26 VCCP193 VSS49 AE30 AM17 VSS134 VSS219 AH1 D
T25 AG15 AM12 AN20 AC3 E29 TP_CPU_E29
VCCP10 VCCP102 VCCP194 VSS50 VSS135 VSS220 TP15
Y28 VCCP11 VCCP103 J22 J24 VCCP195 VSS51 AF10 H14 VSS136 VSS221 V7
AL18 VCCP12 VCCP104 T24 J13 VCCP196 VSS52 AE24 P28 VSS137 VSS222 C13
AC25 VCCP13 VCCP105 AG21 T28 VCCP197 VSS53 AM24 V6 VSS138 VSS223 AK24
W30 AM21 W28 AN23 AK2 AB30 HVCCIOPLL
VCCP14 VCCP106 VCCP198 VSS54 VSS139 VSS224 14 HVCCIOPLL
Y30 VCCP15 VCCP107 J25 J12 VCCP199 VSS55 H9 P27 VSS140 VSS225 L6
AN14 VCCP16 VCCP108 U30 J27 VCCP200 VSS56 H8 P26 VSS141 VSS226 L7
AD28 AL21 AG19 H13 AM28 AB29 HVCCA
VCCP17 VCCP109 VCCP201 VSS57 VSS142 VSS227 14 HVCCA
Y26 VCCP18 VCCP110 AG25 AL9 VCCP202 VSS58 AC6 AJ13 VSS143 VSS228 M1
AC29 VCCP19 VCCP111 AJ18 AD30 VCCP203 VSS59 AC7 W4 VSS144 VSS229 AB28
M29 J19 AF21 AH6 P25 E8 EC24
U24
J23
VCCP21 VCCP113 AH30
J15
Y24
AK14
VCCP205 VSS61 C16
AM16
AJ20
W7
VSS146 VSS231 AG20
AN17
* 100uF
+/-20%
AC27 VCCP23 VCCP115 AG12 J9 VCCP207 VSS63 AE25 P23 VSS148 VSS233 AB27
AM18 VCCP24 VCCP116 AJ22 M27 VCCP208 VSS64 AE27 AG13 VSS149 VSS234 AB26
AM19 VCCP25 VCCP117 J20 AF14 VCCP209 VSS65 AJ28 AG16 VSS150 VSS235 AN16
AB8 VCCP26 VCCP118 AH18 J30 VCCP210 VSS66 AJ7 AG17 VSS151 VSS236 M7
AC26 AH26 AG18 F19 C7 AB25 HVSSA
VCCP27 VCCP119 VCCP211 VSS67 VSS152 VSS237 14 HVSSA
J8 VCCP28 VCCP120 W27 AA8 VCCP212 VSS68 AH13 Y2 VSS153 VSS238 AB24
J28 AL25 AG8 AD7 L30 AB23 Notes:
VCCP29 VCCP121 VCCP213 VSS69 VSS154 VSS239 1. Cap. should be within 1.5" mils of the VCCA and VSSA pins
T30 VCCP30 VCCP122 AN8 AL29 VCCP214 VSS70 AH16 L29 VSS155 VSS240 N3
AM9 AH14 AD29 AK17 D15 AA30 2. VCCA route should be parallel and next to VSSA route to
VCCP31 VCCP123 VCCP215 VSS71 VSS156 VSS241 minimize loop area
AF15 VCCP32 VCCP124 U27 W8 VCCP216 VSS72 E17 AL27 VSS157 VSS242 F4
3. VCCIOPLL route should be parallel and next to VSSA route
AC8 VCCP33 VCCP125 T23 AH8 VCCP217 VSS73 AH17 Y7 VSS158 VSS243 AG10
to minimize loop area
AE14 VCCP34 VCCP126 R8 N24 VCCP218 VSS74 AH20 L27 VSS159 VSS244 AE13
3. Min. 12 mils trace from the filter to the processor pins
N23 VCCP35 VCCP127 AK22 AN22 VCCP219 VSS75 AE5 AA29 VSS160 VSS245 AF30 4. The inductors should be close to the cap.
C W29 VCCP36 VCCP128 AN29 J14 VCCP220 VSS76 AH23 N6 VSS161 VSS246 H28 C
U29 VCCP37 VCCP129 AG11 K26 VCCP221 VSS77 AE7 N7 VSS162 VSS247 F7
AC24 VCCP38 VCCP130 AK26 AF19 VCCP222 VSS78 AM13 AA28 VSS163 VSS248 AF29
AC23 VCCP39 VCCP131 J10 N8 VCCP223 VSS79 AH24 AN13 VSS164 VSS249 AF28
Y23 VCCP40 VCCP132 AJ15 AF12 VCCP224 VSS80 AJ30 AA27 VSS165 VSS250 G1 TP_CPU_G1 14
AN26 VCCP41 VCCP133 AG26 M28 VCCP225 VSS81 AJ10 AA26 VSS166 VSS251 AF27
AN25 VCCP42 VCCP134 AN9 AK9 VCCP226 VSS82 AF3 P4 VSS167 VSS252 AF26
AN11 VCCP43 VCCP135 AH15 VSS83 AK5 AA25 VSS168 VSS253 AF25
AN18 VCCP44 VCCP136 AF18 VSS84 AJ16 AA24 VSS169 VSS254 AN28
Y27 VCCP45 VCCP137 AL15 C10 VSS1 VSS85 AF6 P7 VSS170 VSS255 AN27
Y25 VCCP46 VCCP138 J26 D12 VSS2 VSS86 AK29 E26 VSS171 VSS256 AF24
AD24 J18 AJ17 V30 AF23 VTT_OUT_RIGHT
VCCP47 VCCP139 VSS87 VSS172 VSS257
AE23 VCCP48 VCCP140 J21 C24 VSS4 VSS88 F22 R2 VSS173 VSS258 AG24
AE22 VCCP49 VCCP141 AG27 K2 VSS5 VSS89 AH3 V29 VSS174 VSS259 AF17
AN19 VCCP50 VCCP142 AK15 C22 VSS6 VSS90 AK10 V28 VSS175 VSS260 AN24
V8 VCCP51 VCCP143 AF11 AN1 VSS7 VSS91 AM10 R5 VSS176 VSS261 H3
K8 AD23 B14 F16 V27
**
VCCP52 VCCP144 VSS8 VSS92 VSS177 R237 49.9 +/-1% r0402h4 HCOMP6
AE21 VCCP53 VCCP145 AM15 K7 VSS9 VSS93 AJ23 R7 VSS178 VSS263 P24
AM30 AF8 AE16 F13 E20 AE20 Dummy
VCCP54 VCCP146 VSS10 VSS94 VTT_OUT_LEFT VSS179 VSS264 R240 49.9 +/-1% r0402h4 HCOMP7
AE19 VCCP55 VCCP147 AK21 B11 VSS11 VSS95 AG7 AN10 VSS180 VSS265 AE17
AC30 AG30 AL10 F10 V25 E27 Reserved
VCCP56 VCCP148 VSS12 VSS96 VSS181 VSS266
AE15 VCCP57 VCCP149 AJ21 AK23 VSS13 VSS97 L26 T3 VSS182 VSS267 T7
M30 AM11 H12 AD4 R255 V24 R30 10 mils width
K27
VCCP58
VCCP59
VCCP150
VCCP151 AL11 AF7
VSS14
VSS15
VSS98
VSS99 H11 *
51 Ohm V23
VSS183
VSS184
VSS268
VSS269 AJ27 7 mils spacing to low speed signals
14mils spacing to high speed signals
M24 AJ11 AK7 L24 +/-5% T6 AB1
VCCP60 VCCP152 VSS16 VSS100 r0402h4 VSS185 VSS270 max. 1200mils
AN21 VCCP61 VCCP153 K30 H7 VSS17 VSS101 L23 AL7 VSS186 VSS271 AM4
T8 VCCP62 VCCP154 AL14 E14 VSS18 VSS102 AM23 E25 VSS187 VSS272 V26
B AC28 VCCP63 VCCP155 AN30 L28 VSS19 VSS103 A15 U1 VSS188 VSS273 AA23 B
N25 VCCP64 VCCP156 AH25 Y5 VSS20 VSS104 AH10 R29 VSS189 VSS274 AL28
AE18 AL12 E11 H29 R28 AF20 R163
TP17
*
VCCP65 VCCP157 VSS21 VSS105 VSS190 VSS275 24.9 HCOMP8
W26 VCCP66 VCCP158 AJ9 AL16 VSS22 VSS106 B24 R27 VSS191 VSS276 AG23
AD25 AK11 AL24 L3 R26 +/-1%
VCCP67 VCCP159 VSS23 VSS107 VSS192
M8 VCCP68 VCCP160 AG14 AK13 VSS24 VSS108 H27 R25 VSS193
N30 VCCP69 VCCP161 N29 TP68 AL3 VSS25 VSS109 A21 U7 VSS194
AD26 VCCP70 VCCP162 AL30 D21 VSS26 VSS110 AE2 R24 VSS195
AJ26 AJ25 AL20 AJ29 R23 15 mils width
*
VCCP71 VCCP163 VSS27 VSS111 VSS196 7 mils spacing to low speed signals
AM29 VCCP72 VCCP164 AH9 D18 VSS28 VSS112 A24 P30 VSS197
M25 J29 AN2 AK27 V3 14mils spacing to high speed signals
VCCP73 VCCP165 VRDSEL VSS29 VSS113 R100 VSS198 max. 1200mils
M26 VCCP74 VCCP166 J11 AK16 VSS30 VSS114 AK28 P29 VSS199
L8 K25 AK20 B20 1K AF16 F6 IMPSEL
VCCP75 VCCP167 VSS31 VSS115 +/-5% VSS200 RSVD26
U25 VCCP76 VCCP168 P8 AM27 VSS32 VSS116 AM20 AE10 VSS201
Y8 K23 AM1 H26 r0402h4 AF13 Y3 HCOMP6
VCCP77 VCCP169 VSS33 VSS117 Dummy VSS202 RSVD28 HCOMP7
AJ12 VCCP78 VCCP170 AL19 AL13 VSS34 VSS118 B17 H6 VSS203 RSVD29 AE3
AD27 AM8 AL17 H25 A18
*
VCCP79 VCCP171 VSS35 VSS119 VSS204 R228 51 Ohm IMPSEL
U23 VCCP80 VCCP172 T26 C19 VSS36 VSS120 H24 A2 VSS205 RSVD31 E7
M23 N28 E28 AA3 E2 B13 HCOMP8 +/-5% r0402h4
VCCP81 VCCP173 VSS37 VSS121 VSS206 RSVD32
AG29 VCCP82 VCCP174 AH12 AH7 VSS38 VSS122 AA7 D9 VSS207 RSVD33 D14
N27 VCCP83 VCCP175 AL22 AK30 VSS39 VSS123 H23 C4 VSS208 RSVD34 E6
AM22 VCCP84 VCCP176 AN15 D24 VSS40 VSS124 AA6 A6 VSS209 RSVD35 D1
U28 VCCP85 VCCP177 AJ8 VSS125 H10 D6 VSS210 RSVD36 E5
K28 VCCP86 VCCP178 U26
U8 VCCP87 VCCP179 AJ19 Socket-IntelPrescottCPU Socket-IntelPrescottCPU
AK18 VCCP88 VCCP180 T27
AD8 VCCP89 VCCP181 AK8
A K24 VCCP90 VCCP182 AN12 A
AH28 VCCP91 VCCP183 AG9
AH21 VCCP92 VCCP184 N26
Socket-IntelPrescottCPU FOXCONN PCEG

Title
LGA775-2
Custom G31M05 A
Date: Saturday, January 05, 2008 Sheet 15 of 39

5 4 3 2 1
5 4 3 2 1
*R412
27 *R393
39 *R413
27 *R394
39
+/-1% +/-1% +/-1% +/-1%
U1MCH HDJ[63..0] r0603h6 r0603h6 r0603h6 r0603h6
14 HAJ[35..3] U12B HDJ[63..0] 14 Placed both Resistors close to GMCH
@946 @G31 @946 @G31
HAJ3 J42 R40 HDJ0 Within 750 mils
HAJ4 HA3# HD0# HDJ1 U12E W=4 mils, S=10 mils from GMCH to connector
L39 HA4# HD1# P41
HAJ5 J40 R41 HDJ2
**
HAJ6 HA5# HD2# HDJ3 U1MCH BSEL0 HSYNC_P R150 39 +/-1% #R393#R412
L37 HA6# HD3# N40 U12A G20 BSEL0 HSYNC C15 HSYNC 24
HAJ7 L36 R42 HDJ4 BSEL1 J20 D15 VSYNC_P R145 39 +/-1% #R394#R413
HAJ8 HA7# HD4# HDJ5 EXP_RXP0 EXP_TXP0 BSEL2 BSEL1 VSYNC Modify by Steven 051707 Apply 0402 or not VSYNC 24
K42 HA8# HD5# M39 23 EXP_RXP0 F15 EXP_RXP0 EXP_TXP0 D11 EXP_TXP0 23 J18 BSEL2
HAJ9 N32 N41 HDJ6 EXP_RXN0 G15 D12 EXP_TXN0 TP16 TP_ALLZTEST K20 B18
HA9# HD6# 23 EXP_RXN0 EXP_RXN0* EXP_TXN0* EXP_TXN0 23 ALLZTEST RED RED 24
HAJ10 N34 N42 HDJ7 EXP_RXP1 K15 B11 EXP_TXP1 F20 C19
HA10# HD7# 23 EXP_RXP1 EXP_RXP1 EXP_TXP1 EXP_TXP1 23 XORTEST GREEN GREEN 24
HAJ11 M38 L41 HDJ8 EXP_RXN1 J15 A10 EXP_TXN1 G18 B20
FSB
HA11# HD8# 23 EXP_RXN1 EXP_RXN1* EXP_TXN1* EXP_TXN1 23 RESERVED_24 BLUE BLUE 24
HAJ12 N37 J39 HDJ9 EXP_RXP2 F12 C10 EXP_TXP2 GMCH_EXP_SLR E18 C18 R157 R158 R159
HA12# HD9# 23 EXP_RXP2 EXP_RXP2 EXP_TXP2 EXP_TXP2 23 EXP_SLR RED#
HAJ13 HDJ10 EXP_RXN2 EXP_TXN2
M36 HA13# HD10# L42 23 EXP_RXN2 E12 EXP_RXN2* EXP_TXN2* D9 EXP_TXN2 23 K17 RESERVED_25 GREEN# D19
*150 150 150
+/ -1% *+/ -1% *+/ -1%
VGA
HAJ14 R34 J41 HDJ11 EXP_RXP3 J12 B9 EXP_TXP3 GMCH_EXP_EN_HDR J17 D20
D HA14# HD11# 23 EXP_RXP3 EXP_RXP3 EXP_TXP3 EXP_TXP3 23 EXP_EN BLUE# D
HAJ15 N35 K41 HDJ12 EXP_RXN3 H12 B7 EXP_TXN3 H18 r0402h4 r0402h4 r0402h4
HA15# HD12# 23 EXP_RXN3 EXP_RXN3* EXP_TXN3* EXP_TXN3 23 RESERVED
HAJ16 N38 G40 HDJ13 EXP_RXP4 J11 D7 EXP_TXP4 L13 DDCA_DATA
HA16# HD13# 23 EXP_RXP4 EXP_RXP4 EXP_TXP4 EXP_TXP4 23 DDC_DATA DDCA_DATA 24
HAJ17 U37 F41 HDJ14 EXP_RXN4 H11 D6 EXP_TXN4 L17 M13 DDCA_CLK
HA17# HD14# 23 EXP_RXN4 EXP_RXN4* EXP_TXN4* EXP_TXN4 23 RESERVED_1 DDC_CLK DDCA_CLK 24 Placed close to
HAJ18 N39 F42 HDJ15 EXP_RXP5 F7 B5 EXP_TXP5 N17
HA18# HD15# 23 EXP_RXP5 EXP_RXP5 EXP_TXP5 EXP_TXP5 23 RESERVED_2 GMCH within
HAJ19 R37 C42 HDJ16 EXP_RXN5 E7 B6 EXP_TXN5 N18 A20 REFSET
HA19# HD16# 23 EXP_RXN5 EXP_RXN5* EXP_TXN5* EXP_TXN5 23 RESERVED_3 REFSET 300 mils
HAJ20 P42 D41 HDJ17 EXP_RXP6 E5 B3 EXP_TXP6 N15
HA20# HD17# 23 EXP_RXP6 EXP_RXP6 EXP_TXP6 EXP_TXP6 23 RESERVED_4
HAJ21 R39 F38 HDJ18 EXP_RXN6 F6 B4 EXP_TXN6 M20 C14 CK_96M_P_GMCH
HA21# HD18# 23 EXP_RXN6 EXP_RXN6* EXP_TXN6* EXP_TXN6 23 RESERVED_5 DREFCLKP CK_96M_P_GMCH 8
HAJ22 V36 G37 HDJ19 EXP_RXP7 C2 F2 EXP_TXP7 L15 D13 CK_96M_N_GMCH
HA22# HD19# 23 EXP_RXP7 EXP_RXP7 EXP_TXP7 EXP_TXP7 23 Controller Link Routing RESERVED_6 DREFCLKN CK_96M_N_GMCH 8
HAJ23 R38 E42 HDJ20 EXP_RXN7 D2 E2 EXP_TXN7 L18 L12
HA23# HD20# 23 EXP_RXN7 EXP_RXN7* EXP_TXN7* EXP_TXN7 23 1. width=4 mils, Spacing=7 mils RESERVED_7 VCC 1D25V_MCH
HAJ24 U36 E39 HDJ21 EXP_RXP8 G6 F4 EXP_TXP8 M18 M11
PCIE
HA24# HD21# 23 EXP_RXP8 EXP_RXP8 EXP_TXP8 EXP_TXP8 23 2. CL_CLK and CL_DATA should be length RESERVED_8 VSS
HAJ25 U33 E37 HDJ22 EXP_RXN8 G5 G4 EXP_TXN8
HA25# HD22# 23 EXP_RXN8 EXP_RXN8* EXP_TXN8* EXP_TXN8 23 matched to within 100 mils
HAJ26 R35 C39 HDJ23 EXP_RXP9 L9 J4 EXP_TXP9
HA26# HD23# 23 EXP_RXP9 EXP_RXP9 EXP_TXP9 EXP_TXP9 23
HAJ27 V33 B39 HDJ24 EXP_RXN9 L8 K3 EXP_TXN9
HA27# HD24# 23 EXP_RXN9 EXP_RXN9* EXP_TXN9* EXP_TXN9 23
HAJ28 V35 G33 HDJ25 EXP_RXP10 M8 L2 EXP_TXP10 TP19 AD12 F13 TP_MCH_F13
HA28# HD25# 23 EXP_RXP10 EXP_RXP10 EXP_TXP10 EXP_TXP10 23 CL_DATA RESERVED_001 TP20
HAJ29 Y34 A37 HDJ26 EXP_RXN10 M9 K1 EXP_TXN10 TP18 AD13 F17
HA29# HD26# 23 EXP_RXN10 EXP_RXN10* EXP_TXN10* EXP_TXN10 23 CL_CLK RESERVED_23
HAJ30 V42 F33 HDJ27 EXP_RXP11 M4 N2 EXP_TXP11 CL_VREF_MCH AM5 A14 TP_MCH_A14
MISC
HA30# HD27# 23 EXP_RXP11 EXP_RXP11 EXP_TXP11 EXP_TXP11 23 CL_VREF RESERVED_26 TP22
HAJ31 V38 E35 HDJ28 EXP_RXN11 L4 M2 EXP_TXN11 PLTRSTJR206 1.65KOhm CL_RST AA12 AM18 ICH_PLTRSTJ
HA31# HD28# 23 EXP_RXN11 EXP_RXN11* EXP_TXN11* EXP_TXN11 23 CL_RST# RSTIN# PLTRSTJ 25,29,35
HAJ32 Y36 K32 HDJ29 EXP_RXP12 M5 P3 EXP_TXP12 +/-1% r0402h4 AM15 AM17 PWRGD_3V
EXP_TXP12 23 PWRGD_3V 25,35
*
HAJ33 HA32# HD29# HDJ30 23 EXP_RXP12 EXP_RXN12 EXP_RXP12 EXP_TXP12 EXP_TXN12 R210 1K CL_PWROK PWROK ICH_SYNCJ
Y38 HA33# HD30# H32 23 EXP_RXN12 M6 EXP_RXN12* EXP_TXN12* N4 EXP_TXN12 23 ICH_SYNC# J13 ICH_SYNCJ 25
HAJ34 Y39 B34 HDJ31 EXP_RXP13 R9 R2 EXP_TXP13 +/-1% r0402h4
HA34# HD31# 23 EXP_RXP13 EXP_RXP13 EXP_TXP13 EXP_TXP13 23
HAJ35 AA37 J31 HDJ32 EXP_RXN13 R10 P1 EXP_TXN13 A42 TP_MCH_DET_N
HA35# HD32# 23 EXP_RXN13 EXP_RXN13* EXP_TXN13* EXP_TXN13 23 NC TP23
F32 HDJ33 EXP_RXP14 T4 U2 EXP_TXP14 PWRGD_3V
HD33# 23 EXP_RXP14 EXP_RXP14 EXP_TXP14 EXP_TXP14 23
M31 HDJ34 EXP_RXN14 R4 T2 EXP_TXN14 AA10
14 HREQJ[4..0] HD34# 23 EXP_RXN14 EXP_RXN14* EXP_TXN14* EXP_TXN14 23 RESERVED_9
HREQJ0 F40 E31 HDJ35 EXP_RXP15 R6 V3 EXP_TXP15 AA9 BC43 TP_MCH_CGC_1
HREQ0# HD35# 23 EXP_RXP15 EXP_RXP15 EXP_TXP15 EXP_TXP15 23 RESERVED_10 TEST0 TP24
HREQJ1 L35 K31 HDJ36 EXP_RXN15 R7 U4 EXP_TXN15 AA11 BC1 TP_MCH_CGC_2
HREQ1# HD36# 23 EXP_RXN15 EXP_RXN15* EXP_TXN15* EXP_TXN15 23 RESERVED_11 TEST1 TP26
HREQJ2 L38 G31 HDJ37 Y12 A43 TP_MCH_CGC_3
HREQ2# HD37# RESERVED_12 TEST2 TP25
HREQJ3 G43 K29 HDJ38 DMI_RXP0 W2 V7 C2390.1uF 16V, X7R, +/-10% DMI_TXP0
DMI_TXP0 25
********
HREQJ4 HREQ3# HD38# HDJ39 25 DMI_RXP0 DMI_RXN0 DMI_RXP0 DMI_TXP0 C2380.1uF 16V, X7R, +/-10% DMI_TXN0
J37 HREQ4# HD39# F31 25 DMI_RXN0 V1 DMI_RXN0* DMI_TXN0* V6 DMI_TXN0 25 U30 RESERVED_13
J29 HDJ40 DMI_RXP1 Y8 W4 C2290.1uF 16V, X7R, +/-10% DMI_TXP1 U31 N20
HD40# 25 DMI_RXP1 DMI_RXP1 DMI_TXP1 DMI_TXP1 25 RESERVED_14 NC_1
M34 F29 HDJ41 DMI_RXN1 Y9 Y4 C2330.1uF 16V, X7R, +/-10% DMI_TXN1 R29 BC42
14 HADSTBJ0 HADSTB0# HD41# 25 DMI_RXN1 DMI_RXN1* DMI_TXN1* DMI_TXN1 25 RESERVED_15 NC_2
DMI
U34 L27 HDJ42 DMI_RXP2 AA7 AC8 C2400.1uF 16V, X7R, +/-10% DMI_TXP2 R30 BC2
14 HADSTBJ1 HADSTB1# HD42# 25 DMI_RXP2 DMI_RXP2 DMI_TXP2 DMI_TXP2 25 RESERVED_16 NC_3
K27 HDJ43 DMI_RXN2 AA6 AC9 C2450.1uF 16V, X7R, +/-10% DMI_TXN2 BB43
HD43# 25 DMI_RXN2 DMI_RXN2* DMI_TXN2* DMI_TXN2 25 NC_4
L40 H26 HDJ44 DMI_RXP3 AB3 Y2 C2370.1uF 16V, X7R, +/-10% DMI_TXP3 U12 BB1
14 HDSTBPJ0 HDSTBP0# HD44# 25 DMI_RXP3 DMI_RXP3 DMI_TXP3 DMI_TXP3 25 RESERVED_17 NC_5
M43 L26 HDJ45 DMI_RXN3 AA4 AA2 C2430.1uF 16V, X7R, +/-10% DMI_TXN3 U11 B43
14 HDSTBNJ0 HDSTBN0# HD45# 25 DMI_RXN3 DMI_RXN3* DMI_TXN3* DMI_TXN3 25 RESERVED_18 NC_6
HDBIJ0 M40 J26 HDJ46 R12 B42 3D3V_SYS
14 HDBIJ0 HDINV0# HD46# RESERVED_19 NC_7
G35 M26 HDJ47 R13 B2
14 HDSTBPJ1 HDSTBP1# HD47# RESERVED_20 5 OF 7 NC_8
H33 C33 HDJ48 CK_PE_100M_P_GMCH B12 R191
14 HDSTBNJ1 HDSTBN1# HD48# 8 CK_PE_100M_P_GMCH GCLKP
C HDBIJ1 J33 LE82G31 C35 HDJ49 CK_PE_100M_N_GMCH B13 AC11 GMCH_EXP_COMP 24.9 1D25V_MCH C
14 HDBIJ1 HDINV1# HD49# 8 CK_PE_100M_N_GMCH GCLKN* EXP_COMPO
G27 E41 HDJ50 AC12 +/-1%
14 HDSTBPJ2 HDSTBP2# HD50# HDJ51 EXP_COMPI
14 HDSTBNJ2 H27 HDSTBN2# HD51# B41 23 SDVO_CTRLDATA G17 SDVO_CTRLDATA LE82G31
HDBIJ2 G29 D42 HDJ52 E17 width 10 mils, spacing 6 mils at breakout
14 HDBIJ2
*
HDINV2# HD52# HDJ53 23 SDVO_CTRLCLK SDVO_CTRLCLK 2 OF 7 10 mils after that bga1226_1h25 ICH_SYNCJ R156 1K
14 HDSTBPJ3 B38 HDSTBP3# HD53# C40
HDJ54 Del R934,R935 0Ohm RES +/-5% r0402h4
14 HDSTBNJ3 D38 HDSTBN3# HD54# D35 LE82G31
HDBIJ3 E33 B40 HDJ55
14 HDBIJ3 HDINV3# HD55# #U27#U28
R200,R201,R205,R208,R209,R210 USE 0 OHM FOR 946PL.
C38 HDJ56 bga1226_1h25
HD56# HDJ57 DUMMY R192,R194.
W40 D37
*
14 HADSJ HADS# HD57# HDJ58 PWRGD_3V R62 10K
14 HTRDYJ Y40 HTRDY# HD58# B33
W41 D33 HDJ59 #U27#U28 +/-5% Dummy
14 HDRDYJ HDRDY# HD59# HDJ60
14 HDEFERJ T43 HDEFER# HD60# C34
Y43 B35 HDJ61
14 HITMJ HHITM# HD61# HDJ62 1D25V_MCH
14 HITJ U42 HHIT# HD62# A32
V41 D32 HDJ63
14 HLOCKJ HLOCK# HD63#
AA42
****
14 HBR0J HBREQ0# HSWING DMI_RXP0 R177 4.7K +/-5% R160
14 HBNRJ W42 HBNR# HSWING B25
G39 D23 HRCOMP 1.3KOhm REFSET
14 HBPRIJ HBPRI# HRCOMP HSCOMP DMI_RXP1 R178 4.7K +/-5% +/-1%
14 HDBSYJ U40 HDBSY# HSCOMP C25
U41 D25 HSCOMPJ
14 HRSJ0 HRS0# HSCOMP# MCH_GTLREF DMI_RXP2 R180 4.7K +/-5%
14 HRSJ1 AA41 HRS1# HDVREF D24
U39 B24 placed close to GMCH within 500 mils
14 HRSJ2 HRS2# HACCVREF DMI_RXP3 R184 4.7K +/-5% 4 mils width
14 HCPURSTJ C31 HCPURST# HCLKP R32 CK_200M_P_GMCH 8
U32 6 mils spacing to static signals
HCLKN CK_200M_N_GMCH 8 12 mils spacing to toppling signals
1 OF 7
bga1226_1h25
#U27#U28
FSB_VTT FSB_VTT COMP SIGNAL TERMINATION
*
HSCOMPJ
*R139
301 Resistor and Capacitor
next to each other.
R154
+/-1%
49.9
r0402h4
* 3.3pF
+/-1% C185 50V, NPO, +/-0.25pF
B
Dummy B
*
R152 49.9 HSWING
***
+/-1% r0402h4 FSBSEL0 R135 10K BSEL0
*
R151 49.9 HSCOMP +/-5% 1D25V_MCH

R142 C165 +/-1% r0402h4 C184 FSBSEL1 R136 10K BSEL1
* 100 Ohm
* 10nF
* 3.3pF +/-5%
+/-1% 25V, X7R, +/-10% 50V, NPO, +/-0.25pF FSBSEL2 R134 10K BSEL2
HSWING voltage should be 0.25*FSB_VTT

Dummy 23 GMCH_EXP_EN_HDR
GMCH_EXP_EN_HDR +/-5% *R212
1K
+/-1%
10 mils width, 10 mils spacing r0402h4
max. 3 inches long
CL_VREF_MCH
4 mils width, 6 mils spacing in the breakout FSBSEL0
4 mils width, 14 mils spacing after the breakout 8,14 FSBSEL0
max. 750 mils
routed on a single layer and matched within 50mils
*R207
392
*
C275
0.1uF
0.349V
FSBSEL1 +/-1% 16V, Y5V, +80%/-20%
R155 8,14 FSBSEL1 r0402h4
HRCOMP 16.9 Place close to VREF Pin
+/-1% FSBSEL2
change to 16.9ohm 8,14 FSBSEL2
10 mils width, 7 mils spacing min. 4 mils width

max. 500 mils 10 mils spacing
*
5 on 5 mils in breakout, max 250 mils GMCH_EXP_SLR 5 mils min. for max. of 300 mils in breakout
1D25V_MCH R146 1K
+/-5% r0402h4
ATX: 1
BTX: 0
FSB_VTT
Not used for CoreTM2 Duo and Wolfdale with G31 Chipset
Del or not in G31
*
*R132 R128
100 Ohm +/-5%
0
MCH_GTLREF_CPU 14
+/-1%
*
A R144 MCH_GTLREF A
C164 10
* 1uF *R131
200 +/-1%
*
C167
220pF
+/-1% 50V, NPO, +/-5%
10V, Y5V, +80%/-20%
GTLREF voltage should be 0.63*VTT = 0.75V FOXCONN PCEG

12 mils width, 15 mils spacing
divider should be within 1.5" of the GTLREF pin Title
220pF caps should be placed near MCH pin
place series resistor as close to divider BearLake-GMCH-1
Resistor and Capacitor next to each other Size Document Number Rev
C G31M05 A

5 4 3 2 1
5 4 3 2 1
U12D U1MCH
U12C U1MCH
21,22 M_MAA_B[14..0] M_DQS_B[7..0] 22
M_MAA_B0 BB17 AV6 M_DQS_B0
19,20 M_MAA_A[14..0] M_DQS_A[7..0] 20 SMA_B0 SDQS_B0 M_DQS_BJ[7..0] 22
M_MAA_A0 BA31 AU4 M_DQS_A0 M_MAA_B1 AY17 AU5 M_DQS_BJ0
SMA_A0 SDQS_A0 M_DQS_AJ[7..0] 20 SMA_B1 SDQS_B0# M_DQM_B[7..0] 22
M_MAA_A1 BB25 AR3 M_DQS_AJ0 M_MAA_B2 BA17 AR7 M_DQM_B0
SMA_A1 SDQS_A0# M_DQM_A[7..0] 20 SMA_B2 SDM_B0 M_DATA_B[63..0] 22
M_MAA_A2 BA26 AR2 M_DQM_A0 M_MAA_B3 BC16
SMA_A2 SDM_A0 M_DATA_A[63..0] 20 SMA_B3
M_MAA_A3 BA25 M_MAA_B4 AW15 AN7 M_DATA_B0
M_MAA_A4 SMA_A3 M_DATA_A0 M_MAA_B5 SMA_B4 SDQ_B0 M_DATA_B1
AY25 SMA_A4 SDQ_A0 AR5 BA15 SMA_B5 SDQ_B1 AN8
M_MAA_A5 BA23 AR4 M_DATA_A1 M_MAA_B6 BB15 AW5 M_DATA_B2
M_MAA_A6 SMA_A5 SDQ_A1 M_DATA_A2 M_MAA_B7 SMA_B6 SDQ_B2 M_DATA_B3
AY24 SMA_A6 SDQ_A2 AV3 BA14 SMA_B7 SDQ_B3 AW7
M_MAA_A7 AY23 AV2 M_DATA_A3 M_MAA_B8 AY15 AN5 M_DATA_B4
BB23 SMA_A8 SDQ_A4 AP3 BB14 SMA_B9 SDQ_B5 AN6
M_MAA_A9 BA22 AP2 M_DATA_A5 M_MAA_B10 AW18 AN9 M_DATA_B6
AY33 SMA_A10 SDQ_A6 AU1 BB13 SMA_B11 SDQ_B7 AU7
M_MAA_A11 BB22 AV4 M_DATA_A7 M_MAA_B12 BA13
D SMA_A11 SDQ_A7 SMA_B12 M_DQS_B[7..0] 22 D
M_MAA_A12 AW21 M_MAA_B13 AY29 AR12 M_DQS_B1
SMA_A12 M_DQS_A[7..0] 20 SMA_B13 SDQS_B1 M_DQS_BJ[7..0] 22
M_MAA_A13 AY38 BB3 M_DQS_A1 M_MAA_B14 AY13 AP12 M_DQS_BJ1
SMA_A13 SDQS_A1 M_DQS_AJ[7..0] 20 SMA_B14 SDQS_B1# M_DQM_B[7..0] 22
M_MAA_A14 BA21 BA4 M_DQS_AJ1 AW9 M_DQM_B1
SMA_A14 SDQS_A1# M_DQM_A[7..0] 20 SDM_B1 M_DATA_B[63..0] 22
BA2 M_DQM_A1 BA27
SDM_A1 M_DATA_A[63..0] 20 21,22 M_WE_BJ SWE_B#
BB34 AW29 AT11 M_DATA_B8
19,20 M_WE_AJ SWE_A# M_DATA_A8 21,22 M_CAS_BJ SCAS_B# SDQ_B8 M_DATA_B9
19,20 M_CAS_AJ AY35 SCAS_A# SDQ_A8 AY2 21,22 M_RAS_BJ AW26 SRAS_B# SDQ_B9 AU11
BB33 AY3 M_DATA_A9 AP13 M_DATA_B10
19,20 M_RAS_AJ SRAS_A# SDQ_A9 M_DATA_A10 21,22 M_BS_B[2..0] M_BS_B0 SDQ_B10 M_DATA_B11
SDQ_A10 BB5 AY19 SBS_B0 SDQ_B11 AR13
M_BS_A0 BA33 AY6 M_DATA_A11 M_BS_B1 BA18 AR11 M_DATA_B12
M_BS_A1 SBS_A0 SDQ_A11 M_DATA_A12 M_BS_B2 SBS_B1 SDQ_B12 M_DATA_B13
AW32 SBS_A1 SDQ_A12 AW2 BC12 SBS_B2 SDQ_B13 AU9
M_BS_A2 BB21 AW3 M_DATA_A13 AV12 M_DATA_B14
SBS_A2 SDQ_A13 M_DATA_A14 SDQ_B14 M_DATA_B15
19,20 M_BS_A[2..0] SDQ_A14 BA5 21,22 M_SCS_B0J BB27 SCS_B0# SDQ_B15 AU12
AW35 BB4 M_DATA_A15 BB30
19,20 M_SCS_A0J SCS_A0# SDQ_A15 21,22 M_SCS_B1J SCS_B1# M_DQS_B[7..0] 22
BA35 AY27 AP15 M_DQS_B2
19,20 M_SCS_A1J SCS_A1# M_DQS_A[7..0] 20 SCS_B2# SDQS_B2 M_DQS_BJ[7..0] 22
BA34 BB9 M_DQS_A2 AY31 AR15 M_DQS_BJ2
SCS_A2# SDQS_A2 M_DQS_AJ[7..0] 20 SCS_B3# SDQS_B2# M_DQM_B[7..0] 22
BB38 BA9 M_DQS_AJ2 AW13 M_DQM_B2
SCS_A3# SDQS_A2# M_DQM_A[7..0] 20 21,22 M_SCKE_B[1..0] SDM_B2 M_DATA_B[63..0] 22
AY9 M_DQM_A2 M_SCKE_B0 AY12
19,20 M_SCKE_A[1..0] SDM_A2 M_DATA_A[63..0] 20 SCKE_B0
M_SCKE_A0 BC20 M_SCKE_B1 AW12 AU15 M_DATA_B16
M_SCKE_A1 SCKE_A0 M_DATA_A16 SCKE_B1 SDQ_B16 M_DATA_B17
AY20 SCKE_A1 SDQ_A16 AY7 BB11 SCKE_B2 SDQ_B17 AV13
AY21 BC7 M_DATA_A17 BA11 AU17 M_DATA_B18
SCKE_A2 SDQ_A17 M_DATA_A18 21,22 M_ODT_B[1..0] M_ODT_B0 SCKE_B3 SDQ_B18 M_DATA_B19
BA19 SCKE_A3 SDQ_A18 AW11 BA29 SODT_B0 SDQ_B19 AT17
AY11 M_DATA_A19 M_ODT_B1 BA30 AU13 M_DATA_B20
19,20 M_ODT_A[1..0] M_ODT_A0 SDQ_A19 M_DATA_A20 SODT_B1 SDQ_B20 M_DATA_B21
AY37 SODT_A0 SDQ_A20 BB6 BB29 SODT_B2 SDQ_B21 AM13
M_ODT_A1 BA38 BA6 M_DATA_A21 BB31 AV15 M_DATA_B22
SODT_A1 SDQ_A21 M_DATA_A22 SODT_B3 SDQ_B22 M_DATA_B23
BB35 SODT_A2 SDQ_A22 BA10 SDQ_B23 AW17
BA39 BB10 M_DATA_A23 AV31
SODT_A3 SDQ_A23 22 CK_M_200M_P_DDR0_B SCLK_B0 M_DQS_B[7..0] 22
AW31 AT24 M_DQS_B3
M_DQS_A[7..0] 20 22 CK_M_200M_N_DDR0_B SCLK_B0# SDQS_B3 M_DQS_BJ[7..0] 22
AU31 AT20 M_DQS_A3 AU27 AU26 M_DQS_BJ3
20 CK_M_200M_P_DDR0_A SCLK_A0 SDQS_A3 M_DQS_AJ[7..0] 20 22 CK_M_200M_P_DDR1_B SCLK_B1 SDQS_B3# M_DQM_B[7..0] 22
AR31 AU18 M_DQS_AJ3 AT27 AP23 M_DQM_B3
20 CK_M_200M_N_DDR0_A SCLK_A0# SDQS_A3# M_DQM_A[7..0] 20 22 CK_M_200M_N_DDR1_B SCLK_B1# SDM_B3 M_DATA_B[63..0] 22
AP27 AN18 M_DQM_A3 AV32
20 CK_M_200M_P_DDR1_A SCLK_A1 SDM_A3 M_DATA_A[63..0] 20 22 CK_M_200M_P_DDR2_B SCLK_B2
AN27 AT32 AV24 M_DATA_B24
20 CK_M_200M_N_DDR1_A SCLK_A1# M_DATA_A24 22 CK_M_200M_N_DDR2_B SCLK_B2# SDQ_B24 M_DATA_B25
20 CK_M_200M_P_DDR2_A AV33 SCLK_A2 SDQ_A24 AT18 AU29 SCLK_B3 SDQ_B25 AT23
AW33 AR18 M_DATA_A25 AR29 AT26 M_DATA_B26
20 CK_M_200M_N_DDR2_A SCLK_A2# SDQ_A25 M_DATA_A26 SCLK_B3# SDQ_B26 M_DATA_B27
AP29 SCLK_A3 SDQ_A26 AU21 AV29 SCLK_B4 SDQ_B27 AP26
AP31 AT21 M_DATA_A27 AW27 AU23 M_DATA_B28
SCLK_A3# SDQ_A27 M_DATA_A28 SCLK_B4# SDQ_B28 M_DATA_B29
AM26 SCLK_A4 SDQ_A28 AP17 AN33 SCLK_B5 SDQ_B29 AW23
AM27 AN17 M_DATA_A29 AP32 AR24 M_DATA_B30
SCLK_A4# SDQ_A29 M_DATA_A30 SCLK_B5# SDQ_B30 M_DATA_B31
C AT33 SCLK_A5 SDQ_A30 AP20 SDQ_B31 AN26 C
AU33 AV20 M_DATA_A31
SCLK_A5# SDQ_A31 M_DQS_B[7..0] 22
AW39 M_DQS_B4
M_DQS_A[7..0] 20 SDQS_B4 M_DQS_BJ[7..0] 22
AR41 M_DQS_A4 AU39 M_DQS_BJ4
SDQS_A4 M_DQS_AJ[7..0] 20 SDQS_B4# M_DQM_B[7..0] 22
AR40 M_DQS_AJ4 AU37 M_DQM_B4
SDQS_A4# M_DQM_A[7..0] 20 SDM_B4 M_DATA_B[63..0] 22
AU43 M_DQM_A4
SDM_A4 M_DATA_A[63..0] 20
AW37 M_DATA_B32
M_DATA_A32 SDQ_B32 M_DATA_B33
SDQ_A32 AV42 SDQ_B33 AV38
AU40 M_DATA_A33 BB2 AN36 M_DATA_B34
SDQ_A33 M_DATA_A34 RESERVED_1 SDQ_B34 M_DATA_B35
SDQ_A34 AP42 AW42 RESERVED_2 SDQ_B35 AN37
AN39 M_DATA_A35 AN32 AU35 M_DATA_B36
SDQ_A36 AV40 AM31 RESERVED_4 SDQ_B37 AR35
AV41 M_DATA_A37 AG32 AN35 M_DATA_B38
SDQ_A38 AR42 AF32 RESERVED_6 SDQ_B39 AR37
AP41 M_DATA_A39 TP_MCH_AP21 AP21
SDQ_A39 TP51 SM_SLEWIN0 M_DQS_B[7..0] 22
TP_MCH_AA39 AA39 AL35 M_DQS_B5
M_DQS_A[7..0] 20 TP52 SM_SLEWIN1 SDQS_B5 M_DQS_BJ[7..0] 22
AL41 M_DQS_A5 AL34 M_DQS_BJ5
SDQS_A5 M_DQS_AJ[7..0] 20 SDQS_B5# M_DQM_B[7..0] 22
AL40 M_DQS_AJ5 AM37 M_DQM_B5
SDQS_A5# M_DQM_A[7..0] 20 SDM_B5 M_DATA_B[63..0] 22
AM43 M_DQM_A5
AM35 M_DATA_B40
SDQ_A40 AN41 SDQ_B41 AM38
AM39 M_DATA_A41 AJ34 M_DATA_B42
SDQ_A41 M_DATA_A42 SDQ_B42 M_DATA_B43
SDQ_A42 AK42 SDQ_B43 AL38
AK41 M_DATA_A43 AR39 M_DATA_B44
SDQ_A44 AN40 SDQ_B45 AM34
AN42 M_DATA_A45 AL37 M_DATA_B46
SDQ_A46 AL42 SDQ_B47 AL32
AL39 M_DATA_A47
SDQ_A47 M_DQS_B[7..0] 22
AG35 M_DQS_B6
AG42 M_DQS_A6 AG36 M_DQS_BJ6
SDQS_A6
SDQS_A6# AG41 M_DQS_AJ6
M_DQS_AJ[7..0] 20
M_DQM_A[7..0] 20
DDR_1 SDQS_B6#
SDM_B6 AG39 M_DQM_B6
M_DQM_B[7..0] 22
M_DATA_B[63..0] 22
AG40 M_DQM_A6
AG38 M_DATA_B48
SDQ_A48 AJ40 SDQ_B49 AJ38
AH43 M_DATA_A49 AF35 M_DATA_B50
SDQ_A50 AF39 SDQ_B51 AF33
AE40 M_DATA_A51 AJ37 M_DATA_B52
B SDQ_A52 AJ42 SDQ_B53 AJ35 B
AJ41 M_DATA_A53 TP_MCH_AM21 AM21 AG33 M_DATA_B54
SDQ_A53 TP53 RESERVED_7 SDQ_B54
AF41 M_DATA_A54 AF34 M_DATA_B55
SDQ_A54 M_DATA_A55 DDR_GMCH_VREF SDQ_B55
SDQ_A55 AF42 AM6 SVREF M_DQS_B[7..0] 22
AC36 M_DQS_B7
AC42 M_DQS_A7 AC37 M_DQS_BJ7
DDR_0 SDQS_A7
SDQS_A7# AC41 M_DQS_AJ7
M_DQS_AJ[7..0] 20
M_DQM_A[7..0] 20
SDQS_B7#
SDM_B7 AD38 M_DQM_B7
M_DQM_B[7..0] 22
M_DATA_B[63..0] 22
AC40 M_DQM_A7
AD36 M_DATA_B56
TP_MCH_AN21 M_DATA_A56 SRCOMP0 SDQ_B56 M_DATA_B57
TP54 AN21 RESERVED SDQ_A56 AD40 AN2 SRCOMP0 SDQ_B57 AC33
AD43 M_DATA_A57 SRCOMP1 AN3 AA34 M_DATA_B58
SDQ_A57 M_DATA_A58 SRCOMP2 SRCOMP1 SDQ_B58 M_DATA_B59
SDQ_A58 AB41 BB40 SRCOMP2 SDQ_B59 AA36
AA40 M_DATA_A59 SRCOMP3 BA40 AD34 M_DATA_B60
SDQ_A59 M_DATA_A60 SMRCOMPVOL SRCOMP3 SDQ_B60 M_DATA_B61
SDQ_A60 AE42 DDR2 Compensation Group Signals AM8 SMRCOMPVOL SDQ_B61 AF38
AE41 M_DATA_A61 SMRCOMPVOH AM10 AC34 M_DATA_B62
SDQ_A61 M_DATA_A62 SMRCOMPVOH SDQ_B62 M_DATA_B63
SDQ_A62 AC39 BB19 RESERVED SDQ_B63 AA33
AB42 M_DATA_A63 R203 20 SRCOMP0
SDQ_A63 +/-1% 4 OF 7
3 OF 7
1D8V_STR LE82G31 bga1226_1h25

LE82G31 bga1226_1h25
R198 20 SRCOMP1
C270 +/-1% #U27#U28
#U27#U28 * 0.1uF
16V, Y5V, +80%/-20%
1D8V_STR 1D8V_STR 1D8V_STR
R224 20 SRCOMP2
+/-1% 1D8V_STR
C295 C294
* 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% *R196
1K 1D8V_STR
+/-1% *R204
1K
r0402h4 R223 20 SRCOMP3 +/-1%
SMRCOMPVOH +/-1% r0402h4
C268 DDR_GMCH_VREF
A
* R195
3.01K * 10nF
25V, X7R, +/-10%
A
+/-1% *R209
1K
*
C272
0.1uF
r0402h4 +/-1% 16V, Y5V, +80%/-20%
SMRCOMPVOL r0402h4
*R202
1K C264
+/-1%
r0402h4 * 10nF
25V, X7R, +/-10%
5 mils width, 10 mils spacing, max 500 mils length for breakout region
Place CAP./RES. within 1" of GMCH package. width 10 mils, spacing 10 mils
1D8V_STR: 10 mils width/10 mils spacing.
SMRCOMPVOH: 0.8 *VCCSM
5 mils width/spacing minimum for max. of 300 mils
in GMCH break-out area
FOXCONN PCEG
SMRCOMPVOL: 0.2 *VCCSM Placed close to GMCH pin Title
BearLake-GMCH-2
C G31M05 A

5 4 3 2 1
5 4 3 2 1
1D25V_MCH
U1_1 U12F
8D 8 U12_1 U12G
7 7 1D25V_MCH
2 2 VCC_81 AG25
A D
1 1 VCC_172 AG24 BC37 VSS_1 VSS_181 AF5
VCC_173 AG23 BC32 VSS_2 VSS_182 AF3
FOXCONN AJ12 VCC_1 VCC_174 AG22 BC28 VSS_3 VSS_183 AF2
AJ11 VCC_2 VCC_82 AG21 BC24 VSS_4 VSS_184 AF1
B 5C 5 AJ10 VCC_3 VCC_83 AG20 BC10 VSS_5 VSS_185 AD42
6 6 U27 LE82G31
AJ9 VCC_4 VCC_84 AG19 BC5 VSS_6 VSS_186 AD39
3 3 AJ8 VCC_5 VCC_85 AG18 BB7 VSS_7 VSS_187 AD37
4 B4 Heatsink AJ7 VCC_6 VCC_86 AG17 AY41 VSS_8 VSS_188 AD35
AJ6 VCC_7 VCC_87 AG15 AY4 VSS_9 VSS_189 AD33
G31 AJ5 AG14 AW43 AD25
Heatsink VCC_8 VCC_88 VSS_10 VSS_190
AJ4 VCC_9 VCC_89 AF26 AW41 VSS_11 VSS_191 AD23
AJ3 VCC_10 VCC_90 AF25 AW1 VSS_12 VSS_192 AD21
CLIP1N @G31 AJ2 AF24 AV37 AD19
CLIP2S CLIP4S VCC_11 VCC_91 VSS_13 VSS_193
1 AH4 VCC_12 AV35 VSS_14 VSS_194 AC38
1 1 AH2 AF22 AV27 AC35
GND
POWER
VCC_13 VCC_93 VSS_15 VSS_195
2 AH1 VCC_14 VCC_94 AF20 AV23 VSS_16 VSS_196 AC24
2 2 U28 LE82946GZ AG13 AF18 AV21 AC22
Clip_2P VCC_15 VCC_95 VSS_17 VSS_197
AG12 VCC_16 VCC_96 AF17 AV17 VSS_18 VSS_198 AC20
D Clip_2P Clip_2P AG11 AF15 AV11 AC10 D
946GZ VCC_17 VCC_97 VSS_19 VSS_199
This is for ICH7 heatsink hook. For GMCH heatsink hook AG10 VCC_18 VCC_98 AF14 AV9 VSS_20 VSS_200 AC7
AG9 VCC_19 VCC_99 AE27 AV7 VSS_21 VSS_201 AC5
CLIP3N AG8 AE26 AU42 AB43
@946 VCC_20 VCC_100 VSS_22 VSS_202
1 AG7 VCC_21 VCC_101 AE25 AU38 VSS_23 VSS_203 AB25
AG6 VCC_22 VCC_102 AE23 AU32 VSS_24 VSS_204 AB23
2 AG5 VCC_23 VCC_103 AE21 AU24 VSS_25 VSS_205 AB21
AG4 VCC_24 VCC_104 AE19 AU20 VSS_26 VSS_206 AB19
Clip_2P AG3 AE17 AU6 AB2
AG2 VCC_26 VCC_106 AD27 AU2 VSS_28 VSS_208 AB1
AF13 VCC_27 VCC_107 AD26 AT31 VSS_29 VSS_209 AA38
AD24 VCC_30 VCC_110 AD15 AT13 VSS_32 VSS_212 AA22
AD22 VCC_31 VCC_111 AD14 AT12 VSS_33 VSS_213 AA20
1D25V_MCH AD20 AC27 AR38 AA8
AC25 VCC_80 VCC_113 AC26 AR33 VSS_35 VSS_215 AA5
AC23 VCC_34 VCC_114 AC17 AR32 VSS_36 VSS_216 Y42
L31 1D25V_MCHPCIE AC21 AC15 AR27 Y37
0 VCC_35 VCC_115 VSS_37 VSS_217
AC19 VCC_36 VCC_116 AC14 AR26 VSS_38 VSS_218 Y35
C258 C250 EC35 1D25V_MCH AC13 AB27 AR23 Y33
1
* 10uF
* 0.1uF
16V, Y5V, +80%/-20%
* 220uF
6.3V, +/-20%
AC6
AB24
VCC_38 VCC_118 AB26
AB18
AR21
AR20
VSS_40 VSS_220 Y25
Y23
10V, Y5V, +80%/-20%

10uF C327
AB22 AB17 AR17 Y21
2
1
*
Dummy
AB20
AA25
VCC_41
VCC_42
VCC_121
VCC_122
AA27
AA26
AR9
AR6
VSS_43
VSS_44
VSS_223
VSS_224
Y19
Y10
AA23 AA17 AP43 Y7
2
AA21 VCC_44 VCC_124 AA15 AP24 VSS_46 VSS_226 Y5
AA19 VCC_45 VCC_125 AA14 AP18 VSS_47 VSS_227 Y1
AA13 VCC_46 VCC_126 Y27 AP1 VSS_48 VSS_228 W3
1D25V_MCH AA3 Y26 AN38 V43
Y24 VCC_48 VCC_128 Y18 AN31 VSS_50 VSS_230 V39
Place in 1D25V_MCH_CL plane Y6 W27 AN20 V11
(less than 100 mils from the package) VCC_52 VCC_132 VSS_54 VSS_234
V13 VCC_53 VCC_133 W26 AN15 VSS_55 VSS_235 V8
V9 W21 AN11 U38
*
L22 270nH VCCA_HPLL VCC_56 VCC_136 VSS_58 VSS_238

U13 VCC_57 VCC_137 W19 AN4 VSS_59 VSS_239 U35
+/-20% C170 U10 W18 AM42 U8
1
* 2.2uF
6.3V, Y5V, +80%/-20%
U9
U6
VCC_59
VCC_60
VCC_139
VCC_140
W17
V27
AM40
AM36
VSS_61
VSS_62
VSS_241
VSS_242
U7
U5
U3 V26 AM33 T42
2

N12 VCC_62 VCC_142 V25 AM29 VSS_64 VSS_244 T1
N11 VCC_63 VCC_143 V24 AM24 VSS_65 VSS_245 R36
1D8V_STR Connect ground sides of caps with traces to GND balls N8 V22 AM20 R31
*
L27 2.2uH VCCA_MPLL (less than 100 mils from the package) VCC_65 VCC_145 VSS_67 VSS_247
C +/-20% N3 V20 AM9 R8 C
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%

R133 1 VCC_67 VCC_147 VSS_69 VSS_249
L6 VCC_68 VCC_148 V19 AM7 VSS_70 VSS_250 R5
+/-5% J6 V18 AM4 R3
C301
C300
C297 J3 V17 AM2 P43

1
C157
* * * J2 VCC_71 VCC_151 V15 AM1 VSS_73 VSS_253 P30
1
R130 1
* 10uF G2 VCC_72 VCC_152 V14 AL36 VSS_74 VSS_254 P21
2.2uF
2.2uF
2.2uF
+/-5% 10V, Y5V, +80%/-20% F11 U26 AL33 P18

2

F9 U25 AK43 P17
2

D4 VCC_75 VCC_155 U24 AJ39 VSS_77 VSS_257 P2
1D25V_MCH C13 U23 AJ36 N36
C9 U22 AJ33 N33
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%

C307
C425
C296
1D25V_MCH P20 U21 AH42 N31

1
* * * VCC_159
VCC_160
U20
U19
AG37
AG34
VSS_81
VSS_82
VSS_261
VSS_262
N27
N21
2.2uF
2.2uF
2.2uF
L0805 1uH Y11 U18 AF43 N13

2
L23 1 R137 1 VCCA_EXPPLL GMCH Memory Decoupling VCC_CL_PLL VCC_79 VCC_161 VSS_83 VSS_263
2 Y32 VCC_CL_PLL VCC_162 U17 AF37 VSS_84 VSS_264 N10
+/-10% +/-5% C172 C180 VCCA_EXPPLL B15 U15 AF36 N7
VCCA_EXPPLL VCC_163 VSS_85 VSS_265
1
R138 1 * 10uF
10V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20% * Dummy VCCA_HPLL C23
V31
VCCA_HPLL
RESERVED_002
VCC_164
VCC_165
U14
R20
AF10
AF9
VSS_86
VSS_87
VSS_266
VSS_267
N5
M42
+/-5% VCCA_MPLL A24 R18 AF8 M37
2
VCCA_DPLLA VCCA_MPLL VCC_166 VSS_88 VSS_268

A22 VCCA_DPLLA VCC_167 R17 AF7 VSS_89 VSS_269 M35
3D3V_SYS VCCA_DPLLB C22 R15 AF6 M33
VCCA_DPLLB VCC_168 VSS_90 VSS_270
VCC_169 R14 M27 VSS_91 VSS_271 BC41
1D25V_MCH P15 M21 BC3
VCC_170 VSS_92 VSS_272
B17 VCC3_3 VCC_171 P14 M17 VSS_93 VSS_273 BA1
L0805 10uH FSB_VTT 1D25V_MCH M15 AY40
L20 1 VCCA_DPLLA VSS_94 VSS_274
2 M10 VSS_95 VSS_275 AF23
+/-20% EC29 C186 C182 P29 AL26 M7 AF21
VTT_1 VCC_CL_1 VSS_96 VSS_276
* 220uF
* 0.1uF
* 0.1uF P27 AL24 M1 AF19
10V, Y5V, +80%/-20%

10uF C265
6.3V, +/-20% 16V, Y5V, +80%/-20% C143 16V, Y5V, +80%/-20% P26 AL23 L33 AE24
1
10uF
10V, Y5V, +80%/-20% * * P24
P23
VTT_4
VTT_5
VCC_CL_4
VCC_CL_5
AL21
AL20
L32
L31
VSS_99
VSS_100
VSS_279
VSS_280
AE22
AE20
L19 L0805 10uH Dummy N29 AL18 L29 AE18
2
VCCA_DPLLB VTT_6 VCC_CL_6 VSS_101 VSS_281

1 2 N26 VTT_7 VCC_CL_7 AL17 L21 VSS_102 VSS_282 AC18
EC30 C183 N24 AL15 L20 AA18
+/-20% * 220uF
6.3V, +/-20% * 0.1uF
16V, Y5V, +80%/-20%
N23
M29
VTT_9 VCC_CL_9 AK30
AK29
L11
L7
VSS_104 VSS_284 W24
W22
M24 VTT_11 VCC_CL_11 AK27 L5 VSS_106 VSS_286 W20
Place in the PCI-E power plane M23 AJ31 L3 R21
1D8V_STR (less than 100 mils from the package) VTT_12 VCC_CL_12 VSS_107 VSS_287
L24 VTT_13 VCC_CL_13 AG31 K43 VSS_108 VSS_288 E1
Intel DG: 220uF L23 AF31 K26 C43
K24 VTT_15 VCC_CL_15 AD32 K21 VSS_110 VSS_290 C1
K23 VTT_16 VCC_CL_16 AC32 K18 VSS_111 VSS_291 A41
J24 VTT_17 VCC_CL_17 AA32 K13 VSS_112 VSS_292 A5
1D5V_CORE CP6 J23 AJ30 K12 A3
H24 VTT_19 VCC_CL_19 AJ29 K2 VSS_114
X_COPPER H23 AJ27 J38
FSB_VTT VTT_20 VCC_CL_20 VSS_115
G26 VTT_21 VCC_CL_21 AG30 J35 VSS_116
R148 Need to Check Change to Dummy G24 AG29 J32
*
L21 10 VCCDQ_CRT VTT_22 VCC_CL_22 VSS_117

G23 VTT_23 VCC_CL_23 AG27 J27 VSS_118
B +/-5% r0805h6 F26 AG26 J21 B
VTT_24 VCC_CL_24 VSS_119
2.2uF C159
2.2uF C147
2.2uF C158
1 F24 AF30 J9
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%

1
*R127
Dummy
0
*
C163
1uF
+/-5%
* * * F23
E29
VTT_26
VTT_27
VCC_CL_26
VCC_CL_27
AF29
AF27
J7
J5
VSS_121
VSS_122
+/-5% 10V, Y5V, +80%/-20% E27 AD30 H31
2
Reserved VTT_28 VCC_CL_28 VSS_123

E26 VTT_29 VCC_CL_29 AD29 H29 VSS_124
E23 VTT_30 VCC_CL_30 AC30 H21 VSS_125
Dummy D29 AC29 H20
Dummy VTT_31 VCC_CL_31 VSS_126
D28 VTT_32 VCC_CL_32 AL12 H17 VSS_127
D27 VTT_33 VCC_CL_33 AL11 H15 VSS_128
C30 VTT_34 VCC_CL_34 AL10 H13 VSS_129
Place in FSB_VTT plane as close to the GMCH as possible C29 AL9 G42
L0805 10uH (less than 100 mils from the package) VTT_35 VCC_CL_35 VSS_130
C27 VTT_36 VCC_CL_36 AL8 G38 VSS_131
L29 1 2 VCCD_CRT B30 AL7 G32
+/-20% VTT_37 VCC_CL_37 VSS_132
B29 VTT_38 VCC_CL_38 AL6 G21 VSS_133
C173 C171 B28 AL5 G13
* 4.7uF
6.3V, X5R, +/-10% * 0.1uF
16V, Y5V, +80%/-20%
B27
A30
VTT_40
VTT_41
VCC_CL_40
VCC_CL_41
AL4
AL3
G12
G11
VSS_135
VSS_136
Reserved A28 AL2 G9
R27 VTT_43 VCC_CL_43 AK26 G7 VSS_138
1D8V_STR R26 AK24 G1
R24 VTT_45 VCC_CL_45 AK23 F37 VSS_140
R23 VTT_46 VCC_CL_46 AK21 F35 VSS_141
BC39 VCCSM_1 VCC_CL_47 AK20 F27 VSS_142
3D3V_SYS BC26 AK15 F3
3D3V_SYS VCCSM_4 VCC_CL_50 VSS_145
BC22 VCCSM_5 VCC_CL_51 AK3 E43 VSS_146
Near the FB20 BC18 AK2 E32
VCCSM_6 VCC_CL_52 VSS_147
BC14 VCCSM_7 VCC_CL_53 AK1 E24 VSS_148
*
BB39 VCCSM_8 VCC_CL_54 AJ13 E21 VSS_149

FB13 +/-5% BB37 AD31 E20
C162 C382 VCCSM_9 VCC_CL_55 VSS_150
FB 600 Ohm 1 BB32 VCCSM_10 VCC_CL_56 AC31 E15 VSS_151
* 0.1uF
16V, X7R, +/-10% * 10nF
25V, X7R, +/-10% VCCA_EXP VCCA_DAC
BB28
BB26
VCCSM_11
VCCSM_12
VCC_CL_57
VCC_CL_58
AA31
Y31
E13
E11
VSS_152
VSS_153
Dummy BB24 AJ26 E9
R147 BB20 VCCSM_14 VCC_CL_60 AJ24 E3 VSS_155
1uF C179
C181 BB18 AJ23 D40

1
* * 0.1uF
16V, Y5V, +80%/-20%
BB16
BB12
VCCSM_16
VCCSM_17
VCC_CL_62
VCC_CL_63
AJ21
AJ20
D31
D21
VSS_157
VSS_158
Modify by Steven 051707 AY32 AJ18 D17
10V, Y5V, +80%/-20%
2
Near the NB VCCSM_18 VCC_CL_64 VSS_159

AW24 VCCSM_19 VCC_CL_65 AJ17 D3 VSS_160
Modify by Steven 051707 AW20 AJ15 C26
AV26 VCCSM_21 VCC_CL_67 AJ14 C11 VSS_162
AV18 VCCSM_22 VCC_CL_68 AA30 C6 VSS_163
1D25V_MCHPCIE AD11 AA29 C5
VCC_EXP_1 VCC_CL_69 VSS_164
AD10 VCC_EXP_2 VCC_CL_70 Y30 C4 VSS_165
AD9 VCC_EXP_3 VCC_CL_71 Y29 B37 VSS_166
AD8 V30 1D8V_STR B32
AD7 VCC_EXP_5 VCC_CL_73 V29 B31 VSS_168
A AD6 U29 B26 A
AD5 VCC_EXP_7 VCC_CL_75 U27 B23 VSS_170
2
AD4 AL13 L32 B22

AD2 VCC_EXP_9 VCC_CL_77 AK14 L0805 1uH B19 VSS_172
AD1 VCC_EXP_10 VCC_CL_78 AL29 B14 VSS_173
AC4 VCC_EXP_11 VCC_CL_79 AL27 B10 VSS_174
1D25V_MCH 1D25V_MCH 1D25V_MCH +/-10%
AC3 VCC_EXP_12 A39 VSS_175
AC2 A34
1
VCC_EXP_13 VSS_176
AE4 VCC_EXP_14 VCC_SMCLK_1 BB41 A26 VSS_177
C127 AE3 BA42 A18
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
VCC_EXP_15 VCC_SMCLK_2 VSS_178

10uF C122
10uF C276
10uF C117
10uFC129
1uF C193
1uF C220
1uF C212
1uF C206
10uF
* C130 C123 AE2 AY42 C288 A12
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
VCC_EXP_16 VCC_SMCLK_3 VSS_179

1
10V, Y5V, +80%/-20%

* *
Dummy * * * 10uF
10V, Y5V, +80%/-20% * * * * * 10uF
10V, Y5V, +80%/-20%
VCCA_DAC C17
B16
VCCA_DAC_17
VCCA_DAC_18
VCC_SMCLK_4
VCC_SMCLK_5
BB42
BA43
* 0.1uF
16V, Y5V, +80%/-20%
R222
1
R225
1
A7 VSS_180 7 OF 7
Dummy Dummy VCCA_EXP A16
2
VCCD_CRT VCCA_EXP
C21 VCCD_CRT
VCCDQ_CRT +/-5% +/-5% LE82G31 bga1226_1h25
B21 AL31
Dummy D16
VCCDQ_CRT
VSS_1
RESERVED_1
RESERVED_2 AJ32 FOXCONN PCEG
1
Dummy
Don't use 1.8, use 1.5v.
6 OF 7 * C310
10uF #U27#U28 Title
BearLake-GMCH-3
2
Dummy Dummy Place in 1D25V_MCH plane as close to GMCH as possible 10V, Y5V, +80%/-20%
LE82G31 bga1226_1h25 Size Document Number Rev
Custom G31M05 A
#U27#U28 Date: Tuesday, January 08, 2008 Sheet 18 of 39

5 4 3 2 1
5 4 3 2 1
VTT_DDR M_ODT_A[1..0] 17,20
D M_SCKE_A[1..0] 17,20 D
M_BS_A[2..0] 17,20
R297 33 +/-5% M_MAA_A2
M_MAA_A[14..0] 17,20
R294 33 +/-5% M_MAA_A13
RN32
*1 2 M_RAS_AJ
M_WE_AJ
17,20
17,20
VTT_DDR
3 4 Need to Check Change to Dummy Need to Check Change to Dummy

5 6 M_CAS_AJ 17,20 1D8V_STR
7 8
33
C413
C353
C358
C357
C361
+/-5%
C437
C377
C354
C356
C374
C438
C435
RN28
*1 2
M_MAA_A14
M_BS_A2 * * * * *
3 4
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
5
7
6
8
M_MAA_A12
M_MAA_A11 * * * * * * *
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
33
+/-5%
VTT_DDR
C C
RN29
*1 2
M_MAA_A9
M_MAA_A7 Reserved Reserved
3 4 M_MAA_A8
5 6 M_MAA_A5 Reserved Reserved
7 8
33
+/-5%
Channel A VTT_0.9V high-frequency decoupling caps.
RN30
Place as close to termination resistors as possible
*1 2
M_MAA_A6
M_MAA_A4
3 4 M_MAA_A3
5 6 M_MAA_A1
7 8 VTT_DDR
33
+/-5%
RN31
*1 2
M_MAA_A0
M_BS_A1
3 4 M_MAA_A10
5 6 M_BS_A0
7 8
33
+/-5% C429 C365
1
B * 4.7uF
* 4.7uF
6.3V, X5R, +/-10% Dummy
6.3V, X5R, +/-10%
B
VTT_DDR
2
R295 43 Ohm
R296 43 Ohm M_SCKE_A1
M_SCKE_A0
VTT_DDR
Channel A VTT_0.9V Mid Range decoupling caps.
R298
R300
43 Ohm
43 Ohm
Placed in termination Island
M_SCS_A0J 17,20
R299 43 Ohm
M_ODT_A0 17,20
M_SCS_A1J 17,20
R293 43 Ohm
M_ODT_A1 17,20
A A
FOXCONN PCEG
Title
DDR2 Channel A Termination
Custom G31M05 A

5 4 3 2 1
5 4 3 2 1
DIMM1
3D3V_SPD
2 VSS NC_1 68 3D3V_SYS
5 102 1D8V_STR
VSS NC/TEST R310
8 19 M_ODT_A[1..0] 17,19
*
VSS NC_2
11 VSS
14 VSS
17 77 M_ODT_A1
VSS ODT1 M_ODT_A0 0 C161
20 VSS ODT0 195
+/-5%
23
26
VSS
VSS
* 100pF
50V, NPO, +/-5% * C408
0.1uF * C412
0.1uF
29 VSS
32 42 For EMI
VSS CB<0> Dummy
35 VSS CB<1> 43
38 VSS CB<2> 48
41 49 16V, Y5V, +80%/-20%
VSS CB<3> 16V, Y5V, +80%/-20%
D
44 VSS CB<4> 161 D
1D8V_STR 47 162
VSS CB<5>
50 VSS CB<6> 167
65 VSS CB<7> 168
66 VSS
79 VSS
EC38 EC40 82 VSS
* 1000uF
+/-20%
* 1000uF
+/-20%
85
88
VSS M_DQS_AJ[7..0] 17
1D8V_STR
VSS M_DQS_A0
91 VSS DQS<0> 7
94 VSS DQS#<0> 6
97 M_DQS_AJ0
VSS M_DQS_A1
100 VSS DQS<1> 16
103 VSS DQS#<1> 15
M_DQS_AJ1
Place between Ch A DIMM II
and Ch B DIMM 1
106
109
VSS
VSS DQS<2> 28 M_DQS_A2 *R302
1K
112 27 +/-1%
VSS DQS#<2> M_DQS_AJ2 r0402h4
115 VSS
118 37 M_DQS_A3
VSS DQS<3>
121 VSS DQS#<3> 36
124 M_DQS_AJ3 SMVREF_A
VSS M_DQS_A4 SMVREF_A 22
127 VSS DQS<4> 84
130 VSS DQS#<4> 83
M_DQS_AJ4
133
136
VSS
VSS DQS<5> 93 M_DQS_A5 *R301
1K
*
C369
0.1uF *
C363
0.1uF
139 92 +/-1% 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%
VSS DQS#<5> M_DQS_AJ5 r0402h4
142 VSS
145 105 M_DQS_A6
VSS DQS<6> Dummy
148 VSS DQS#<6> 104
151 M_DQS_AJ6
VSS M_DQS_A7
154 VSS DQS<7> 114
157 VSS DQS#<7> 113
160 M_DQS_AJ7
VSS M_DQS_A[7..0] 17 close to DIMM pin
163 VSS DQS<8> 46
166 45 Width 10 mils minimum, Spacing 10 mils minimum.
VSS DQS#<8>
169 VSS
198 125 M_DQM_A0
VSS DM0/DQS9
201 VSS NC/DQS9# 126
C 204 VSS
C
1D8V_STR 207 134 M_DQM_A1
VSS DM1/DQS10
210 VSS NC/DQS10# 135
213 VSS
216 146 M_DQM_A2
VSS DM2/DQS11
219 VSS NC/DQS11# 147
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603
222 VSS
225 155 M_DQM_A3
VSS DM3/DQS12 1D8V_STR
C386
C339
C338
C340
C424
228 VSS NC/DQS12# 156

231 VSS
234 202 M_DQM_A4
VSS DM4/DQS13
* * * * *
Dummy
1D8V_STR 237
51
VSS
VDDQ
NC/DQS13# 203
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
56 211 M_DQM_A5
VDDQ DM5/DQS14
1uF
1uF
1uF
1uF
1uF
62 VDDQ NC/DQS14# 212
C375
C419
C427
C139
C389
72 VDDQ
75 223 M_DQM_A6
VDDQ DM6/DQS15
191
194
VDDQ
VDDQ DM7/DQS16 232 M_DQM_A7 * * * * *
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
175 VDDQ M_DQM_A[7..0] 17
170 VDDQ DM8/DQS17 164
53 VDD NC/DQS17# 165
59 VDD M_DATA_A[63..0] 17
64 3 M_DATA_A0
VDD DQ<0> M_DATA_A1
197 VDD DQ<1> 4
69 9 M_DATA_A2
Channel A DIMM 1 1.8V high-frequency decoupling caps. VDD DQ<2> M_DATA_A3
172 VDD DQ<3> 10
place as close to DIMM power pins as possible 187 122 M_DATA_A4
VDD DQ<4> M_DATA_A5
184 VDD DQ<5> 123
178 128 M_DATA_A6
VDD DQ<6> M_DATA_A7
189 VDD DQ<7> 129
67 12 M_DATA_A8 Channel A DIMM II 1.8V high-frequency decoupling caps.
VDD DQ<8> M_DATA_A9 place as close to DIMM power pins as possible
DQ<9> 13
21 M_DATA_A10
DQ<10> M_DATA_A11
18 RC1 DQ<11> 22
3D3V_SPD 55 131 M_DATA_A12
B RC0 DQ<12> M_DATA_A13 B
238 VDDSPD DQ<13> 132
SMVREF_A 1 140 M_DATA_A14
8,22,36 SMB_CLK_MAIN VREF DQ<14> M_DATA_A15
120 SCL DQ<15> 141
119 24 M_DATA_A16
8,22,36 SMB_DATA_MAIN SDA DQ<16> M_DATA_A17
DQ<17> 25
101 30 M_DATA_A18
SA2 DQ<18> M_DATA_A19
240 SA1 DQ<19> 31
239 143 M_DATA_A20
SA2 SA1 SA0 SA0 DQ<20> M_DATA_A21
DQ<21> 144
0 0 0 190 149 M_DATA_A22
17,19 M_BS_A[2..0] M_BS_A1 BA1 DQ<22> M_DATA_A23
71 BA0 DQ<23> 150
M_BS_A0 33 M_DATA_A24
DQ<24> M_DATA_A25
DQ<25> 34
17,19 M_SCKE_A[1..0] M_SCKE_A1 171 39 M_DATA_A26
M_SCKE_A0 CKE1 DQ<26> M_DATA_A27
52 CKE0 DQ<27> 40
152 M_DATA_A28
DQ<28> M_DATA_A29
DQ<29> 153
158 M_DATA_A30
DQ<30> M_DATA_A31
76 S1# DQ<31> 159
17,19 M_SCS_A1J 193 80 M_DATA_A32
17,19 M_SCS_A0J S0# DQ<32> M_DATA_A33
DQ<33> 81
221 86 M_DATA_A34
17 CK_M_200M_N_DDR2_A CK2#/RFU DQ<34> M_DATA_A35
220 CK2/RFU DQ<35> 87
17 CK_M_200M_P_DDR2_A 138 199 M_DATA_A36
17 CK_M_200M_N_DDR1_A CK1#/RFU DQ<36> M_DATA_A37
137 CK1/RFU DQ<37> 200
17 CK_M_200M_P_DDR1_A 186 205 M_DATA_A38
17 CK_M_200M_N_DDR0_A CK0# DQ<38> M_DATA_A39
185 CK0 DQ<39> 206
17 CK_M_200M_P_DDR0_A 89 M_DATA_A40
17,19 M_MAA_A[14..0] M_MAA_A0 DQ<40> M_DATA_A41
188 A0 DQ<41> 90
M_MAA_A1 183 95 M_DATA_A42
M_MAA_A2 A1 DQ<42> M_DATA_A43
63 A2 DQ<43> 96
61 A4 DQ<45> 209
180 A6 DQ<47> 215
179 A8 DQ<49> 99
A M_MAA_A9 177 107 M_DATA_A50 A
70 A10/AP DQ<51> 108
176 A12 DQ<53> 218
M_MAA_A13 196 226 M_DATA_A54
174 A14 DQ<55> 227
173 110 M_DATA_A56
17,19 M_BS_A[2..0] M_BS_A2 A15 DQ<56> M_DATA_A57
54 A16/BA2 DQ<57> 111
116 M_DATA_A58
DQ<58> M_DATA_A59
117
17,19 M_CAS_AJ 74 CAS#
DQ<59>
DQ<60> 229 M_DATA_A60
M_DATA_A61
FOXCONN PCEG
17,19 M_RAS_AJ 192 RAS# DQ<61> 230
73 235 M_DATA_A62 Title
17,19 M_WE_AJ WE# DQ<62> M_DATA_A63
DQ<63> 236 Index Page
DDR II
C G31M05 A

5 4 3 2 1
5 4 3 2 1
M_SCKE_B[1..0] 17,22
M_BS_B[2..0] 17,22
M_MAA_B[14..0] 17,22
M_ODT_B[1..0] 17,22
D D
VTT_DDR
VTT_DDR R334 33 +/-5% M_MAA_B2
R331 33 +/-5% M_MAA_B13
R336 43 Ohm
R335 43 Ohm M_SCKE_B1 RN34
M_SCKE_B0
*1 2 M_RAS_BJ 17,22
3 4 M_WE_BJ 17,22
5 6 M_CAS_BJ 17,22
7 8
33
+/-5%
VTT_DDR RN35
R329 43 Ohm
*1 2
M_BS_B2
M_MAA_B12
R330 43 Ohm 3 4 M_MAA_B14
M_SCS_B0J 17,22 5 6
R332 43 Ohm M_MAA_B11
M_ODT_B0 17,22 7 8
M_SCS_B1J 17,22
R333 43 Ohm 33
+/-5%
M_ODT_B1 17,22
C C
RN36
*1 2
M_MAA_B7
M_MAA_B9
3 4 M_MAA_B8
5 6 M_MAA_B6
7 8
33
+/-5%
RN37
*1 2
M_MAA_B5
M_MAA_B4
3 4 M_MAA_B3
5 6 M_MAA_B1
7 8
33
+/-5%
RN33
*1 2
M_MAA_B0
M_MAA_B10
3 4 M_BS_B1
5 6 M_BS_B0
7 8
33
+/-5%
B B
VTT_DDR Need to Check Change to Dummy

VTT_DDR Need to Check Change to Dummy 1D8V_STR
C434
C433
C376
C360
C436
C362
C432
C372
C355
C418
C359
C414
C411 C367
* * * * * * * * * * * *
1
* 4.7uF
* 4.7uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
6.3V, X5R, +/-10% 6.3V, X5R, +/-10%
2
VTT_DDR
A A
Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Channel B VTT_0.9V Mid Range decoupling caps. Channel B VTT_0.9V high-frequency decoupling caps.
Placed in termination Island Place as close to termination resistors as possible
FOXCONN PCEG
Title
Index Page
C G31M05 A

5 4 3 2 1
5 4 3 2 1
DIMM2
2 VSS NC_1 68
5 VSS NC/TEST 102
8 VSS NC_2 19 M_ODT_B[1..0] 17,21
11 VSS
14 VSS
17 77 M_ODT_B1
VSS ODT1 M_ODT_B0
20 VSS ODT0 195
23 VSS
26 VSS
29 VSS
32 VSS CB<0> 42
35 VSS CB<1> 43
38 VSS CB<2> 48
41 VSS CB<3> 49
44 VSS CB<4> 161
D
47 VSS CB<5> 162 D
50 VSS CB<6> 167
65 VSS CB<7> 168
66 VSS
79 VSS
82 VSS
85 VSS M_DQS_BJ[7..0] 17
88 VSS
91 7 M_DQS_B0
VSS DQS<0>
94 VSS DQS#<0> 6
97 M_DQS_BJ0
VSS M_DQS_B1
100 VSS DQS<1> 16
103 VSS DQS#<1> 15
106 M_DQS_BJ1
VSS M_DQS_B2
109 VSS DQS<2> 28
112 VSS DQS#<2> 27
115 M_DQS_BJ2
VSS M_DQS_B3
118 VSS DQS<3> 37
121 VSS DQS#<3> 36
124 M_DQS_BJ3
VSS M_DQS_B4
127 VSS DQS<4> 84
130 VSS DQS#<4> 83
133 M_DQS_BJ4
1D8V_STR VSS M_DQS_B5
136 VSS DQS<5> 93
139 VSS DQS#<5> 92
142 M_DQS_BJ5
VSS M_DQS_B6
145 VSS DQS<6> 105
148 VSS DQS#<6> 104
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603
151 M_DQS_BJ6
VSS M_DQS_B7
154 VSS DQS<7> 114
C426
C387
C341
157 VSS DQS#<7> 113

160 M_DQS_BJ7
VSS M_DQS_B[7..0] 17
163 VSS DQS<8> 46
* * * 166
169
VSS
VSS
DQS#<8> 45
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
198 125 M_DQM_B0

VSS DM0/DQS9
1uF
1uF
1uF
201 VSS NC/DQS9# 126

204 VSS
C 207 134 M_DQM_B1 1D8V_STR C
VSS DM1/DQS10
210 VSS NC/DQS10# 135
213 VSS
216 146 M_DQM_B2
VSS DM2/DQS11
219 VSS NC/DQS11# 147
222 C366 C381 C352 C150
VSS M_DQM_B3
225
228
VSS
VSS
DM3/DQS12
NC/DQS12#
155
156
* 0.1uF * 0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
* 0.1uF
16V, Y5V, +80%/-20%
* 0.1uF
16V, Y5V, +80%/-20%
231 VSS
234 202 M_DQM_B4
1D8V_STR VSS DM4/DQS13
237 VSS NC/DQS13# 203
Channel B DIMM1 1.8V high-frequency decoupling caps. 51
place as close to DIMM power pins as possible VDDQ M_DQM_B5
72 VDDQ
75 223 M_DQM_B6
VDDQ DM6/DQS15
191 VDDQ
194 232 M_DQM_B7
VDDQ DM7/DQS16
175 VDDQ M_DQM_B[7..0] 17
53 VDD NC/DQS17# 165
59 VDD M_DATA_B[63..0] 17
64 3 M_DATA_B0
VDD DQ<0> M_DATA_B1
197 VDD DQ<1> 4
69 9 M_DATA_B2
VDD DQ<2> M_DATA_B3
172 VDD DQ<3> 10
187 122 M_DATA_B4 1D8V_STR
VDD DQ<4> M_DATA_B5
184 VDD DQ<5> 123
178 128 M_DATA_B6
VDD DQ<6> M_DATA_B7
189 VDD DQ<7> 129
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603
67 12 M_DATA_B8
VDD DQ<8> M_DATA_B9
DQ<9> 13
C423
C421
C385
C380
21 M_DATA_B10
DQ<10> M_DATA_B11
18 RC1 DQ<11> 22
3D3V_SPD 55 131 M_DATA_B12
RC0 DQ<12> M_DATA_B13
B
238
1
VDDSPD
VREF
DQ<13>
DQ<14>
132
140 M_DATA_B14 *
Dummy * * *
Dummy
B
20 SMVREF_A
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%

120 141 M_DATA_B15
8,20,36 SMB_CLK_MAIN SCL DQ<15>
1uF
1uF
1uF
1uF
119 24 M_DATA_B16
8,20,36 SMB_DATA_MAIN SDA DQ<16> M_DATA_B17
DQ<17> 25
101 30 M_DATA_B18
SA2 DQ<18> M_DATA_B19
240 SA1 DQ<19> 31
239 143 M_DATA_B20
SA2 SA1 SA0 SA0 DQ<20> M_DATA_B21
DQ<21> 144
0 1 0 190 149 M_DATA_B22
17,21 M_BS_B[2..0] M_BS_B1 BA1 DQ<22> M_DATA_B23
71 BA0 DQ<23> 150
M_BS_B0 33 M_DATA_B24
DQ<24> M_DATA_B25
DQ<25> 34
17,21 M_SCKE_B[1..0] M_SCKE_B1 171 39 M_DATA_B26
M_SCKE_B0 CKE1 DQ<26> M_DATA_B27
52 CKE0 DQ<27> 40
152 M_DATA_B28
DQ<28> M_DATA_B29
DQ<29> 153
158 M_DATA_B30 Channel B DIMM II 1.8V high-frequency decoupling caps.
DQ<30> M_DATA_B31 place as close to DIMM power pins as possible
76 S1# DQ<31> 159
17,21 M_SCS_B1J 193 80 M_DATA_B32
17,21 M_SCS_B0J S0# DQ<32> M_DATA_B33
DQ<33> 81
221 86 M_DATA_B34
17 CK_M_200M_N_DDR2_B CK2#/RFU DQ<34> M_DATA_B35
220 CK2/RFU DQ<35> 87
17 CK_M_200M_P_DDR2_B 138 199 M_DATA_B36
17 CK_M_200M_N_DDR1_B CK1#/RFU DQ<36> M_DATA_B37
137 CK1/RFU DQ<37> 200
17 CK_M_200M_P_DDR1_B 186 205 M_DATA_B38
17 CK_M_200M_N_DDR0_B CK0# DQ<38> M_DATA_B39
185 CK0 DQ<39> 206
17 CK_M_200M_P_DDR0_B 89 M_DATA_B40
17,21 M_MAA_B[14..0] M_MAA_B0 DQ<40> M_DATA_B41
188 A0 DQ<41> 90
M_MAA_B1 183 95 M_DATA_B42
M_MAA_B2 A1 DQ<42> M_DATA_B43
63 A2 DQ<43> 96
61 A4 DQ<45> 209
180 A6 DQ<47> 215
179 A8 DQ<49> 99
A 70 A10/AP DQ<51> 108 A
176 A12 DQ<53> 218
M_MAA_B13 196 226 M_DATA_B54
174 A14 DQ<55> 227
173 110 M_DATA_B56
17,21 M_BS_B[2..0] M_BS_B2 A15 DQ<56> M_DATA_B57
54 A16/BA2 DQ<57> 111
116 M_DATA_B58
DQ<58> M_DATA_B59
DQ<59> 117
M_DATA_B60
17,21 M_CAS_BJ
17,21 M_RAS_BJ
74
192
CAS#
RAS#
DQ<60>
DQ<61>
229
230 M_DATA_B61 FOXCONN PCEG
73 235 M_DATA_B62
17,21 M_WE_BJ WE# DQ<62> M_DATA_B63 Title
DQ<63> 236
Index Page
DDR II Size Document Number Rev
C G31M05 A

5 4 3 2 1
5 4 3 2 1
D D
3D3V_SB 3D3V_SYS 12V_SYS 12V_SYS 3D3V_SYS 12V_SYS 12V_SYS 3D3V_SYS 3D3V_SB

12V_SYS
PCI-E1_16X C168 C95
1
* C230
* C109
* 0.1uF * 0.1uF
1
B1
B2
12V PRSNT1# A1
A2
* C188
0.1uF
0.1uF 0.1uF 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%
2
12V 12V 25V, X7R, +/-10% 25V, X7R, +/-10%
B3 A3
2
RSVD1 12V 25V, X7R, +/-10%
B4 GND GND A4
25,31,36 SMB_CLK_RESUME B5 SMCLK JTAG2 A5
25,31,36 SMB_DATA_RESUME B6 SMDAT JTAG3 A6
B7 GND JTAG4 A7
B8 3.3V JTAG5 A8
B9 JTAG1 3.3V A9
B10 3.3VAUX 3.3V A10
WAKEJ B11 A11 ICH_G_PLTRSTJ
25 WAKEJ WAKE# PWRGD ICH_G_PLTRSTJ 35
All AC Coupling caps. should be placed within 250 mils of the connector KEY 3D3V_SYS 12V_SYS
B12 RSVD2 GND A12
B13 A13 CK_PE_100M_P_16PORT
GND REFCLK+ CK_PE_100M_P_16PORT 8
EXP_TXP0_C B14 A14 CK_PE_100M_N_16PORT EC49 EC22
16 EXP_TXP0 CK_PE_100M_N_16PORT 8
*
HSOP0 REFCLK-
C174 0.1uF 16V, X7R, +/-10%
16 EXP_TXN0
EXP_TXN0_C B15 A15 * 1000uF * 470uF
*
C166 0.1uF 16V, X7R, +/-10% HSON0 GND +/-20% 16V, +/-20%
B16 GND HSIP0 A16 EXP_RXP0 16
SDVO_CTRLCLK B17 A17
16 SDVO_CTRLCLK PRSNT2_B17# HSIN0 EXP_RXN0 16
B18 GND GND A18
EXP_TXP1_C B19 A19

16 EXP_TXP1
*
C178 0.1uF 16V, X7R, +/-10% EXP_TXN1_C HSOP1 RSVD5

C
16 EXP_TXN1 B20 A20 C
*
C187 0.1uF 16V, X7R, +/-10% HSON1 GND
B22 GND HSIN1 A22 EXP_RXN1 16
EXP_TXP2_C B23 A23
16 EXP_TXP2
*
C194 0.1uF 16V, X7R, +/-10% EXP_TXN2_C HSOP2 GND

16 EXP_TXN2 B24 A24
*
C198 0.1uF 16V, X7R, +/-10% HSON2 GND
EXP_TXP3_C B27 A27
16 EXP_TXP3
*
C207 0.1uF 16V, X7R, +/-10% EXP_TXN3_C HSOP3 GND

16 EXP_TXN3 B28 A28
*
C211 0.1uF 16V, X7R, +/-10% HSON3 GND
B30 RSVD3 HSIN3 A30 EXP_RXN3 16
SDVO_CTRLDATA B31 A31
16 SDVO_CTRLDATA PRSNT2_B31# GND
B32 GND RSVD6 A32
16 EXP_TXP4 B33 A33

*
C218 0.1uF 16V, X7R, +/-10% HSOP4 RSVD7

16 EXP_TXN4 B34 A34
*
C221 0.1uF 16V, X7R, +/-10% HSON4 GND
16 EXP_TXP5 B37 A37
*
C224 0.1uF 16V, X7R, +/-10% HSOP5 GND

16 EXP_TXN5 B38 A38
*
C223 0.1uF 16V, X7R, +/-10% HSON5 GND
16 EXP_TXP6 B41 A41
*
C228 0.1uF 16V, X7R, +/-10% HSOP6 GND

16 EXP_TXN6 B42 A42
*
C227 0.1uF 16V, X7R, +/-10% HSON6 GND
16 EXP_TXP7 B45 A45
*
C235 0.1uF 16V, X7R, +/-10% HSOP7 GND

16 EXP_TXN7
* B46 HSON7 GND A46
C231 0.1uF 16V, X7R, +/-10% B47 A47
GND HSIP7 EXP_RXP7 16
16 GMCH_EXP_EN_HDR B48 PRSNT2_B48# HSIN7 A48 EXP_RXN7 16
B49 GND GND A49
16 EXP_TXP8 B50 A50

*
C242 0.1uF 16V, X7R, +/-10% HSOP8 RSVD8

16 EXP_TXN8 B51 A51
*
C249 0.1uF 16V, X7R, +/-10% HSON8 GND

16 EXP_TXP9 B54 A54
*
B
C257 0.1uF 16V, X7R, +/-10% HSOP9 GND B
16 EXP_TXN9 B55 A55
*
C259 0.1uF 16V, X7R, +/-10% HSON9 GND

16 EXP_TXP10 B58 A58
*
C271 0.1uF 16V, X7R, +/-10% HSOP10 GND

16 EXP_TXN10 B59 A59
*
C267 0.1uF 16V, X7R, +/-10% HSON10 GND

*
C278 0.1uF 16V, X7R, +/-10% HSOP11 GND

*
C274 0.1uF 16V, X7R, +/-10% HSON11 GND

*
C283 0.1uF 16V, X7R, +/-10% HSOP12 GND

*
C282 0.1uF 16V, X7R, +/-10% HSON12 GND

*
C293 0.1uF 16V, X7R, +/-10% HSOP13 GND

*
C290 0.1uF 16V, X7R, +/-10% HSON13 GND

*
C309 0.1uF 16V, X7R, +/-10% HSOP14 GND

*
C308 0.1uF 16V, X7R, +/-10% HSON14 GND

*
C316 0.1uF 16V, X7R, +/-10% HSOP15 GND

*
C315 0.1uF 16V, X7R, +/-10% HSON15 GND

B81 PRSNT2_B81# HSIN15 A81 EXP_RXN15 16
B82 RSVD4 GND A82
Slot-PCIE-16X
All AC Coupling caps. should be placed within 250 mils of the connector
A A
FOXCONN PCEG
Title
Index Page
C G31M05 A

5 4 3 2 1
5 4 3 2 1
D D
L43
L42
*
82nH@100MHz L0603 0.1uH
@G31 @946
L5 L2
RED 5V_SYS
16 RED
*
C517
5V_SYS 5V_SYS 82nH@100MHz L0603 0.1uH * 10pF
50V, NPO, +/-5%
#L42#L43 c0402h6
*
C38 R26 C24 C8 @G31
C59 C104
* 3.3pF * 150
* 22pF
* 10pF C518 F3
* 0.1uF
16V, Y5V, +80%/-20%
* 0.1uF
16V, Y5V, +80%/-20%
50V, NPO, +/-0.25pF+/ -1%
r0402h4
50V, NPO, +/-5% 50V, NPO, +/-5%
#C517#C518 * 6.8pF
+/-0.5pF
Fuse 1.5A
c0402h6
@946
Dummy L45
L44
*
82nH@100MHz L0603 0.1uH
@G31 @946
L6 L3
L_RED
EMI cap. for RGB layer change GREEN L_GREEN
16 GREEN
*
L_BLUE
C520
82nH@100MHz L0603 0.1uH
C39 R27 C25 C9 * 10pF
50V, NPO, +/-5% VGA
* 3.3pF * 150
#L44#L45 * 22pF
* 10pF c0402h6 VGA
50V, NPO, +/-0.25pF+/ -1% 50V, NPO, +/-5% 50V, NPO, +/-5% @G31 5V_DDCA_CLK 15 SCL GND 5
RGB routing r0402h4 #C520#C521 C521 5V_DDCA_DATA 10 GND
C
1. from GMCH to the first 150 ohm resistor: 7.5 mils(min. 6 mils spacing ) * 6.8pF
+/-0.5pF
14 VSYNC
9 NC
ID0 4 C
2. from the first 150 ohm res. to the second 150 ohm resistor: 4 mils c0402h6 13 HSYNC B 3
3. from the second 150 ohm resistor to connector: 4 mils @946 8 GND
L46 L47 12 SDA G 2
4. spacing minimum 6 mils, 30 mils spacing is recommended
*
7 GND
16V, Y5V, +80%/-20%

5. R,G,B should be length matched to 700 mils, max. length is 8400 mils 82nH@100MHz 11 ID1 R 1
6. R,G,B signals should be ground referenced @G31 L0603 0.1uH
@946
L1 * C3
0.1uF
6 GND
BLUE L7 CONN-VGA
16
17
16 BLUE
*
C522
82nH@100MHz L0603 0.1uH * 10pF
50V, NPO, +/-5%
C40 R28 C26 C6 c0402h6
* 3.3pF * 150
#L46#L47 * 22pF
* 10pF @G31
50V, NPO, +/-0.25pF+/ -1% 50V, NPO, +/-5% 50V, NPO, +/-5% C523
3D3V_SYS 5V_SYS r0402h4 #C522#C523
* 6.8pF
+/-0.5pF
c0402h6
@946
BAV99
RN3 D9
2
4
6
8
2.2K
+/-5% The 150 Ohm resistors near VGA connector and 1 2 3D3V_SYS
* 13
5
7
minimizing length to filter. The filters to VGA

connector maximum distance 800 mils. 3D3V_SYS
3
RED
BAV99
D10
3D3V_SYS
1 2 C55
VSYNC_S 3D3V_SYS
* 0.1uF
16V, Y5V, +80%/-20%
3
GREEN
HSYNC_S
B B
BAV99
D6
D11
BAV99
1 2 5V_SYS 1 2 3D3V_SYS
3
3
BLUE
Q4
*
DDCA_CLK 2N7002 R22 +/-1% 5V_DDCA_CLK

16 DDCA_CLK
100 Ohm
Q2
*
DDCA_DATA 2N7002 R10 +/-1%5V_DDCA_DATA

16 DDCA_DATA
100 Ohm
3
1 2 5V_SYS
D1
BAV99
3D3V_SYS
3D3V_SYS
16 VSYNC
VSYNC R29
+/-5% * 0
Reserved
VSYNC_S
C51
C43
* 10nF
3
*
C23
10pF 1 2 3D3V_SYS
* 0.1uF
16V, Y5V, +80%/-20%
25V, X7R, +/-10%
Dummy
50V, NPO, +/-5%
Dummy D7
BAV99
A A
C15,C26 Near by the connector
*
HSYNC R23 0 HSYNC_S

16 HSYNC
+/-5% Reserved
3
C7
* 10pF 1
50V, NPO, +/-5%
2 3D3V_SYS FOXCONN PCEG
Dummy D2 Title
BAV99
Index Page
C G31M05 A

5 4 3 2 1
5 4 3 2 1
GPIO[39:36,23:21,19,7:0]: default as inputs and should be

pulled up to Vcc3_3 if unused.
GPIO[31:29,15:8]: default as inputs and should be pulled up to
VccSus3_3 if unused.
double check unused GPIO

pins
SIO PME change to GPIO8

U1F
U1C
ICH7
ICH7
D 29,35 L_AD[3..0] Need to Checked D
DMI_TXN0 V26 DMI0RXN USBP0N F1 USBP0N AA5 LDRQ1*/GPIO23 GPIO0/BM_BUSY* AB18 ICH7_GPIO0
16 DMI_TXN0 USBN0 38
DMI_TXP0 V25 DMI0RXP USBP0P F2 USBP0P L_AD0 AA6 LAD0 GPIO6 AC21 ICH7_GPIO6
16 DMI_TXP0 USBP0 38
DMI_RXN0 C348 0.1uF 16V, X7R, +/-10% U28 DMI0TXN USBP1N G4 USBP1N L_AD1 AB5 LAD1 GPIO7 AC18 ICH7_GPIO7
** ** ** **
16 DMI_RXN0 USBN1 38
LPC
DMI_RXP0 C349 0.1uF 16V, X7R, +/-10% DMI_RXP0_ICHU27 DMI0TXP USBP1P G3 USBP1P L_AD2 AC4 LAD2 GPIO8 E21 L_PMEJ
16 DMI_RXP0 DMI_TXN1 USBP2N USBP1 38 L_AD3 ICH7_GPIO9 L_PMEJ 35
16 DMI_TXN1 Y26 DMI1RXN USBP2N H1 USBN2 38 Y6 LAD3 GPIO9 E20 P66DET 26
DMI_TXP1 Y25 DMI1RXP USBP2P H2 USBP2P AC3 LDRQ0* GPIO10 A20 ICH7_GPIO10
16 DMI_TXP1 USBP2 38 35 L_DRQ0J
DMI_RXN1 C351 0.1uF 16V, X7R, +/-10% W28 DMI1TXN USBP3N J4 USBP3N AB3 LFRAME* GPIO12 F19 LAN_PMEJ
16 DMI_RXN1 USBN3 38 29,35 L_FRAMEJ LAN_PMEJ 32
DMI
DMI_RXP1 C368 0.1uF 16V, X7R, +/-10% DMI_RXP1_ICHW27 DMI1TXP USBP3P J3 USBP3P GPIO13 E19 ICH7_GPIO13 1D8V_GPIO13 13
**
16 DMI_RXP1 DMI_TXN2 USBP4N USBP3 38 R289 33+/-5% r0402h4 ICH7_GPIO14
16 DMI_TXN2 AB26 DMI2RXN USBP4N K1 USBN4 28 33 ICH_BCLK U1 ACZ_BCLK GPIO14 R4 1D8V_GPIO14 13
DMI_TXP2 AB25 DMI2RXP USBP4P K2 USBP4P R284 33 +/-5% r0402h4 R5 ACZ_RST* GPIO15 E22 ICH7_GPIO15
16 DMI_TXP2 USBP4 28 33 ICH_RSTJ
AUDIO
DMI_RXN2 C379 0.1uF 16V, X7R, +/-10% USBP5N Need to Checked
16 DMI_RXN2 AA28 DMI2TXN USBP5N L4 USBN5 28 T2 ACZ_SDI_0 GPIO16/DPRSLPVR AC22
DMI_RXP2 C373 0.1uF 16V, X7R, +/-10% DMI_RXP2_ICH
AA27 DMI2TXP USBP5P L5 USBP5P T3 ACZ_SDI_1 GPIO18/STPPCI* AC20 ICH7_GPIO18
16 DMI_RXP2 DMI_TXN3 USBP6N USBP5 28
16 DMI_TXN3 AD25 DMI3RXN USBP6N M1 T1 ACZ_SDI_2 GPIO20/STPCPU* AF21
**
DMI_TXP3 USBP6P USBN6 32 33 ICH_SDIN2 R287 33 +/-5% r0402h4
16 DMI_TXP3 AD24 DMI3RXP USBP6P M2 T4 ACZ_SDOUT GPIO24 R3
*
DMI_RXN3 C390 0.1uF 16V, X7R, +/-10% USBP7N USBP6 32 33 ICH_SDOUT R286 33 +/-5% r0402h4
16 DMI_RXN3 AC28 DMI3TXN USBP7N N4 USBN7 32 33 ICH_SYNC R6 ACZ_SYNC GPIO25 D20 R269 1K
DMI_RXP3 C388 0.1uF 16V, X7R, +/-10% DMI_RXP3_ICH
AC27 DMI3TXP USBP7P N3 USBP7P AC1 CLK14 EL_RSVD/GPIO26 A21 +/-5% r0402h4 Reserved
16 DMI_RXP3 USBP7 32 8 CK_14M_ICH
USB
EL_STATE0/GPIO27 B21
EPROM
W1 EE_CS EL_STATE1/GPIO28 E23
F26 PERN_1 OC0* D3 W3 EE_DIN GPIO32/CLKRUN* AG18
F25 PERP_1 OC1* C4 Y2 EE_DOUT GPIO33/AZ_DOCK_EN* AC19 Board_ID0 29
E28 PETN_1 OC2* D5 ICH_BCLK Y1 EE_SHCLK GPIO34/AZ_DOCK_RST* U2 Board_ID1 29
USB_OCJ_FRONT 38
E27 PETP_1 OC3* D4 GPIO35 AD21
H26 PERN_2 OC4* E5 V3 LAN_CLK GPIO38 AD20 ICH7_GPIO38
32 HSI_N2_LAN Board_ID2 29Need to Checked
H25 PERP_2 OC5*/GPIO29 C3 C346 U3 LAN_RSTSYNC GPIO39 AE20 BIOS_WPJ
32 HSI_P2_LAN
*
HSO_N2
C333 0.1uF 16V, X7R, +/-10% G28 PETN_2 OC6*/GPIO30 A2
* 22pF R268 ICH_LAN_RSTJ C19 LAN_RST* CPUPWRGD_GPIO49 AG24
**
32 HSO_N2_LAN C335 0.1uF 16V, X7R, +/-10% HSO_P2 50V, NPO, +/-5% 10K +/-5% r0402h4 CPU_PWRG 14
32 HSO_P2_LAN G27 PETP_2 OC7*/GPIO31 B3 USB_OCJ_BACK 32 U5 LAN_RXD0
PERN_3 LAN_RXD1 THRM* ICH_THRM_UP
LAN
K26 R282 V4 AF20 ICH_THRM_UP 14,35
K25 PERP_3 T5 LAN_RXD2 VRMPWRGD AD22 ICH_VRMPWRGD_UP
MISC
J28 PETN_3 USBRBIAS D1 USBRBIAS_ICH U7 LAN_TXD0 MCH_SYNC* AH20 ICH_SYNCJ 16
PCI-EXPRESS
J27 PETP_3 USBRBIAS* D2 Dummy V6 LAN_TXD1 PWRBTN* C23 PWRBTNJ 35
M26 PERN_4 V7 LAN_TXD2 RI* A28 ICH_RIJ_PU
22.6 LPCPDJ ICH_RIJ_PU 37
M25 PERP_4 SUS_STAT* A27 LPCPDJ 29
L28 PETN_4 +/-1% ICH_RTCX1 AB1 RTCX1 SUSCLK C20 TP_SUSCLK VCCRTC
RTC
TP55
L27 PETP_4 CLK48 B2 CK_48M_ICH ICH_RTCX2 AB2 RTCX2 SYS_RST* A22
CK_48M_ICH 8 RTCRSTJ PLTRSTJ ICH_SYS_RSTJ 8,9,14
P26 PERN_5 26 RTCRSTJ AA3 RTCRST* PLTRST* C26 PLTRSTJ 16,29,35
P25 PERP_5 WAKE* F20 WAKEJ
USBRBIAS connection SMB_ALERT_PU INTRUDERJ WAKEJ 23 R306
C N28 PETN_5 B23 SMBALERT*/GPIO11 INTRUDER* Y5 C
N27 PETP_5 5 mils width, length no longer than 500 mils C22 SMBCLK PWROK AA4 390K
Trace tied together close to pins. 23,31,36 SMB_CLK_RESUME NB_RSMRSTJ PWRGD_3V 16,35 +/-5%
T25 PERN_6 23,31,36 SMB_DATA_RESUME B22 SMBDATA RSMRST* Y4
T24 PERP_6 SMALERT_ICH A26 LINKALERT* INTVRMEN W4 INTVRMEN
SMB
R28 PETN_6 SMLINK0 B25 SMLINK0 SPKR A19 SPKR
SPKR 9 check pull-up resistor
1D5V_PE_ICH R27 PETP_6 SMLINK1 A25 SMLINK1
SLP_S3* B24 SLP_S3J 35
R278 24.9 DMI_COMP_ICH C25 DMI_ZCOMP ICH_SPI_MOSI P5 SPI_MOSI SLP_S4* D23
+/-1% ICH_SPI_MISO SLP_S4J 13
D25 DMI_IRCOMP P2 SPI_MISO SLP_S5*
SPI
F22 TP66
ICH_SPI_CSJ P6 SPI_CS*
DMI compensation CK_PE_100M_N_ICH AE28 DMI_CLKN ICH_SPI_CLK R2 SPI_CLK TP0/BATLOW* C21 ICH_BATLOW_PU
5 mils width, 7 mils spacing 8 CK_PE_100M_N_ICH
CK_PE_100M_P_ICH AE27 DMI_CLKP 2 of 6 TP56 SPI_ARB P1 SPI_ARB TP1/DPRSTP* AF24 TP_ICH7_AF24
Place the resistor within 500 mils of ICH7 8 CK_PE_100M_P_ICH TP57
TP2/DPSLP* AH25 TP_ICH7_AH25
TP59
bga652h26_ich7 TP3 TP_ICH7_F21
1 ? 4 of 6 F21 TP58
bga652h26_ich7
1 ?
3D3V_SB
*
8,10,14 VRMPWRGD R344 0 Dummy ICH_VRMPWRGD_UP
+/-5% r0402h4
*R281
1uF C410
3D3V_SYS 1K
1
3D3V_SB *
Dummy
+/-5% Need Check??
RN26
10V, Y5V, +80%/-20%

2
*
1
3
* 2
4 SMALERT_ICH
R283
0
+/-5%
RN38 SMLINK0
5 6
ICH7_GPIO6
ICH_VRMPWRGD_UP
*
1
3
2
4
7 8 SMLINK1
35 RSMRSTJ
RSMRSTJ E
Q21
Dummy
C NB_RSMRSTJ
ICH_THRM_UP 10K MMBT3906

ICH7_GPIO7
5
7
6
8 +/-5% *R285
10K
Dummy
B
8p4r0603h7 +/-5%
10K
+/-5% 3D3V_SB
R280
RN27
*
*
B B
ICH7_GPIO0 R338 10K +/-5% 1
3
* 2 L_PMEJ
4 ICH7_GPIO15
3D3V_SB
5 6 SMB_ALERT_PU 4.7K
1
7 8 ICH_BATLOW_PU VCCRTC
+/-5%
10K Dummy 3
*
+/-5% INTRUDERJ R363 1M
8p4r0603h7 +/-5% r0402h4 D38
BAV99
A 2
3D3V_SB 3D3V_SB Dummy
RN21 D36
1* 2 ICH7_GPIO10
4 LAN_PMEJ
Dummy
Chassis Intruder Header 3
5 6 WAKEJ LS4148-F
7 8
C
INTR
INTRUDERJ 10K
1
2 +/-5% SPI_SOCKET_1 *R270
2.2K
*
8p4r0603h7 LPCPDJ R267 10K +/-5% +/-5%

Header_1X2 Use 3D3V_SYS or not r0402h4 Dummy
1 8
Dummy
Steven Sun Update 2007.03.28 CS VCC 3D3V_SYS
2 DO 7
HOLD
3 WP CLK 6
Use 3D3V_SYS or not

4 GND DIO 5 *R345
4.7K
+/-5%
3D3V_SB W25X80VDAIZ r0402h4
Dummy ICH7_GPIO18
C
ICH_RTCX2
*
7
5
3
1 *
R353 1K Q28
B Dummy
close to ICH7 Use 3D3V_SYS or not 10,14 VID_SELECT MMBT3904-7-F
ICH_RTCX1 RN16 r0402h4 +/-5%
10K Dummy
E
3D3V_SB
+/-5%
*
R309 10M
+/-5%
8
6
4
2
A A
X3 XTAL-32.768kHz X3_1 16V, Y5V, +80%/-20%
2 1 3D3V_SB C302 0.1uF *R213
10K
*
+/-5%
Need to Apply C383 C384 SPI_SOCKET Reserved
4
* 12pF
* 12pF 8 CS 1
ICH_SPI_CSJ r0402h4
*
50V, NPO, +/-5% 50V, NPO, +/-5% Crystal Retainer ICH_SPI_HOLDJ VCC SPI_MISO R216 47 ICH_SPI_MISO
7 DO 2
**
ICH_SPI_CLK R221 47 +/-5% r0402h4 SPI_CLK HOLD +/-5% r0402h4BIOS_WPJ

6 CLK WP 3
ICH_SPI_MOSI R201 47 +/-5% r0402h4 SPI_MOSI 5 DIO GND 4
This clip is for ICH7
32.768Khz Crystal clip. close to ICH7 within 100 mils Socket
FOXCONN PCEG
Assume Capastor CL value is 12.5 Title
SPI Population Options Index Page
C G31M05 A

5 4 3 2 1
5 4 3 2 1
U1B 1
SATA_1 3D3V_SYS
ICH7 SATA_TXP0 C454 10nF 25V, X7R, +/-10% SATA_TXP0_C 2
** **
SATA_TXN0 C455 10nF 25V, X7R, +/-10% SATA_TXN0_C 3 8
PIDE_D0 AB15 DD0 SATA0RXN AF3 SATA_RXN0 4
PIDE_D1 AE14 DD1 SATA0RXP AE3 SATA_RXP0 SATA_RXN0 C465 10nF 25V, X7R, +/-10% SATA_RXN0_C 5 9
PIDE_D2 AG13 DD2 SATA0TXN AG2 SATA_TXN0 SATA_RXP0 C466 10nF 25V, X7R, +/-10% SATA_RXP0_C 6
PIDE_D3 SATA0TXP SATA_TXP0
D
PIDE_D4
AF13
AD14
DD3
DD4 RSVD/SATA1RXN
AH2
AE5
7
*R365
8.2K *R364
4.7K D
PIDE_D5 AC13 DD5 RSVD/SATA1RXP AD5 CONN-SATA +/-5% +/-5%
PIDE_D6 AD12 DD6 RSVD/SATA1TXN AG4 r0402h4 r0402h4
PIDE_D7 AC12 DD7 RSVD/SATA1TXP AH4 SATA_2
PIDE_D8 AE12 DD8 SATA2RXN AF7 SATA_RXN2 1
PIDE_D9 SATA_RXP2 SATA_TXP2 SATA_TXP2_C
SATA
AF12 DD9 SATA2RXP AE7 C444 10nF 25V, X7R, +/-10% 2
** **
PIDE_D10 AB13 DD10 SATA2TXN AG6 SATA_TXN2 SATA_TXN2 C453 10nF 25V, X7R, +/-10% SATA_TXN2_C 3 8 PIDE
PIDE_D11 AC14 DD11 SATA2TXP AH6 SATA_TXP2 4 P_IDERSTJ 1 2
PIDE_D12 AF14 DD12 IDE RSVD/SATA3RXN AD9 SATA_RXN2 C458 10nF 25V, X7R, +/-10% SATA_RXN2_C 5 9 PIDE_D7 3 4 PIDE_D8
PIDE_D13 AH13 DD13 RSVD/SATA3RXP AE9 SATA_RXP2 C460 10nF 25V, X7R, +/-10% SATA_RXP2_C 6 PIDE_D6 5 6 PIDE_D9
PIDE_D14 AH14 DD14 RSVD/SATA3TXN AG8 7 PIDE_D5 7 8 PIDE_D10
PIDE_D15 AC15 DD15 RSVD/SATA3TXP AH8 PIDE_D4 9 10 PIDE_D11
SATACLKN AF1 CK_SATA_100M_N_ICH CONN-SATA PIDE_D3 11 12 PIDE_D12
CK_SATA_100M_N_ICH 8
PIDE_DAKJ AF16 DDACK* SATACLKP AE1 CK_SATA_100M_P_ICH PIDE_D2 13 14 PIDE_D13
CK_SATA_100M_P_ICH 8
PIDE_DREQ AE15 DDREQ PIDE_D1 15 16 PIDE_D14
PIDE_IORJ AF15 DIOR* PIDE_D0 17 18 PIDE_D15
PIDE_IOWJ AH15 DIOW* SATARBIASN AH10 SATARBIAS_ICH R337 24.9 19 X
PIDE_RDY AG16 IORDY AG10 SATARBIAS connection PIDE_DREQ 21 22
SATARBIASP SATA_LED PIDE_IOWJ Cable detection
SATALED* AF18 5 mils width, length no longer than 500 mils 23 24
PIDE_A0 AH17 DA0 PIDE_IORJ 25 26 high: 40-conductor cable(ATA 33)
PIDE_A1 R349 10K
Trace tied together close to pins. PIDE_RDY low: 80-conductor cable(ATA 66/100)
AE17 DA1 GPIO21/SATA0GP AF19 3D3V_SYS 27 28
*
PIDE_A2 AF17 DA2 GPIO19/SATA1GP AH18 +/-5% r0402h4 PIDE_DAKJ 29 30
GPIO36/SATA2GP AH19 IRQ14 31 32
PIDE_CS1J AE16 DCS1* GPIO37/SATA3GP AE19 PIDE_A1 33 34
PIDE_CS3J PIDE_A0 PIDE_A2 P66DET 25
AD16 DCS3* 35 36
A20GATE AE22 A20GATE 35
PIDE_CS1J 37 38 PIDE_CS3J ?
A20M* AH28 A20MJ 14
PIDE_LED 39 40
IRQ14 AH16 IDEIRQ CPUSLP* AG27 TESTHI_13 14
IGNNE*
INIT3_3V*
AG22
AG21
IGNNEJ 14 Header_2X20_20
*R367
10K
HOST
INIT* AF22 +/-5%

INITJ 14
INTR AF25 HDD1 r0402h4
INTR 14
FERR* AG26 FERRJ
FERRJ 14
NMI AH24 NMI 14
RCIN* AG23 KBRSTJ 35
SERIRQ AH21 SERIRQ 29,35
SMI* AF23 SMIJ 14
C STPCLK* AH22 STPCLKJ 14 C
3 of 6 THERMTRIP* AF26 THERMTRIPJ
THERMTRIPJ 14
IDE data lines should be matched to strobes(IORJ, RDY)within +/- 250 mils,
strobes should be matched to their complement within +/- 10 mils
1
bga652h26_ich7 ?
Reserved
*
R373 33 P_IDERSTJ
35 IDE_RSTJ +/-5% r0402h4
C463
3D3V_SB
placed near IDE connector
* 0.1uF
16V, Y5V, +80%/-20%
VCCRTC Dummy
FSB_VTT D35
1 width 20 mils
3
VBAT 2
3D3V_SYS
*
R315 62 THERMTRIPJ
B
+/-5% r0402h4 BAT54C *R376
20K
B
+/-1%
C289
*R362 *R357
*
FERRJ
R316
+/-5%
62
r0402h4
R217
1K * 1uF
10V, Y5V, +80%/-20%
10K
+/-5%
10K
+/-5%
+/-1% VCCRTC_PWR r0402h4 r0402h4
C471
1
C399
Place at ICH7 end of route
* 1uF
10V, Y5V, +80%/-20% PIDE_LED
+
* 1uF BAT1
2 1
D45
10V, Y5V, +80%/-20% 3

Dummy Battery Holder HDD_LEDJ 9
2
-
SATA_LED
CLR_CMOS CLR_CMOS(2-3) BAT54A
1 1
25 RTCRSTJ 2 2
VCCRTC_PWR 3 3
Header_1X3 Jumper_2P_Blu
BAT1_1
LITHIUM BATT
CR2032
Battery
Clear CMOS
For battery cell.
CLR_CMOS CMOS
A Clear (1-2) A
Normal (2-3) Default
FOXCONN PCEG
Title
Index Page
C G31M05 A

5 4 3 2 1
5 4 3 2 1
U1E
ICH7
U1D E4 VSS VSS A4
U1A ICH7 1D5V_CORE
AG11 VSS VSS A23
C27 VSS VSS B1
ICH7 1D5V_CORE REF5V R14 VSS VSS B8
AD[31..0] R15 VSS VSS B11
AD[31..0] 31
A1 VCC1_5_A R16 VSS VSS B14
31 PAR PAR E10 PAR AD0 E18 AD0 AB10 VCC1_5_A V5REF AD17 R17 VSS VSS B17
31 DEVSELJ DEVSELJ A12 DEVSEL* AD1 C18 AD1 AB17 VCC1_5_A V5REF G10 R18 VSS VSS B20
1
8 CK_33M_ICH A9 PCICLK AD2 A16 AD2 AB7 VCC1_5_A REF5V_SUS T6 VSS VSS B26
B18 PCIRST* AD3 F18 AD3 AB8 VCC1_5_A V5REF_SUS F6 VCCRTC L35 T12 VSS VSS B28
31 PCIRSTJ
31 IRDYJ IRDYJ A7 IRDY* AD4 E16 AD4 AB9 VCC1_5_A L0805 10uH T13 VSS VSS C2
PMEJ B19 PME* AD5 A18 AD5 AC10 VCC1_5_A VCCRTC W5 1D5V_CORE T14 VSS VSS C6
31
31
PMEJ
SERRJ SERRJ
STOPJ
B10
F15
SERR*
STOP*
PCI AD6
AD7
E17
A17
AD6
AD7
AC17
AC6
VCC1_5_A
VCC1_5_A VCCUSBPLL C1
+/-20% T15
T16
VSS
VSS
VSS
VSS
D10
D13
31 STOPJ
2
31 LOCKJ LOCKJ E11 PLOCK* AD8 A15 AD8 3D3V_SYS AC7 VCC1_5_A T17 VSS VSS D18
31 TRDYJ TRDYJ F14 TRDY* AD9 C14 AD9 AC8 VCC1_5_A VCCSATAPLL AD2 U4 VSS VSS D21
D 31 PERRJ PERRJ C9 PERR* AD10 E14 AD10 AD10 VCC1_5_A U12 VSS VSS D24 D
31 FRAMEJ FRAMEJ F16 FRAME* AD11 D14 AD11 C324 AD6 VCC1_5_A VCCDMIPLL AG28 VCCDMIPLL 1D05V_SYS C400 C395 U13 VSS VSS E1
1
AD12
31 GNT0J E7 GNT0* AD13
B12
C13
AD12
AD13 *
Dummy
0.1uF AE10
AE6
VCC1_5_A
VCC1_5_A VCC1_05 L11
* 10uF
10V, Y5V, +80%/-20% * 0.1uF Near AD2 U14
U15
VSS
VSS
VSS
VSS
E2
E8
D16 GNT1* AD14 G15 AD14 16V, Y5V, +80%/-20% AF10 VCC1_5_A VCC1_05 L12 16V, Y5V, +80%/-20% U16 VSS VSS E15
2
D17 GNT2* AD15 G13 AD15 AF5 VCC1_5_A VCC1_05 L14 U17 VSS VSS F3
F13 GNT3* AD16 E12 AD16 AF6 VCC1_5_A VCC1_05 L16 U24 VSS VSS F4
A14 GNT4*/GPIO48 AD17 C11 AD17 AF9 VCC1_5_A VCC1_05 L17 U25 VSS VSS F5
GNT5J D8 GNT5*/GPIO17 AD18 D11 AD18 AG5 VCC1_5_A VCC1_05 L18 U26 VSS VSS F12
AD19 A11 AD19 AG9 VCC1_5_A VCC1_05 M11 V2 VSS VSS F27
D7 REQ0* AD20 A10 AD20 AH5 VCC1_5_A VCC1_05 M18 V13 VSS VSS F28
31 PREQ0J
31 PREQ1J C16 REQ1* AD21 F11 AD21 AH9 VCC1_5_A VCC1_05 P11 V15 VSS VSS G1
31 PREQ2J C17 REQ2* AD22 F10 AD22 F17 VCC1_5_A VCC1_05 P18 V24 VSS VSS G5
31 PREQ3J E13 REQ3* AD23 E9 AD23 G17 VCC1_5_A VCC1_05 T11 V27 VSS VSS G2
31 PREQ4J A13 REQ4*/GPIO22 AD24 D9 AD24 H6 VCC1_5_A VCC1_05 T18 V28 VSS VSS G6
31 PREQ5J C8 GPIO1/REQ5* AD25 B9 AD25 H7 VCC1_5_A VCC1_05 U11 W6 VSS VSS G9
AD26 A8 AD26 J6 VCC1_5_A VCC1_05 U18 W24 VSS VSS G14
31 INTAJ A3 PIRQA* AD27 A6 AD27 J7 VCC1_5_A VCC1_05 V11 W25 VSS VSS G18
31 INTBJ B4 PIRQB* AD28 C7 AD28 1D5V_PE_ICH T7 VCC1_5_A VCC1_05 V12 W26 VSS VSS G21
31 INTCJ C5 PIRQC* AD29 B6 AD29 VCC1_05 V14 Y3 VSS VSS G24
31 INTDJ B5 PIRQD* AD30 E6 AD30 D26 VCC1_5_B VCC1_05 V16 Y24 VSS VSS G25
31 INTEJ G8 GPIO2/PIRQE* AD31 D6 AD31 D27 VCC1_5_B VCC1_05 V17 Y27 VSS VSS G26
31 INTFJ F7 GPIO3/PIRQF* D28 VCC1_5_B VCC1_05 V18 Y28 VSS VSS H3
31 INTGJ F8 GPIO4/PIRQG* C/BE0* B15 CBEJ0 E24 VCC1_5_B AA1 VSS VSS H4
CBEJ1 CBEJ0 31 FSB_VTT
31 INTHJ G7 GPIO5/PIRQH* C/BE1* C12 CBEJ1 31
E25 VCC1_5_B AA24 VSS VSS H5
C/BE2* D12 CBEJ2 E26 VCC1_5_B V_CPU_IO AE23 AA25 VSS VSS H24
1 of 6 C/BE3* C15 CBEJ3 CBEJ2 31
F23 VCC1_5_B V_CPU_IO AE26 AA26 VSS VSS H27
POWER
CBEJ3 31 3D3V_SYS
F24 VCC1_5_B V_CPU_IO AH26 AB4 VSS VSS H28
G22 VCC1_5_B AB6 VSS VSS J1
1
bga652h26_ich7 G23 VCC1_5_B VCC3_3 A5 AB11 VSS VSS J2
H22 VCC1_5_B VCC3_3 AA7 AB14 VSS VSS J5
GNT5J GNT4J BOOT H23 VCC1_5_B VCC3_3 AB12 AB16 VSS VSS J24
0 1 SPI J22 VCC1_5_B VCC3_3 AB20 AB19 VSS VSS J25
1 0 PCI J23 VCC1_5_B VCC3_3 AC16 AB21 VSS VSS J26
1 1 LPC 1D5V_CORE K22 VCC1_5_B VCC3_3 AD13 AB24 VSS VSS K24
VCCDMIPLL LRC Filter K23 VCC1_5_B VCC3_3 AD18 AB27 VSS VSS K27
L22 VCC1_5_B VCC3_3 AG12 AB28 VSS VSS K28
*
GNT5J R271 1K L23 VCC1_5_B VCC3_3 AG15 AC2 VSS VSS L13
+/-5% r0402h4 Reserved M22 VCC1_5_B VCC3_3 AG19 AC5 VSS VSS L15
L0805 1uH M23 VCC1_5_B VCC3_3 AH11 AC9 VSS VSS L24
L34 1 2 VCCDMIPLL N22 VCC1_5_B VCC3_3 B13 AC11 VSS VSS L25
+/-10% N23 VCC1_5_B VCC3_3 B16 AD1 VSS VSS L26
C405 C403 P22 VCC1_5_B VCC3_3 B27 AD3 VSS VSS M3
1
extra one 47uF(backside) in DG0.7
Rated at least 100mA
* 10uF
10V, Y5V, +80%/-20% * 10nF P23
R22
VCC1_5_B
VCC1_5_B
VCC3_3
VCC3_3
B7
C10
AD4
AD7
VSS
VSS
VSS
VSS
M4
M5
C Dummy 25V, X7R, +/-10% R23 VCC1_5_B VCC3_3 D15 AD8 VSS VSS M12 C
2
R24 VCC1_5_B VCC3_3 F9 AD11 VSS VSS M13
R25 VCC1_5_B VCC3_3 G11 AD15 VSS VSS M14
R26 VCC1_5_B VCC3_3 G12 AD19 VSS VSS M15
1D05V_SYS 1D5V_CORE T22 VCC1_5_B VCC3_3 G16 AD23 VSS VSS M16
1D5V_CORE T23 VCC1_5_B VCC3_3 U6 3D3V_SB AE2 VSS VSS M17
Place LRC near pin AG28 T26 VCC1_5_B VCCSUS3_3 A24 AE4 VSS VSS M24
T27 VCC1_5_B VCCSUS3_3 C24 AE8 VSS VSS M27
C256 C299 T28 VCC1_5_B VCCSUS3_3 D19 AE11 VSS VSS M28
C343 C344 0.1uF C298 0.1uF 1D5V_CORE U22 VCC1_5_B VCCSUS3_3 D22 AE13 VSS VSS N1
* 0.1uF
* 1uF
* * 0.1uF
* U23 VCC1_5_B VCCSUS3_3 E3 AE18 VSS VSS N2
10V, Y5V, +80%/-20%
Dummy V22 VCC1_5_B VCCSUS3_3 G19 AE21 VSS VSS N5

16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20% V23 VCC1_5_B VCCSUS3_3 K3 AE24 VSS VSS N6

Dummy Dummy VCC1_5_B LC Filter W22 VCC1_5_B VCCSUS3_3 K4 AE25 VSS VSS N11
W23 VCC1_5_B VCCSUS3_3 K5 AF2 VSS VSS N12
Y22 VCC1_5_B VCCSUS3_3 K6 AF4 VSS VSS N13
Near D28, T28,and AD28 Y23 VCC1_5_B VCCSUS3_3 L1 AF8 VSS VSS N14
*
L33 1D5V_PE_ICH AA22 VCC1_5_B VCCSUS3_3 L2 AF11 VSS VSS N15

L1206 0.47uH C394 C393 C378 AA23 VCC1_5_B VCCSUS3_3 L3 AF27 VSS VSS N16
EC43 0.1uF 0.1uF 0.1uF C392 AB22 VCC1_5_B VCCSUS3_3 L6 AF28 VSS VSS N17
1
ICH7 Core decoupling caps. * 100uF
16V, +/-20% Dummy * * * * 10uF AB23
AC23
VCC1_5_B
VCC1_5_B
VCCSUS3_3
VCCSUS3_3
L7
M6
AG1
AG3
VSS
VSS
VSS
VSS
N18
N24
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
Dummy AC24 VCC1_5_B VCCSUS3_3 M7 AG7 VSS VSS N25

2
AC25 VCC1_5_B VCCSUS3_3 N7 AG14 VSS VSS N26

AC26 VCC1_5_B VCCSUS3_3 P7 AG17 VSS VSS P12
AD26 VCC1_5_B VCCSUS3_3 R7 AG20 VSS VSS P13
AD27 VCC1_5_B VCCSUS3_3 V1 AG25 VSS VSS P14
AD28 VCC1_5_B VCCSUS3_3 V5 AH1 VSS VSS P15
VCCSUS3_3 W2 AH3 VSS VSS P3
1D5V_PE_ICH 3D3V_SYS VCCSUS3_3 W7 VSS P4
VSS P16
Place LC near pin D28 VCCSUS1_05 AA2 AH7 VSS VSS P17
C322 VCCSUS1_05 C28 AH23 VSS VSS P24
C331 0.1uF VCCSUS1_05 G20 AH27 VSS VSS P27
*
0.1uF
Reserved * 16V, Y5V, +80%/-20%
5 of 6
VCCSUS1_05
VCCSUS1_05
K7
Y7 AH12 VSS
VSS
VSS
P28
R1
5V_SB 3D3V_SB VSS R11
16V, Y5V, +80%/-20% VSS R12
bga652h26_ich7 VSS R13
1 ? 6 of 6
A
Place near B27 D39

* R279 Dummy bga652h26_ich7
10
Place near D28 LS4148-F REF5V_SUS 3D3V_SB
+/-1%
C
B PCI-E decoupling caps. C330 REF5V_SUS

B
0.1uF
* 16V, Y5V, +80%/-20%
C350
0.1uF
place cap. near pin F6 * 16V, Y5V, +80%/-20%

within 40 mils
1D5V_CORE 1D5V_CORE
V5REF_SUS / 3D3V_SB Power Sequencing
Place near V1
C332 C334
*
0.1uF
*
Dummy
10nF
Reserved 25V, X7R, +/-10% VCCRTC

16V, Y5V, +80%/-20% LAN decoupling caps. FSB_VTT FSB_VTT
double check in new CRB or DG
Place near A1 Place near C1 C398 C397 C467 C370
*
0.1uF
*
0.1uF
C416
*
0.1uF
*
Dummy
1uF
10V, Y5V, +80%/-20%
1
5V_SYS 3D3V_SYS
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%

3D3V_SB
Dummy * 4.7uF
6.3V, X5R, +/-10% Dummy
3D3V_SYS
2
A
D43
R327 1D5V_CORE 1D5V_CORE
3D3V_SB 1K
Need to Check Change to Dummy
+/-1% LS4148-F
C66
C
16V, Y5V, +80%/-20%
C345 C406 C420 0.1uF Place near W5

C342
0.1uF
*
0.1uF
*
C336
10nF REF5V
REF5V
* 0.1uF
* 1uF
10V, Y5V, +80%/-20% * Near AE23 and AE26 Place near AH26
* Reserved
Dummy
16V, Y5V, +80%/-20% 25V, X7R, +/-10%
C409
0.1uF
16V, Y5V, +80%/-20%
Dummy
Dummy 16V, Y5V, +80%/-20%
RTC decoupling caps.
* 16V, Y5V, +80%/-20%
CPU decoupling caps.
Place near AH5 Place near AH9 Place near U6
place cap. near pin AD17/G10
Near L1 and K3 within 40 mils
Place near E3
V5REF / 3D3V_SYS Power Sequencing Audio decoupling caps. 3D3V_SYS
3D3V_SYS 1D5V_CORE
A USB decoupling caps. A
3D3V_SYS 3D3V_SYS
C519
VCCDMIPLL C439 C407 0.1uF C323 C329 C328 C320
*
Dummy
0.1uF
* 0.1uF
* 16V, Y5V, +80%/-20%
*
0.1uF
*
0.1uF
*
0.1uF
*
0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% C415 Dummy Dummy Dummy
16V, Y5V, +80%/-20%

C402 0.1uF Please Bottom
* 10nF
* 16V, Y5V, +80%/-20%
near Pin AB12
within 40mil
25V, X7R, +/-10% Place near AH11 Place near AD2
Dummy
FOXCONN PCEG
Place near AG28
Place near AG15/AB12 Place near A5, B7, C10 Title
Index Page
DMI decoupling caps. SATA decoupling caps. PCI decoupling caps. Size Document Number Rev
IDE decoupling caps. Custom G31M05 A

5 4 3 2 1
5 4 3 2 1
D D
Rear Dual USB Connector
SVCC2
C C
C46
* 0.1uF
16V, Y5V, +80%/-20%

Reserved
L9 Dummy
1 4
2 3 USB USBN4 USBP4

Common Choke 90 Ohm_2L
3
1
**
USBN5 R37 0 V0
25 USBN5 2 -D0 1 2 SVCC2 1 2 SVCC2
USBP5 R36 +/-5%
0 3 5 6 7 8
25 USBP5 +/-5% +D0
4 G0 D15 D21
5 BAV99 BAV99
**
USBN4 R39 0 V1 1 2 3 4 Reserved Reserved

25 USBN4 6 -D1
B USBP4 0
+/-5% 7 USBP5 USBN5 B
25 USBP4 R38 +/-5% +D1
8
CG1
CG2
CG3
CG4
G1
3
1 2 SVCC2 1 2 SVCC2
L10 Dummy CONN-USBx2
9
10
11
12
1 4 Reserved
D20 D14
2 3 BAV99 BAV99
Reserved Reserved
Common Choke 90 Ohm_2L
A A
FOXCONN PCEG
Title
REAR USB
Custom G31M05 A

5 4 3 2 1
5 4 3 2 1
5V_SYS
3D3V_SYS
MH4 MH3 MH1 MH5 MH6 MH2
TPM Mounting Hole Mounting Hole Mounting Hole Mounting Hole Mounting Hole Mounting Hole
1 2 R90
8 CK_33M_TPM LCLK GND
6
5
6
5
6
5
6
5
6
5
6
5
D
* 0 D
25,35 L_FRAMEJ 3 LFRAMEn KEY +/-5% 7 4 7 4 7 4 7 4 7 4 7 4
8 3 8 3 8 3 8 3 8 3 8 3
5 6 @TPM 9 2 9 2 9 2 9 2 9 2 9 2
16,25,35 PLTRSTJ LRESETn NC_3
1
L_AD3 7 8 L_AD2
25,35 L_AD3 LAD3 LAD2 L_AD2 25,35 mh40x80_8 mh40x80_8 mh40x80_8 mh40x80_8 mh40x80_8 mh40x80_8
9 10 L_AD1
VDD LAD1 L_AD1 25,35
L_AD0 11 12
25,35 L_AD0 LAD0 GND R129
** r0402h4
*
3D3V_SYS @TPM R125 R141 13 NC_1 NC_4 14 1K @TPM 3D3V_SYS
3D3V_SB 1K@TPM+/-5%
r0402h4 15 16 3D3V_SYS
NC_2 SERIRQ SERIRQ 26,35
17 18 +/-5%
0 GND CLKRUNin
+/-5%
25 LPCPDJ 19 LPCPDn NC_5 20
*R351
1K *R290
1K *R350
1K
+/-5% +/-5% +/-5%
Header_2X10_4 (TPM) r0402h4 r0402h4 r0402h4
@TPM Reserved Reserved
Board_ID2 Board_ID2 25
Board_ID1 Board_ID1 25
Board_ID0
C Need check? Board_ID0 25 C
*R340
1K *R288
1K *R339
1K
+/-5% +/-5% +/-5%
r0402h4 r0402h4 r0402h4
Dummy Dummy Dummy
5V_SYS
T4 T2
1 1
2 2
B T1 T1 B
5V_SYS
T3 T1 FD1 FD2 FD3

1 1 FMARK FMARK FMARK
2 2 FD40 FD40 FD40
T1 T1
1
A A
FOXCONN PCEG
Title
FWH
Custom G31M05 A

5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
FOXCONN PCEG
Title
PCI Express x1 Slot
Custom G31M05 A

5 4 3 2 1
5 4 3 2 1
5V_SYS
3D3V_SYS 3D3V_SYS
-12V_SYS 5V_SYS 12V_SYS
Note: 20-24 mils PCI1

B1 -12V TRST# A1
B2 TCK +12V A2
B3 GND1 TMS A3
B4 TDO TDI A4
B5 +5V1 +5V2 A5
B6 A6 INTBJ INTBJ 27
INTCJ +5V3 INTA# INTDJ
27 INTCJ B7 INTB# INTC# A7 INTDJ 27
27 INTAJ INTAJ B8 A8
INTD# +5V4 3D3V_SB
D
B9 PRSNT1# RSV1 A9 D
B10 RSV2 +5V5 A10
B11 PRSNT2# RSV3 A11
B12 GND2 GND3 A12
B13 GND4 GND5 A13
B14 RSV4 SB3V A14
B15 GND6 RESET# A15 PCIRSTJ 27
8 CK_33M_PCI1 B16 CLK +5V6 A16
B17 GND7 GNT# A17 GNT0J 27
PREQ0J B18 A18
REQ# GND8
B19 +5V7 PCI_PME# A19 PMEJ 27
AD31 B20 A20 AD30
AD29 AD(31) AD(30)
B21 AD(29) +3.3V1 A21
B22 A22 AD28
AD27 GND9 AD(28) AD26
B23 AD(27) AD(26) A23
AD25 B24 A24
AD(25) GND10 AD24
B25 +3.3V2 AD(24) A25
CBEJ3 B26 A26 IDSEL0
27 CBEJ3 C/BE#(3) IDSEL
AD23 B27 A27
AD(23) +3.3V3 AD22
B28 GND11 AD(22) A28
AD21 B29 A29 AD20
AD19 AD(21) AD(20)
B30 AD(19) GND12 A30
B31 A31 AD18
AD17 +3.3V4 AD(18) AD16
B32 AD(17) AD(16) A32
B33 C/BE#(2) +3.3V5 A33
27 CBEJ2 B34 A34 FRAMEJ
GND13 FRAME# FRAMEJ 27
IRDYJ B35 A35
27 IRDYJ IRDY# GND14
B36 A36 TRDYJ
+3.3V6 TRDY# TRDYJ 27
DEVSELJ B37 A37
27 DEVSELJ DEVSEL# GND15
B38 A38 STOPJ
GND16 STOP# STOPJ 27
LOCKJ B39 A39
27 LOCKJ LOCK# +3.3V7
PERRJ B40 A40 PSCLK
27 PERRJ PERR# SDONE PSDATA
B41 +3.3V8 SBO# A41
SERRJ B42 A42
27 SERRJ SERR# GND17
B43 A43 PAR
+3.3V9 PAR PAR 27
CBEJ1 B44 A44 AD15
27 CBEJ1 AD14 C/BE#(1) AD(15)
B45 AD(14) +3.3V10 A45
B46 A46 AD13
AD12 GND18 AD(13) AD11
C B47 AD(12) AD(11) A47 C
AD10 B48 A48
AD(10) GND19 AD9
B49 GND20 AD(9) A49
AD8 B52 A52 CBEJ0

AD(8) C/BE#(0) CBEJ0 27
AD7 B53 A53
AD(7) +3.3V11 AD6
B54 +3.3V12 AD(6) A54
AD5 B55 A55 AD4
AD3 AD(5) AD(4)
B56 AD(3) GND21 A56
B57 A57 AD2
AD1 GND22 AD(2) AD0
B58 AD(1) AD(0) A58
B59 +5V8 +5V9 A59
ACK64J B60 A60 REQ64_1J
ACK64# REQ64#
B61 +5V10 +5V11 A61
B62 +5V12 +5V13 A62
Slot,PCI CONN
AD[31..0]
AD[31..0] 27
IDSEL0 R171 330 AD18

+-5%
5V_SYS 3D3V_SYS -12V_SYS

3D3V_SYS
C108 C263
B CP8 B
0.1uF EC27 0.1uF
2
*
EC19
* * 1000uF
* C284 PSCLK 2 1 SMB_CLK_RESUME 23,25,36
470uF
16V, +/-20%
Dummy
16V, Y5V, +80%/-20% +/-20% 16V, Y5V, +80%/-20%
* 0.1uF
16V, Y5V, +80%/-20%
* C100
0.1uF Del R351,R352
1
X_COPPER
Dummy CP7
25V, X7R, +/-10% PSDATA 2 1 SMB_DATA_RESUME 23,25,36
X_COPPER
5V_SYS
3D3V_SYS
RN12
R251
*1 2
INTBJ
INTCJ
INTBJ 27 R249
ACK64J
3 4 INTCJ 27
INTDJ REQ64_1J
5 6 INTDJ 27
INTAJ
7 8 INTAJ 27 2.7K
8.2K +/-5%2.7K
+/-5% +/-5%
RN20
*1 2 PREQ1J 27
3 4 PREQ2J 27
3D3V_SYS
5 6 PREQ3J 27
7 8 RN15
8.2K
+/-5% PLACE ICH7 *1 2
STOPJ
LOCKJ
RN25 3 4 PERRJ
5 6
*1 2
INTEJ
INTHJ
INTEJ 27 7 8
SERRJ
3 4 INTHJ 27
A INTFJ 8.2K A
5 6 INTFJ 27
INTGJ +/-5%
7 8 INTGJ 27
8.2K
+/-5% RN14
Reserved
*1 2
FRAMEJ
IRDYJ
* **
R265 8.2K +/-5% r0402h4 3 4 TRDYJ

PREQ4J 27 5 6
R272 8.2K +/-5% r0402h4 DEVSELJ
PREQ5J 27 7 8
8.2K FOXCONN PCEG
R273 8.2K +/-5% r0402h4 +/-5%
PREQ0J 27 Title
PCI Slot
C
G31M05 A
Date: Thursday, January 10, 2008 Sheet 31 of 41

5 4 3 2 1
5 4 3 2 1
U26 U25 U82 AVDDL VDD33

3D3V_SB
VDD33 U4
RTL8111B-VC-GR EECS 1 8 VDD33 C34
CS VCC
1
*R6 RTL8101E-GR RTL8111C-GR
* C86 EESK 2 7
* 0.1uF
E
0 10uF EEDI/AUX SK DC
3 DI ORG 6
10V, Y5V, +80%/-20%

+/-5% B Q3 EEDO 4 5 16V, Y5V, +80%/-20%
2
@8111C BCP69T1G DO GND Reserved
R13
@8101E @8111C @8111B @8111B @8111B AT93C46DN-SH-T
*
R30
L4
C
4
*
0 VDD33
*
Dummy 0 @8111C +/-5%
GVDD 4.7uH Dummy
+/-5% Near to pin 200mil
* C31 C11 Width >40mil
0
2KOhm R25
* 0.1uF
* 1uF CTRL18 L8 AVDDL
VDD33
AVDDH
XTAL2
XTAL1
+/-5%
DVDD
#R389#R390
+/-1% 16V, X7R, +/-10% 10V, Y5V, +80%/-20%
GVDD
DVDD
DVDD
LED0
LED1
LED2
LED3
@8111B @8111B @8101E C57 C60 C62 C47 EEDI/AUX R34 3.6K +/-1% 33VAUX
CTRL15
D 3D3V_SB D
*R389 *R390 r0805h6
* 0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
RSET
1
2.49K 2KOhm
* C77
* C37
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%

+/-1% +/-1% 10uF 10uF
C13 VDD33
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%

r0402h4 r0402h4 EGND R60 +/-5%
2
@8111C/8111B @8101E U6 XTAL1 Reserved
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
*
0 r0805h6
1
RSET
VDD33D
VDD15D
65
VCTRL15
NC22
CKTAL2
CKTAL1
NC21
LED0
LED1
LED2
LED3
NC20
NC19
NC18
VDD15E
33pF
1
+/-5% X6
XTAL-25MHz
* C28
10uF * C76
10uF
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%

CTRL18 1 48 EESK
C12
2
AVDDH VCTRL18 EESK EEDI/AUX Reserved Reserved
2 47
2
MDI0+ AVDD33 EEDI/AUX VDD33 XTAL2
3 46
*
MDI0- MDIP0 VDD33C EEDO
4 MDIN0 EEDO 45
AVDDL 5 44 EECS 3D3V_SYS
AVDD18A EECS 33pF
RTL8101E
MDI1+ 6 43 DVDD
MDI1- MDIP1 VDD15C +/-5% @8111B @8111B
7 MDIN1 NC17 42 R50
AVDDL 8 41 DVDD
MDI2+ 9
AVDD18B
NC1
NC16
NC15 40 *1K
+/-5%
MDI2- 10 39 3D3V_SB FB9 +/-5% VDD33
AVDDL NC2 NC14 DVDD r0402h4 AVDDL L14
11 NC3 NC13 38 AVDDL
MDI3+ 12 37 VDD33 0 0
MDI3- NC4 VDD33B R47
13 NC5 ISOLATEB 36 1 2+/-1% +/-5% r0805h6 C48 C58
1
AVDDL
DVDD
14
15
NC6 NC12 35
34
15K Reserved @8111C
r0805h6 VDD33 * C88
*
10uF
C87
10uF * 0.1uF
* 0.1uF
LANWAKEB
VDD15A NC11
REFCLK_N
REFCLK_P
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%

VDD33 16 33 R55 0 DVDD Dummy
EVDD18A
EVDD18B
2
VDD33A NC10
PERSTB
*
VDD15B
+/-5%
EGNDA
EGNDB
E
HSON
HSOP
MDI0+
MDI1+
@8101E/8111B
MDI0-
MDI1-
HSIN
HSIP
NC7
NC8
NC9
B Q6
BCP69T1G
#U26#U25#U82 @8111B
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
*R33 *R35 *R40 *R41
C
4
49.9 49.9 49.9 49.9 CTRL15 L15 DVDD
+/-1% +/-1% +/-1% +/-1% 0
EVDD18
EVDD18
DVDD
r0402h4 r0402h4 r0402h4 r0402h4 +/-5% C74 C52 C56 C33 C85 C35 AVDDH FB7 +/-5%
DVDD
AVDDH VDD33
@8101E @8101E @8101E @8101E @8101E
* 0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
EGND
25 LAN_PMEJ
1
r0805h6
* C70 0
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%

35 ICH_LAN_PLTRSTJ
C45 C53
* C22 10uF r0805h6
10V, Y5V, +80%/-20%

C
* 0.1uF
* 0.1uF 10uF C
2
10V, Y5V, +80%/-20%
16V, X7R, +/-10% 16V, X7R, +/-10% C32
25 HSO_P2_LAN
2
25 HSO_N2_LAN
C84 0.1uF 16V, X7R, +/-10%
HSI_N2_LAN 25
@8101E @8101E * 0.1uF
**
16V, Y5V, +80%/-20%

C83 0.1uF 16V, X7R, +/-10%
HSI_P2_LAN 25
EGND
REFCLK- Reserved Reserved Reserved

CK_PE_100M_N_LAN 8
@8101E/8111B
REFCLK+ @8101E
CK_PE_100M_P_LAN 8
AVDDL AVDDL R59 +/-5% EVDD18

0 #FB23#R391
3D3V_SB R3 CTRL15 r0805h6
0 C81 C82
+/-5% C30 R391 FB23
* 0.1uF
* 0.1uF
1
@8111C
* C2
* C10
* 0.1uF 0 FB 100 Ohm
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%

r0805h6 10uF 10uF +/-5% +/-25%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%

@8111C
2
@8111B @8101E/8111C
r0805h6 0805h11
AVDDL
R21
0
+/-5% @8111C @8111C
@8101E
USBPWR2
C20 C21 USBPWR2(1-2)
1
check 0.1uF
* * 1nF
50V, X7R, +/-10% 3
2
3
2
5V_SB
16V, Y5V, +80%/-20% @8101E @8101E 3D3V_SB 1
BACK PANEL ( LAN + 2 USB Connector ) 5V_SYS
2
1
B B
Jumper_2P_Blu
Header_1X3
R66 R65 F2
150 150 Fuse 2.6A
*
D5 +/-5% +/-5% fs1813h13
LED1 C A SVCC2
C92 @8111C/8111B Reserved
LS4148-F
@8101E D4 * 0.1uF
16V, Y5V, +80%/-20% NIC_USB
*
LED2 C A @946
25 USB_OCJ_BACK
LS4148-F 27 SVCC2 R70
1
*
LED3 R24 0 22 28 C97 R76 47K EC13

*
YLW_LED
+/-5% @8111C/8111B C90

0.1uF
*
21 29 L12 Dummy
* 0.1uF 56K
+/-5%
+/-5%
r0402h4
470uF
16V, +/-20%
USB-2
USB-1
30 1 4
16V, Y5V, +80%/-20% r0402h4
16V, Y5V, +80%/-20% Dummy 2
2 3
9 1
MDI0+ 10 5 Common Choke 90 Ohm_2L
MDI0- 11
** **
RJ45-MJ2
MDI1+ 12 2 R46 0 +/-5% USBN6

MDI1- R54 0 +/-5% USBN7 USBN6 25 USBN6 USBP6
13 6 USBN7 25
MDI2+ 14
3
AVDDL MDI2- 15 3 R42 0 USBP6
MDI3+ R48 0
+/-5% USBP7 USBP6 25
16 7 USBP7 25 1 2 SVCC2 1 2 SVCC2
MDI3- 17 +/-5%
*
R68 0 18 4 L13 Dummy

+/-5% C93 D13 D12
Dummy 8 1 4
BAV99 BAV99
*R69 0.1uF
GRN_LED
0
+/-5% * 16V, Y5V, +80%/-20% 20 23
2 3
USBP7 USBN7
Reserved Dummy 19 24 Common Choke 90 Ohm_2L
3
25
26 1 2 SVCC2 1 2 SVCC2
A CONN-USBx2_RJ45 * C79
0.1uF D16 D19
A
BAV99 BAV99
3D3V_SB R67 150 +/-5% #NIC_USB1#NIC_USB2#NIC_USB3 16V, Y5V, +80%/-20%
LED0
NIC_USB1 NIC_USB2 NIC_USB3
C91 JFM24U13-21U5-4F RU1-250ARWGF RU1-250ARWGF

FOXCONN PCEG
* 0.1uF
16V, Y5V, +80%/-20%
Title
Index Page
@946
CONN-USBx2_RJ45
@8101E CONN-USBx2_RJ45 CONN-USBx2_RJ45
C G31M05 A
@8111C/8111B/G31 @8111C/8111B/946 Date: Thursday, January 10, 2008 Sheet 32 of 39

5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
FOXCONN PCEG
Title
Index Page
Custom G31M05 A

5 4 3 2 1
5 4 3 2 1
*
TMPIN2 R121 Dummy
10K SIOVREF
+/-1% r0402h4
C128
0.1uF
* Dummy RT1
C
16V, Y5V, +80%/-20% 10K
T Q10 FB 80Ohm
+/-1% B
* MMBT3904-7-F 5V_SYS
Reserved
E
5V_SYS 5V_SB
FB12
Note:
GNDA C89 *Place CAPs close to pin 67, trace minimum 12 mils
System Temperature Monitor GNDA
* 0.1uF
16V, Y5V, +80%/-20% *
C132
D
* 10uF C124
0.1uF
*
10V, Y5V, +80%/-20% *
EC25
100uF
D
+/-20%
35
99
67
4
5V_SYS 5V_SYS U7
COM A
VCC
VCC
VCC
VCCH
CP3
TMPIN1 C121 C96 FAN half speed
THERMDA 14
C133 CP2 X_COPPER THERMDC 14
* 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
37
37
DCDAJ
RIAJ
118
119
DCD1#
RI1#
PD7
PD6
116
115
* 3.3nF
16V, NPO, +/-5% X_COPPER
37
37
CTSAJ
DTRAJ
120
121
CTS1#
DTR1#/JP1
PD5
PD4
114
113
Parallel Port
THERMDA/THERMDC 122 112
1. width=10 mils, spacing=10 mils. 37 RTSAJ RTS1#/JP2 PD3
GNDA 123 111
2. route the lines in parallel 37 DSRAJ DSR1# PD2
Serial Port 1/2

GNDA
For EMI 37 SOUTA 124
125
SOUT1/JP3 PD1 110
109
CPU Temperature Monitor 37 SINA
126
SIN1
DCD2#
PD0
STB# 108
RIBJ 127 107
RI2# AFD#
128 CTS2# ERR# 106
DTRBJ 1 105
RTSBJ DTR2#/JP4 INIT#
2 RTS2# SLIN# 104
3 DSR2# ACK# 103
SOUTB 5 102
SOUT2 BUSY CIRTX
6 SIN2 IT8718F-S/GX-L PE 101
100
CIRTX 36
5V_SYS COM B SLCT
Power-on Control
3D3V_SYS
5V_SYS PVID5 20
R79 PVID4 JSBB2/GP27
Add for RI2 PVID3
21 JSBB1/GP26 GP40 79
Need to checked
22 78 R118 10K +/-5% 5V_SB
JSBCY/GP25 PWROK2/GP41
*
CP1 4.7K +/-5% DTRAJ PVID2 R117 10K +/-5% r0402h4
JP1 23 77
Gameport/MIDI
JSBCX/GP24 GP53
*
*
r0402h4 24 76 r0402h4
+/-5% 14,25 ICH_THRM_UP JSAB2/GP23 PSON#/GP42 PS_ONJ 9
X_COPPER 9 S1_LED 25 75 PBTNJ_SIO 9
4.7K * PVID1 JSAB1/GP22 PANSWH#/GP43 PWRON
26 72 PWRBTNJ 25
*
R77 R71 680 +/-5% SOUTB Need to check PVID0 JSACY/GP21 PWRON#GP44 SLP_S3J
r0402h4
JP6 FLOPPY PVID6
27
28
JSACX/GP20 PSIN/GP45 71 SLP_S3J 25
VIDVCC RIBJ MIDI_OUT/GP17
29
*
*
R78 RTSAJ 9 SIO_BEEP MIDI_IN/GP16 CIRTX R64 10K +/-5%
C
JP2 1 2 RESETCON#/CIRTX/GP15 30 5V_SYS C
MISC.
Need to check r0402h4
4 RSMRST#/CIRRX/GP55 85 RSMRSTJ 25
5V_SYS 680 +/-5% r0402h4 5 6 DENSELJ 51 66
5V_SYS DENSEL# IRTX/GP47 IRTX 36
7 8 INDEXJ 63 70 IRRX 36
*
*
R80 8.2K +/-5% A20GATE MOTEAJ INDEX# IRRX/GP46 CASEOPENJ 1K
r0402h4 Dummy
JP7 9
11
10
12
52
55
MTRA# COPEN# 68
R115 +/-5%
14 PECI DRVB#
DRVAJ
*R75
2.2K
*R72
13
15
14
16
54
53
DRVA# CIRRX
Floppy I/F
MTRB#/THRMO# PCIRST4#/SCRPRES#/GP10 84 CIRRX 36
SCR I/F
+/-5% 2.2K 5V_SYS 17 18 DIRJ 57 34
+/-5% STEPJ DIR# PCIRST3#/SCRCLK/GP11 ICH_G_PLTRSTJ 23
19 20 58 33 ICH_LAN_PLTRSTJ 32
*
Dummy r0402h4 WDATAJ STEP# PCIRST2#/SCRIO/GP12 R57 10K
21 22 56 WDATA# PWROK1/SCRPFET#/GP13 32 3D3V_SYS
Dummy RN10 23 24 WGATEJ 60 31 IDE_RSTJ +/-5% r0402h4
WGATE# PCIRST1#/SCRRST/GP14 IDE_RSTJ 26
DTRBJ RTSBJ TK00J
JP4 JP5 25 26 62 TRK0# PWRGD_3V 16,25
*
1 2 TK00J 27 28 WPTJ 64 98 VIN0
**
WPTJ RDATAJ WPT# VIN0 VIN1
*R74
680
* R73
680
3
5
4
6 RDATAJ
29
31
30
32 SIDE1J
61
59
RDATA#
HDSEL#
VIN1
VIN2
97
96 VIN2
R110 10K +/-5% Reserved 5V_SYS
+/-5% +/-5% 7 8 DSKCHGJ 33 34 DSKCHGJ 65 95 R99 0
DSKCHG# VIN3/ATXPG PWRG_ATX 9,13
r0402h4 94 VIN4 +/-5% r0402h4 Reserved
Reserved Reserved 150 +/-5% VIN4 VID7
VIN5 93
Hardware Monitoring
Header_2X17_K3 VIDVCC 36 92 VID6
INDEXJ 16,25,29 PLTRSTJ LPCPD# VIN6 VIN7
37 LRESET# VIN7 91
RESET OPEN DRAIN 38 90 SIOVREF
R85 25 L_DRQ0J LDRQ# VREF TMPIN1 C141
select "high" 26,29 SERIRQ 39 SERIRQ TMPIN1 89
TMPIN2
150
+/-5% 25,29 L_FRAMEJ L_AD0
40
41
LFRAME#
LAD0
TMPIN2
TMPIN3
88
87
* 1uF
L_AD1 Need to checked

42 LAD1 FAN_CTL3/GP36 12
L_AD2 43 11
L_AD3 LAD2 FAN_TAC3/GP37
44 10 Place cap close to pin90, and
LPC I/F
LAD3 FAN_CTL2/GP51 FANOUT2 36
CK_33M_SIO 47 9 GNDA
8 CK_33M_SIO PVID7 PCICLK FAN_TAC2/GP52 FANIN2 36 Do Not remove it.
48 CLKRUN#/GP50/PCIRST5# FAN_CTL1 8 FANOUT1 36
CK_48M_SIO 49 7
8 CK_48M_SIO CLKIN FAN_TAC1 VID0 FANIN1 36
25 L_PMEJ 73 PME#/GP54 VID0/GP30 19
for KB/MOUSE wake 18 VID1
VID1/GP31 VID2
VID2/GP32 17
L_AD[3..0] 45 16 VID3
25,29 L_AD[3..0] 26 KBRSTJ KRST# VID3/GP33
L_AD3 46 14 VID4
Voltage Monitor L_AD2
26
36
A20GATE
KBDATA 80
GA20
KDAT
VID4/GP34
VID5/GP35 13 VID5
L_AD1 81
B 36 KBCLK KCLK B
KB/MS
Del CP21 Reserved R359 L_AD0 82
Steven Sun Update 2007.03.28 36 MSDATA MDAT
36 MSCLK 83 MCLK VBAT 69 VBAT
VCCP 1D8V_STR 3D3V_SYS 12V_SYS C125
GNDD
GNDD
GNDD
GNDD
GNDA
* 1uF
10V, Y5V, +80%/-20%
*R119 *R112 *R111 *R109
15
50
74
117
86
10K 10K 10K 30K Place cap close to pin 69
**
+/-1% R116 4.7K +/-5% SLP_S3J
+/-1% +/-1% +/-1% r0402h4 FB11 r0402h4
r0402h4 r0402h4 r0402h4 * FB 80Ohm R61 1K ICH_LAN_PLTRSTJ
Reserved Reserved +/-5% r0402h4 Reserved
VIN0
VIN1
*
VIN2 Power On Strapping Options 3D3V_SYS R56 1K ICH_G_PLTRSTJ
GNDA +/-5% r0402h4 Reserved
VIN4 Symbol value Description RN8
1 Disabled.
*
1
3
2
4
SERIRQ
KBRSTJ
JP1 5 6 A20GATE
Pin 121 Flashseg1_EN 0 Flash I/F Address Segment 1 (FFF8_0000h~FFFF_FFFFh, 7 8

000E_0000h~000F_FFFFh) is enabled 10K
JP2 1 Disable VID output pins 3D3V_SYS +/-5%
Dummy
Pin 122 VIDO_EN RN5
Dummy
C146
Dummy
C135
C134
0.1uF
Reserved
C131
0 Enable VID output pins 10 PVID7
PVID7
PVID6
*1 2
10 PVID6 3 4
0.1uF 0.1uF
* R98 0.1uF Use for chip 1 when two IT8718F exit in the same system. Chip is selected 10 PVID5
PVID5
5 6
16V, Y5V, +80%/-20%
* * 10K
* JP3 1 in conjunction with "Global Configuration Register - Index 22, bit 7 10 PVID4
PVID4
7 8
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
* +/-1%
Pin 124 CHIP_SEL Modify for Steven 090407
r0402h4 Use for chip 0 when two IT8718F exit in the same system. Chip is selected 680 +/-5% 8p4r0603h7
* *
0 in conjunction with "Global Configuration Register - Index 22, bit 7 RN4
R108
Reserved
4.7K +/-5% VIN7
r0402h4
JP4 BUF_SEL 1
The output buffers of PCIRST1#, PCIRST2#, PCIRST3# and 10 PVID3
PVID3
PVID2
*1 2 R63 4.7K +/-5% IDE_RSTJ
PCIRST4# are open-drain. 10 PVID2 PVID1 3 4 5V_SYS
r0402h4
GNDA GNDA GNDA GNDA Pin 1 0 The output buffers are push-pull.
10 PVID1 PVID0 5 6
GNDA 10 PVID0 7 8
A A
11 The default value of EC Index 15h / 16h / 17h is 00h 680 +/-5%
8p4r0603h7
JP5:JP7 10 The default value of EC Index 15h / 16h / 17h is 20h
Pin 2 & 46 FAN_CTL_SEL
VID0
14 VID0
01 The default value of EC Index 15h / 16h / 17h is 40h
Change to analog GND or not VID1
14 VID1
VID2
14 VID2
00 The default value of EC Index 15h / 16h / 17h is 60h 14 VID3
VID3
VID4
14 VID4
JP6 1 The threshold voltage of VID is 2.0 / 0.8V 14 VID5
VID5
FOXCONN PCEG
Pin 5 VID_ISEL 14 VID6
VID6
0 The threshold voltage of VID is 0.8 / 0.4V 14 VID7
VID7
Title
JP7 1 Disable WDT to reset PWROK Super I/O ITE8712F/IX
Pin 46 WDT_EN Size Document Number Rev
0 Enable WDT to reset PWROK C G31M05 A

5 4 3 2 1
5 4 3 2 1
3D3V_SYS 5V_AUDIO Rear AUDIO

ALC662
25
38
U3
1
9
DVdd1
DVdd2
AVdd1
AVdd2
3 GPIO1
AUD_PRESENCE_L 2 GPIO0
AUD_RST# 11
ALC662 35 FRONT-L
25 ICH_RSTJ RESET# FRONT_L
AUDIO_BCLK 6 36 FRONT-R
25 ICH_BCLK BCLK FRONT_R CMIC1-VREFO-L
25 ICH_SYNC 10 37
*
R52 22 +/-5% SYNC LINE1-VREFO-R 10K R18
25 ICH_SDIN2 8 SDATA_IN DCVOL 33 5V_AUDIO
5 34 MIC2/LINE2-JD Dummy CMIC1-VREFO-R
25 ICH_SDOUT SDATA_OUT Sense B (JD2)
SURR-OUT-L 39
40 JD_REF 10uF DIP ECAP for THD+N R19
D
C71 12 PC_BEEP
JDREF (or NC)
SURR-OUT-R 41 +/-5%
* R31
Low Frequency Response 2.2K * R20 D
1
*
* 10pF
50V, NPO, +/-5%
SENSEA
LINE2-L
13
14
Sense A (JD1) CEN-OUT 43
44 Near the codec
20K
+/-1% R7 +/-5%
2.2K
+/-5% FB3 FB 600 Ohm
* *
LINE2-R LINE2-L LFE-OUT MIC1-R EC14 100uF +/-20% 75 MIC1-RF * MIC1_R5
15 45
2
LINE2-R SIDESURR-L
* *
Dummy MIC2-L 16 46 +/-5%
MIC2-R MIC2-L SIDESURR-R R4
17 MIC2-R *
CD_L 18 28 CMIC1-VREFO-L MIC1-L EC10 100uF +/-20% 75 MIC1-LF FB2 FB 600 Ohm MIC1_L2
CD_GND CD_L MIC1-VREFO-L CODEC_VREF +/-5%
19 CD_GND VREF 27
CD_R 20 29 Close to Chip
MIC1-L CD_R LINE1-VREFO MIC2-VREFO C14 C16
21 MIC1-L MIC2-VREFO 30 Close to Chip
1
MIC1-R LINE2-VREFO
22 31
* 4.7uF
* 0.1uF R5 FB4 FB 600 Ohm
*
LINE1-L MIC1-R LINE2-VREFO CMIC1-VREFO-R check 6.3V, X5R, +/-10% 16V, Y5V, +80%/-20% FRONT-R EC1 100uF +/-20% 75 LINE_OUT_R5_L * LINE_OUT_R5
23 LINE_L MIC1-VREFO-R 32
*
LINE1-R 24 Dummy +/-5%
2
LINE_R
DVss1
DVss2
AVss1
AVss2
47 SPDIFI(EAPD)
48 SPDIFO
Close to Chip
ALC662-GR R9 FB5 FB 600 Ohm
4
7
26
42
*
FRONT-L EC2 100uF +/-20% 75 LINE_OUT_L2_L * LINE_OUT_L2
*
+/-5%
AUDIO_BCLK R2 FB1 FB 600 Ohm
*
5V_AUDIO LINE1-R EC4 100uF +/-20% 75 LINE1-RF * LINE1_R5
*
C72 +/-5%
1
5V_AUDIO
C15 C17 * 10pF
50V, NPO, +/-5%
1
* 4.7uF
* 0.1uF R1 FB6 FB 600 Ohm
*
10V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% C42 dummy LINE1-L EC3 100uF +/-20% 75 LINE1-LF * LINE1_L2
1
*
* 4.7uF
* +/-5%
2
Dummy 10V, Y5V, +80%/-20% C41 Place near codec

0.1uF Close to Chip
2
Dummy 16V, Y5V, +80%/-20% AUD_RST#

Place near Pin 25 10uF DIP ECAP for THD+N
C73
Low Frequency Response
1
Place near Pin 38
* 10pF
50V, NPO, +/-5%
2
C dummy C
MIC1-RF LINE_OUT_L2 LINE_OUT_R5_L
Place near codec MIC1-LF LINE1_L2 LINE_OUT_L2_L
SHORT1 LINE1-RF
2 1 Dummy 3D3V_SYS LINE1-LF
C18 C27 2 2
X_COPPER RN1
* 180pF
* 180pF R8 R15
2
4
6
8
C19
22K 50V, NPO, +/-5%
50V, NPO, +/-5% 22K 22K
0.1uF 16V, Y5V, +80%/-20% C75 +/-5% +/-5%
*
* 13
5
7
* 4.7uF
10V, Y5V, +80%/-20%* C68 * C67
0.1uF +/-5% 1 1
SHORT3 0.1uF 16V, Y5V, +80%/-20%
2
2 1 Dummy 16V, Y5V, +80%/-20% Dummy

X_COPPER
R32
*
Dummy Place near Pin 1,9

AUDIO
SHORT2 5V_SB
0 12V_SYS LINE1_L2 INSULATOR
2 1 Dummy 32
LINE1-JD 33
A
A
X_COPPER MIC1_L2 34
+/-5% D22 MIC1_R5 LINE1_R5 35
SD103AW LINE1_R5
LS4148-F
D8 LINE_OUT_R5
U5 R53 36
C
C
5V_AUDIO 1 3 10 *
OUT IN +/-5% LINE_OUT_L2 22
EC11 BCN1 FRONT-JD 23 37
GND
* 100uF C61 C69 180pF 24

* C44
0.1uF
Dummy
+/-20%
L78L05N * 0.1uF
* 4.7uF
25V,Y5V,+80/-20%
Dummy
LINE_OUT_R5 25
38
2
16V, Y5V, +80%/-20% 50V, NPO, +/-10%

25V, X7R, +/-10%
Dummy C15 MIC1_L2 2 39
Swain 110406 MIC1-JD 3
4
MIC1_R5 5
B B
CD_IN1 12V to 5V Power Regulator D17
1
CD_L C36 1uF 1 10V,

2 Y5V, +80%/-20% 1 BAT54A CONN-JACK
***
2 1
CD_GND C29 1uF 1 10V,
2 Y5V, +80%/-20% 3 LINE2-VREFO 3
4 2
CD_R C1 1uF 1 10V,
2 Y5V, +80%/-20%
Header_1X4 FRONT AUDIO HEADER D18
BAT54A
1
MIC2-VREFO 3
2
SPDIF Header
RN6
*
3D3V_SYS
1
3
5
7
2
4
6
8
MIC2-L EC12 100uF +/-20% R83
*
2.2K
* 1K
+/-5%
del SPDIF OUT Close to Chip RN7 F_AUDIO1
+/-5%
MIC2-R EC7 100uF +/-20%

*1 2 1
3
2
4 AUD_PRESENCE_L
3 4
*
5 6 5 6
7 8 7 X
Close to Chip 9 10
75
+/-5% Header_2X5_K8
LINE2-R EC5 100uF +/-20% R16
* *R17
*
RN9 39.2K 20K
8
6
4
2
22K +/-1% +/-1%
Close to Chip
7
5
3
1
All JD resistors should be placed near CODEC
*
LINE2-L EC6 100uF +/-20% +/-5% MIC2/LINE2-JD
*
A A
SENSEA R44 5.1KOhm FRONT-JD
+/-1% Close to Chip
* *
R45 10K LINE1-JD

+/-1%
R43 20K MIC1-JD

+/-1%
FOXCONN PCEG
Title
AUDIO 655/861
C
G31M05 A

5 4 3 2 1
5 4 3 2 1
Peak fan current draw: 1.5A
Average fan current draw: 1.1A
Fan start-up current draw: 2.2A
Fan start-up current draw maximum duration: 1.0 second
SM Bus Bridge 5V_SYS

Fan header voltage: 12V +/- 10%
*R274
4.7K
+/-5%
r0402h4
R275
35 FANOUT2
100 +/-1%
If use SUIO power good 3D3V_SYS
D D
12V_SYS
function, dummy Q7,Q6,Q8 R311 2.7K +/-5% SMB_DATA_MAIN
pop R25,R18 R312 2.7K +/-5% SMB_CLK_MAIN
12V_SYS
Near the Memory
CP4
C
D37
8,20,22 SMB_DATA_MAIN SMB_DATA_RESUME 23,25,31
R276
X_COPPER * 4.7K
CPU_FAN +/-5% LS4148-F
for Clock Generator/DIMMs/TPM/Clock Buffer 2FAN2_2
A
for PCI-E x16/ICH7/LAN/PCI/PCI-E x1/Riser Card/New Card +12V
CMD 4FAN2_4
1 R277
*
GND
CP5 ? TACH 3FAN2_3 27KOhm
FANIN2 35
C326 +/-5%
Max. output current = 3A
8,20,22 SMB_CLK_MAIN SMB_CLK_RESUME 23,25,31
*
EC39
100uF Header_1X4 FAN4P * 47pF
50V, NPO, +/-5%
2
R266
X_COPPER CPU FAN 16V, +/-20%
Dummy
22K
+/-5%
1
C C
5V_SYS
5V_SB
C50
0.1uF
16V, Y5V, +80%/-20% *
Dummy IR/CIR 1 5V_SYS
1 2
4 3 5V_SYS
X CIRRX 35 IRRX
5 6 4
35 IRRX 5 GND
7 8 CIRTX 35 IRTX
35 IRTX 9 X
*R82
4.7K
Header_2X5_K3K10 +/-5%
#IR#IR/CIR1 r0402h4 R81
C64 C63
IR 35 FANOUT1
* *
470pF 470pF
50V, X7R,50V,
+/-10%
X7R, +/-10% IR/CIR CONNECTOR 5
IR/CIR1
100 +/-1%
Dummy Dummy 4
Need check whether follow up 3
X
TF spec?? 1 X
Header_2X5_K3K10
Header_1X5_K2 @TF
@CLONE
12V_SYS
12V_SYS
C
R84 D23
SYS_FAN * 4.7K
+12V 2FAN1_2 +/-5%
CMD 4FAN1_4 LS4148-F
1 R87
*
A
B 5V_SB GND B
5V_SB TACH 3FAN1_3 27KOhm
FANIN1 35
+/-5%
C65 C99 2
F1 * 0.1uF
Dummy
Header_1X4 FAN4P
* 47pF
50V, NPO, +/-5%
R86
22K
Fuse 1.5A +/-5%
Max. output current = 3A
System FAN
*
1
8
6
4
2
RN2 FB8 KB/MS

4.7K 300 Ohm@100MHz
*
+/-5%
*
16
7
5
3
1
13
35 KBCLK CLK_NET03 5 11
3 9
35 KBDATA 1 7
2 17
4 8
6 10
12
14
UP DOWN 15
PS2X2
PWR_NET02
CLK_NET02
35 MSCLK
A A
35 MSDATA
C54
* * 0.1uF
16V, Y5V, +80%/-20%

50V, NPO, +/-10%
180pF
CN3 FOXCONN PCEG
Title
Keyboard / Mouse / Fan
KB\MS Size
C
Document Number
G31M05
Rev
A

5 4 3 2 1
5 4 3 2 1
D D
C C
5V_SYS
C325
* 0.1uF
16V, Y5V, +80%/-20%
Dummy
For EMI
U2 -12V_SYS 5V_SYS 12V_SYS

B B
5V_SYS 20 1 12V_SYS
VCC +12V C49
2
NRTSA
35 RTSAJ 16 DA1 DY1 5
* 0.1uF
* C5
16V, Y5V, +80%/-20%
15 6 NDTRA * C4 0.1uF
35 DTRAJ DA2 DY2 NSOUTA Reserved
13 8 0.1uF
1
35 SOUTA DA3 DY3 NRIA 25V, X7R, +/-10%

35 RIAJ 19 RY1 RA1 2
18 3 NCTSA
35 CTSAJ RY2 RA2 NDSRA 25V, X7R, +/-10%
35 DSRAJ 17 RY3 RA3 4
14 7 NSINA
35 SINA RY4 RA4 NDCDA
35 DCDAJ 12 RY5 RA9 9
11 GND -12V 10 -12V_SYS

GD75232
placed near GD75232
RS232 Drivers and Receivers
COM1
PRT PORT
11
NDCDA 1
NDSRA 6
NSINA 2
NRTSA 7
NSOUTA 3 3D3V_SB
NCTSA 8
NDTRA 4
NRIA 9 R11
5 8.2K
* * * +/-5%
50V, NPO, +/-10% 50V, NPO, +/-10% 10
180pF 180pF
CN2 CN1
Reserved Reserved CONN-COM PORT ICH_RIJ_PU 25
Update by Steven 053107

A R14 Q1 A
NRIA 10K 2N7002
*
+/-5%
COM 1 R12
C
10K D3
* +/-5%
placed near connector

LS4148-F Ring
FOXCONN PCEG
A
Title
Serial / Parallel
C
G31M05 A

5 4 3 2 1
5 4 3 2 1
USBPWR1(1-2)
USBPWR1
3 5V_SB 5V_SYS 5V_SYS
3
2 2
1 1 5V_SYS
Jumper_2P_Blu C347 C391
D
Header_1X3 * 0.1uF
16V, Y5V, +80%/-20%
Dummy * 0.1uF
16V, Y5V, +80%/-20% D
F4
FUSB_PWR Fuse 2.6A
*
fs1813h13
EC20 C200
*
* 470uF
16V, +/-20% * 0.1uF R165
+/-5%
10K Reserved
r0402h4
USB_OCJ_FRONT 25
USBN3 USBP3
16V, Y5V, +80%/-20%
3
1
R164 C199 1 2 FUSB_PWR 1 2 FUSB_PWR
FOR EMI ISSUE 15K
+/-1% * 0.1uF
D24 D25
16V, Y5V, +80%/-20%
2 BAV99 BAV99
USBN0 USBP0
3
F_USB1 1 2 FUSB_PWR 1 2 FUSB_PWR
1 2
**
**
USBN3 R93 0 3 4 R106 0 USBN0
25 USBN3 USBN0 25 D26 D27
C USBP3 R101 +/-5%
0 5 6 R120 +/-5%
0 USBP0 C
25 USBP3 USBP0 25 BAV99 BAV99
+/-5% 7 8 +/-5%
L17 Dummy X 10 L18 Dummy
1 4 1 4
Header_2X5_K9
2 3 2 3
Common Choke 90 Ohm_2L Common Choke 90 Ohm_2L
USB Front Header II
FUSB_PWR
5V_SYS
C113 C149
* 0.1uF
* 0.1uF
16V, Y5V, +80%/-20%
Dummy
16V, Y5V, +80%/-20%
FOR EMI ISSUE
B B
USBN1 USBP1
3
F_USB2
1 2 1 2 FUSB_PWR 1 2 FUSB_PWR
**
**
USBN1 R149 0 3 4 R140 0 USBN2
25 USBN1 USBP1 R153 0
+/-5% R143 0
+/-5% USBP2 USBN2 25
25 USBP1 5 6 USBP2 25 D30 D31
+/-5% 7 8 +/-5%
L30 Dummy 10 L24 Dummy BAV99 BAV99
X
1 4 1 4
Header_2X5_K9 USBN2 USBP2
2 3 2 3
3
Common Choke 90 Ohm_2L Common Choke 90 Ohm_2L 1 2 FUSB_PWR 1 2 FUSB_PWR
USB Front Header 1
D28 D29
BAV99 BAV99
A A
FOXCONN PCEG
Title
Serial / Parallel
Custom G31M05 A

5 4 3 2 1
5 4 3 2 1
1. Change Lan RTL8111B colay RTL8101E to RTL8111C colay RTL8101E

2. Change Audio ALC888 colay ALC883 to ALC662 colay ALC888
3. Reserved Memory ratio schematic for over clock.
4. Del R108,C139,Q22,Q20,R107 and then connect VRMPWGD directly for VRD11.
5. Add R371,C501 for power button debounce circuit.
6. Reserved U15,U17 for TF spec.
7. Reserved TPM Header for TF spec.
D 8. Reserved U3,U6 for TF spec. D
9. Add R8,R1,R5,R10,R6,R14,R87,R86,R85,R84,R78,R76,R73,R75,R41,R55 for Audio ESD
10. Reserved CIR function for TF spec.
11. Reserved NB FAN.
12. Reserved C307,C314,C324,C318,C348,C350,C360,C357 for TF Front Panel
13. Change R335 to 91ohm,R337 to 115ohm for Memory Power
14. Remove R338 and stuff R332 for FAN half speed when Power on.
15. Reserved R46 for realtek's suggestion
16. Reserved U9,C144,C145 for VCCA_DAC
17. Add RT8111B SCH
18. Del EC72,EC55,EC54,EC73 for placement issue
19. Reserved R40,R25 For EMI
21. Add C16,C17 For RTL8111B LAN Chip EMI
22. Add FB22 For ITE suggestion
23. Reserved C497 for Front Panel ESD
24. Del Power V15SFR SCH
25. Add R208,R220 for further CPU
26. Reserved R321,R109,R320 for PCI RST
27. Disconnect SLP_S4 with CLK Gen
28. Change C368,C371 from 18pF to 12pF
29. Change F_AUDIO Pin7 connect to Audio_GND directly and connect Pin6,Pin10 to codec through the resistor.
After Gerber Out:
C
30. Reserved C506 C
31. Change R363 size from 0402 to 0603
32. Change R111 to 33ohm 1%
33. Add R400 100ohm 1%
34. Dummy Q24 C146
35. Reserved R94 In 8KS2H SKU
36. Reserved R114,C147,R110,Q23,Q26
37. Change R116,R118 to 10K 1%
38. Change C160 to 1uF 0603
39. Reserved Q39
40. Del CP2
41. Del EC29
42. Reserved R356
43. Change PCIe_16x slot to 2EG48211-S7Y-4F
44. Del EC65,EC66
45. Add EC68
46. Change L25,L38 to 630307400-176-G
47. Reserved C451,C396,C375,C381,C430,C441,C355,C436,C447,C448,C397,C385,C446,C427,C405,C401,C395,C353,C390
48. Del RN17
49. Add R401,R402,R403 10K 5%
50. Add JP1,JP2, JP1(P1&P2),JP2(P1&P2)
51. Add R404 470ohm
52. Add EC69
B B
53. Del EC46,EC47
54. Change L26,L37 to APL1108P-2R5L
55. Change C5,C6,C7 to 10pf
56. Change L8,L9,L10 to GL1608082NJT
57. Reserved C38,C65
58. Change CP14 to L40 10uH
59. Change L23 to 10uH
60. Add C139,C513,C514 10uF
61. Add EC65
62. Del CP24
63. Add R25 for EMC
64. Add R409,R410,R411 for Audio codec ESD protection
65. Change EC55 to 680uF
66. Change L23 From 10uH Inductor to 10ohm Resistor
A A
FOXCONN PCEG
Title
CHANGE LIST
C G31M05 A

5 4 3 2 1

G31MV PDF

Загружено:

Сведения о документе

Оригинальное название

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

G31MV PDF

Загружено:

Авторское право:

Доступные форматы

5 4 3 2 1

Foxconn Precision Co. Inc.

06. Power Sequence 30. PCIE1X

15. LGA775 -2 39. changlist B

16. Broadwater -GMCH -1

Date: Friday, January 18, 2008 Sheet 1 of 41

Cedar Mill, Presler ,

PCI Express x 16 Channel A DDR2

GMCH DDR2 667/800 Channel B DDR2

Date: Friday, January 04, 2008 Sheet 2 of 39

Front Panel PWROK ACZ_RST#

RSMRST circuit FOXCONN PCEG

Date: Friday, January 04, 2008 Sheet 3 of 39

MCH 200/266/333 MHz Diff Pair

PCI Express/DMI 100 MHz Diff Pair

TPM 33 MHz TPM

SIO 33 MHz Super I/O

SATA 100 MHz Diff Pair

Date: Friday, January 04, 2008 Sheet 4 of 39

3.3V Super I/O

1.2V FSB 5VSB

GMCH 1.25 V Vcore (Core Logic) PCI Express X16

Nineveh GbE Lan

1.8V ANALOG 418.2mA BJT

Date: Friday, January 04, 2008 Sheet 5 of 39

+3D3V_DUAL +3D3V_SYS +3D3V_SYS +3D3V_DUAL

+5V_SYS +5V_DUAL +5V_DUAL +5V_SYS

+3D3V_SYS +3D3V_DUAL +3D3V_DUAL +3D3V_SYS

+1D8V_STR +1D8V_STR +1D8V_STR +1D8V_STR

Date: Friday, January 04, 2008 Sheet 6 of 39

Date: Friday, January 04, 2008 Sheet 7 of 39

FB10 0 3D3V_CLK 3D3V_CLK_SATA_25M

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

25V, X7R, +/-10%

25V, X7R, +/-10%

C101 C155 C140

25V, X7R, +/-10%

25V, X7R, +/-10%

CK_33M_SIO 3D3V_CLK **GSEL/24.576Mhz VDDSATA_STB SATA_100M_P_ICH

R1264.7K +/-5% r0402h4 *SEL24_48#/24_48Mhz CPUT_LR0 200M_N_CPU

CK_33M_PCI1 ICS_FSBSEL0 R1222.2K +/-5% r0402h4 FSBSEL0

CK_33M_SIO ICS_FSBSEL2 R1032.2K +/-5% r0402h4 FSBSEL2

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

C154 C152 C118 C137 C114 C138

A Dummy Dummy Dummy Dummy Dummy Dummy A

Date: Tuesday, January 08, 2008 Sheet 8 of 39

5V_SYS 5V_SYS 5V_SYS 5V_SYS

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

5V_SB -12V_SYS 3D3V_SYS 3D3V_SYS 12V_SYS 5V_SB

25V, X7R, +/-10%

25V, X7R, +/-10%

25V, X7R, +/-10%

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%