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Design,ASIC Implementation and Verification of Synchronous and

Asynchronous FIFO

Conference Paper · July 2012

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 Proceedings of International Conference on Innovation in Electronics and Communications Engineering (ICIECE-2012)

Design,ASIC Implementation and Verification of

Synchronous and Asynchronous FIFO
Arun Teja S 1, S Nagakishore B 2, Swetha A 3
1
Guru Nanak Institute of Technology, M.Tech, E.C.E Dept., Ibrahimpatnam, Hyderabad, India
Email: itsmearun69@gmail.com
2, 3
Guru Nanak Institute of Technology, Asst. Prof , E.C.E Dept., Ibrahimpatnam, Hyderabad, India
Email:{ kishorereddy.vlsi@gmail.com, swethavlsi@yahoo.com }

Abstract : synchrous FIFO read and write operations are controlled

by a single clock, whereas in asynchronous FIFO read and
A FIFO is used as a “First In First Out” memory buffer write operations are controlled by individual clocks (i.e
between two asynchronous systems with simultaneous write
read clock and write clock).
and read access to and from the FIFO, these accesses being
independent of one another. In FIFO, the comparator shown in Fig. 1, is used to know
wheather the FIFO is full or empty.
FIFO has an input (write) port and an output (read) port.
Each port has its own associated pointers which points to a
location in the memory, after a FIFO reset both the write and
read pointers will be at the first memory location within the
FIFO. Each write operation will cause the write pointer to
increment to the next location in memory; similarly every
read operation will cause the read pointer to increment to the
next location. FIFO can be either synchronous or
asynchronous.

The basic difference between them is that the entire operation

of synchronous FIFO is entirely dependent on the clock
where as the write operation and read operation of
asynchronous FIFO are asynchronous to each other. The
entire ASIC (Application Specific Integrated Circuit) Flow is
carriedout using Synopsys tools.

Keywords - FIFO, Physical Design (ICC), Simulation (VCS),

Synthesis (DC), Verification (VCS).

I. INTRODUCTION

FIFOs are an increasingly important component as design

has become more modular. The choice of which structured
memory to employ can have significant impact on the
power, performance, and cost of a design. The choices are
broad and range from synchronous to asynchronous
designs. Some excellent work on the properties of FIFOs
has been published. Yet a clear understanding of the
comparative cost of different designs in terms of power,
throughput, latency, and area – and of the key differences
between specific structures– is not generally available.
This paper reports on a study performed for a two fold
purpose: to help designers choose the best FIFO for their
target design, and to develop the foundation for an
Fig.1.Comparator.
automatic CAD tool for selecting and synthesizing the best
structure.
The end goal is to develop synchronous and asynchronous
The most common synchronous and asynchronous designs FIFO in ASIC and to compare the difference between
are compared across a broad range of design metrics. The synchronous and asynchronous FIFO.
designs are characterized for power, timing, throughput II. DESIGN AND CHARACTERIZATION
for a given occupancy, and area.
The results reported in this paper are derived from the
This work evaluates the difference between synchronous layout of designs that have been automatically synthesized
and asynchronous FIFO. The synchronous designs operate and characterized. The implementations are designed to
entirely in a single clock domain, and asynchronous achieve the goal of making them as comparable as
designs may operate at different clock domains. In possible.
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 Proceedings of International Conference on Innovation in Electronics and Communications Engineering (ICIECE-2012)

This is accomplished by employing the same universal

subcomponents to construct both the asynchronous and
synchronous FIFO designs. For instance, the same
synchronous binary shift register is used for address
selection in the synchronous head / tail pointer design as
well as the asynchronous parallel and rectangular FIFOs.

The design and characterization flow proceed as follows.

First, a small set of shared circuit templates were designed.
Each are implemented as a behavioral or structural Verilog
module. The structural modules are mapped to the Artisan
65nm static library. There are 10 separate modules, three
of which are asynchronous state machines, the rest consist
of “clocked” components. The data registers are composed
of banks of flip-flops for the clocked head / tail pointer
design, and data latches for all other designs.
Fig. 2. Synchronous FIFO schematic view.
This characterization includes formal verification to prove
behavioral and timing correctness. Constraints are In asynchronous FIFO, we use two clocks that is write
employed to ensure the structure of the cells are not clock and read clock, write clock will take care of write
modified by the CAD tools, but that the drive strengths can operation and read clock will take care of read operation as
be correctly optimized for power and delay by using the shown in Fig.3. It means that both wr ite and read
set_size_only commands for these modules. Specific operations are asynchronous to each other. So, it is called
timing in the asynchronous modules not understood by the as asynchronous FIFO.
clocked CAD are defined with set_max_delay,
set_min_delay, and set_data_check commands. These sdc
commands are used by the logic synthesis and place and
route tools. They are employed in a way that ensures that
the asynchronous designs are power and timing optimized
just as the clocked modules.

A custom parameterized TCL script was written to

synthesize the completed FIFO architectures as Verilog
designs. The result of the script is a Verilog register
transfer level (RTL) design. The RTL typically consists of
both structural and behavioral modules.

The Verilog designs are synthesized using Design

Compiler (DC) and then physically placed and routed
using Integrated Circuit Compiler (ICC). The design area
is measured from ICC and then simulated for power and
performance using Verilog Compile Simulator (VCS).
Results from VCS import delays calculated from parasitic
extraction from the physical layout in ICC using the
standard delay format (sdf).
One simulation in VCS is designed to measure the power.
This simulation generates a switching activity information
file (saif) file that logs the switching activity on every node
in the design. The saif file is imported into ICC which
generates the power results based on the parasitics and
actual activity factors of the nodes from simulation.
The design is verified using Synopsys tool, that is VCS it
is a simulation tool.
Fig. 3. Asynchronous FIFO schematic view.
In this design, both synchronous and asynchronous FIFO
uses the same conditions as shown in Fig. 4. In FIFO, if
write pointer is equal to read pointer then the FIFO is
empty, else if write pointer is not equal to read pointer then
the FIFO is full or it has some data. The FIFO will be full,
when it satisfies the condition rptr = {~wptr[2], wptr[1:0] }.
Both synchronous and asynchronous FIFO schematic view
is generated by using Design Compiler (DC), it is a
Synopsys tool used for synthesis.

III. IMPLEMENTATION OF SYNCHRONOUS AND

ASYNCHRONOUS FIFO

In synchronous FIFO, we use only single clock that

controls both write and read operations as shown in the
Fig.2. It means that both write and read operations are
synchronous to each other. So, it is called as synchronous
FIFO. Fig. 4. FIFO full and empty condition.
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 Proceedings of International Conference on Innovation in Electronics and Communications Engineering (ICIECE-2012)

IV. FIGURES AND REPORTS

Simulation Result of Asynchronous FIFO Top Module:
Top Module for Synchronous FIFO:

Fig. 8. Simulation Result of Asynchronous FIFO.

Fig. 5. Synchronous FIFO Top Module.

Simulation Result of Synchronous FIFO Top Module:

Physical Design Reports for Synchronous FIFO:

Clock Report:
***************************************
Report : clocks
Design : fifo_top_syn
Version: C-2009.06-ICC
Date : Sat Jun 4 00:20:21 2011
***************************************

Attributes:
d - dont_touch_network
f - fix_hold
p - propagated_clock
G - generated_clock

Clock Period Waveform

Attrs Sources
Fig. 6. Simulation Result of Synchronous FIFO.
---------------------------------------
clk 2.00 {0 1}
Top Module for Asynchronous FIFO: f p {clk}
---------------------------------------

Constraint Report:

***************************************
Report : constraint
Design : fifo_top_syn
Version: C-2009.06-ICC
Date : Sat Jun 4 00:18:15 2011

Constraint Cost
--------------------------------
max_transition 0.00 (MET)
max_capacitance 0.00 (MET)
max_delay/setup 0.03 (MET)
critical_range 0.03 (MET)
min_delay/hold 0.00 (MET)
max_dynamic_power 0.00 (MET)
Fig. 7. Asynchronous FIFO Top Module. max_leakage_powe 0.00 (MET)
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 Proceedings of International Conference on Innovation in Electronics and Communications Engineering (ICIECE-2012)

Layout View of Placed and Routed Asynchronous FIFO:

Physical Design Reports for Asynchronous FIFO:

Clock Report:

***************************************
Report : clocks
Design : fifo_top_asyn
Version: C-2009.06-ICC
Date : Mon May 2 16:52:39 2011
***************************************

Attributes:
d - dont_touch_network
f - fix_hold
p - propagated_clock
G - generated_clock

Clock Period Waveform

Attrs Sources
---------------------------------------
r_clk 2.00 {0 1}
f p {r_clk} Fig. 10. Layout view of synchronous FIFO
w_clk 2.00 {0 1}
f p {w_clk} Verification Report of Synchronous FIFO:
---------------------------------------
Constraint Report:
***************************************
Report : constraint
Design : fifo_top_asyn
Version: C-2009.06-ICC
Date : Mon May 2 16:50:34 2011

Constraint Cost
---------------------------------
max_transition 0.00 (MET)
max_capacitance 0.00 (MET)
max_delay/setup 0.00 (MET)
critical_range 0.00 (MET)
min_delay/hold 0.00 (MET)
max_dynamic_power 0.00 (MET)
max_leakage_power 0.00 (MET)

Layout View of Placed and Routed Synchronous FIFO:

Fig. 9. Layout view of synchronous FIFO Fig. 11.Verification Report of synchronous FIFO

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 Proceedings of International Conference on Innovation in Electronics and Communications Engineering (ICIECE-2012)
Verification Report of Asynchronous FIFO:
Fig. 12.Verification Report of Asynchronous FIFO
V. CONCLUSION
The Synchronous & Asynchronous FIFO is operated at a
frequency of 500MHZ that is its clock period is 2ns. The
Design is free from LVS & DRC violations. But the
Asynchronous FIFO takes more area & more power,
because it requires two clocks. The entire ASIC Flow is
carriedout using Synopsys tools.
ACKNOWLEDGEMENT
I would like to articulate my profound gratitude and
indebtedness to Dr. Srinivasulu Thadisetty, Principal,
GNIT, Prof N. C Pant, Prof. B. Kedarnath, Mr.
Mallikarjun Rapolu, Assoc. Prof., for guiding and
encouraging me in all aspects.
I wish to extend my sincere thanks to Mr. Padmanabam ,
Asst. Prof.,for giving support.
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