COURSE INFORMATION SHEET

FACULTY Dr.B.KRISHNA KUMAR

PROGRAMME: Electronics & Communication DEGREE: BTECH
Engineering Engineering
COURSE: Linear & Digital IC Applications SEMESTER: III, I SEM CREDITS: 4
COURSE CODE: 55009 COURSE TYPE: CORE /ELECTIVE / BREADTH/
REGULATION: R13 S&H: CORE

COURSE AREA/DOMAIN: : CORE CONTACT HOURS: 4+1 (Tutorial) hours/Week.

CORRESPONDING LAB COURSE CODE (IF ANY): LAB COURSE NAME: IC & HDL Simulation Lab
55607

SYLLABUS:
UNIT DETAILS HOURS
I Operational Amplifier: ideal and practical Op-amp, internal circuits, Op-amp characteristics, 13
DC and AC characteristics 741 op-amp and its features, modes of operation-inverting, non-
inverting, differential, Instrumentation Amplifier, AC amplifier, Differentiators and
Integrators, Comparators, Schmitt Trigger, Introduction to voltage Regulators, Features of 723
Regulators, Three Terminal Voltage Regulators.

II OP-AMP, IC-555 & IC 565 Applications: Introduction to Active Filters, Characteristics of 12

Band pass, Band pass, Band reject and All Pass Filters, Analysis of 1st order LPF & HPF
Butterworth Filters, Waveform Generators- Triangular, Sawtooth, Square wave, IC555 Timer-
Functional Diagram, Monostable and Astable Operations, Applications, IC 565PLL –Block
Schematic, Description of Individual Blocks, Applications.

III DATA CONVERTERS; Introduction, Basic DAC techniques, Different types of DACs- 8
weighted resistor DAC, R-2R ladder DAC, Inverted R-2R DAC, Different types of ADCs –
Parallel Comparator type ADC, Counter type ADC, Successive Approximation, ADC and Dual
Slope ADC, DAC and ADC specifications.

IV DIGITAL INTEGRATED CIRCUITS: Classification of Integrated circuits, Comparison of 12

various Logic Families, CMOS Transmission Gate, IC interfacing- TTL Driving CMOS &
CMOS Driving TTL, Combinational Logic ICs – Specifications and Applications of TTL-
74XX & CMOS 40XX Series ICs - Code converters, Decoders, Demultiplexers, LED & LCD
Decoders with Drivers, Encoders, Multiplexers, Demultiplexers, Priority Generators/ Checkers,
Parallel Binary Adder/substractor, magnitude comparators.

V SEQUENTIAL LOGIC IC’s AND MEMORIES : Familiarity with commonly available 10

74XX & CMOS 40XX Series ICs - All types of Flip-flops, synchronous counters, Decade
counters, shift registers.Memories – ROM Architecture, Types of ROMS & Applications,
RAM Architecture, Static & Dynamic RAMs.

TOTAL HOURS 55
Tutorial Classes 16
Descriptive Tests 02
 Classes for beyond syllabus 03
Remedial Classes/NPTL 04
Total Number of Classes 80

TEXT/REFERENCE BOOKS:
T/R BOOK TITLE/AUTHORS/PUBLICATION
Text Book 1. OP-amps and linear integrated circuits-Ramakanth A.Gayakwad,PHI 2003

Text Book 2. Linear Integrated Circuits- D.Roy Chowdhury, New age International(p) Ltd, 2nd Ed..,2003

Text Book 3.Digital fundamentals – Floyd and Jain , Pearson Education, 8th Edition, 2005

Reference 1.Op-Amps and Linear Integrated Circuits - Concepts and Applications by James M.Fiore, Cengage/
Book Jaicc, 2/e, 2009.

Reference 2.Operational Amplifiers with Linear Integrated Circuits by K. Lal Kishore – Pearson,2009
Book
Reference 3. Linear Integrated Circuits and Applications – Salivahana, TMH
Book

Reference 4.Modern Digital Electronics - RP Jain - 4/e - TMH, 2010.

Book

Reference 5.Operational Amplifiers with Liner Integrated Circuits, 4/e William D. Stanley, Pearson Education
Book India,2009

COURSE PRE-REQUISITES:
C.CODE COURSE NAME DESCRIPTION SEM
53009 EDC Students learn the fundamental concepts of all II-I
electronic devices,
54021 PDC Students learn linear and non linear circuits, II-II
filters

COURSE OBJECTIVES:
1 To introduce the basic building blocks of linear integrated circuits.

2 To teach the linear and non-linear applications of operational amplifiers.

3 To introduce the theory and applications of analog multipliers and PLL

4 To teach the theory of ADC and DAC

5 To introduce the concepts of waveform generation and introduce some special function ICs
6 To understand and implement the working of basic digital circuits.
COURSE OUTCOMES:
SNO DESCRIPTION PO
MAPPING
1 A thorough understanding of operational amplifiers with linear integrated a,b,e
circuits
2 Understanding of the different families of digital integrated circuits and their b,c,d,i
characteristics
3 Also students will be able to design circuits using operational amplifiers for l,g
various applications.

GAPS IN THE SYLLABUS - TO MEET INDUSTRY/PROFESSION REQUIREMENTS:

SNO DESCRIPTION PROPOSED
ACTIONS
1 Students need practical knowledge on linear ICs 741, 555, 723, 565/566 to work in the Student
industry and need to do application orientation projects project
2 Students need practical knowledge on Digital ICs 74x74, 74x138, 74x90, 74x194, 74x85, Student
74x151 to work in the industry and need to do application orientation projects project
PROPOSED ACTIONS: TOPICS BEYOND SYLLABUS/ASSIGNMENT/INDUSTRY VISIT/GUEST
LECTURER/NPTEL ETC

TOPICS BEYOND SYLLABUS/ADVANCED TOPICS/DESIGN:

1 Higher order filters
2 Applications of PLL

WEB SOURCE REFERENCES:

1 www.emedia.ee.unsw.edu.au Video lecturers: -Dept.Digital Library

2 www.nptel.edu.in Video lecturers of 1).Analog IC Design Dr. Nagendra Krishnapura,
IITM -Dept.Digital Library
3 www.ucberkely.edu.in
4 Solution Manuals:1). Op-Amps and Linear Integrated Circuits - Concepts and Applications by
James M.Fiore, Cengage/ Jaicc, 2/e, 2009. -Dept.Digital Library
5 E-books: 1). Op-Amps and Linear Integrated Circuits - Concepts and Applications by James
M.Fiore, Cengage/ Jaicc, 2/e, 2009.
6 2). Digital Fundamentals - Floyd and Jain, Pearson Education,8th Edition, 2005.
7 All 8-units having PPTS

DELIVERY/INSTRUCTIONAL METHODOLOGIES:
√ CHALK & TALK √ STUD. ASSIGNMENT ☐ WEB RESOURCES
√LCD/SMART BOARDS √STUD. SEMINARS ☐ ADD-ON COURSES

ASSESSMENT METHODOLOGIES-DIRECT
√ ASSIGNMENTS √STUD. SEMINARS √ TESTS/MODEL ☐√UNIV. EXAMINATION
EXAMS
√STUD. LAB √ STUD. VIVA √ MINI/MAJOR ☐ CERTIFICATIONS
PRACTICES PROJECTS
☐ ADD-ON COURSES ☐ OTHERS

ASSESSMENT METHODOLOGIES-INDIRECT
√ASSESSMENT OF COURSE OUTCOMES (BY √STUDENT FEEDBACK ON FACULTY (TWICE)
FEEDBACK, ONCE)
√ ASSESSMENT OF MINI/MAJOR PROJECTS BY EXT. ☐ OTHERS
EXPERTS

Prepared by

Dr.B.KRISHNA KUMAR

Course objectives:

1 To introduce the basic building blocks of linear integrated circuits.

2 To teach the linear and non-linear applications of operational amplifiers.

3 To introduce the theory and applications of analog multipliers and PLL

4 To teach the theory of ADC and DAC

5 To introduce the concepts of waveform generation and introduce some special function ICs
6 To understand and implement the working of basic digital circuits.

Course Outcomes:

1 A thorough understanding of operational amplifiers with linear integrated

circuits
2 Understanding of the different families of digital integrated circuits and their
characteristics
3 Also students will be able to design circuits using operational amplifiers for
various applications.
 IC Applications – MODEL LESSON PLAN
No. of Cumulative Teaching AID
Sl No Name of the Topic Classes number of
required periods

LINEAR INTEGRATED CIRCUITS

Unit1 Operational Amplifier

1 ideal and practical Op-amp 02 2 Chalk & Talk

2 Op-amp characteristics 01 3 Chalk & Talk

3 DC and AC characteristics, 741 op-amp and its features 02 5 Chalk & Talk

4 modes of operation-inverting, non-inverting, differential 02 7 Chalk & Talk

5 Instrumentation Amplifier, AC amplifier 02 9 Chalk & Talk

6 Differentiators and Integrators 01 10

6 Comparators, Schmitt Trigger 01 11 Chalk & Talk

Introduction to voltage Regulators, Features of 723 Chalk & Talk

7 01 12
Regulators

8 Three Terminal Voltage Regulators. 01 13 Chalk & Talk

OP-AMP, IC-555 & IC 565 Applications

Introduction to Active Filters, Characteristics of Band Chalk & Talk

10 01 14
pass

11 Band pass, Band reject and All Pass Filters 01 15 Chalk & Talk

12 Analysis of 1st order LPF & HPF Butterworth Filters 02 17 Chalk & Talk

Waveform Generators- Triangular, Sawtooth, Square Chalk & Talk

12 02 19
wave

13 IC555 Timer- Functional Diagram 01 20 Chalk & Talk

14 Monostable and Astable Operations, Applications 02 22 Chalk & Talk

IC 565PLL –Block Schematic, Description of Individual Chalk & Talk

15 03 25
Blocks, Applications..

DATA CONVERTERS

16 Introduction, Basic DAC techniques 01 26 Chalk & Talk

17 Different types of DACs- weighted resistor DAC 01 27 Chalk & Talk

18 R-2R ladder DAC, Inverted R-2R DAC 01 28 Chalk & Talk

19 Different types of ADCs – Parallel Comparator type ADC 01 29 Chalk & Talk

20 Counter type ADC, Successive Approximation, 02 31 Chalk & Talk

ADC and Dual Slope ADC, DAC and ADC Chalk & Talk
21 02 33
specifications.

DIGITAL INTEGRATED CIRCUITS

Classification of Integrated circuits, Comparison of Chalk & Talk

22 01 34
various Logic Families

CMOS Transmission Gate, IC interfacing- TTL Driving Chalk & Talk

23 02 36
CMOS & CMOS Driving TTL

Combinational Logic ICs – Specifications and Chalk & Talk

24 02 38
Applications of TTL-74XX & CMOS 40XX Series ICs

Code converters, Decoders, Demultiplexers, LED & LCD Chalk & Talk
25 02 40
Decoders with Drivers

26 Encoders, Multiplexers, Demultiplexers 01 41 Chalk & Talk

27 Priority Generators/ Checkers 01 42 Chalk & Talk

Parallel Binary Adder/substractor, magnitude Chalk & Talk

28 03 45
comparators.
 SEQUENTIAL LOGIC IC’s AND MEMORIES

Familiarity with commonly available 74XX & CMOS Chalk & Talk
29 01 46
40XX Series ICs

All types of Flip-flops, synchronous counters, Decade Chalk & Talk

30 03 49
counters, shift registers

31 Memories – ROM Architecture 01 50 Chalk & Talk

29 Types of ROMS & Applications 02 52 Chalk & Talk

30 RAM Architecture, Static & Dynamic RAMs. 03 55 Chalk & Talk

TOTAL HOURS 55
Tutorial Classes 16
Descriptive Tests 02
Classes for beyond syllabus 03
Remedial Classes/NPTL 04
Total Number of Classes 80
Tutorial Classes

S. No. Date Topic delivered Teaching AID HOD

Sign
Unit-1
1 1.calculate CMMR for the given Chalk & Talk
values of Ad=6000 and Ac=15
2. an op amp has slew rate of 1.5
v/µsec. what is the maximum
frequency of output wave whose peak
value is 10 volts.
2 1. If in an op- amps inverting input is Chalk & Talk
zero, what is the voltage at non
inverting terminal for an output of
5 volts and A=50,000
2. How first can the output of an
opamp can change by 10volts if its
slew rate is 1v/µsec
3 1.design an adder circuit using op- Chalk & Talk
amp to get the output expression v0= -
(0.1V1+10V2+V3)\
2.in an integrator Ri=10K ohms.
Cf=1Farad,t he input is step signal
Vi=2V for 0≤ t ≤4, determine the
output voltage and sketch.
 .
4 1.in the differentiator circuit the input Chalk & Talk
is a sine wave with a peak to peak
amplitude of 3v at 200Hz. Sketch the
output wave

Unit-2
5 1. Design first order filter with Chalk & Talk
fl=1KHz and Af=1.5
2. Design WBPF with fl=400Hz
, fh=2KHz and pass band gain
of 4
6 1. Design wide band reject filter Chalk & Talk
with fl=200Hz and fh=1KHz
7 1. Design monostable Chalk & Talk
multivibrator using 555 timer
to produce pulse width of
100µsec
8 1. Applications of monostable Chalk & Talk
and astable multivibrator
using 555 timer
Unit-3
9 1.the LSB of a 6 bit DAC represents Chalk & Talk
0.1 volts , what voltage value will be
represented by following words
a) 101010 b)110110
2. a 12 bit DAC has full scale range
of 15 volts . its maximum linearity
error is ±1/2 LSB. What is the
percentages of resolutions

10 1.how many resistors are required for

an 8 bit weighted resistor DAC and
what are the resistor values, assume
smallest resistor is R.
Unit-4
11 1.design 3 input TTL Nand gate Chalk & Talk

12 1.Design 3 input CMOS NOR gate LCD

13 1. Design a code converter LCD

which converts binary to gray
code
2. Realize 16x1 MUX using two
8x1 MUX
14 1. Design 2 bit digital Chalk & Talk
comparator

Unit-5
15 1. Design conversion circuit to LCD
convert a)JK to T Flip Flop
b) JK Flip Flop to D FF

16 2. Design Mod -12 ripple Chalk & Talk

counter using IC 74x74
17 3. Draw the Architecture of Chalk & Talk
ROM and RAM

GAPS & PLANS for Add-on programs

SNO DESCRIPTION PROPOSED
ACTIONS
1 Students need practical knowledge on linear ICs 741, 555, 723, 565/566 to work in the Student
industry and need to do application orientation projects project
2 Students need practical knowledge on Digital ICs 74x74, 74x138, 74x90, 74x194, 74x85, Student
74x151 to work in the industry and need to do application orientation projects project
PROPOSED ACTIONS: TOPICS BEYOND SYLLABUS/ASSIGNMENT/INDUSTRY VISIT/GUEST
LECTURER/NPTEL ETC

TOPICS BEYOND SYLLABUS/ADVANCED TOPICS/DESIGN:

1 Higher order filters
2 Applications of PLL

WEB SOURCE REFERENCES:

1 www.emedia.ee.unsw.edu.au Video lecturers: -Dept.Digital Library
2 www.nptel.edu.in Video lecturers of 1).Analog IC Design Dr. Nagendra Krishnapura,
IITM -Dept.Digital Library
3 www.ucberkely.edu.in
4 Solution Manuals:1). Op-Amps and Linear Integrated Circuits - Concepts and Applications by
James M.Fiore, Cengage/ Jaicc, 2/e, 2009. -Dept.Digital Library
5 E-books: 1). Op-Amps and Linear Integrated Circuits - Concepts and Applications by James
M.Fiore, Cengage/ Jaicc, 2/e, 2009.
6 2). Digital Fundamentals - Floyd and Jain, Pearson Education,8th Edition, 2005.
7 All 8-units having PPTS
Srl. No. Name of the resource Publisher

1 IEEE circuits and system society IEEE

2. IEEE components, packaging and IEEE

manufacturing technology society

3. IEEE consumer society IEEE

4. IEEE electronics devices society IEEE

Remedial classes
Srl. No. DATE topics Student present

2.

3.

4.

Unit 1

2 Marks Questions
1. What is an Operational Amplifier?
2. What is a Voltage transfer curve of an Op-amp?
3. Define CMRR & why does an op-amp have high CMRR.
4. Define Slew rate & what is slew rate of an operational amplifier.
5. Name three important specifications of IC op-amps & what is voltage gain of a practical
op-amp

3 Marks Questions
1. Explain features of 741 op amp
2. Explain the role of negative feedback in op amp
3. Draw and explain the practical offset voltage measurement of op amp
4. Draw and explain in op-amp as a i) summing amplifier ii) subtractor
 5. What is an Instrumentation Amplifier. How does it differ from an ordinary op-amp.

5 Marks Questions
1. With help of a block diagram explain the basic building blocks of an op-amp
2. Define CMRR, PSRR, Slew rate, input , output offset voltage and zero offset
3. Explain operation of integrator and differentiator.
4. Explain the Instrumentation amplifier and show that the output voltage is directly
proportional to the differential change in transducer resistance.
5. Write short notes on the following
i) AC amplifier
ii) Summing amplifier
iii) Voltage regulator

Objective Q&A
1. An ideal operational amplifier has [C]

A. infinite output impedance

B. zero input impedance
C. infinite bandwidth
D. All of the above
2. Another name for a unity gain amplifier is: [D]
A. difference amplifier
B. comparator
C. single ended
D.voltage follower
3.The open-loop voltage gain (Aol) of an op-amp is the [B]
A. external voltage gain the device is capable of
. B. internal voltage gain the device is capable of
C. most controlled parameter
D.same as Acl
4.A series dissipative regulator is an example of a: [A]
A. linear regulator
. B. switching regulator
C. shunt regulator
D.dc-to-dc converter
5.A noninverting closed-loop op-amp circuit generally has a gain factor: [B]
A. less than one
. B. greater than one
C. of zero
D.equal to one
6.In order for an output to swing above and below a zero reference, the op-amp circuit requires:
[D]
.
A. a resistive feedback network
B. zero offset
 C. a wide bandwidth
D.a negative and positive supply

7.Decreasing the gain in the given circuit could be achieved by [C]

A. reducing the amplitude of the input voltage
B. increasing the value of the feedback resistor
C. increasing the value of the input resistor
D. removing the feedback resistor
8. If ground is applied to the (+) terminal of an inverting op-amp, the (–) terminal will: [B]
A.not need an input resistor
B. be virtual ground
C. have high reverse current
D.not invert the signal
9.With negative feedback, the returning signal: [C]
A. aids the input signal
B. is proportional to output current
C. opposes the input signal
D.is proportional to differential voltage gain
10.A portion of the output that provides circuit stabilization is considered to be: [A]
A. negative feedback
B. distortion
C. open-loop
D.positive feedback

Fill in the blanks:

11. The Schmitt trigger is a two-state device that is used for_______ pulse shaping_______________

12.A circuit that has an output equal to the algebraic sum of the inputs is called a(n) ___SUMMING
AMPLIFIER___

13.An op-amp circuit in which the output voltage is equal to the difference between the two input
voltages is called a(n) ____DIFFERENTIAL AMPLIFIER__

14.
.

The feedback resistor has a value of __40kΩ____ in the given circuit

15.The voltage required to force the differential output to zero is called __input-offset voltage___

16.The common-mode rejection ratio (CMMR) is the ratio of __ the differential voltage gain ___ to ___ the
common-mode voltage gain ___.

17.Most of linear ICs are based on the two transistor differential amplifier because of its _______High
CMRR_

18. A op-amp is so named because __various mathematical operations like addition,subtraction,scale

changing,integration, & so on can be done____________

19. The values of Avol & BW for an ideal op-amp are ___infinite__&______infinite_____

20.The values of PSRR & CMRR for ideal op-amp are respectively ____zero___&____infinite___

21. The op-amp voltage follower circuit is also known as ____Buffer(or) Unity gain follower____

22. The temperature range in which 741C Op-amp is used is ___0degree centerade to 70 degree
centigrade__________

23. Offset adjustment in an op-amp is done with pin numbers _______1 & 5__________

24. The expression for input offset voltage drift is ____∆Vio/∆T_________

25. If Vo=Vi Sinwt, the expression for slewrate(SR) is ________SR=dVo/dt max = 2∏fVm
V/µsec_________

UNIT 2

2 Marks Questions
1. What is the difference between Active and Passive filters & why are active filters are
preferred
 2. What is a Low pass filter and what is a High pass filter
3. What is a wide band pass filter & what is a Notch filter.
4. What is 555 Timer & what are the two basic modes in which the 555 timer operates.
5. What is PLL & what are the basic building blocks of a PLL.

3 Marks Questions
1. List out the merits and demerits of active filters over passive filters.
2. Explain operation of 555 timer as Schmitt trigger
3. what is PLL and what are its basic building blocks.
4. Write short notes on the following i) Instrumentation amplifier ii) PLL applications
5. Define ‘Lock range’ and ‘capture range’ of a PLL

5 Marks Questions
1. Design first order Butterworth HPF with lower cut off frequency of 1kHz and pass band
gain of 2.Derive transfer function of above filter
2. Explain operation of 555 timer Monostable multivibrator. Write any one application of
Monostable multivibrator using 555.
3. Draw the internal block diagram of IC 555 and explain its operation.
4. Explain an Astable multivibrator using a 555 timer.
5. What is PLL? List one application of PLL and then briefly describe the role of the PLL in
that application.

Objective Q&A
1. What is the output waveform? [D]

A.sine wave
B. square wave
C. sawtooth wave
D.triangle wave
2. What is this circuit? [D]
A. a low-pass filter
B. a high-pass filter
C. a bandpass filter
D.a band-stop filter
3.Op-amps used as high- and low-pass filter circuits employ which configuration? [D]
A.noninverting B. comparator
C. open-loop D.inverting
4.An astable multivibrator is also known as a: [B]
A. one-shot multivibrator
B. free-running multivibrator
C. bistable multivibrator
D.monostable multivibrator
5.What starts a free-running multivibrator? [D]
A. a trigger
B. an input signal
C. an external circuit
D.nothing
6.What is the output waveform? [A]

A. sine wave
B. square wave
C. +15 V
D.–15 V
7.What is the output waveform of the circuit? [B]

A. sine wave
B. square wave
C. sawtooth wave
D.triangle wave
8.What is the frequency of this 555 astable multivibrator? [B]

A. 278 Hz
B. 178 Hz
C. 78 Hz
D.8 Hz
9.What three subcircuits does a phase locked loop (PLL) consist of? [D]
A. phase comparator, comparator, and VCO
B. phase comparator, bandpass filter, and VCO
C. phase comparator, bandpass filter, and demodulator
D.phase comparator, low-pass filter, and VCO
10.If the input to a comparator is a sine wave, the output is a: [C]
 A. ramp voltage
B. sine wave
C. rectangular wave
D.sawtooth wave

Fill in the blanks:

11.A PLL can be used as a(n)_______FREQUENCY MULTIPLIER__________

12.Switching voltage regulators have ___GREATER EFFICIENCY___ than linear regulators.

13.The 555 timer can be connected to operate a(n) ____astable multivibrator and a monostable________

14.An oscillator whose frequency can be controlled by an input "control voltage" is called a(n) __VCO____

15. The 555 timer IC is made up of a combination of _______linear comparators and digital flip-flops____.

16. By using active filters, loading effect can be __MINIMIZED___

17. With higher-order filters, the sharpness of the frequency response curve __INCREASES___

18. An op-amp differentiator circuit can be used as a __HPF__filter.

19. An op-amp integrator circuit can be used as a __LPF__ filter.

20. The transfer function sCR/1+sCR represents a __FIRST-ORDER HPF_ filter

21. The transfer function 1/sCR represents a __FIRST ORDER LPF__ filter.

22. The maximum output current Io that can be delivered from a 555 IC is __200µA___

23. The expression for T1 in the case of a 555 astable multivibrator is __T1 = 0.69(R A+ RB).C___

24. The expression for f, the frequency of oscillations, in the case of 555 astable multi is
___f=1.46/(RA+2RB)C___

25. The expression for f0 in the case of 565 PLL IC is __ f0=1.2/4R1C1____

UNIT 3

2 Marks Questions
1. What is Analog to Digital converter. And what is Digital to Analog converter
2. What is resolution for a DAC.
3. What is meant by Accuracy of a DAC
4. What is Quantization error in ADC.
5. What are the sources of Analog error in an ADC

3 Marks Questions
 1. Explain the operation of 3-bit weighted resistor DAC with neat diagram.
2. Explain the operation of 3-bit R-2R ladder DAC with neat diagram.
3. Explain the operation of 3-bit Inverted R-2R DAC with neat diagram.
4. Explain the operation of Counter type ADC with neat diagram.
5. Explain the operation of Parallel Comparator type ADC with neat diagram.

5 Marks Questions
1. Breifly explain specifications of ADC&DAC
2. Explain about D to A converter with R-2R ladder DAC
3. Explain about D to A converter with weighted resisters
4. Explain the operation of successive approximation ADC
5. Explain the operation of Dual slope ADC

Objective Q&A
Multiple choice:

1. What is the first phase of the dual-slope method of conversion? [A]

A. Connecting the analog voltage to the integrator for a fixed time

B. Setting the counter to zero

C. Connecting the integrator to a reference voltage

D.All of the above

2.What is the maximum conversion time of a clock rate of 1 MHz operating a 10-stage counter in an
ADC? [D]
A. 1.024 s

B. 102.3 ms

C. 10.24 ms

D.1.024 ms

3. What is the function of a ladder network? [C]

A. Changing an analog signal to a digital signal

B. Changing a linear signal to a digital signal

C. Changing a digital signal to an analog signal

D.None of the above

4.Which of the slope intervals of the integrator does the counter in the analog-to-digital converter (ADC)
operate? [C]
A. Positive

B. Negative

C. Both positive and negative

D.Neither positive nor negative

5.What is (are) the level(s) of the input voltage to a ladder-network conversion? [C]
A. 0

B. Vref

C. 0 V or Vref

D.None of the above

6.What is (are) the input(s) to the comparator in the ladder-network conversion of an ADC? [C]
A. Staircase voltage

B. Analog input voltage

C. Both staircase and analog input voltage

D.None of the above

7. This circuit is an example of a ________. [D]

A. comparator

B. 555 timer

C. D to A converter

D.ladder network

8.Which of the following devices is (are) a component of a digital-to-analog converter (DAC)? [D]

A. Integrator

B. Comparator
 C. Digital counter

D.All of the above

9.What is the voltage resolution of an 8-stage ladder network? [B]

A. Vref /128

B. Vref /256

C. Vref /512

D.Vref /1024

10. The fastest ADC is [C]

A. Counter type ADC

B. Successive approximation type ADC

C. Flash type ADC

D. None of the above

Fill in the blanks:

11. The disadvantage of a weighed resistor-network type DAC is __DIFFERENT VALUES

OF RESISTORS HAVE TO BE USED_____
12. The disadvantage of an R-2R ladder-network type DAC is __GREATER NUMBER OF
RESISTORS HAVE TO BE USED FOR A GIVEN BIT COMPARED TO THE
WEIGHTED RESISTOR NETWORK TYPE DAC____
13. To account for variations in logic levels, DACs employ ___LEVEL AMPLIFIERS___
14. For an n-bit DAC, the expression for resolution is __(1/2 n-1)x100%__
15. The range of settling time for a 12-bit DAC is ___1 µsec to 20 µsec____
16. The slew rate in DACs is defined as __MAXIMUM RATE OF CHANGE OF OUTPUT
VOLTAGE__
17. Between counter-ramp type and successive-approximation type ADCs, the one having
lesser conversion time for a given input is ___SUCCESSIVE-APPROXIMATION
TYPE__
18. The major advantage of a dual-slope-integrating type ADC is __THE OUTPUT IS
INDEPENDENT OF THE TOLERANCE OF THE PASSIVE COMPONENTS R AND
C___
19. The number of comparators required in the case of a simultaneous-conversion type ADC
for n-bit conversion is ___2n-1___
20. ADCs are classified broadly as __DIRECT CONVERSION TYPE, INDIRECT
CONVERSION TYPE__
21. Example for Direct conversion type ADCs are ___FLASH TYPE, COUNTER TYPE,
SUCCESSIVE APPROXIMATION TYPE ADC__
 22. Example for In-Direct conversion type ADCs are__ DUAL SLOPE INTEGRATED
TYPE ADC___
23. The parameters of ADCs and DACs are__ CONVERSION TIME, ACCURACY, INPUT
IMPEDANCE, AQUISITION TIME,DROOP RATE AND MONOTONOCITY__
24. DAC types are namely __WEIGHTED RESISTOR TYPE,R-2R LADDER TYPE__
25. DACs are used in __BIOMEDICAL, AEROSPACE, TELEMETRY AND
INSTRUMENTATION APPLICATIONS__

UNIT 4

2 Marks Questions
1. Define Decoder? What is binary decoder?
2. Define Encoder? What is parity encoder?
3. Define Multiplexer?
4. What do you mean by comparator?
5. Given the comparison between combinational circuits & sequential circuits?

3 Marks Questions
1. Sketch TTL NOR Gate and NAND Gate explain its working
2. Explain about MOS&CMOS open drain and Tristate outputs
3. Explain the operation of 4-bit magnitude comparator with truth-table.
4. Explain the operation of Parity generator with neat diagram.
5. What are the draw backs of TTL gate and explain how they are overcome by using
Schottky clamping transistors

5 Marks Questions
1. Explain the operation of two input TTL NAND gate
2. Design 32x1 MUX using four 8x1 MUX
3. Design code converter circuit that converts BCD code to Excess -3 code
4. Design 4:16 decoder using two 3:8 decoders
5. Sketch 2-input CMOS NOR Gate and NAND Gate explain its working

Objective Q&A
Multiple choice:

1.For a CMOS gate, which is the best speed-power product? [A]

A. 1.4 pJ

B. 1.6 pJ
C. 2.4 pJ

D.3.3 pJ

2.In a TTL circuit, if an excessive number of load gate inputs are connected, ________. [B]

A. VOH(min) drops below VOH

B. VOH drops below VOH(min)

C. VOH exceeds VOH(min)

D.VOH and VOH(min) are unaffected

3. An open-drain gate is the CMOS counterpart of ________. [A]

A. an open-collector TTL gate

B. a tristate TTL gate

C. a bipolar junction transistor

D.an emitter-coupled logic gate

4.A TTL NAND gate with IIL(max) of –1.6 mA per input drives
eight TTL inputs. How much current does the drive output
sink? [A]
A. –12.8 mA

B. –8 mA

C. –1.6 mA

D.–25.6 mA

5. The nominal value of the dc supply voltage for TTL and

CMOS is ________. [B]
A. +3 V

B. +5 V

C. +9 V

D.+12 V

6.Which logic family combines the advantages of CMOS and TTL? [A]
A.BiCMOS B. TTL/CMOS

C. ECL D.TTL/MOS
7.Which equation is correct? [D]

A. VNL = VIL(max) + VOL(max)

B. VNH = VOH(min) + VIH(min)

C. VNL = VOH(min) – VIH(min)

D.VNH = VOH(min) – VIH(min)

8.An open-collector output requires ________. [B]

A. a pull-down resistor

B. a pull-up resistor

C. no output resistor

D.an output resistor

9.Which factor does not affect CMOS loading? [C]

A. Charging time associated with the output resistance of the driving gate

B. Discharging time associated with the output resistance of the driving gate

C. Output capacitance of the load gates

D.Input capacitance of the load gates

10.The greater the propagation delay, the ________ [A]

A. lower the maximum frequency

B. higher the maximum frequency

C. maximum frequency is unaffected

D.minimum frequency is unaffected

11.What is the no. of OR IC. :[C]

a) 7402
b) 7486
c) 7432
d) 7404

12. What is the no. of AND IC. : [B]

a) 7402
b) 7408
c) 7447
d) 7492

13. What is the no. of NOR IC. : [A]

a) 7402
b) 7486
c) 7447
d) 7492

14. What is the no. of NAND IC. : [C]

a) 7402
b) 7404
c) 7400
d) 7492

15. What is the no. of NOT IC. : [C]

a) 7402
b) 7486
c) 7404
d) 7492

Fill in the blanks:

16.Multiplexer is : _________ many inputs 1 output__________

17.Demultiplexer is :________ 1 input many output___________
18. In 8:1 mux the no. of select lines are____3___________
19. In 16:1 mux the no. of select lines are _____4____________
20 In 3: 8 decoder the no. of inputs are _______3_________

21. Decoder is:_____ many input many output_________

22. TTL uses:______ multi emitter transistors____
23. A TTL circuit with totem pole output has :____ low output impedance__
24. What is the no. of EX-OR IC. :_____ 7486______

25. What is the no of three input NAND gate:___7410__

Multiplexer is : _________ many inputs 1 output__________
26.Demultiplexer is :________ 1 input many output___________
27. In 8:1 mux the no. of select lines are____3___________
28. In 16:1 mux the no. of select lines are _____4____________
29 In 3: 8 decoder the no. of inputs are _______3_________

30. Decoder is:_____ many input many output_________

31. TTL uses:______ multi emitter transistors____
32. A TTL circuit with totem pole output has :____ low output impedance__
33. What is the no. of EX-OR IC. :_____ 7486______
34. What is the no of three input NAND gate:___7410__

UNIT 5

2 Marks Questions
1. Define Sequential circuit.
2. What are the types of sequential circuits.
3. Define Synchronous sequential circuit.
4. Define Asynchronous sequential circuit.
5. Define 6-Transistor SRAM.

3 Marks Questions
1. Design a 4 bit synchronous decade counter using D-flipflop 74XX IC
2. Draw the JK flip flop and explain the operation with truth table? What is race around
condition?
3. Design & Explain the 3-bit Up/Down counter using JK Flipflops.
4. Explain the read and write operations of SRAM Memory cell with neat diagrams.
5. Explain the operation of DRAM Memory cell with neat diagram?

5 Marks Questions
1. Write the characteristic table, excitation table for JK, SR, T and D flip-flops.
2. Design a modulo-10 counter using JK flip flops
3. Design 8 bit adder using 74283
4. Draw the D flip flop and T flip flop and explain the operation and draw the their truth
tables
5. Briefly explain the RAM operation with the help of RAM Architecture?

Objective Q&A
Multiple choice:

1.Sequential circuit has :

a) feedback
b) no feedback
c) may or may not
d) none of these

2. For a level input sequential circuit :

a) output in a level only

b) output is in the pulse form
c) output may be a pulse or a level form
d) none of these

3.In a ring counter 1 for N clock pulse the scale for the counter is :

a) N:1
b) N:2
c) N:10
d) N:100
3. For a decade counter, number of binaries required is :
a) five
b) ten
c) eight
d) two

4.Counter ;

a) it counts the no. randomly

b) it counts the no. sequentially
c) both a and b
d) none of these

5. What is asynchronous counter :

a) each flip-flop has it own clock

b) all the flip-flop are combined to common clock
c) both a and b
d) none of the above

6. UP Counter is :

a) it counts in upward manner

b) it count in down ward manner
c) it counts in both the direction
d) none of the above

7. DOWN counter is:

a) it counts in upward manner

b) it count in down ward manner
c) it counts in both the direction
d) none of the above

8. Another name of Johnson counter :

a) asynchronous counter
b) synchronous counter
c) ring counter
d) none of above
9. Give full form of SIPO shift registers :

a) serial in parallel output

b) single in parallel output
c) series input peripherals output
d) none of above

10. Give full form of PISO shift registers :

a) primary input secondary output

b) parallel in secondary output
c) parallel in serial out
d) none of above

11. Give full form of PIPO shift registers :

a) parallel in parallel out

b) primary in parallel out
c) parallel in primary out
d) none

12. What is tristate shift registers :

a) it has 3 inputs
b) it has high , low or high impedance output
c) both a and b
d) none

13. Which ICs belongs to tristate shift registers

a) 7483
b) 7492
c) 74164
d) none

14. In bidirectional shift registers date can be shifted to:

a) right or left
b) up or down
c) both
d) none

15. How many 7490 ICs are to be cascaded to count upto 999:

a) 1
b) 2
c) 3
d) 4

Fill in the blanks:

16. A ring counter is same as :_______ up-down counter ___
17. What is the no. of 16-bit RAM IC___7484_________
18. What is the no. of 4-bit Magnitude Comparator IC____7485__________
19. What is the no. of 256 bit ROM IC_________7488____________
20. What is the no. of 4-bit decade counter IC____________7468____________